./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i -s /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 840e3ba93a4f821803f9089812ff1f73e2838277 ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i -s /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 840e3ba93a4f821803f9089812ff1f73e2838277 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Result: UNKNOWN: Overapproximated counterexample --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-09 17:50:48,257 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-09 17:50:48,258 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-09 17:50:48,267 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-09 17:50:48,267 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-09 17:50:48,268 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-09 17:50:48,269 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-09 17:50:48,270 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-09 17:50:48,271 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-09 17:50:48,272 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-09 17:50:48,272 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-09 17:50:48,272 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-09 17:50:48,273 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-09 17:50:48,274 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-09 17:50:48,274 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-09 17:50:48,275 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-09 17:50:48,276 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-09 17:50:48,277 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-09 17:50:48,278 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-09 17:50:48,279 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-09 17:50:48,280 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-09 17:50:48,281 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-09 17:50:48,283 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-09 17:50:48,283 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-09 17:50:48,283 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-09 17:50:48,284 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-09 17:50:48,284 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-09 17:50:48,285 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-09 17:50:48,285 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-09 17:50:48,286 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-09 17:50:48,286 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-09 17:50:48,287 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-09 17:50:48,287 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-09 17:50:48,287 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-09 17:50:48,288 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-09 17:50:48,288 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-09 17:50:48,288 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Default.epf [2018-12-09 17:50:48,296 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-09 17:50:48,296 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-09 17:50:48,297 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-09 17:50:48,297 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-09 17:50:48,297 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-09 17:50:48,298 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-09 17:50:48,298 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-09 17:50:48,298 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-12-09 17:50:48,298 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-09 17:50:48,298 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-09 17:50:48,298 INFO L133 SettingsManager]: * Log string format=TERM [2018-12-09 17:50:48,298 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-12-09 17:50:48,298 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-12-09 17:50:48,299 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-09 17:50:48,299 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-09 17:50:48,299 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-09 17:50:48,299 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-09 17:50:48,299 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-09 17:50:48,299 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-09 17:50:48,300 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-09 17:50:48,300 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-09 17:50:48,300 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-09 17:50:48,300 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-09 17:50:48,300 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-09 17:50:48,300 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-09 17:50:48,300 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-09 17:50:48,301 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 17:50:48,301 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-09 17:50:48,301 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-09 17:50:48,301 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-09 17:50:48,301 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-12-09 17:50:48,301 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-09 17:50:48,301 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-09 17:50:48,301 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-12-09 17:50:48,302 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-12-09 17:50:48,302 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 840e3ba93a4f821803f9089812ff1f73e2838277 [2018-12-09 17:50:48,324 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-09 17:50:48,331 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-09 17:50:48,334 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-09 17:50:48,334 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-09 17:50:48,335 INFO L276 PluginConnector]: CDTParser initialized [2018-12-09 17:50:48,335 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-09 17:50:48,372 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/data/784fe3f48/eec5fb7309ae40bf956500afdc167543/FLAG40e9492fc [2018-12-09 17:50:48,891 INFO L307 CDTParser]: Found 1 translation units. [2018-12-09 17:50:48,891 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-09 17:50:48,902 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/data/784fe3f48/eec5fb7309ae40bf956500afdc167543/FLAG40e9492fc [2018-12-09 17:50:49,352 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/data/784fe3f48/eec5fb7309ae40bf956500afdc167543 [2018-12-09 17:50:49,354 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-09 17:50:49,355 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-09 17:50:49,355 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-09 17:50:49,355 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-09 17:50:49,357 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-09 17:50:49,358 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 05:50:49" (1/1) ... [2018-12-09 17:50:49,359 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2c9c5a09 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49, skipping insertion in model container [2018-12-09 17:50:49,360 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 05:50:49" (1/1) ... [2018-12-09 17:50:49,364 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-09 17:50:49,401 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-09 17:50:49,816 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 17:50:49,827 INFO L191 MainTranslator]: Completed pre-run [2018-12-09 17:50:49,893 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 17:50:49,922 INFO L195 MainTranslator]: Completed translation [2018-12-09 17:50:49,923 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49 WrapperNode [2018-12-09 17:50:49,923 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-09 17:50:49,923 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-09 17:50:49,923 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-09 17:50:49,924 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-09 17:50:49,929 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49" (1/1) ... [2018-12-09 17:50:49,945 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49" (1/1) ... [2018-12-09 17:50:49,951 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-09 17:50:49,951 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-09 17:50:49,951 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-09 17:50:49,951 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-09 17:50:49,957 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49" (1/1) ... [2018-12-09 17:50:49,958 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49" (1/1) ... [2018-12-09 17:50:49,962 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49" (1/1) ... [2018-12-09 17:50:49,962 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49" (1/1) ... [2018-12-09 17:50:49,980 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49" (1/1) ... [2018-12-09 17:50:49,985 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49" (1/1) ... [2018-12-09 17:50:49,988 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49" (1/1) ... [2018-12-09 17:50:49,993 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-09 17:50:49,993 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-09 17:50:49,993 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-09 17:50:49,993 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-09 17:50:49,994 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 17:50:50,027 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-12-09 17:50:50,028 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-12-09 17:50:50,028 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2018-12-09 17:50:50,028 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_get_drvdata [2018-12-09 17:50:50,028 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_unregister [2018-12-09 17:50:50,028 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_unregister [2018-12-09 17:50:50,028 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-09 17:50:50,028 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-12-09 17:50:50,028 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-12-09 17:50:50,029 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-12-09 17:50:50,029 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-12-09 17:50:50,029 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize [2018-12-09 17:50:50,029 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize [2018-12-09 17:50:50,029 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-12-09 17:50:50,029 INFO L130 BoogieDeclarations]: Found specification of procedure external_alloc [2018-12-09 17:50:50,029 INFO L138 BoogieDeclarations]: Found implementation of procedure external_alloc [2018-12-09 17:50:50,029 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-12-09 17:50:50,029 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-12-09 17:50:50,029 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2018-12-09 17:50:50,030 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_time_to_tm [2018-12-09 17:50:50,030 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-12-09 17:50:50,030 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-12-09 17:50:50,030 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-12-09 17:50:50,030 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-12-09 17:50:50,030 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2018-12-09 17:50:50,030 INFO L138 BoogieDeclarations]: Found implementation of procedure irq_set_irq_wake [2018-12-09 17:50:50,030 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-12-09 17:50:50,030 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-12-09 17:50:50,030 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-12-09 17:50:50,031 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-12-09 17:50:50,031 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-12-09 17:50:50,031 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-12-09 17:50:50,031 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2018-12-09 17:50:50,031 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_tm_to_time [2018-12-09 17:50:50,031 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2018-12-09 17:50:50,031 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2018-12-09 17:50:50,031 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-12-09 17:50:50,031 INFO L138 BoogieDeclarations]: Found implementation of procedure kfree [2018-12-09 17:50:50,031 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2018-12-09 17:50:50,032 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2018-12-09 17:50:50,032 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-12-09 17:50:50,032 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-12-09 17:50:50,032 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-12-09 17:50:50,032 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-12-09 17:50:50,032 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-12-09 17:50:50,032 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_release_3 [2018-12-09 17:50:50,032 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_release_3 [2018-12-09 17:50:50,032 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-12-09 17:50:50,032 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-12-09 17:50:50,033 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-12-09 17:50:50,033 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-12-09 17:50:50,033 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-12-09 17:50:50,033 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-12-09 17:50:50,033 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-12-09 17:50:50,033 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-12-09 17:50:50,033 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-12-09 17:50:50,033 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-12-09 17:50:50,033 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2018-12-09 17:50:50,033 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_iounmap [2018-12-09 17:50:50,034 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_probe [2018-12-09 17:50:50,034 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_probe [2018-12-09 17:50:50,034 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_valid_tm [2018-12-09 17:50:50,034 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_valid_tm [2018-12-09 17:50:50,034 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-12-09 17:50:50,034 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-12-09 17:50:50,034 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-09 17:50:50,034 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-09 17:50:50,034 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-12-09 17:50:50,034 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-12-09 17:50:50,035 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-12-09 17:50:50,035 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-12-09 17:50:50,035 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-12-09 17:50:50,035 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-12-09 17:50:50,035 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_update_irq [2018-12-09 17:50:50,035 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_update_irq [2018-12-09 17:50:50,035 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2018-12-09 17:50:50,035 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_device_unregister [2018-12-09 17:50:50,035 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-09 17:50:50,035 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-09 17:50:50,035 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2018-12-09 17:50:50,036 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2018-12-09 17:50:50,036 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-12-09 17:50:50,036 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-12-09 17:50:50,036 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-12-09 17:50:50,036 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-12-09 17:50:50,036 INFO L130 BoogieDeclarations]: Found specification of procedure _raw_spin_unlock_irqrestore [2018-12-09 17:50:50,036 INFO L138 BoogieDeclarations]: Found implementation of procedure _raw_spin_unlock_irqrestore [2018-12-09 17:50:50,036 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-12-09 17:50:50,036 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-12-09 17:50:50,036 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-12-09 17:50:50,036 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-12-09 17:50:50,037 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-12-09 17:50:50,037 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-12-09 17:50:50,037 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-12-09 17:50:50,037 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-12-09 17:50:50,037 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-12-09 17:50:50,037 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2018-12-09 17:50:50,037 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_resource [2018-12-09 17:50:50,037 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-09 17:50:50,037 INFO L130 BoogieDeclarations]: Found specification of procedure dev_set_drvdata [2018-12-09 17:50:50,037 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_set_drvdata [2018-12-09 17:50:50,037 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-12-09 17:50:50,038 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-12-09 17:50:50,038 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-12-09 17:50:50,038 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-12-09 17:50:50,038 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-12-09 17:50:50,038 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-12-09 17:50:50,038 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-12-09 17:50:50,038 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-12-09 17:50:50,038 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-12-09 17:50:50,038 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-12-09 17:50:50,038 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-12-09 17:50:50,038 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-12-09 17:50:50,039 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-12-09 17:50:50,039 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-12-09 17:50:50,039 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-12-09 17:50:50,039 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-12-09 17:50:50,039 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-12-09 17:50:50,039 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-12-09 17:50:50,039 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-12-09 17:50:50,039 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-12-09 17:50:50,039 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-12-09 17:50:50,039 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-12-09 17:50:50,040 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_3 [2018-12-09 17:50:50,040 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_3 [2018-12-09 17:50:50,040 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_2 [2018-12-09 17:50:50,040 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_2 [2018-12-09 17:50:50,040 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-12-09 17:50:50,040 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-12-09 17:50:50,040 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2018-12-09 17:50:50,040 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2018-12-09 17:50:50,040 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-12-09 17:50:50,040 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-12-09 17:50:50,040 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-12-09 17:50:50,041 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-12-09 17:50:50,041 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-09 17:50:50,041 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-09 17:50:50,756 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-09 17:50:50,757 INFO L280 CfgBuilder]: Removed 0 assue(true) statements. [2018-12-09 17:50:50,757 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 05:50:50 BoogieIcfgContainer [2018-12-09 17:50:50,757 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-09 17:50:50,758 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-09 17:50:50,758 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-09 17:50:50,761 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-09 17:50:50,761 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 09.12 05:50:49" (1/3) ... [2018-12-09 17:50:50,762 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7d926dca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 05:50:50, skipping insertion in model container [2018-12-09 17:50:50,762 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:50:49" (2/3) ... [2018-12-09 17:50:50,762 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7d926dca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 05:50:50, skipping insertion in model container [2018-12-09 17:50:50,762 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 05:50:50" (3/3) ... [2018-12-09 17:50:50,764 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-09 17:50:50,772 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-09 17:50:50,778 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-09 17:50:50,789 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-09 17:50:50,816 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-09 17:50:50,816 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-09 17:50:50,816 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-09 17:50:50,816 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-09 17:50:50,816 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-09 17:50:50,817 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-09 17:50:50,817 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-09 17:50:50,817 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-09 17:50:50,839 INFO L276 IsEmpty]: Start isEmpty. Operand 487 states. [2018-12-09 17:50:50,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-09 17:50:50,846 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:50:50,846 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:50:50,848 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:50:50,853 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:50:50,853 INFO L82 PathProgramCache]: Analyzing trace with hash -458857320, now seen corresponding path program 1 times [2018-12-09 17:50:50,855 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:50:50,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:50,892 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:50:50,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:50,892 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:50:50,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:50:51,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 17:50:51,037 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:50:51,037 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 17:50:51,038 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:50:51,041 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 17:50:51,048 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 17:50:51,049 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:50:51,050 INFO L87 Difference]: Start difference. First operand 487 states. Second operand 3 states. [2018-12-09 17:50:51,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:50:51,108 INFO L93 Difference]: Finished difference Result 824 states and 1044 transitions. [2018-12-09 17:50:51,109 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 17:50:51,110 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-12-09 17:50:51,110 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:50:51,118 INFO L225 Difference]: With dead ends: 824 [2018-12-09 17:50:51,119 INFO L226 Difference]: Without dead ends: 332 [2018-12-09 17:50:51,123 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:50:51,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 332 states. [2018-12-09 17:50:51,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 332 to 332. [2018-12-09 17:50:51,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 332 states. [2018-12-09 17:50:51,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 332 states to 332 states and 403 transitions. [2018-12-09 17:50:51,165 INFO L78 Accepts]: Start accepts. Automaton has 332 states and 403 transitions. Word has length 47 [2018-12-09 17:50:51,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:50:51,166 INFO L480 AbstractCegarLoop]: Abstraction has 332 states and 403 transitions. [2018-12-09 17:50:51,166 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 17:50:51,166 INFO L276 IsEmpty]: Start isEmpty. Operand 332 states and 403 transitions. [2018-12-09 17:50:51,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-12-09 17:50:51,168 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:50:51,169 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:50:51,169 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:50:51,169 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:50:51,169 INFO L82 PathProgramCache]: Analyzing trace with hash -717010078, now seen corresponding path program 1 times [2018-12-09 17:50:51,169 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:50:51,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:51,172 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:50:51,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:51,172 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:50:51,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:50:51,235 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:50:51,235 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:50:51,235 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 17:50:51,236 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:50:51,237 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 17:50:51,237 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 17:50:51,237 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:50:51,237 INFO L87 Difference]: Start difference. First operand 332 states and 403 transitions. Second operand 3 states. [2018-12-09 17:50:51,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:50:51,304 INFO L93 Difference]: Finished difference Result 777 states and 946 transitions. [2018-12-09 17:50:51,304 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 17:50:51,304 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2018-12-09 17:50:51,304 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:50:51,307 INFO L225 Difference]: With dead ends: 777 [2018-12-09 17:50:51,307 INFO L226 Difference]: Without dead ends: 462 [2018-12-09 17:50:51,309 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:50:51,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-12-09 17:50:51,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 459. [2018-12-09 17:50:51,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 459 states. [2018-12-09 17:50:51,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 559 transitions. [2018-12-09 17:50:51,328 INFO L78 Accepts]: Start accepts. Automaton has 459 states and 559 transitions. Word has length 68 [2018-12-09 17:50:51,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:50:51,328 INFO L480 AbstractCegarLoop]: Abstraction has 459 states and 559 transitions. [2018-12-09 17:50:51,328 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 17:50:51,328 INFO L276 IsEmpty]: Start isEmpty. Operand 459 states and 559 transitions. [2018-12-09 17:50:51,330 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-12-09 17:50:51,330 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:50:51,330 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:50:51,330 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:50:51,330 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:50:51,330 INFO L82 PathProgramCache]: Analyzing trace with hash 1417324652, now seen corresponding path program 1 times [2018-12-09 17:50:51,330 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:50:51,332 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:51,332 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:50:51,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:51,333 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:50:51,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:50:51,399 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:50:51,399 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:50:51,399 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 17:50:51,399 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:50:51,399 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 17:50:51,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 17:50:51,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 17:50:51,400 INFO L87 Difference]: Start difference. First operand 459 states and 559 transitions. Second operand 5 states. [2018-12-09 17:50:51,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:50:51,488 INFO L93 Difference]: Finished difference Result 1345 states and 1665 transitions. [2018-12-09 17:50:51,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 17:50:51,488 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2018-12-09 17:50:51,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:50:51,491 INFO L225 Difference]: With dead ends: 1345 [2018-12-09 17:50:51,491 INFO L226 Difference]: Without dead ends: 913 [2018-12-09 17:50:51,493 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-09 17:50:51,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 913 states. [2018-12-09 17:50:51,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 913 to 890. [2018-12-09 17:50:51,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 890 states. [2018-12-09 17:50:51,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 890 states to 890 states and 1092 transitions. [2018-12-09 17:50:51,527 INFO L78 Accepts]: Start accepts. Automaton has 890 states and 1092 transitions. Word has length 70 [2018-12-09 17:50:51,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:50:51,527 INFO L480 AbstractCegarLoop]: Abstraction has 890 states and 1092 transitions. [2018-12-09 17:50:51,527 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 17:50:51,528 INFO L276 IsEmpty]: Start isEmpty. Operand 890 states and 1092 transitions. [2018-12-09 17:50:51,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-12-09 17:50:51,529 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:50:51,529 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:50:51,529 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:50:51,529 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:50:51,529 INFO L82 PathProgramCache]: Analyzing trace with hash -837085032, now seen corresponding path program 1 times [2018-12-09 17:50:51,529 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:50:51,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:51,531 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:50:51,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:51,531 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:50:51,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:50:51,613 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:50:51,613 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:50:51,613 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 17:50:51,613 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:50:51,614 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 17:50:51,614 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 17:50:51,614 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 17:50:51,614 INFO L87 Difference]: Start difference. First operand 890 states and 1092 transitions. Second operand 5 states. [2018-12-09 17:50:51,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:50:51,679 INFO L93 Difference]: Finished difference Result 1785 states and 2210 transitions. [2018-12-09 17:50:51,680 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 17:50:51,680 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2018-12-09 17:50:51,680 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:50:51,682 INFO L225 Difference]: With dead ends: 1785 [2018-12-09 17:50:51,683 INFO L226 Difference]: Without dead ends: 922 [2018-12-09 17:50:51,684 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-09 17:50:51,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 922 states. [2018-12-09 17:50:51,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 922 to 898. [2018-12-09 17:50:51,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 898 states. [2018-12-09 17:50:51,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 898 states to 898 states and 1094 transitions. [2018-12-09 17:50:51,711 INFO L78 Accepts]: Start accepts. Automaton has 898 states and 1094 transitions. Word has length 71 [2018-12-09 17:50:51,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:50:51,711 INFO L480 AbstractCegarLoop]: Abstraction has 898 states and 1094 transitions. [2018-12-09 17:50:51,711 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 17:50:51,711 INFO L276 IsEmpty]: Start isEmpty. Operand 898 states and 1094 transitions. [2018-12-09 17:50:51,712 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-09 17:50:51,712 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:50:51,712 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:50:51,712 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:50:51,712 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:50:51,712 INFO L82 PathProgramCache]: Analyzing trace with hash 564763209, now seen corresponding path program 1 times [2018-12-09 17:50:51,712 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:50:51,714 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:51,714 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:50:51,714 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:51,714 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:50:51,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:50:51,772 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:50:51,772 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:50:51,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 17:50:51,772 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:50:51,773 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 17:50:51,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 17:50:51,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 17:50:51,773 INFO L87 Difference]: Start difference. First operand 898 states and 1094 transitions. Second operand 5 states. [2018-12-09 17:50:51,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:50:51,832 INFO L93 Difference]: Finished difference Result 1801 states and 2210 transitions. [2018-12-09 17:50:51,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 17:50:51,832 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 72 [2018-12-09 17:50:51,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:50:51,834 INFO L225 Difference]: With dead ends: 1801 [2018-12-09 17:50:51,835 INFO L226 Difference]: Without dead ends: 930 [2018-12-09 17:50:51,836 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-09 17:50:51,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 930 states. [2018-12-09 17:50:51,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 930 to 906. [2018-12-09 17:50:51,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 906 states. [2018-12-09 17:50:51,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 906 states to 906 states and 1096 transitions. [2018-12-09 17:50:51,861 INFO L78 Accepts]: Start accepts. Automaton has 906 states and 1096 transitions. Word has length 72 [2018-12-09 17:50:51,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:50:51,861 INFO L480 AbstractCegarLoop]: Abstraction has 906 states and 1096 transitions. [2018-12-09 17:50:51,861 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 17:50:51,861 INFO L276 IsEmpty]: Start isEmpty. Operand 906 states and 1096 transitions. [2018-12-09 17:50:51,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-09 17:50:51,862 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:50:51,862 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:50:51,862 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:50:51,863 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:50:51,863 INFO L82 PathProgramCache]: Analyzing trace with hash -653509867, now seen corresponding path program 1 times [2018-12-09 17:50:51,863 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:50:51,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:51,864 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:50:51,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:51,864 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:50:51,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:50:51,905 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:50:51,905 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:50:51,905 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 17:50:51,905 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:50:51,905 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 17:50:51,905 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 17:50:51,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 17:50:51,906 INFO L87 Difference]: Start difference. First operand 906 states and 1096 transitions. Second operand 5 states. [2018-12-09 17:50:51,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:50:51,984 INFO L93 Difference]: Finished difference Result 1712 states and 2088 transitions. [2018-12-09 17:50:51,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 17:50:51,984 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2018-12-09 17:50:51,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:50:51,988 INFO L225 Difference]: With dead ends: 1712 [2018-12-09 17:50:51,988 INFO L226 Difference]: Without dead ends: 833 [2018-12-09 17:50:51,990 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-09 17:50:51,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 833 states. [2018-12-09 17:50:52,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 833 to 815. [2018-12-09 17:50:52,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 815 states. [2018-12-09 17:50:52,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 815 states to 815 states and 980 transitions. [2018-12-09 17:50:52,025 INFO L78 Accepts]: Start accepts. Automaton has 815 states and 980 transitions. Word has length 73 [2018-12-09 17:50:52,025 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:50:52,025 INFO L480 AbstractCegarLoop]: Abstraction has 815 states and 980 transitions. [2018-12-09 17:50:52,025 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 17:50:52,025 INFO L276 IsEmpty]: Start isEmpty. Operand 815 states and 980 transitions. [2018-12-09 17:50:52,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-12-09 17:50:52,027 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:50:52,027 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:50:52,027 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:50:52,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:50:52,027 INFO L82 PathProgramCache]: Analyzing trace with hash 1428324143, now seen corresponding path program 1 times [2018-12-09 17:50:52,027 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:50:52,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:52,029 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:50:52,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:52,029 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:50:52,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:50:52,111 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-09 17:50:52,112 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:50:52,112 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:50:52,112 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 86 with the following transitions: [2018-12-09 17:50:52,113 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [667], [700], [705], [711], [713], [724], [729], [731], [758], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:50:52,138 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:50:52,138 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:50:52,319 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:50:52,319 INFO L272 AbstractInterpreter]: Visited 18 different actions 18 times. Never merged. Never widened. Performed 1017 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1017 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 177 variables. [2018-12-09 17:50:52,324 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:50:52,324 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:50:52,417 INFO L227 lantSequenceWeakener]: Weakened 16 states. On average, predicates are now at 94.21% of their original sizes. [2018-12-09 17:50:52,417 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:50:52,474 INFO L418 sIntCurrentIteration]: We unified 84 AI predicates to 84 [2018-12-09 17:50:52,474 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:50:52,475 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:50:52,475 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [9] total 16 [2018-12-09 17:50:52,475 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:50:52,475 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-12-09 17:50:52,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-12-09 17:50:52,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-09 17:50:52,476 INFO L87 Difference]: Start difference. First operand 815 states and 980 transitions. Second operand 9 states. [2018-12-09 17:50:54,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:50:54,366 INFO L93 Difference]: Finished difference Result 1950 states and 2346 transitions. [2018-12-09 17:50:54,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-12-09 17:50:54,366 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 85 [2018-12-09 17:50:54,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:50:54,371 INFO L225 Difference]: With dead ends: 1950 [2018-12-09 17:50:54,371 INFO L226 Difference]: Without dead ends: 1159 [2018-12-09 17:50:54,373 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 85 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-12-09 17:50:54,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1159 states. [2018-12-09 17:50:54,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1159 to 1095. [2018-12-09 17:50:54,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1095 states. [2018-12-09 17:50:54,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1095 states to 1095 states and 1324 transitions. [2018-12-09 17:50:54,421 INFO L78 Accepts]: Start accepts. Automaton has 1095 states and 1324 transitions. Word has length 85 [2018-12-09 17:50:54,421 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:50:54,421 INFO L480 AbstractCegarLoop]: Abstraction has 1095 states and 1324 transitions. [2018-12-09 17:50:54,421 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-12-09 17:50:54,421 INFO L276 IsEmpty]: Start isEmpty. Operand 1095 states and 1324 transitions. [2018-12-09 17:50:54,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-12-09 17:50:54,423 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:50:54,423 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:50:54,423 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:50:54,424 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:50:54,424 INFO L82 PathProgramCache]: Analyzing trace with hash 1160945827, now seen corresponding path program 1 times [2018-12-09 17:50:54,424 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:50:54,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:54,426 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:50:54,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:50:54,426 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:50:54,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:50:54,527 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-09 17:50:54,527 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:50:54,528 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:50:54,528 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 87 with the following transitions: [2018-12-09 17:50:54,528 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [667], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:50:54,530 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:50:54,531 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:50:54,650 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:50:54,650 INFO L272 AbstractInterpreter]: Visited 38 different actions 46 times. Merged at 3 different actions 5 times. Never widened. Performed 1463 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1463 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:50:54,652 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:50:54,653 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:50:54,808 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:50:54,809 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:50:55,787 INFO L418 sIntCurrentIteration]: We unified 85 AI predicates to 85 [2018-12-09 17:50:55,787 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:50:55,788 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:50:55,788 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [9] total 33 [2018-12-09 17:50:55,788 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:50:55,788 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-12-09 17:50:55,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-12-09 17:50:55,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=533, Unknown=0, NotChecked=0, Total=650 [2018-12-09 17:50:55,789 INFO L87 Difference]: Start difference. First operand 1095 states and 1324 transitions. Second operand 26 states. [2018-12-09 17:51:11,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:51:11,791 INFO L93 Difference]: Finished difference Result 2630 states and 3199 transitions. [2018-12-09 17:51:11,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-12-09 17:51:11,791 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 86 [2018-12-09 17:51:11,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:51:11,796 INFO L225 Difference]: With dead ends: 2630 [2018-12-09 17:51:11,796 INFO L226 Difference]: Without dead ends: 1563 [2018-12-09 17:51:11,799 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 87 GetRequests, 60 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 287 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=132, Invalid=624, Unknown=0, NotChecked=0, Total=756 [2018-12-09 17:51:11,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1563 states. [2018-12-09 17:51:11,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1563 to 1135. [2018-12-09 17:51:11,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1135 states. [2018-12-09 17:51:11,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1135 states to 1135 states and 1377 transitions. [2018-12-09 17:51:11,861 INFO L78 Accepts]: Start accepts. Automaton has 1135 states and 1377 transitions. Word has length 86 [2018-12-09 17:51:11,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:51:11,861 INFO L480 AbstractCegarLoop]: Abstraction has 1135 states and 1377 transitions. [2018-12-09 17:51:11,861 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-12-09 17:51:11,861 INFO L276 IsEmpty]: Start isEmpty. Operand 1135 states and 1377 transitions. [2018-12-09 17:51:11,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-12-09 17:51:11,863 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:51:11,863 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:51:11,863 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:51:11,863 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:51:11,863 INFO L82 PathProgramCache]: Analyzing trace with hash 1794890282, now seen corresponding path program 1 times [2018-12-09 17:51:11,863 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:51:11,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:51:11,865 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:51:11,865 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:51:11,865 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:51:11,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:51:11,955 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-09 17:51:11,955 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:51:11,955 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:51:11,955 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 88 with the following transitions: [2018-12-09 17:51:11,955 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [672], [674], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:51:11,957 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:51:11,957 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:51:12,051 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:51:12,051 INFO L272 AbstractInterpreter]: Visited 41 different actions 58 times. Merged at 3 different actions 8 times. Widened at 1 different actions 1 times. Performed 1679 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1679 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:51:12,055 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:51:12,055 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:51:12,188 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:51:12,188 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:51:13,241 INFO L418 sIntCurrentIteration]: We unified 86 AI predicates to 86 [2018-12-09 17:51:13,241 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:51:13,241 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:51:13,241 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-12-09 17:51:13,241 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:51:13,241 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-09 17:51:13,242 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-09 17:51:13,242 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=121, Invalid=581, Unknown=0, NotChecked=0, Total=702 [2018-12-09 17:51:13,242 INFO L87 Difference]: Start difference. First operand 1135 states and 1377 transitions. Second operand 27 states. [2018-12-09 17:51:24,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:51:24,698 INFO L93 Difference]: Finished difference Result 2665 states and 3243 transitions. [2018-12-09 17:51:24,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-12-09 17:51:24,698 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 87 [2018-12-09 17:51:24,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:51:24,703 INFO L225 Difference]: With dead ends: 2665 [2018-12-09 17:51:24,703 INFO L226 Difference]: Without dead ends: 1877 [2018-12-09 17:51:24,705 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 88 GetRequests, 60 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 307 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=136, Invalid=676, Unknown=0, NotChecked=0, Total=812 [2018-12-09 17:51:24,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1877 states. [2018-12-09 17:51:24,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1877 to 1196. [2018-12-09 17:51:24,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1196 states. [2018-12-09 17:51:24,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1196 states to 1196 states and 1462 transitions. [2018-12-09 17:51:24,788 INFO L78 Accepts]: Start accepts. Automaton has 1196 states and 1462 transitions. Word has length 87 [2018-12-09 17:51:24,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:51:24,789 INFO L480 AbstractCegarLoop]: Abstraction has 1196 states and 1462 transitions. [2018-12-09 17:51:24,789 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-09 17:51:24,789 INFO L276 IsEmpty]: Start isEmpty. Operand 1196 states and 1462 transitions. [2018-12-09 17:51:24,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-12-09 17:51:24,790 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:51:24,790 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:51:24,790 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:51:24,790 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:51:24,790 INFO L82 PathProgramCache]: Analyzing trace with hash -1236221092, now seen corresponding path program 1 times [2018-12-09 17:51:24,790 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:51:24,791 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:51:24,792 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:51:24,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:51:24,792 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:51:24,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:51:24,856 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-09 17:51:24,856 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:51:24,856 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:51:24,856 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 89 with the following transitions: [2018-12-09 17:51:24,857 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:51:24,858 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:51:24,858 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:51:24,946 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:51:24,946 INFO L272 AbstractInterpreter]: Visited 42 different actions 55 times. Merged at 3 different actions 5 times. Never widened. Performed 1675 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1675 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:51:24,948 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:51:24,948 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:51:25,073 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:51:25,074 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:51:26,185 INFO L418 sIntCurrentIteration]: We unified 87 AI predicates to 87 [2018-12-09 17:51:26,186 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:51:26,186 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:51:26,186 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [28] imperfect sequences [10] total 36 [2018-12-09 17:51:26,186 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:51:26,186 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-12-09 17:51:26,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-12-09 17:51:26,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=125, Invalid=631, Unknown=0, NotChecked=0, Total=756 [2018-12-09 17:51:26,186 INFO L87 Difference]: Start difference. First operand 1196 states and 1462 transitions. Second operand 28 states. [2018-12-09 17:51:37,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:51:37,446 INFO L93 Difference]: Finished difference Result 2707 states and 3297 transitions. [2018-12-09 17:51:37,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-12-09 17:51:37,446 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 88 [2018-12-09 17:51:37,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:51:37,450 INFO L225 Difference]: With dead ends: 2707 [2018-12-09 17:51:37,450 INFO L226 Difference]: Without dead ends: 1919 [2018-12-09 17:51:37,451 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 89 GetRequests, 60 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 327 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=140, Invalid=730, Unknown=0, NotChecked=0, Total=870 [2018-12-09 17:51:37,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1919 states. [2018-12-09 17:51:37,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1919 to 1231. [2018-12-09 17:51:37,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1231 states. [2018-12-09 17:51:37,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1231 states to 1231 states and 1509 transitions. [2018-12-09 17:51:37,514 INFO L78 Accepts]: Start accepts. Automaton has 1231 states and 1509 transitions. Word has length 88 [2018-12-09 17:51:37,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:51:37,514 INFO L480 AbstractCegarLoop]: Abstraction has 1231 states and 1509 transitions. [2018-12-09 17:51:37,514 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-12-09 17:51:37,514 INFO L276 IsEmpty]: Start isEmpty. Operand 1231 states and 1509 transitions. [2018-12-09 17:51:37,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-12-09 17:51:37,515 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:51:37,515 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:51:37,515 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:51:37,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:51:37,516 INFO L82 PathProgramCache]: Analyzing trace with hash -1919946173, now seen corresponding path program 1 times [2018-12-09 17:51:37,516 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:51:37,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:51:37,517 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:51:37,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:51:37,517 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:51:37,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:51:37,590 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-09 17:51:37,590 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:51:37,590 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:51:37,590 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 90 with the following transitions: [2018-12-09 17:51:37,590 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:51:37,592 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:51:37,592 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:51:37,697 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:51:37,697 INFO L272 AbstractInterpreter]: Visited 43 different actions 56 times. Merged at 3 different actions 5 times. Never widened. Performed 1689 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1689 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:51:37,699 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:51:37,699 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:51:37,826 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:51:37,826 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:51:39,104 INFO L418 sIntCurrentIteration]: We unified 88 AI predicates to 88 [2018-12-09 17:51:39,104 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:51:39,104 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:51:39,105 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [29] imperfect sequences [10] total 37 [2018-12-09 17:51:39,105 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:51:39,105 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-12-09 17:51:39,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-12-09 17:51:39,105 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=129, Invalid=683, Unknown=0, NotChecked=0, Total=812 [2018-12-09 17:51:39,105 INFO L87 Difference]: Start difference. First operand 1231 states and 1509 transitions. Second operand 29 states. [2018-12-09 17:51:58,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:51:58,055 INFO L93 Difference]: Finished difference Result 2749 states and 3350 transitions. [2018-12-09 17:51:58,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-09 17:51:58,055 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 89 [2018-12-09 17:51:58,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:51:58,059 INFO L225 Difference]: With dead ends: 2749 [2018-12-09 17:51:58,059 INFO L226 Difference]: Without dead ends: 1961 [2018-12-09 17:51:58,061 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 90 GetRequests, 60 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 347 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=144, Invalid=786, Unknown=0, NotChecked=0, Total=930 [2018-12-09 17:51:58,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1961 states. [2018-12-09 17:51:58,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1961 to 1266. [2018-12-09 17:51:58,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1266 states. [2018-12-09 17:51:58,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1266 states to 1266 states and 1555 transitions. [2018-12-09 17:51:58,141 INFO L78 Accepts]: Start accepts. Automaton has 1266 states and 1555 transitions. Word has length 89 [2018-12-09 17:51:58,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:51:58,141 INFO L480 AbstractCegarLoop]: Abstraction has 1266 states and 1555 transitions. [2018-12-09 17:51:58,141 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-12-09 17:51:58,141 INFO L276 IsEmpty]: Start isEmpty. Operand 1266 states and 1555 transitions. [2018-12-09 17:51:58,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-12-09 17:51:58,143 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:51:58,143 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:51:58,143 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:51:58,143 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:51:58,143 INFO L82 PathProgramCache]: Analyzing trace with hash 1725251545, now seen corresponding path program 1 times [2018-12-09 17:51:58,143 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:51:58,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:51:58,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:51:58,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:51:58,145 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:51:58,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:51:58,222 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-09 17:51:58,222 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:51:58,222 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:51:58,222 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 93 with the following transitions: [2018-12-09 17:51:58,222 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [667], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-09 17:51:58,224 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:51:58,224 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:51:58,315 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:51:58,315 INFO L272 AbstractInterpreter]: Visited 44 different actions 56 times. Merged at 3 different actions 8 times. Widened at 1 different actions 1 times. Performed 1667 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1667 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:51:58,316 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:51:58,317 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:51:58,449 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:51:58,449 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:51:59,489 INFO L418 sIntCurrentIteration]: We unified 91 AI predicates to 91 [2018-12-09 17:51:59,489 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:51:59,489 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:51:59,490 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [9] total 34 [2018-12-09 17:51:59,490 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:51:59,490 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-09 17:51:59,490 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-09 17:51:59,490 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=579, Unknown=0, NotChecked=0, Total=702 [2018-12-09 17:51:59,490 INFO L87 Difference]: Start difference. First operand 1266 states and 1555 transitions. Second operand 27 states. [2018-12-09 17:52:12,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:52:12,588 INFO L93 Difference]: Finished difference Result 3103 states and 3795 transitions. [2018-12-09 17:52:12,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-12-09 17:52:12,588 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 92 [2018-12-09 17:52:12,589 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:52:12,592 INFO L225 Difference]: With dead ends: 3103 [2018-12-09 17:52:12,592 INFO L226 Difference]: Without dead ends: 2036 [2018-12-09 17:52:12,593 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 93 GetRequests, 65 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 308 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=138, Invalid=674, Unknown=0, NotChecked=0, Total=812 [2018-12-09 17:52:12,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2036 states. [2018-12-09 17:52:12,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2036 to 1301. [2018-12-09 17:52:12,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1301 states. [2018-12-09 17:52:12,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1301 states to 1301 states and 1601 transitions. [2018-12-09 17:52:12,672 INFO L78 Accepts]: Start accepts. Automaton has 1301 states and 1601 transitions. Word has length 92 [2018-12-09 17:52:12,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:52:12,672 INFO L480 AbstractCegarLoop]: Abstraction has 1301 states and 1601 transitions. [2018-12-09 17:52:12,672 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-09 17:52:12,672 INFO L276 IsEmpty]: Start isEmpty. Operand 1301 states and 1601 transitions. [2018-12-09 17:52:12,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-12-09 17:52:12,673 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:52:12,673 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:52:12,673 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:52:12,674 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:52:12,674 INFO L82 PathProgramCache]: Analyzing trace with hash 2108498356, now seen corresponding path program 1 times [2018-12-09 17:52:12,674 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:52:12,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:52:12,675 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:52:12,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:52:12,675 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:52:12,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:52:12,744 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-09 17:52:12,744 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:52:12,744 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:52:12,745 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 94 with the following transitions: [2018-12-09 17:52:12,745 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [672], [674], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-09 17:52:12,746 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:52:12,746 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:52:12,846 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:52:12,846 INFO L272 AbstractInterpreter]: Visited 47 different actions 64 times. Merged at 3 different actions 8 times. Widened at 1 different actions 1 times. Performed 1853 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1853 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:52:12,851 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:52:12,851 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:52:12,981 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:52:12,981 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:52:14,116 INFO L418 sIntCurrentIteration]: We unified 92 AI predicates to 92 [2018-12-09 17:52:14,117 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:52:14,117 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:52:14,117 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [28] imperfect sequences [10] total 36 [2018-12-09 17:52:14,117 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:52:14,117 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-12-09 17:52:14,117 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-12-09 17:52:14,118 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=629, Unknown=0, NotChecked=0, Total=756 [2018-12-09 17:52:14,118 INFO L87 Difference]: Start difference. First operand 1301 states and 1601 transitions. Second operand 28 states. [2018-12-09 17:52:28,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:52:28,166 INFO L93 Difference]: Finished difference Result 2863 states and 3500 transitions. [2018-12-09 17:52:28,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-12-09 17:52:28,166 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 93 [2018-12-09 17:52:28,166 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:52:28,170 INFO L225 Difference]: With dead ends: 2863 [2018-12-09 17:52:28,170 INFO L226 Difference]: Without dead ends: 2075 [2018-12-09 17:52:28,171 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 94 GetRequests, 65 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 329 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=142, Invalid=728, Unknown=0, NotChecked=0, Total=870 [2018-12-09 17:52:28,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2075 states. [2018-12-09 17:52:28,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2075 to 1362. [2018-12-09 17:52:28,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1362 states. [2018-12-09 17:52:28,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1362 states to 1362 states and 1686 transitions. [2018-12-09 17:52:28,264 INFO L78 Accepts]: Start accepts. Automaton has 1362 states and 1686 transitions. Word has length 93 [2018-12-09 17:52:28,264 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:52:28,264 INFO L480 AbstractCegarLoop]: Abstraction has 1362 states and 1686 transitions. [2018-12-09 17:52:28,264 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-12-09 17:52:28,264 INFO L276 IsEmpty]: Start isEmpty. Operand 1362 states and 1686 transitions. [2018-12-09 17:52:28,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-12-09 17:52:28,266 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:52:28,267 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:52:28,267 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:52:28,267 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:52:28,267 INFO L82 PathProgramCache]: Analyzing trace with hash -104305390, now seen corresponding path program 1 times [2018-12-09 17:52:28,267 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:52:28,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:52:28,269 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:52:28,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:52:28,269 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:52:28,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:52:28,352 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-09 17:52:28,352 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:52:28,353 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:52:28,353 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 95 with the following transitions: [2018-12-09 17:52:28,353 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-09 17:52:28,354 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:52:28,354 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:52:28,449 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:52:28,449 INFO L272 AbstractInterpreter]: Visited 48 different actions 61 times. Merged at 3 different actions 5 times. Never widened. Performed 1849 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1849 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:52:28,450 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:52:28,450 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:52:28,581 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:52:28,582 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:52:29,817 INFO L418 sIntCurrentIteration]: We unified 93 AI predicates to 93 [2018-12-09 17:52:29,817 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:52:29,818 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:52:29,818 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [29] imperfect sequences [10] total 37 [2018-12-09 17:52:29,818 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:52:29,818 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-12-09 17:52:29,818 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-12-09 17:52:29,818 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=681, Unknown=0, NotChecked=0, Total=812 [2018-12-09 17:52:29,818 INFO L87 Difference]: Start difference. First operand 1362 states and 1686 transitions. Second operand 29 states. [2018-12-09 17:52:41,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:52:41,224 INFO L93 Difference]: Finished difference Result 2905 states and 3554 transitions. [2018-12-09 17:52:41,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-09 17:52:41,224 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 94 [2018-12-09 17:52:41,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:52:41,227 INFO L225 Difference]: With dead ends: 2905 [2018-12-09 17:52:41,227 INFO L226 Difference]: Without dead ends: 2117 [2018-12-09 17:52:41,228 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 95 GetRequests, 65 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 350 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=146, Invalid=784, Unknown=0, NotChecked=0, Total=930 [2018-12-09 17:52:41,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2117 states. [2018-12-09 17:52:41,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2117 to 1397. [2018-12-09 17:52:41,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1397 states. [2018-12-09 17:52:41,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1397 states to 1397 states and 1733 transitions. [2018-12-09 17:52:41,331 INFO L78 Accepts]: Start accepts. Automaton has 1397 states and 1733 transitions. Word has length 94 [2018-12-09 17:52:41,331 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:52:41,332 INFO L480 AbstractCegarLoop]: Abstraction has 1397 states and 1733 transitions. [2018-12-09 17:52:41,332 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-12-09 17:52:41,332 INFO L276 IsEmpty]: Start isEmpty. Operand 1397 states and 1733 transitions. [2018-12-09 17:52:41,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-12-09 17:52:41,334 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:52:41,334 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:52:41,334 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:52:41,334 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:52:41,334 INFO L82 PathProgramCache]: Analyzing trace with hash -1190297779, now seen corresponding path program 1 times [2018-12-09 17:52:41,334 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:52:41,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:52:41,336 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:52:41,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:52:41,336 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:52:41,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:52:41,425 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-12-09 17:52:41,425 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:52:41,425 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:52:41,425 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 96 with the following transitions: [2018-12-09 17:52:41,425 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-09 17:52:41,426 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:52:41,426 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:52:41,521 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:52:41,521 INFO L272 AbstractInterpreter]: Visited 49 different actions 62 times. Merged at 3 different actions 5 times. Never widened. Performed 1863 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1863 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:52:41,523 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:52:41,523 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:52:41,657 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:52:41,657 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:52:43,014 INFO L418 sIntCurrentIteration]: We unified 94 AI predicates to 94 [2018-12-09 17:52:43,014 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:52:43,015 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:52:43,015 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [30] imperfect sequences [10] total 38 [2018-12-09 17:52:43,015 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:52:43,015 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-12-09 17:52:43,015 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-12-09 17:52:43,015 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=735, Unknown=0, NotChecked=0, Total=870 [2018-12-09 17:52:43,015 INFO L87 Difference]: Start difference. First operand 1397 states and 1733 transitions. Second operand 30 states. [2018-12-09 17:52:56,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:52:56,861 INFO L93 Difference]: Finished difference Result 2947 states and 3607 transitions. [2018-12-09 17:52:56,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-09 17:52:56,861 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 95 [2018-12-09 17:52:56,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:52:56,865 INFO L225 Difference]: With dead ends: 2947 [2018-12-09 17:52:56,865 INFO L226 Difference]: Without dead ends: 2159 [2018-12-09 17:52:56,866 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 96 GetRequests, 65 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 371 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=150, Invalid=842, Unknown=0, NotChecked=0, Total=992 [2018-12-09 17:52:56,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2159 states. [2018-12-09 17:52:56,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2159 to 1432. [2018-12-09 17:52:56,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1432 states. [2018-12-09 17:52:56,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1432 states to 1432 states and 1779 transitions. [2018-12-09 17:52:56,967 INFO L78 Accepts]: Start accepts. Automaton has 1432 states and 1779 transitions. Word has length 95 [2018-12-09 17:52:56,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:52:56,968 INFO L480 AbstractCegarLoop]: Abstraction has 1432 states and 1779 transitions. [2018-12-09 17:52:56,968 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-12-09 17:52:56,968 INFO L276 IsEmpty]: Start isEmpty. Operand 1432 states and 1779 transitions. [2018-12-09 17:52:56,969 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-12-09 17:52:56,969 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:52:56,969 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:52:56,969 INFO L423 AbstractCegarLoop]: === Iteration 16 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:52:56,969 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:52:56,970 INFO L82 PathProgramCache]: Analyzing trace with hash 825686790, now seen corresponding path program 1 times [2018-12-09 17:52:56,970 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:52:56,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:52:56,971 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:52:56,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:52:56,971 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:52:56,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:52:57,009 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-09 17:52:57,010 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:52:57,010 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 17:52:57,010 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:52:57,010 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 17:52:57,010 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 17:52:57,010 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:52:57,011 INFO L87 Difference]: Start difference. First operand 1432 states and 1779 transitions. Second operand 3 states. [2018-12-09 17:52:57,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:52:57,156 INFO L93 Difference]: Finished difference Result 2763 states and 3432 transitions. [2018-12-09 17:52:57,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 17:52:57,156 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 98 [2018-12-09 17:52:57,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:52:57,159 INFO L225 Difference]: With dead ends: 2763 [2018-12-09 17:52:57,159 INFO L226 Difference]: Without dead ends: 1696 [2018-12-09 17:52:57,160 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:52:57,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1696 states. [2018-12-09 17:52:57,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1696 to 1693. [2018-12-09 17:52:57,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1693 states. [2018-12-09 17:52:57,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1693 states to 1693 states and 2110 transitions. [2018-12-09 17:52:57,265 INFO L78 Accepts]: Start accepts. Automaton has 1693 states and 2110 transitions. Word has length 98 [2018-12-09 17:52:57,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:52:57,265 INFO L480 AbstractCegarLoop]: Abstraction has 1693 states and 2110 transitions. [2018-12-09 17:52:57,265 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 17:52:57,265 INFO L276 IsEmpty]: Start isEmpty. Operand 1693 states and 2110 transitions. [2018-12-09 17:52:57,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-12-09 17:52:57,266 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:52:57,266 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:52:57,266 INFO L423 AbstractCegarLoop]: === Iteration 17 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:52:57,266 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:52:57,266 INFO L82 PathProgramCache]: Analyzing trace with hash 782895118, now seen corresponding path program 1 times [2018-12-09 17:52:57,266 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:52:57,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:52:57,267 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:52:57,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:52:57,267 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:52:57,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:52:57,332 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 17:52:57,332 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:52:57,332 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:52:57,333 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 105 with the following transitions: [2018-12-09 17:52:57,333 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [672], [674], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:52:57,334 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:52:57,334 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:52:57,435 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:52:57,435 INFO L272 AbstractInterpreter]: Visited 46 different actions 70 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1875 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1875 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:52:57,438 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:52:57,439 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:52:57,596 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:52:57,596 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:52:58,983 INFO L418 sIntCurrentIteration]: We unified 103 AI predicates to 103 [2018-12-09 17:52:58,983 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:52:58,983 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:52:58,983 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-12-09 17:52:58,983 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:52:58,984 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-12-09 17:52:58,984 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-12-09 17:52:58,984 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=786, Unknown=0, NotChecked=0, Total=930 [2018-12-09 17:52:58,984 INFO L87 Difference]: Start difference. First operand 1693 states and 2110 transitions. Second operand 31 states. [2018-12-09 17:53:17,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:53:17,291 INFO L93 Difference]: Finished difference Result 3592 states and 4427 transitions. [2018-12-09 17:53:17,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-09 17:53:17,291 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 104 [2018-12-09 17:53:17,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:53:17,295 INFO L225 Difference]: With dead ends: 3592 [2018-12-09 17:53:17,295 INFO L226 Difference]: Without dead ends: 2597 [2018-12-09 17:53:17,296 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 105 GetRequests, 73 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 404 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=159, Invalid=897, Unknown=0, NotChecked=0, Total=1056 [2018-12-09 17:53:17,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2597 states. [2018-12-09 17:53:17,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2597 to 1737. [2018-12-09 17:53:17,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1737 states. [2018-12-09 17:53:17,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1737 states to 1737 states and 2167 transitions. [2018-12-09 17:53:17,423 INFO L78 Accepts]: Start accepts. Automaton has 1737 states and 2167 transitions. Word has length 104 [2018-12-09 17:53:17,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:53:17,423 INFO L480 AbstractCegarLoop]: Abstraction has 1737 states and 2167 transitions. [2018-12-09 17:53:17,423 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-12-09 17:53:17,423 INFO L276 IsEmpty]: Start isEmpty. Operand 1737 states and 2167 transitions. [2018-12-09 17:53:17,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-12-09 17:53:17,424 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:53:17,424 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:53:17,424 INFO L423 AbstractCegarLoop]: === Iteration 18 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:53:17,424 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:53:17,424 INFO L82 PathProgramCache]: Analyzing trace with hash -149649163, now seen corresponding path program 1 times [2018-12-09 17:53:17,424 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:53:17,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:53:17,425 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:53:17,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:53:17,425 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:53:17,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:53:17,495 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 17:53:17,495 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:53:17,495 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:53:17,496 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 106 with the following transitions: [2018-12-09 17:53:17,496 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [672], [674], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:53:17,497 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:53:17,497 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:53:17,597 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:53:17,597 INFO L272 AbstractInterpreter]: Visited 47 different actions 71 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1889 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1889 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:53:17,598 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:53:17,598 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:53:17,758 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:53:17,759 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:53:19,331 INFO L418 sIntCurrentIteration]: We unified 104 AI predicates to 104 [2018-12-09 17:53:19,331 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:53:19,331 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:53:19,331 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [10] total 40 [2018-12-09 17:53:19,331 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:53:19,331 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-09 17:53:19,332 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-09 17:53:19,332 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=844, Unknown=0, NotChecked=0, Total=992 [2018-12-09 17:53:19,332 INFO L87 Difference]: Start difference. First operand 1737 states and 2167 transitions. Second operand 32 states. [2018-12-09 17:53:29,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:53:29,504 INFO L93 Difference]: Finished difference Result 3643 states and 4491 transitions. [2018-12-09 17:53:29,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-09 17:53:29,504 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 105 [2018-12-09 17:53:29,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:53:29,508 INFO L225 Difference]: With dead ends: 3643 [2018-12-09 17:53:29,508 INFO L226 Difference]: Without dead ends: 2648 [2018-12-09 17:53:29,510 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 106 GetRequests, 73 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 424 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=163, Invalid=959, Unknown=0, NotChecked=0, Total=1122 [2018-12-09 17:53:29,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2648 states. [2018-12-09 17:53:29,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2648 to 1781. [2018-12-09 17:53:29,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1781 states. [2018-12-09 17:53:29,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1781 states to 1781 states and 2224 transitions. [2018-12-09 17:53:29,645 INFO L78 Accepts]: Start accepts. Automaton has 1781 states and 2224 transitions. Word has length 105 [2018-12-09 17:53:29,645 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:53:29,645 INFO L480 AbstractCegarLoop]: Abstraction has 1781 states and 2224 transitions. [2018-12-09 17:53:29,645 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-09 17:53:29,645 INFO L276 IsEmpty]: Start isEmpty. Operand 1781 states and 2224 transitions. [2018-12-09 17:53:29,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-12-09 17:53:29,646 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:53:29,646 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:53:29,646 INFO L423 AbstractCegarLoop]: === Iteration 19 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:53:29,646 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:53:29,647 INFO L82 PathProgramCache]: Analyzing trace with hash -548505771, now seen corresponding path program 1 times [2018-12-09 17:53:29,647 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:53:29,647 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:53:29,647 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:53:29,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:53:29,648 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:53:29,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:53:29,732 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 17:53:29,732 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:53:29,732 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:53:29,732 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 103 with the following transitions: [2018-12-09 17:53:29,732 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [667], [669], [672], [674], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1001], [1002], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:53:29,734 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:53:29,734 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:53:29,819 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:53:29,819 INFO L272 AbstractInterpreter]: Visited 43 different actions 58 times. Merged at 5 different actions 7 times. Never widened. Performed 1657 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1657 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:53:29,822 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:53:29,822 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:53:29,972 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:53:29,972 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:53:31,328 INFO L418 sIntCurrentIteration]: We unified 101 AI predicates to 101 [2018-12-09 17:53:31,328 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:53:31,328 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:53:31,328 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [30] imperfect sequences [10] total 38 [2018-12-09 17:53:31,328 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:53:31,329 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-12-09 17:53:31,329 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-12-09 17:53:31,329 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=730, Unknown=0, NotChecked=0, Total=870 [2018-12-09 17:53:31,329 INFO L87 Difference]: Start difference. First operand 1781 states and 2224 transitions. Second operand 30 states. [2018-12-09 17:53:48,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:53:48,741 INFO L93 Difference]: Finished difference Result 3694 states and 4554 transitions. [2018-12-09 17:53:48,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-12-09 17:53:48,741 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 102 [2018-12-09 17:53:48,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:53:48,745 INFO L225 Difference]: With dead ends: 3694 [2018-12-09 17:53:48,745 INFO L226 Difference]: Without dead ends: 2699 [2018-12-09 17:53:48,747 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 103 GetRequests, 72 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 389 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=155, Invalid=837, Unknown=0, NotChecked=0, Total=992 [2018-12-09 17:53:48,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2699 states. [2018-12-09 17:53:48,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2699 to 1686. [2018-12-09 17:53:48,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1686 states. [2018-12-09 17:53:48,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1686 states to 1686 states and 2091 transitions. [2018-12-09 17:53:48,882 INFO L78 Accepts]: Start accepts. Automaton has 1686 states and 2091 transitions. Word has length 102 [2018-12-09 17:53:48,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:53:48,882 INFO L480 AbstractCegarLoop]: Abstraction has 1686 states and 2091 transitions. [2018-12-09 17:53:48,882 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-12-09 17:53:48,882 INFO L276 IsEmpty]: Start isEmpty. Operand 1686 states and 2091 transitions. [2018-12-09 17:53:48,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-12-09 17:53:48,883 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:53:48,883 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:53:48,883 INFO L423 AbstractCegarLoop]: === Iteration 20 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:53:48,883 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:53:48,883 INFO L82 PathProgramCache]: Analyzing trace with hash 1995317747, now seen corresponding path program 1 times [2018-12-09 17:53:48,883 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:53:48,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:53:48,884 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:53:48,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:53:48,884 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:53:48,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:53:48,914 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-12-09 17:53:48,914 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:53:48,914 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 17:53:48,914 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:53:48,914 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 17:53:48,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 17:53:48,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:53:48,915 INFO L87 Difference]: Start difference. First operand 1686 states and 2091 transitions. Second operand 3 states. [2018-12-09 17:53:49,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:53:49,046 INFO L93 Difference]: Finished difference Result 3017 states and 3718 transitions. [2018-12-09 17:53:49,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 17:53:49,046 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 107 [2018-12-09 17:53:49,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:53:49,050 INFO L225 Difference]: With dead ends: 3017 [2018-12-09 17:53:49,050 INFO L226 Difference]: Without dead ends: 1680 [2018-12-09 17:53:49,052 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:53:49,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1680 states. [2018-12-09 17:53:49,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1680 to 1614. [2018-12-09 17:53:49,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1614 states. [2018-12-09 17:53:49,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1614 states to 1614 states and 2010 transitions. [2018-12-09 17:53:49,179 INFO L78 Accepts]: Start accepts. Automaton has 1614 states and 2010 transitions. Word has length 107 [2018-12-09 17:53:49,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:53:49,179 INFO L480 AbstractCegarLoop]: Abstraction has 1614 states and 2010 transitions. [2018-12-09 17:53:49,179 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 17:53:49,179 INFO L276 IsEmpty]: Start isEmpty. Operand 1614 states and 2010 transitions. [2018-12-09 17:53:49,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-12-09 17:53:49,180 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:53:49,180 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:53:49,180 INFO L423 AbstractCegarLoop]: === Iteration 21 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:53:49,180 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:53:49,180 INFO L82 PathProgramCache]: Analyzing trace with hash -1387401743, now seen corresponding path program 1 times [2018-12-09 17:53:49,180 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:53:49,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:53:49,181 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:53:49,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:53:49,182 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:53:49,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:53:49,239 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-12-09 17:53:49,239 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:53:49,239 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:53:49,239 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 107 with the following transitions: [2018-12-09 17:53:49,239 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [669], [676], [679], [681], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1003], [1004], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:53:49,240 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:53:49,240 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:53:49,340 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:53:49,341 INFO L272 AbstractInterpreter]: Visited 47 different actions 71 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1889 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1889 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:53:49,342 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:53:49,342 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:53:49,506 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:53:49,506 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:53:51,089 INFO L418 sIntCurrentIteration]: We unified 105 AI predicates to 105 [2018-12-09 17:53:51,089 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:53:51,089 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:53:51,089 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [10] total 40 [2018-12-09 17:53:51,089 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:53:51,089 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-09 17:53:51,090 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-09 17:53:51,090 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=844, Unknown=0, NotChecked=0, Total=992 [2018-12-09 17:53:51,090 INFO L87 Difference]: Start difference. First operand 1614 states and 2010 transitions. Second operand 32 states. [2018-12-09 17:54:05,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:54:05,178 INFO L93 Difference]: Finished difference Result 3527 states and 4367 transitions. [2018-12-09 17:54:05,178 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-09 17:54:05,179 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 106 [2018-12-09 17:54:05,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:54:05,182 INFO L225 Difference]: With dead ends: 3527 [2018-12-09 17:54:05,182 INFO L226 Difference]: Without dead ends: 2580 [2018-12-09 17:54:05,184 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 107 GetRequests, 74 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 424 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=163, Invalid=959, Unknown=0, NotChecked=0, Total=1122 [2018-12-09 17:54:05,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2580 states. [2018-12-09 17:54:05,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2580 to 1754. [2018-12-09 17:54:05,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1754 states. [2018-12-09 17:54:05,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1754 states to 1754 states and 2201 transitions. [2018-12-09 17:54:05,344 INFO L78 Accepts]: Start accepts. Automaton has 1754 states and 2201 transitions. Word has length 106 [2018-12-09 17:54:05,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:54:05,344 INFO L480 AbstractCegarLoop]: Abstraction has 1754 states and 2201 transitions. [2018-12-09 17:54:05,344 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-09 17:54:05,344 INFO L276 IsEmpty]: Start isEmpty. Operand 1754 states and 2201 transitions. [2018-12-09 17:54:05,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2018-12-09 17:54:05,345 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:54:05,345 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:54:05,345 INFO L423 AbstractCegarLoop]: === Iteration 22 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:54:05,345 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:54:05,345 INFO L82 PathProgramCache]: Analyzing trace with hash -867054703, now seen corresponding path program 1 times [2018-12-09 17:54:05,345 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:54:05,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:54:05,346 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:54:05,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:54:05,346 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:54:05,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:54:05,407 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 17:54:05,407 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:54:05,407 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:54:05,408 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 104 with the following transitions: [2018-12-09 17:54:05,408 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [667], [669], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:54:05,408 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:54:05,408 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:54:05,499 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:54:05,499 INFO L272 AbstractInterpreter]: Visited 44 different actions 63 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1713 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1713 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:54:05,501 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:54:05,501 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:54:05,654 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:54:05,654 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:54:07,090 INFO L418 sIntCurrentIteration]: We unified 102 AI predicates to 102 [2018-12-09 17:54:07,090 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:54:07,090 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:54:07,090 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-12-09 17:54:07,090 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:54:07,091 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-12-09 17:54:07,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-12-09 17:54:07,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=786, Unknown=0, NotChecked=0, Total=930 [2018-12-09 17:54:07,091 INFO L87 Difference]: Start difference. First operand 1754 states and 2201 transitions. Second operand 31 states. [2018-12-09 17:54:16,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:54:16,868 INFO L93 Difference]: Finished difference Result 3613 states and 4477 transitions. [2018-12-09 17:54:16,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-09 17:54:16,869 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 103 [2018-12-09 17:54:16,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:54:16,873 INFO L225 Difference]: With dead ends: 3613 [2018-12-09 17:54:16,873 INFO L226 Difference]: Without dead ends: 2666 [2018-12-09 17:54:16,874 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 104 GetRequests, 72 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 414 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=159, Invalid=897, Unknown=0, NotChecked=0, Total=1056 [2018-12-09 17:54:16,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2666 states. [2018-12-09 17:54:17,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2666 to 1833. [2018-12-09 17:54:17,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1833 states. [2018-12-09 17:54:17,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1833 states to 1833 states and 2304 transitions. [2018-12-09 17:54:17,060 INFO L78 Accepts]: Start accepts. Automaton has 1833 states and 2304 transitions. Word has length 103 [2018-12-09 17:54:17,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:54:17,060 INFO L480 AbstractCegarLoop]: Abstraction has 1833 states and 2304 transitions. [2018-12-09 17:54:17,060 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-12-09 17:54:17,060 INFO L276 IsEmpty]: Start isEmpty. Operand 1833 states and 2304 transitions. [2018-12-09 17:54:17,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-12-09 17:54:17,062 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:54:17,062 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:54:17,062 INFO L423 AbstractCegarLoop]: === Iteration 23 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:54:17,062 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:54:17,062 INFO L82 PathProgramCache]: Analyzing trace with hash 934277294, now seen corresponding path program 1 times [2018-12-09 17:54:17,062 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:54:17,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:54:17,063 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:54:17,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:54:17,064 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:54:17,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:54:17,118 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 17:54:17,118 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:54:17,118 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:54:17,118 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 105 with the following transitions: [2018-12-09 17:54:17,118 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [637], [662], [665], [667], [669], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:54:17,120 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:54:17,120 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:54:17,213 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:54:17,213 INFO L272 AbstractInterpreter]: Visited 45 different actions 64 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1727 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1727 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:54:17,215 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:54:17,215 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:54:17,372 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:54:17,372 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:54:18,962 INFO L418 sIntCurrentIteration]: We unified 103 AI predicates to 103 [2018-12-09 17:54:18,962 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:54:18,962 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:54:18,962 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [10] total 40 [2018-12-09 17:54:18,962 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:54:18,962 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-09 17:54:18,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-09 17:54:18,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=844, Unknown=0, NotChecked=0, Total=992 [2018-12-09 17:54:18,963 INFO L87 Difference]: Start difference. First operand 1833 states and 2304 transitions. Second operand 32 states. [2018-12-09 17:54:35,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:54:35,471 INFO L93 Difference]: Finished difference Result 3664 states and 4539 transitions. [2018-12-09 17:54:35,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-09 17:54:35,471 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 104 [2018-12-09 17:54:35,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:54:35,475 INFO L225 Difference]: With dead ends: 3664 [2018-12-09 17:54:35,475 INFO L226 Difference]: Without dead ends: 2717 [2018-12-09 17:54:35,476 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 105 GetRequests, 72 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 439 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=163, Invalid=959, Unknown=0, NotChecked=0, Total=1122 [2018-12-09 17:54:35,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2717 states. [2018-12-09 17:54:35,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2717 to 1877. [2018-12-09 17:54:35,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1877 states. [2018-12-09 17:54:35,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1877 states to 1877 states and 2359 transitions. [2018-12-09 17:54:35,675 INFO L78 Accepts]: Start accepts. Automaton has 1877 states and 2359 transitions. Word has length 104 [2018-12-09 17:54:35,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:54:35,675 INFO L480 AbstractCegarLoop]: Abstraction has 1877 states and 2359 transitions. [2018-12-09 17:54:35,676 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-09 17:54:35,676 INFO L276 IsEmpty]: Start isEmpty. Operand 1877 states and 2359 transitions. [2018-12-09 17:54:35,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-12-09 17:54:35,677 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:54:35,677 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:54:35,677 INFO L423 AbstractCegarLoop]: === Iteration 24 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:54:35,677 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:54:35,677 INFO L82 PathProgramCache]: Analyzing trace with hash 27781771, now seen corresponding path program 1 times [2018-12-09 17:54:35,677 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:54:35,678 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:54:35,678 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:54:35,678 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:54:35,678 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:54:35,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:54:35,736 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 17:54:35,736 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:54:35,736 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:54:35,736 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 109 with the following transitions: [2018-12-09 17:54:35,737 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [667], [669], [672], [674], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1001], [1002], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-09 17:54:35,737 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:54:35,737 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:54:35,856 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:54:35,857 INFO L272 AbstractInterpreter]: Visited 49 different actions 68 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1861 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1861 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:54:35,858 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:54:35,858 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:54:36,016 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:54:36,016 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:54:37,357 INFO L418 sIntCurrentIteration]: We unified 107 AI predicates to 107 [2018-12-09 17:54:37,358 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:54:37,358 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:54:37,358 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [31] imperfect sequences [10] total 39 [2018-12-09 17:54:37,358 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:54:37,358 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-12-09 17:54:37,358 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-12-09 17:54:37,358 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=146, Invalid=784, Unknown=0, NotChecked=0, Total=930 [2018-12-09 17:54:37,359 INFO L87 Difference]: Start difference. First operand 1877 states and 2359 transitions. Second operand 31 states. [2018-12-09 17:54:56,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:54:56,937 INFO L93 Difference]: Finished difference Result 3706 states and 4595 transitions. [2018-12-09 17:54:56,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-09 17:54:56,937 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 108 [2018-12-09 17:54:56,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:54:56,941 INFO L225 Difference]: With dead ends: 3706 [2018-12-09 17:54:56,941 INFO L226 Difference]: Without dead ends: 2759 [2018-12-09 17:54:56,942 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 109 GetRequests, 77 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 414 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=161, Invalid=895, Unknown=0, NotChecked=0, Total=1056 [2018-12-09 17:54:56,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2759 states. [2018-12-09 17:54:57,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2759 to 1927. [2018-12-09 17:54:57,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1927 states. [2018-12-09 17:54:57,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1927 states to 1927 states and 2422 transitions. [2018-12-09 17:54:57,157 INFO L78 Accepts]: Start accepts. Automaton has 1927 states and 2422 transitions. Word has length 108 [2018-12-09 17:54:57,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:54:57,157 INFO L480 AbstractCegarLoop]: Abstraction has 1927 states and 2422 transitions. [2018-12-09 17:54:57,157 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-12-09 17:54:57,157 INFO L276 IsEmpty]: Start isEmpty. Operand 1927 states and 2422 transitions. [2018-12-09 17:54:57,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-12-09 17:54:57,159 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:54:57,159 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:54:57,159 INFO L423 AbstractCegarLoop]: === Iteration 25 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:54:57,159 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:54:57,159 INFO L82 PathProgramCache]: Analyzing trace with hash 1387189799, now seen corresponding path program 1 times [2018-12-09 17:54:57,159 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:54:57,160 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:54:57,160 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:54:57,160 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:54:57,160 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:54:57,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:54:57,210 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-12-09 17:54:57,210 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:54:57,210 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:54:57,210 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 113 with the following transitions: [2018-12-09 17:54:57,210 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [676], [679], [681], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1003], [1004], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-09 17:54:57,211 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:54:57,211 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:54:57,314 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:54:57,314 INFO L272 AbstractInterpreter]: Visited 53 different actions 77 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 2063 root evaluator evaluations with a maximum evaluation depth of 10. Performed 2063 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:54:57,316 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:54:57,316 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:54:57,487 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:54:57,488 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:54:59,334 INFO L418 sIntCurrentIteration]: We unified 111 AI predicates to 111 [2018-12-09 17:54:59,334 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:54:59,334 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:54:59,334 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [10] total 41 [2018-12-09 17:54:59,334 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:54:59,335 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-12-09 17:54:59,335 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-12-09 17:54:59,335 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-12-09 17:54:59,335 INFO L87 Difference]: Start difference. First operand 1927 states and 2422 transitions. Second operand 33 states. [2018-12-09 17:55:17,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:55:17,674 INFO L93 Difference]: Finished difference Result 3750 states and 4652 transitions. [2018-12-09 17:55:17,674 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-12-09 17:55:17,674 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 112 [2018-12-09 17:55:17,674 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:55:17,677 INFO L225 Difference]: With dead ends: 3750 [2018-12-09 17:55:17,678 INFO L226 Difference]: Without dead ends: 2803 [2018-12-09 17:55:17,679 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 113 GetRequests, 79 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 451 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=169, Invalid=1021, Unknown=0, NotChecked=0, Total=1190 [2018-12-09 17:55:17,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2803 states. [2018-12-09 17:55:17,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2803 to 1971. [2018-12-09 17:55:17,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1971 states. [2018-12-09 17:55:17,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1971 states to 1971 states and 2479 transitions. [2018-12-09 17:55:17,908 INFO L78 Accepts]: Start accepts. Automaton has 1971 states and 2479 transitions. Word has length 112 [2018-12-09 17:55:17,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:55:17,908 INFO L480 AbstractCegarLoop]: Abstraction has 1971 states and 2479 transitions. [2018-12-09 17:55:17,908 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-12-09 17:55:17,908 INFO L276 IsEmpty]: Start isEmpty. Operand 1971 states and 2479 transitions. [2018-12-09 17:55:17,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-12-09 17:55:17,909 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:55:17,909 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:55:17,909 INFO L423 AbstractCegarLoop]: === Iteration 26 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:55:17,910 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:55:17,910 INFO L82 PathProgramCache]: Analyzing trace with hash -407277920, now seen corresponding path program 1 times [2018-12-09 17:55:17,910 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:55:17,910 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:55:17,910 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:55:17,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:55:17,911 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:55:17,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:55:17,967 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 17:55:17,967 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:55:17,967 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:55:17,967 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 111 with the following transitions: [2018-12-09 17:55:17,967 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [672], [674], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-09 17:55:17,968 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:55:17,968 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:55:18,070 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:55:18,070 INFO L272 AbstractInterpreter]: Visited 52 different actions 76 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 2049 root evaluator evaluations with a maximum evaluation depth of 10. Performed 2049 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:55:18,075 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:55:18,075 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:55:18,240 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:55:18,240 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:55:19,741 INFO L418 sIntCurrentIteration]: We unified 109 AI predicates to 109 [2018-12-09 17:55:19,741 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:55:19,741 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:55:19,741 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [10] total 40 [2018-12-09 17:55:19,741 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:55:19,742 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-09 17:55:19,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-09 17:55:19,742 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=150, Invalid=842, Unknown=0, NotChecked=0, Total=992 [2018-12-09 17:55:19,742 INFO L87 Difference]: Start difference. First operand 1971 states and 2479 transitions. Second operand 32 states. [2018-12-09 17:55:40,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:55:40,108 INFO L93 Difference]: Finished difference Result 3810 states and 4725 transitions. [2018-12-09 17:55:40,108 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-09 17:55:40,109 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 110 [2018-12-09 17:55:40,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:55:40,112 INFO L225 Difference]: With dead ends: 3810 [2018-12-09 17:55:40,112 INFO L226 Difference]: Without dead ends: 2863 [2018-12-09 17:55:40,113 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 111 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 435 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=165, Invalid=957, Unknown=0, NotChecked=0, Total=1122 [2018-12-09 17:55:40,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2863 states. [2018-12-09 17:55:40,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2863 to 2017. [2018-12-09 17:55:40,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2017 states. [2018-12-09 17:55:40,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2017 states to 2017 states and 2538 transitions. [2018-12-09 17:55:40,357 INFO L78 Accepts]: Start accepts. Automaton has 2017 states and 2538 transitions. Word has length 110 [2018-12-09 17:55:40,358 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:55:40,358 INFO L480 AbstractCegarLoop]: Abstraction has 2017 states and 2538 transitions. [2018-12-09 17:55:40,358 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-09 17:55:40,358 INFO L276 IsEmpty]: Start isEmpty. Operand 2017 states and 2538 transitions. [2018-12-09 17:55:40,359 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-12-09 17:55:40,359 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:55:40,359 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:55:40,359 INFO L423 AbstractCegarLoop]: === Iteration 27 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:55:40,359 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:55:40,359 INFO L82 PathProgramCache]: Analyzing trace with hash -182010085, now seen corresponding path program 1 times [2018-12-09 17:55:40,359 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:55:40,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:55:40,360 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:55:40,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:55:40,360 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:55:40,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:55:40,410 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 17:55:40,410 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:55:40,410 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:55:40,410 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 110 with the following transitions: [2018-12-09 17:55:40,410 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [667], [669], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-09 17:55:40,411 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:55:40,411 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:55:40,502 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:55:40,502 INFO L272 AbstractInterpreter]: Visited 50 different actions 65 times. Merged at 5 different actions 7 times. Never widened. Performed 1857 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1857 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:55:40,507 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:55:40,507 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:55:40,669 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:55:40,669 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:55:42,235 INFO L418 sIntCurrentIteration]: We unified 108 AI predicates to 108 [2018-12-09 17:55:42,235 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:55:42,235 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:55:42,235 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [10] total 40 [2018-12-09 17:55:42,235 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:55:42,236 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-12-09 17:55:42,236 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-12-09 17:55:42,236 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=150, Invalid=842, Unknown=0, NotChecked=0, Total=992 [2018-12-09 17:55:42,236 INFO L87 Difference]: Start difference. First operand 2017 states and 2538 transitions. Second operand 32 states. [2018-12-09 17:56:08,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:56:08,944 INFO L93 Difference]: Finished difference Result 3861 states and 4788 transitions. [2018-12-09 17:56:08,944 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-12-09 17:56:08,944 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 109 [2018-12-09 17:56:08,944 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:56:08,947 INFO L225 Difference]: With dead ends: 3861 [2018-12-09 17:56:08,947 INFO L226 Difference]: Without dead ends: 2914 [2018-12-09 17:56:08,948 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 110 GetRequests, 77 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 440 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=165, Invalid=957, Unknown=0, NotChecked=0, Total=1122 [2018-12-09 17:56:08,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2914 states. [2018-12-09 17:56:09,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2914 to 2061. [2018-12-09 17:56:09,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2061 states. [2018-12-09 17:56:09,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2061 states to 2061 states and 2594 transitions. [2018-12-09 17:56:09,222 INFO L78 Accepts]: Start accepts. Automaton has 2061 states and 2594 transitions. Word has length 109 [2018-12-09 17:56:09,222 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:56:09,222 INFO L480 AbstractCegarLoop]: Abstraction has 2061 states and 2594 transitions. [2018-12-09 17:56:09,222 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-12-09 17:56:09,222 INFO L276 IsEmpty]: Start isEmpty. Operand 2061 states and 2594 transitions. [2018-12-09 17:56:09,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-12-09 17:56:09,224 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:56:09,224 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:56:09,224 INFO L423 AbstractCegarLoop]: === Iteration 28 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:56:09,224 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:56:09,224 INFO L82 PathProgramCache]: Analyzing trace with hash -1992511617, now seen corresponding path program 1 times [2018-12-09 17:56:09,224 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:56:09,225 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:56:09,225 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:56:09,225 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:56:09,225 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:56:09,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:56:09,277 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 17:56:09,278 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:56:09,278 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:56:09,278 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 112 with the following transitions: [2018-12-09 17:56:09,278 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [669], [672], [674], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1001], [1002], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-09 17:56:09,279 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:56:09,279 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:56:09,381 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:56:09,381 INFO L272 AbstractInterpreter]: Visited 53 different actions 73 times. Merged at 5 different actions 7 times. Never widened. Performed 2033 root evaluator evaluations with a maximum evaluation depth of 10. Performed 2033 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 4 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:56:09,383 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:56:09,383 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:56:09,556 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:56:09,556 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:56:11,237 INFO L418 sIntCurrentIteration]: We unified 110 AI predicates to 110 [2018-12-09 17:56:11,237 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:56:11,237 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:56:11,237 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [10] total 41 [2018-12-09 17:56:11,237 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:56:11,238 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-12-09 17:56:11,238 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-12-09 17:56:11,238 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-12-09 17:56:11,238 INFO L87 Difference]: Start difference. First operand 2061 states and 2594 transitions. Second operand 33 states. [2018-12-09 17:56:24,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:56:24,189 INFO L93 Difference]: Finished difference Result 3907 states and 4846 transitions. [2018-12-09 17:56:24,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-12-09 17:56:24,189 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 111 [2018-12-09 17:56:24,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:56:24,192 INFO L225 Difference]: With dead ends: 3907 [2018-12-09 17:56:24,192 INFO L226 Difference]: Without dead ends: 2960 [2018-12-09 17:56:24,193 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 112 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 461 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=169, Invalid=1021, Unknown=0, NotChecked=0, Total=1190 [2018-12-09 17:56:24,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2960 states. [2018-12-09 17:56:24,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2960 to 2107. [2018-12-09 17:56:24,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2107 states. [2018-12-09 17:56:24,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2107 states to 2107 states and 2652 transitions. [2018-12-09 17:56:24,489 INFO L78 Accepts]: Start accepts. Automaton has 2107 states and 2652 transitions. Word has length 111 [2018-12-09 17:56:24,489 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:56:24,490 INFO L480 AbstractCegarLoop]: Abstraction has 2107 states and 2652 transitions. [2018-12-09 17:56:24,490 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-12-09 17:56:24,490 INFO L276 IsEmpty]: Start isEmpty. Operand 2107 states and 2652 transitions. [2018-12-09 17:56:24,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-12-09 17:56:24,491 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:56:24,491 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:56:24,491 INFO L423 AbstractCegarLoop]: === Iteration 29 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:56:24,491 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:56:24,491 INFO L82 PathProgramCache]: Analyzing trace with hash 695823972, now seen corresponding path program 1 times [2018-12-09 17:56:24,492 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:56:24,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:56:24,492 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:56:24,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:56:24,492 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:56:24,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:56:24,545 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 9 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 17:56:24,545 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:56:24,545 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:56:24,545 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 111 with the following transitions: [2018-12-09 17:56:24,546 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [469], [472], [473], [474], [480], [481], [637], [662], [665], [667], [669], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [793], [794], [796], [797], [799], [803], [805], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [913], [914], [915], [916], [917], [923], [999], [1000], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1035], [1036], [1049], [1050], [1051] [2018-12-09 17:56:24,546 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:56:24,546 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:56:24,643 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:56:24,643 INFO L272 AbstractInterpreter]: Visited 51 different actions 70 times. Merged at 5 different actions 10 times. Widened at 1 different actions 1 times. Performed 1901 root evaluator evaluations with a maximum evaluation depth of 10. Performed 1901 inverse root evaluator evaluations with a maximum inverse evaluation depth of 10. Found 5 fixpoints after 3 different actions. Largest state had 177 variables. [2018-12-09 17:56:24,644 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:56:24,644 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:56:24,809 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-12-09 17:56:24,810 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:56:26,374 INFO L418 sIntCurrentIteration]: We unified 109 AI predicates to 109 [2018-12-09 17:56:26,374 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:56:26,374 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:56:26,374 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [10] total 41 [2018-12-09 17:56:26,374 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:56:26,374 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-12-09 17:56:26,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-12-09 17:56:26,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2018-12-09 17:56:26,375 INFO L87 Difference]: Start difference. First operand 2107 states and 2652 transitions. Second operand 33 states. [2018-12-09 17:56:59,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:56:59,066 INFO L93 Difference]: Finished difference Result 3958 states and 4908 transitions. [2018-12-09 17:56:59,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-12-09 17:56:59,066 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 110 [2018-12-09 17:56:59,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:56:59,069 INFO L225 Difference]: With dead ends: 3958 [2018-12-09 17:56:59,069 INFO L226 Difference]: Without dead ends: 3011 [2018-12-09 17:56:59,070 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 111 GetRequests, 77 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 466 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=169, Invalid=1021, Unknown=0, NotChecked=0, Total=1190 [2018-12-09 17:56:59,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3011 states. [2018-12-09 17:56:59,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3011 to 1715. [2018-12-09 17:56:59,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1715 states. [2018-12-09 17:56:59,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2137 transitions. [2018-12-09 17:56:59,311 INFO L78 Accepts]: Start accepts. Automaton has 1715 states and 2137 transitions. Word has length 110 [2018-12-09 17:56:59,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:56:59,311 INFO L480 AbstractCegarLoop]: Abstraction has 1715 states and 2137 transitions. [2018-12-09 17:56:59,311 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-12-09 17:56:59,311 INFO L276 IsEmpty]: Start isEmpty. Operand 1715 states and 2137 transitions. [2018-12-09 17:56:59,312 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-09 17:56:59,312 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:56:59,313 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:56:59,313 INFO L423 AbstractCegarLoop]: === Iteration 30 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:56:59,313 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:56:59,313 INFO L82 PathProgramCache]: Analyzing trace with hash -1533572085, now seen corresponding path program 1 times [2018-12-09 17:56:59,313 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:56:59,314 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:56:59,314 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:56:59,314 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:56:59,314 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:56:59,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:56:59,365 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 17:56:59,365 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:56:59,365 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:56:59,365 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 116 with the following transitions: [2018-12-09 17:56:59,365 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [44], [47], [50], [62], [65], [68], [70], [73], [82], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [462], [464], [465], [469], [472], [473], [591], [593], [594], [637], [662], [665], [667], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [768], [769], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [857], [858], [859], [860], [913], [914], [915], [916], [917], [923], [927], [928], [973], [974], [999], [1000], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:56:59,366 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:56:59,366 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:56:59,637 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:56:59,637 INFO L272 AbstractInterpreter]: Visited 63 different actions 141 times. Merged at 18 different actions 28 times. Widened at 1 different actions 1 times. Performed 5832 root evaluator evaluations with a maximum evaluation depth of 4. Performed 5832 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 7 fixpoints after 5 different actions. Largest state had 182 variables. [2018-12-09 17:56:59,640 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:56:59,640 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:56:59,777 INFO L227 lantSequenceWeakener]: Weakened 73 states. On average, predicates are now at 94.04% of their original sizes. [2018-12-09 17:56:59,777 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:56:59,936 INFO L418 sIntCurrentIteration]: We unified 114 AI predicates to 114 [2018-12-09 17:56:59,936 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:56:59,936 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:56:59,936 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [9] total 33 [2018-12-09 17:56:59,936 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:56:59,936 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-12-09 17:56:59,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-12-09 17:56:59,936 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=558, Unknown=0, NotChecked=0, Total=650 [2018-12-09 17:56:59,937 INFO L87 Difference]: Start difference. First operand 1715 states and 2137 transitions. Second operand 26 states. [2018-12-09 17:57:09,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:57:09,175 INFO L93 Difference]: Finished difference Result 3756 states and 4649 transitions. [2018-12-09 17:57:09,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-12-09 17:57:09,176 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 115 [2018-12-09 17:57:09,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:57:09,178 INFO L225 Difference]: With dead ends: 3756 [2018-12-09 17:57:09,178 INFO L226 Difference]: Without dead ends: 2500 [2018-12-09 17:57:09,180 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 136 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 486 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=338, Invalid=1918, Unknown=0, NotChecked=0, Total=2256 [2018-12-09 17:57:09,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2500 states. [2018-12-09 17:57:09,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2500 to 2043. [2018-12-09 17:57:09,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2043 states. [2018-12-09 17:57:09,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2043 states to 2043 states and 2540 transitions. [2018-12-09 17:57:09,471 INFO L78 Accepts]: Start accepts. Automaton has 2043 states and 2540 transitions. Word has length 115 [2018-12-09 17:57:09,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:57:09,471 INFO L480 AbstractCegarLoop]: Abstraction has 2043 states and 2540 transitions. [2018-12-09 17:57:09,471 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-12-09 17:57:09,471 INFO L276 IsEmpty]: Start isEmpty. Operand 2043 states and 2540 transitions. [2018-12-09 17:57:09,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-12-09 17:57:09,472 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:57:09,472 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:57:09,473 INFO L423 AbstractCegarLoop]: === Iteration 31 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:57:09,473 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:57:09,473 INFO L82 PathProgramCache]: Analyzing trace with hash -130786366, now seen corresponding path program 1 times [2018-12-09 17:57:09,473 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:57:09,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:57:09,474 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:57:09,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:57:09,474 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:57:09,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:57:09,524 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 3 proven. 7 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-09 17:57:09,524 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:57:09,525 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:57:09,525 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 117 with the following transitions: [2018-12-09 17:57:09,525 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [44], [47], [50], [62], [65], [68], [70], [73], [82], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [462], [464], [465], [469], [472], [473], [591], [593], [594], [637], [662], [665], [669], [672], [674], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [768], [769], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [857], [858], [859], [860], [913], [914], [915], [916], [917], [923], [927], [928], [973], [974], [999], [1001], [1002], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:57:09,526 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:57:09,526 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:57:09,856 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:57:09,856 INFO L272 AbstractInterpreter]: Visited 66 different actions 161 times. Merged at 18 different actions 25 times. Never widened. Performed 7292 root evaluator evaluations with a maximum evaluation depth of 4. Performed 7292 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 6 fixpoints after 5 different actions. Largest state had 182 variables. [2018-12-09 17:57:09,858 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:57:09,858 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:57:10,013 INFO L227 lantSequenceWeakener]: Weakened 74 states. On average, predicates are now at 92.13% of their original sizes. [2018-12-09 17:57:10,013 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:57:10,208 INFO L418 sIntCurrentIteration]: We unified 115 AI predicates to 115 [2018-12-09 17:57:10,208 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:57:10,209 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:57:10,209 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-12-09 17:57:10,209 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:57:10,209 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-09 17:57:10,209 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-09 17:57:10,209 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=624, Unknown=0, NotChecked=0, Total=702 [2018-12-09 17:57:10,209 INFO L87 Difference]: Start difference. First operand 2043 states and 2540 transitions. Second operand 27 states. [2018-12-09 17:57:28,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:57:28,360 INFO L93 Difference]: Finished difference Result 4662 states and 5817 transitions. [2018-12-09 17:57:28,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-09 17:57:28,360 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 116 [2018-12-09 17:57:28,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:57:28,363 INFO L225 Difference]: With dead ends: 4662 [2018-12-09 17:57:28,363 INFO L226 Difference]: Without dead ends: 3406 [2018-12-09 17:57:28,365 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 163 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1384 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=704, Invalid=4846, Unknown=0, NotChecked=0, Total=5550 [2018-12-09 17:57:28,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3406 states. [2018-12-09 17:57:28,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3406 to 2371. [2018-12-09 17:57:28,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2371 states. [2018-12-09 17:57:28,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2371 states to 2371 states and 2957 transitions. [2018-12-09 17:57:28,713 INFO L78 Accepts]: Start accepts. Automaton has 2371 states and 2957 transitions. Word has length 116 [2018-12-09 17:57:28,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:57:28,713 INFO L480 AbstractCegarLoop]: Abstraction has 2371 states and 2957 transitions. [2018-12-09 17:57:28,713 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-09 17:57:28,713 INFO L276 IsEmpty]: Start isEmpty. Operand 2371 states and 2957 transitions. [2018-12-09 17:57:28,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-12-09 17:57:28,715 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:57:28,715 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:57:28,715 INFO L423 AbstractCegarLoop]: === Iteration 32 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:57:28,715 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:57:28,715 INFO L82 PathProgramCache]: Analyzing trace with hash -802655036, now seen corresponding path program 1 times [2018-12-09 17:57:28,715 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:57:28,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:57:28,716 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:57:28,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:57:28,716 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:57:28,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:57:28,788 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 3 proven. 7 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-09 17:57:28,788 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:57:28,788 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:57:28,788 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 118 with the following transitions: [2018-12-09 17:57:28,789 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [44], [47], [50], [62], [65], [68], [70], [73], [82], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [462], [464], [465], [469], [472], [473], [591], [593], [594], [637], [662], [665], [669], [676], [679], [681], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [768], [769], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [857], [858], [859], [860], [913], [914], [915], [916], [917], [923], [927], [928], [973], [974], [999], [1003], [1004], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:57:28,790 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:57:28,790 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:57:29,176 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:57:29,176 INFO L272 AbstractInterpreter]: Visited 67 different actions 168 times. Merged at 18 different actions 28 times. Widened at 1 different actions 1 times. Performed 7416 root evaluator evaluations with a maximum evaluation depth of 4. Performed 7416 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 7 fixpoints after 5 different actions. Largest state had 182 variables. [2018-12-09 17:57:29,179 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:57:29,179 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:57:29,319 INFO L227 lantSequenceWeakener]: Weakened 75 states. On average, predicates are now at 92.14% of their original sizes. [2018-12-09 17:57:29,319 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:57:29,519 INFO L418 sIntCurrentIteration]: We unified 116 AI predicates to 116 [2018-12-09 17:57:29,519 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:57:29,519 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:57:29,519 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-12-09 17:57:29,519 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:57:29,519 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-09 17:57:29,519 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-09 17:57:29,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=624, Unknown=0, NotChecked=0, Total=702 [2018-12-09 17:57:29,520 INFO L87 Difference]: Start difference. First operand 2371 states and 2957 transitions. Second operand 27 states. [2018-12-09 17:57:47,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:57:47,770 INFO L93 Difference]: Finished difference Result 5015 states and 6225 transitions. [2018-12-09 17:57:47,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-09 17:57:47,770 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 117 [2018-12-09 17:57:47,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:57:47,773 INFO L225 Difference]: With dead ends: 5015 [2018-12-09 17:57:47,773 INFO L226 Difference]: Without dead ends: 3737 [2018-12-09 17:57:47,775 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 164 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1384 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=704, Invalid=4846, Unknown=0, NotChecked=0, Total=5550 [2018-12-09 17:57:47,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3737 states. [2018-12-09 17:57:48,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3737 to 2398. [2018-12-09 17:57:48,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2398 states. [2018-12-09 17:57:48,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2398 states to 2398 states and 3001 transitions. [2018-12-09 17:57:48,158 INFO L78 Accepts]: Start accepts. Automaton has 2398 states and 3001 transitions. Word has length 117 [2018-12-09 17:57:48,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:57:48,158 INFO L480 AbstractCegarLoop]: Abstraction has 2398 states and 3001 transitions. [2018-12-09 17:57:48,158 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-09 17:57:48,158 INFO L276 IsEmpty]: Start isEmpty. Operand 2398 states and 3001 transitions. [2018-12-09 17:57:48,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-09 17:57:48,159 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:57:48,159 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:57:48,160 INFO L423 AbstractCegarLoop]: === Iteration 33 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:57:48,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:57:48,160 INFO L82 PathProgramCache]: Analyzing trace with hash 748857671, now seen corresponding path program 1 times [2018-12-09 17:57:48,160 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:57:48,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:57:48,161 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:57:48,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:57:48,161 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:57:48,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:57:48,190 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 17:57:48,190 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:57:48,190 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 17:57:48,190 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:57:48,191 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 17:57:48,191 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 17:57:48,191 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:57:48,191 INFO L87 Difference]: Start difference. First operand 2398 states and 3001 transitions. Second operand 3 states. [2018-12-09 17:57:48,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:57:48,716 INFO L93 Difference]: Finished difference Result 5079 states and 6260 transitions. [2018-12-09 17:57:48,716 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 17:57:48,716 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 115 [2018-12-09 17:57:48,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:57:48,720 INFO L225 Difference]: With dead ends: 5079 [2018-12-09 17:57:48,720 INFO L226 Difference]: Without dead ends: 3303 [2018-12-09 17:57:48,722 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:57:48,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3303 states. [2018-12-09 17:57:49,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3303 to 3240. [2018-12-09 17:57:49,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3240 states. [2018-12-09 17:57:49,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3240 states to 3240 states and 3962 transitions. [2018-12-09 17:57:49,189 INFO L78 Accepts]: Start accepts. Automaton has 3240 states and 3962 transitions. Word has length 115 [2018-12-09 17:57:49,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:57:49,189 INFO L480 AbstractCegarLoop]: Abstraction has 3240 states and 3962 transitions. [2018-12-09 17:57:49,189 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 17:57:49,189 INFO L276 IsEmpty]: Start isEmpty. Operand 3240 states and 3962 transitions. [2018-12-09 17:57:49,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-12-09 17:57:49,190 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:57:49,190 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:57:49,191 INFO L423 AbstractCegarLoop]: === Iteration 34 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:57:49,191 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:57:49,191 INFO L82 PathProgramCache]: Analyzing trace with hash -1364300325, now seen corresponding path program 1 times [2018-12-09 17:57:49,191 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:57:49,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:57:49,192 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:57:49,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:57:49,192 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:57:49,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:57:49,255 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 3 proven. 7 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-09 17:57:49,255 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:57:49,255 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:57:49,255 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 119 with the following transitions: [2018-12-09 17:57:49,256 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [35], [38], [44], [47], [50], [62], [65], [68], [70], [73], [82], [404], [406], [409], [411], [433], [436], [439], [442], [458], [460], [461], [462], [464], [465], [469], [472], [473], [591], [593], [594], [637], [662], [665], [669], [676], [683], [686], [688], [700], [705], [711], [713], [724], [729], [731], [758], [762], [764], [765], [768], [769], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [853], [854], [857], [858], [859], [860], [913], [914], [915], [916], [917], [923], [927], [928], [973], [974], [999], [1005], [1006], [1009], [1011], [1012], [1015], [1016], [1049], [1050], [1051] [2018-12-09 17:57:49,257 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:57:49,257 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:57:49,608 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 17:57:49,608 INFO L272 AbstractInterpreter]: Visited 68 different actions 171 times. Merged at 18 different actions 28 times. Widened at 1 different actions 1 times. Performed 7482 root evaluator evaluations with a maximum evaluation depth of 4. Performed 7482 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 7 fixpoints after 5 different actions. Largest state had 182 variables. [2018-12-09 17:57:49,610 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:57:49,610 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 17:57:49,753 INFO L227 lantSequenceWeakener]: Weakened 76 states. On average, predicates are now at 92.15% of their original sizes. [2018-12-09 17:57:49,753 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 17:57:49,951 INFO L418 sIntCurrentIteration]: We unified 117 AI predicates to 117 [2018-12-09 17:57:49,951 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 17:57:49,951 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:57:49,951 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [10] total 35 [2018-12-09 17:57:49,951 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 17:57:49,951 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-12-09 17:57:49,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-12-09 17:57:49,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=624, Unknown=0, NotChecked=0, Total=702 [2018-12-09 17:57:49,952 INFO L87 Difference]: Start difference. First operand 3240 states and 3962 transitions. Second operand 27 states. [2018-12-09 17:58:08,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:08,445 INFO L93 Difference]: Finished difference Result 6946 states and 8456 transitions. [2018-12-09 17:58:08,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-12-09 17:58:08,445 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 118 [2018-12-09 17:58:08,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:08,450 INFO L225 Difference]: With dead ends: 6946 [2018-12-09 17:58:08,450 INFO L226 Difference]: Without dead ends: 5118 [2018-12-09 17:58:08,452 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 165 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1384 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=704, Invalid=4846, Unknown=0, NotChecked=0, Total=5550 [2018-12-09 17:58:08,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5118 states. [2018-12-09 17:58:08,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5118 to 3267. [2018-12-09 17:58:08,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3267 states. [2018-12-09 17:58:08,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3267 states to 3267 states and 4003 transitions. [2018-12-09 17:58:08,994 INFO L78 Accepts]: Start accepts. Automaton has 3267 states and 4003 transitions. Word has length 118 [2018-12-09 17:58:08,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:08,994 INFO L480 AbstractCegarLoop]: Abstraction has 3267 states and 4003 transitions. [2018-12-09 17:58:08,994 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-12-09 17:58:08,994 INFO L276 IsEmpty]: Start isEmpty. Operand 3267 states and 4003 transitions. [2018-12-09 17:58:08,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-12-09 17:58:08,995 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:08,996 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:08,996 INFO L423 AbstractCegarLoop]: === Iteration 35 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:08,996 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:08,996 INFO L82 PathProgramCache]: Analyzing trace with hash -415603186, now seen corresponding path program 1 times [2018-12-09 17:58:08,996 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:58:08,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:58:08,997 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:08,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:58:08,997 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:58:09,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:09,039 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-09 17:58:09,039 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:58:09,039 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:58:09,039 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 117 with the following transitions: [2018-12-09 17:58:09,039 INFO L205 CegarAbsIntRunner]: [17], [19], [20], [25], [27], [30], [32], [44], [47], [50], [62], [65], [68], [70], [73], [82], [101], [265], [268], [271], [274], [281], [285], [292], [311], [340], [359], [362], [365], [367], [462], [464], [465], [469], [472], [473], [561], [591], [593], [594], [637], [705], [711], [713], [724], [729], [731], [740], [742], [744], [758], [762], [764], [765], [768], [769], [789], [790], [793], [794], [796], [797], [799], [802], [806], [845], [846], [847], [848], [849], [850], [851], [852], [857], [858], [859], [860], [893], [905], [906], [927], [928], [961], [973], [974], [1009], [1011], [1012], [1015], [1016], [1019], [1020], [1021], [1022], [1023], [1049], [1050], [1051] [2018-12-09 17:58:09,040 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 17:58:09,040 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 17:58:09,411 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 17:58:09,411 INFO L272 AbstractInterpreter]: Visited 98 different actions 235 times. Merged at 30 different actions 58 times. Never widened. Performed 7443 root evaluator evaluations with a maximum evaluation depth of 4. Performed 7443 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 6 fixpoints after 5 different actions. Largest state had 185 variables. [2018-12-09 17:58:09,414 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:09,415 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 17:58:09,415 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:58:09,415 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 17:58:09,425 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:09,425 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 17:58:09,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:09,519 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:09,558 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 17:58:09,558 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:09,656 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-09 17:58:09,671 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 17:58:09,671 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 11 [2018-12-09 17:58:09,671 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 17:58:09,672 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-09 17:58:09,672 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-09 17:58:09,672 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-12-09 17:58:09,672 INFO L87 Difference]: Start difference. First operand 3267 states and 4003 transitions. Second operand 8 states. [2018-12-09 17:58:10,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:10,206 INFO L93 Difference]: Finished difference Result 6510 states and 7980 transitions. [2018-12-09 17:58:10,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 17:58:10,207 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 116 [2018-12-09 17:58:10,207 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:10,210 INFO L225 Difference]: With dead ends: 6510 [2018-12-09 17:58:10,210 INFO L226 Difference]: Without dead ends: 3268 [2018-12-09 17:58:10,214 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 237 GetRequests, 226 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=51, Invalid=81, Unknown=0, NotChecked=0, Total=132 [2018-12-09 17:58:10,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3268 states. [2018-12-09 17:58:10,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3268 to 3268. [2018-12-09 17:58:10,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3268 states. [2018-12-09 17:58:10,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3268 states to 3268 states and 4004 transitions. [2018-12-09 17:58:10,738 INFO L78 Accepts]: Start accepts. Automaton has 3268 states and 4004 transitions. Word has length 116 [2018-12-09 17:58:10,738 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:10,738 INFO L480 AbstractCegarLoop]: Abstraction has 3268 states and 4004 transitions. [2018-12-09 17:58:10,738 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-09 17:58:10,738 INFO L276 IsEmpty]: Start isEmpty. Operand 3268 states and 4004 transitions. [2018-12-09 17:58:10,739 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-12-09 17:58:10,739 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:10,740 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:10,740 INFO L423 AbstractCegarLoop]: === Iteration 36 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:10,740 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:10,740 INFO L82 PathProgramCache]: Analyzing trace with hash -482142694, now seen corresponding path program 2 times [2018-12-09 17:58:10,740 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:58:10,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:58:10,741 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:10,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:58:10,741 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:58:10,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:10,795 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-09 17:58:10,795 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:58:10,795 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:58:10,796 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 17:58:10,796 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 17:58:10,796 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:58:10,796 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 17:58:10,803 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-12-09 17:58:10,803 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-12-09 17:58:10,895 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-12-09 17:58:10,895 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 17:58:10,900 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:10,930 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 17:58:10,931 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:10,999 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-09 17:58:11,014 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 17:58:11,014 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 14 [2018-12-09 17:58:11,014 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 17:58:11,014 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-12-09 17:58:11,015 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-12-09 17:58:11,015 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=111, Unknown=0, NotChecked=0, Total=182 [2018-12-09 17:58:11,015 INFO L87 Difference]: Start difference. First operand 3268 states and 4004 transitions. Second operand 10 states. [2018-12-09 17:58:11,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:11,519 INFO L93 Difference]: Finished difference Result 6511 states and 7981 transitions. [2018-12-09 17:58:11,520 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 17:58:11,520 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 117 [2018-12-09 17:58:11,520 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:11,523 INFO L225 Difference]: With dead ends: 6511 [2018-12-09 17:58:11,523 INFO L226 Difference]: Without dead ends: 3269 [2018-12-09 17:58:11,526 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 226 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=82, Invalid=128, Unknown=0, NotChecked=0, Total=210 [2018-12-09 17:58:11,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3269 states. [2018-12-09 17:58:12,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3269 to 3269. [2018-12-09 17:58:12,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3269 states. [2018-12-09 17:58:12,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3269 states to 3269 states and 4005 transitions. [2018-12-09 17:58:12,036 INFO L78 Accepts]: Start accepts. Automaton has 3269 states and 4005 transitions. Word has length 117 [2018-12-09 17:58:12,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:12,036 INFO L480 AbstractCegarLoop]: Abstraction has 3269 states and 4005 transitions. [2018-12-09 17:58:12,036 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-12-09 17:58:12,036 INFO L276 IsEmpty]: Start isEmpty. Operand 3269 states and 4005 transitions. [2018-12-09 17:58:12,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-12-09 17:58:12,038 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:12,038 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:12,039 INFO L423 AbstractCegarLoop]: === Iteration 37 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:12,039 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:12,039 INFO L82 PathProgramCache]: Analyzing trace with hash 1750099854, now seen corresponding path program 3 times [2018-12-09 17:58:12,039 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:58:12,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:58:12,040 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 17:58:12,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:58:12,040 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:58:12,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:12,109 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-09 17:58:12,110 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:58:12,110 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 17:58:12,110 INFO L187 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-12-09 17:58:12,110 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-12-09 17:58:12,110 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:58:12,110 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 17:58:12,118 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-12-09 17:58:12,118 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-12-09 17:58:12,188 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-12-09 17:58:12,188 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-12-09 17:58:12,192 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:12,226 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 4 proven. 6 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 17:58:12,226 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:12,305 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-09 17:58:12,320 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2018-12-09 17:58:12,321 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 16 [2018-12-09 17:58:12,321 INFO L249 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-12-09 17:58:12,321 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-12-09 17:58:12,321 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-12-09 17:58:12,321 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=146, Unknown=0, NotChecked=0, Total=240 [2018-12-09 17:58:12,321 INFO L87 Difference]: Start difference. First operand 3269 states and 4005 transitions. Second operand 12 states. [2018-12-09 17:58:12,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:12,836 INFO L93 Difference]: Finished difference Result 6512 states and 7982 transitions. [2018-12-09 17:58:12,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 17:58:12,837 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 118 [2018-12-09 17:58:12,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:12,840 INFO L225 Difference]: With dead ends: 6512 [2018-12-09 17:58:12,840 INFO L226 Difference]: Without dead ends: 3270 [2018-12-09 17:58:12,844 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 226 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=106, Invalid=166, Unknown=0, NotChecked=0, Total=272 [2018-12-09 17:58:12,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3270 states. [2018-12-09 17:58:13,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3270 to 3270. [2018-12-09 17:58:13,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3270 states. [2018-12-09 17:58:13,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3270 states to 3270 states and 4006 transitions. [2018-12-09 17:58:13,353 INFO L78 Accepts]: Start accepts. Automaton has 3270 states and 4006 transitions. Word has length 118 [2018-12-09 17:58:13,354 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:13,354 INFO L480 AbstractCegarLoop]: Abstraction has 3270 states and 4006 transitions. [2018-12-09 17:58:13,354 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-12-09 17:58:13,354 INFO L276 IsEmpty]: Start isEmpty. Operand 3270 states and 4006 transitions. [2018-12-09 17:58:13,355 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-12-09 17:58:13,355 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:13,355 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:13,355 INFO L423 AbstractCegarLoop]: === Iteration 38 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:13,355 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:13,355 INFO L82 PathProgramCache]: Analyzing trace with hash -2064825190, now seen corresponding path program 4 times [2018-12-09 17:58:13,356 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 17:58:13,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:58:13,356 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-12-09 17:58:13,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 17:58:13,356 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 17:58:13,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 17:58:13,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 17:58:13,432 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-09 17:58:13,452 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-12-09 17:58:13,491 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 192 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-09 17:58:13,491 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 226 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-09 17:58:13,491 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 234 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-09 17:58:13,492 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 190 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-09 17:58:13,499 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,501 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,501 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,501 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,502 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,505 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,505 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,506 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,506 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,510 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,510 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,511 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,511 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,511 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,511 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,512 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,512 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,513 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,513 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,513 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,513 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,514 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,514 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,515 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,515 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,515 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,515 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,516 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,516 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,516 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,517 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,517 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,517 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,518 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,518 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,518 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,518 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,518 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,519 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:13,540 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 09.12 05:58:13 BoogieIcfgContainer [2018-12-09 17:58:13,540 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-09 17:58:13,540 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-09 17:58:13,540 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-09 17:58:13,540 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-09 17:58:13,541 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 05:50:50" (3/4) ... [2018-12-09 17:58:13,543 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-12-09 17:58:13,543 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-09 17:58:13,544 INFO L168 Benchmark]: Toolchain (without parser) took 444189.33 ms. Allocated memory was 1.0 GB in the beginning and 2.1 GB in the end (delta: 1.1 GB). Free memory was 956.0 MB in the beginning and 530.1 MB in the end (delta: 425.9 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2018-12-09 17:58:13,544 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 982.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 17:58:13,545 INFO L168 Benchmark]: CACSL2BoogieTranslator took 567.68 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 109.6 MB). Free memory was 956.0 MB in the beginning and 1.1 GB in the end (delta: -105.6 MB). Peak memory consumption was 52.3 MB. Max. memory is 11.5 GB. [2018-12-09 17:58:13,545 INFO L168 Benchmark]: Boogie Procedure Inliner took 27.84 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 17:58:13,545 INFO L168 Benchmark]: Boogie Preprocessor took 41.77 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 11.5 GB. [2018-12-09 17:58:13,545 INFO L168 Benchmark]: RCFGBuilder took 764.00 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 921.1 MB in the end (delta: 133.4 MB). Peak memory consumption was 133.4 MB. Max. memory is 11.5 GB. [2018-12-09 17:58:13,545 INFO L168 Benchmark]: TraceAbstraction took 442782.09 ms. Allocated memory was 1.1 GB in the beginning and 2.1 GB in the end (delta: 945.3 MB). Free memory was 921.1 MB in the beginning and 530.1 MB in the end (delta: 391.0 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2018-12-09 17:58:13,545 INFO L168 Benchmark]: Witness Printer took 2.81 ms. Allocated memory is still 2.1 GB. Free memory is still 530.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 17:58:13,547 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 982.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 567.68 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 109.6 MB). Free memory was 956.0 MB in the beginning and 1.1 GB in the end (delta: -105.6 MB). Peak memory consumption was 52.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 27.84 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 41.77 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 764.00 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 921.1 MB in the end (delta: 133.4 MB). Peak memory consumption was 133.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 442782.09 ms. Allocated memory was 1.1 GB in the beginning and 2.1 GB in the end (delta: 945.3 MB). Free memory was 921.1 MB in the beginning and 530.1 MB in the end (delta: 391.0 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. * Witness Printer took 2.81 ms. Allocated memory is still 2.1 GB. Free memory is still 530.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 192 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 226 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 234 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 190 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1664]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of large string literal at line 2219, overapproximation of bitwiseAnd at line 1830. Possible FailurePath: [L1687] int ldv_irq_1_2 = 0; [L1688] int LDV_IN_INTERRUPT = 1; [L1689] int ldv_irq_1_3 = 0; [L1690] struct platform_device *tegra_rtc_driver_group0 ; [L1691] void *ldv_irq_data_1_1 ; [L1692] int ldv_irq_1_1 = 0; [L1693] int ldv_irq_1_0 = 0; [L1694] int ldv_irq_line_1_3 ; [L1695] void *ldv_irq_data_1_0 ; [L1696] int ldv_state_variable_0 ; [L1697] struct device *tegra_rtc_ops_group1 ; [L1698] int ldv_state_variable_3 ; [L1699] int ldv_irq_line_1_0 ; [L1700] int ldv_state_variable_2 ; [L1701] void *ldv_irq_data_1_3 ; [L1702] int ref_cnt ; [L1703] int ldv_irq_line_1_1 ; [L1704] struct rtc_time *tegra_rtc_ops_group0 ; [L1705] void *ldv_irq_data_1_2 ; [L1706] int ldv_state_variable_1 ; [L1707] int ldv_irq_line_1_2 ; [L1708] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2050-L2052] static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2218-L2219] static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2235] int ldv_retval_2 ; [L2236] int ldv_retval_0 ; [L2238] int ldv_retval_1 ; [L2761] int ldv_init = 0; VAL [\old(LDV_IN_INTERRUPT)=171, \old(ldv_init)=197, \old(ldv_irq_1_0)=204, \old(ldv_irq_1_1)=195, \old(ldv_irq_1_2)=207, \old(ldv_irq_1_3)=194, \old(ldv_irq_data_1_0)=198, \old(ldv_irq_data_1_0)=161, \old(ldv_irq_data_1_1)=214, \old(ldv_irq_data_1_1)=185, \old(ldv_irq_data_1_2)=176, \old(ldv_irq_data_1_2)=189, \old(ldv_irq_data_1_3)=202, \old(ldv_irq_data_1_3)=154, \old(ldv_irq_line_1_0)=205, \old(ldv_irq_line_1_1)=233, \old(ldv_irq_line_1_2)=228, \old(ldv_irq_line_1_3)=166, \old(ldv_retval_0)=170, \old(ldv_retval_1)=164, \old(ldv_retval_2)=188, \old(ldv_state_variable_0)=184, \old(ldv_state_variable_1)=216, \old(ldv_state_variable_2)=208, \old(ldv_state_variable_3)=236, \old(ref_cnt)=203, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver_group0)=199, \old(tegra_rtc_driver_group0)=224, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops_group0)=201, \old(tegra_rtc_ops_group0)=179, \old(tegra_rtc_ops_group1)=220, \old(tegra_rtc_ops_group1)=193, \old(tegra_rtc_ops_group2)=157, \old(tegra_rtc_ops_group2)=173, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2390] struct seq_file *ldvarg1 ; [L2391] void *tmp ; [L2392] unsigned int ldvarg0 ; [L2393] unsigned int tmp___0 ; [L2394] pm_message_t ldvarg2 ; [L2395] int tmp___1 ; [L2396] int tmp___2 ; [L2397] int tmp___3 ; [L2398] int tmp___4 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] CALL, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result={0:0}, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, size=136, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2400] RET, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_zalloc(136U)={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] tmp = ldv_zalloc(136U) [L2401] ldvarg1 = (struct seq_file *)tmp [L2402] tmp___0 = __VERIFIER_nondet_uint() [L2403] ldvarg0 = tmp___0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178] [L2404] FCALL ldv_initialize() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178] [L2405] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, memset((void *)(& ldvarg2), 0, 4U)={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178] [L2406] ldv_state_variable_1 = 1 [L2407] ref_cnt = 0 [L2408] ldv_state_variable_0 = 1 [L2409] ldv_state_variable_3 = 0 [L2410] ldv_state_variable_2 = 0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=1] [L2421] COND TRUE ldv_state_variable_0 != 0 [L2422] tmp___2 = __VERIFIER_nondet_int() [L2424] case 0: [L2432] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=1, tmp___2=1] [L2433] COND TRUE ldv_state_variable_0 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=1, tmp___2=1] [L2434] CALL, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2222] int tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] CALL, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, arg0={210:0}, arg1={-1:11}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2842] return __VERIFIER_nondet_int(); [L2224] RET, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe)=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2225] return (tmp); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp=0] [L2434] RET, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_init()=0, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=1, tmp___2=1] [L2434] ldv_retval_0 = tegra_rtc_init() [L2435] COND TRUE ldv_retval_0 == 0 [L2436] ldv_state_variable_0 = 3 [L2437] ldv_state_variable_2 = 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=1, tmp___2=1] [L2438] CALL ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2355] void *tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] CALL, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result={0:0}, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, size=624, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2357] RET, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] tmp = ldv_zalloc(624U) [L2358] tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2438] RET ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=1, tmp___2=1] [L2441] COND FALSE !(ldv_retval_0 != 0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=1, tmp___2=1] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=3, tmp___2=1] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: [L2566] case 1: [L2576] case 2: [L2596] case 3: [L2606] case 4: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=3, tmp___2=1, tmp___4=4] [L2607] COND TRUE ldv_state_variable_2 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=3, tmp___2=1, tmp___4=4] [L2608] CALL ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2830] return __VERIFIER_nondet_int(); [L2608] RET ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_probe_2()=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=3, tmp___2=1, tmp___4=4] [L2609] ldv_state_variable_2 = 2 [L2610] ref_cnt = ref_cnt + 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=3, tmp___2=1, tmp___4=4] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=3, tmp___2=1, tmp___4=4] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=3, tmp___2=1, tmp___4=0] [L2555] COND FALSE !(ldv_state_variable_2 == 4) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=3, tmp___2=1, tmp___4=0] [L2560] COND TRUE ldv_state_variable_2 == 2 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=178, ldvarg1={0:0}, ldvarg2={227:0}, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=178, tmp___1=3, tmp___2=1, tmp___4=0] [L2561] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2214] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1952] struct tegra_rtc_info *info ; [L1953] void *tmp ; [L1954] unsigned int status ; [L1955] unsigned long sl_irq_flags ; [L1956] u32 __v ; [L1957] u32 __v___0 ; VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, dev={0:12}, dev={0:12}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_nondet_pointer(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, arg0={0:12}, arg0={0:12}, external_alloc()={196:232}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1959] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={196:232}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] tmp = dev_get_drvdata((struct device const *)dev) [L1960] info = (struct tegra_rtc_info *)tmp VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, dev={0:12}, dev={0:12}, enabled=0, info={196:232}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={196:232}] [L1961] CALL tegra_rtc_wait_while_busy(dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1835] struct tegra_rtc_info *info ; [L1836] void *tmp ; [L1837] int retries ; [L1838] int tmp___0 ; [L1839] u32 tmp___1 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, dev={0:12}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_nondet_pointer(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, arg0={0:12}, arg0={0:12}, external_alloc()={221:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1841] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={221:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] tmp = dev_get_drvdata((struct device const *)dev) [L1842] info = (struct tegra_rtc_info *)tmp [L1843] retries = 500 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, dev={0:12}, dev={0:12}, info={221:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={221:0}] [L1854] CALL, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, info={221:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1825] u32 __v ; [L1826] u32 __v___0 ; [L1828] EXPR info->rtc_base [L1828] EXPR (unsigned int volatile *)info->rtc_base + 4U [L1828] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1829] __v = __v___0 [L1830] return (__v & 1U); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, __v=156, __v___0=156, info={221:0}, info={221:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1854] RET, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, dev={0:12}, dev={0:12}, info={221:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_check_busy(info)=0, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={221:0}] [L1854] tmp___1 = tegra_rtc_check_busy(info) [L1855] COND FALSE !(tmp___1 != 0U) [L1859] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result=0, __this_module={162:200}, dev={0:12}, dev={0:12}, info={221:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={221:0}, tmp___1=0] [L1961] RET tegra_rtc_wait_while_busy(dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, dev={0:12}, dev={0:12}, enabled=0, info={196:232}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={196:232}] [L1962] CALL ldv_spin_lock_check() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2775] COND FALSE !(ldv_init == 1) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2777] CALL ldv_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1664] __VERIFIER_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={162:200}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={210:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={225:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 65 procedures, 489 locations, 1 error locations. UNSAFE Result, 442.7s OverallTime, 38 OverallIterations, 4 TraceHistogramMax, 395.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 15785 SDtfs, 15985 SDslu, 58697 SDs, 0 SdLazy, 12242 SolverSat, 4276 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 190.3s Time, PredicateUnifierStatistics: 50 DeclaredPredicates, 3513 GetRequests, 2543 SyntacticMatches, 24 SemanticMatches, 946 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12569 ImplicationChecksByTransitivity, 31.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3270occurred in iteration=37, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 3.9s AbstIntTime, 26 AbstIntIterations, 25 AbstIntStrong, 0.9927433883928556 AbsIntWeakeningRatio, 2.3484609313338596 AbsIntAvgWeakeningVarsNumRemoved, 51.701262825572215 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 7.1s AutomataMinimizationTime, 37 MinimizatonAttempts, 21108 StatesRemovedByMinimization, 33 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 2.1s InterpolantComputationTime, 4101 NumberOfCodeBlocks, 4101 NumberOfCodeBlocksAsserted, 44 NumberOfCheckSat, 4290 ConstructedInterpolants, 0 QuantifiedInterpolants, 647840 SizeOfPredicates, 3 NumberOfNonLiveVariables, 3120 ConjunctsInSsa, 15 ConjunctsInUnsatCore, 43 InterpolantComputations, 9 PerfectInterpolantSequences, 879/1084 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-635dfa2 [2018-12-09 17:58:14,965 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-09 17:58:14,966 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-09 17:58:14,972 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-09 17:58:14,973 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-09 17:58:14,973 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-09 17:58:14,974 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-09 17:58:14,974 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-09 17:58:14,975 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-09 17:58:14,975 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-09 17:58:14,976 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-09 17:58:14,976 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-09 17:58:14,976 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-09 17:58:14,977 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-09 17:58:14,977 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-09 17:58:14,978 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-09 17:58:14,978 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-09 17:58:14,979 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-09 17:58:14,980 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-09 17:58:14,981 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-09 17:58:14,981 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-09 17:58:14,982 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-09 17:58:14,983 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-09 17:58:14,983 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-09 17:58:14,983 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-09 17:58:14,983 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-09 17:58:14,984 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-09 17:58:14,984 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-09 17:58:14,984 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-09 17:58:14,985 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-09 17:58:14,985 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-09 17:58:14,985 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-09 17:58:14,985 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-09 17:58:14,986 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-09 17:58:14,986 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-09 17:58:14,986 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-09 17:58:14,987 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2018-12-09 17:58:14,994 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-09 17:58:14,994 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-09 17:58:14,994 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-09 17:58:14,994 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-09 17:58:14,995 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-09 17:58:14,995 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-09 17:58:14,995 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-09 17:58:14,995 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-09 17:58:14,995 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-09 17:58:14,995 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-09 17:58:14,995 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-09 17:58:14,995 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-09 17:58:14,996 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-09 17:58:14,996 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-09 17:58:14,996 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-09 17:58:14,996 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-12-09 17:58:14,996 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-12-09 17:58:14,996 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-09 17:58:14,996 INFO L133 SettingsManager]: * Use constant arrays=true [2018-12-09 17:58:14,996 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-09 17:58:14,996 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-09 17:58:14,996 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-09 17:58:14,996 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-09 17:58:14,997 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-09 17:58:14,997 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 17:58:14,997 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-09 17:58:14,997 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-09 17:58:14,997 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-09 17:58:14,997 INFO L133 SettingsManager]: * Trace refinement strategy=WALRUS [2018-12-09 17:58:14,997 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-09 17:58:14,997 INFO L133 SettingsManager]: * Command for external solver=cvc4 --incremental --rewrite-divk --print-success --lang smt [2018-12-09 17:58:14,997 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-12-09 17:58:14,997 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 840e3ba93a4f821803f9089812ff1f73e2838277 [2018-12-09 17:58:15,016 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-09 17:58:15,025 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-09 17:58:15,028 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-09 17:58:15,029 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-09 17:58:15,029 INFO L276 PluginConnector]: CDTParser initialized [2018-12-09 17:58:15,030 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-09 17:58:15,076 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/data/3ccb95e28/447bad89b5f84b4f8968aee5c9f71ab0/FLAG3ffe85730 [2018-12-09 17:58:15,660 INFO L307 CDTParser]: Found 1 translation units. [2018-12-09 17:58:15,660 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-09 17:58:15,674 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/data/3ccb95e28/447bad89b5f84b4f8968aee5c9f71ab0/FLAG3ffe85730 [2018-12-09 17:58:16,055 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/data/3ccb95e28/447bad89b5f84b4f8968aee5c9f71ab0 [2018-12-09 17:58:16,058 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-09 17:58:16,059 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-09 17:58:16,060 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-09 17:58:16,060 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-09 17:58:16,063 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-09 17:58:16,064 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 05:58:16" (1/1) ... [2018-12-09 17:58:16,066 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@47abe2bb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16, skipping insertion in model container [2018-12-09 17:58:16,066 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 05:58:16" (1/1) ... [2018-12-09 17:58:16,071 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-09 17:58:16,119 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-09 17:58:16,565 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 17:58:16,642 INFO L191 MainTranslator]: Completed pre-run [2018-12-09 17:58:16,745 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 17:58:16,803 INFO L195 MainTranslator]: Completed translation [2018-12-09 17:58:16,803 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16 WrapperNode [2018-12-09 17:58:16,803 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-09 17:58:16,804 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-09 17:58:16,804 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-09 17:58:16,804 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-09 17:58:16,812 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16" (1/1) ... [2018-12-09 17:58:16,834 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16" (1/1) ... [2018-12-09 17:58:16,842 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-09 17:58:16,843 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-09 17:58:16,843 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-09 17:58:16,843 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-09 17:58:16,851 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16" (1/1) ... [2018-12-09 17:58:16,851 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16" (1/1) ... [2018-12-09 17:58:16,857 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16" (1/1) ... [2018-12-09 17:58:16,857 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16" (1/1) ... [2018-12-09 17:58:16,882 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16" (1/1) ... [2018-12-09 17:58:16,888 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16" (1/1) ... [2018-12-09 17:58:16,894 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16" (1/1) ... [2018-12-09 17:58:16,902 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-09 17:58:16,902 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-09 17:58:16,902 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-09 17:58:16,902 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-09 17:58:16,903 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 17:58:16,938 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-12-09 17:58:16,938 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-12-09 17:58:16,938 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2018-12-09 17:58:16,938 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_get_drvdata [2018-12-09 17:58:16,939 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1 [2018-12-09 17:58:16,939 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_unregister [2018-12-09 17:58:16,939 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_unregister [2018-12-09 17:58:16,939 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE8 [2018-12-09 17:58:16,939 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-12-09 17:58:16,939 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-12-09 17:58:16,939 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-12-09 17:58:16,939 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-12-09 17:58:16,939 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-12-09 17:58:16,940 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-12-09 17:58:16,940 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize [2018-12-09 17:58:16,940 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize [2018-12-09 17:58:16,940 INFO L130 BoogieDeclarations]: Found specification of procedure external_alloc [2018-12-09 17:58:16,940 INFO L138 BoogieDeclarations]: Found implementation of procedure external_alloc [2018-12-09 17:58:16,940 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-12-09 17:58:16,940 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-12-09 17:58:16,940 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2018-12-09 17:58:16,940 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_time_to_tm [2018-12-09 17:58:16,941 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-12-09 17:58:16,941 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-12-09 17:58:16,941 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-12-09 17:58:16,941 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-12-09 17:58:16,941 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2018-12-09 17:58:16,941 INFO L138 BoogieDeclarations]: Found implementation of procedure irq_set_irq_wake [2018-12-09 17:58:16,941 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-12-09 17:58:16,941 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-12-09 17:58:16,941 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-12-09 17:58:16,941 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-12-09 17:58:16,941 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-12-09 17:58:16,941 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-12-09 17:58:16,941 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2018-12-09 17:58:16,942 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_tm_to_time [2018-12-09 17:58:16,942 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2018-12-09 17:58:16,942 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2018-12-09 17:58:16,942 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-12-09 17:58:16,942 INFO L138 BoogieDeclarations]: Found implementation of procedure kfree [2018-12-09 17:58:16,942 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2018-12-09 17:58:16,942 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2018-12-09 17:58:16,942 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-12-09 17:58:16,942 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-12-09 17:58:16,942 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-12-09 17:58:16,942 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-12-09 17:58:16,942 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_release_3 [2018-12-09 17:58:16,942 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_release_3 [2018-12-09 17:58:16,943 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-12-09 17:58:16,943 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-12-09 17:58:16,943 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-12-09 17:58:16,943 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-12-09 17:58:16,943 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-12-09 17:58:16,943 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-12-09 17:58:16,943 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-12-09 17:58:16,943 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-12-09 17:58:16,943 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-12-09 17:58:16,944 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-12-09 17:58:16,944 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2018-12-09 17:58:16,944 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_iounmap [2018-12-09 17:58:16,944 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_probe [2018-12-09 17:58:16,944 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_probe [2018-12-09 17:58:16,944 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_valid_tm [2018-12-09 17:58:16,944 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_valid_tm [2018-12-09 17:58:16,944 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-12-09 17:58:16,944 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-12-09 17:58:16,944 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-09 17:58:16,944 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-09 17:58:16,944 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-12-09 17:58:16,944 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-12-09 17:58:16,945 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-12-09 17:58:16,945 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-12-09 17:58:16,945 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-12-09 17:58:16,945 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-12-09 17:58:16,945 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_update_irq [2018-12-09 17:58:16,945 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_update_irq [2018-12-09 17:58:16,945 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2018-12-09 17:58:16,945 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_device_unregister [2018-12-09 17:58:16,945 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-09 17:58:16,946 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-09 17:58:16,946 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2018-12-09 17:58:16,946 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2018-12-09 17:58:16,946 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-12-09 17:58:16,946 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-12-09 17:58:16,946 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-12-09 17:58:16,946 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-12-09 17:58:16,946 INFO L130 BoogieDeclarations]: Found specification of procedure _raw_spin_unlock_irqrestore [2018-12-09 17:58:16,946 INFO L138 BoogieDeclarations]: Found implementation of procedure _raw_spin_unlock_irqrestore [2018-12-09 17:58:16,946 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-12-09 17:58:16,946 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-12-09 17:58:16,946 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-12-09 17:58:16,946 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-12-09 17:58:16,946 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-12-09 17:58:16,947 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-12-09 17:58:16,947 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-12-09 17:58:16,947 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-12-09 17:58:16,947 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-12-09 17:58:16,947 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2018-12-09 17:58:16,947 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_resource [2018-12-09 17:58:16,947 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE8 [2018-12-09 17:58:16,947 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1 [2018-12-09 17:58:16,947 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-12-09 17:58:16,947 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-12-09 17:58:16,947 INFO L130 BoogieDeclarations]: Found specification of procedure dev_set_drvdata [2018-12-09 17:58:16,947 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_set_drvdata [2018-12-09 17:58:16,947 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-12-09 17:58:16,947 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-12-09 17:58:16,947 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-12-09 17:58:16,947 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-12-09 17:58:16,948 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-12-09 17:58:16,948 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-12-09 17:58:16,948 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-12-09 17:58:16,948 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1 [2018-12-09 17:58:16,948 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-12-09 17:58:16,948 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-12-09 17:58:16,948 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-12-09 17:58:16,948 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-12-09 17:58:16,948 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-12-09 17:58:16,948 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-12-09 17:58:16,948 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-12-09 17:58:16,948 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-12-09 17:58:16,949 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-12-09 17:58:16,949 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-12-09 17:58:16,949 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-12-09 17:58:16,949 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-12-09 17:58:16,949 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-12-09 17:58:16,949 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-12-09 17:58:16,949 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_3 [2018-12-09 17:58:16,949 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_3 [2018-12-09 17:58:16,949 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_2 [2018-12-09 17:58:16,950 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_2 [2018-12-09 17:58:16,950 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-12-09 17:58:16,950 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-12-09 17:58:16,950 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2018-12-09 17:58:16,950 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2018-12-09 17:58:16,950 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-12-09 17:58:16,950 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-12-09 17:58:16,950 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-12-09 17:58:16,950 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-12-09 17:58:16,950 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-09 17:58:16,951 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-09 17:58:19,835 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-09 17:58:19,836 INFO L280 CfgBuilder]: Removed 0 assue(true) statements. [2018-12-09 17:58:19,836 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 05:58:19 BoogieIcfgContainer [2018-12-09 17:58:19,836 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-09 17:58:19,837 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-09 17:58:19,837 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-09 17:58:19,840 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-09 17:58:19,840 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 09.12 05:58:16" (1/3) ... [2018-12-09 17:58:19,840 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@19860ac2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 05:58:19, skipping insertion in model container [2018-12-09 17:58:19,841 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 05:58:16" (2/3) ... [2018-12-09 17:58:19,841 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@19860ac2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 05:58:19, skipping insertion in model container [2018-12-09 17:58:19,841 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 05:58:19" (3/3) ... [2018-12-09 17:58:19,842 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.i [2018-12-09 17:58:19,850 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-09 17:58:19,857 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-09 17:58:19,870 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-09 17:58:19,897 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-12-09 17:58:19,898 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-09 17:58:19,898 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-09 17:58:19,898 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-09 17:58:19,899 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-09 17:58:19,899 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-09 17:58:19,899 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-09 17:58:19,899 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-09 17:58:19,899 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-09 17:58:19,916 INFO L276 IsEmpty]: Start isEmpty. Operand 486 states. [2018-12-09 17:58:19,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-12-09 17:58:19,924 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:19,924 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:19,926 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:19,929 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:19,929 INFO L82 PathProgramCache]: Analyzing trace with hash 1646624460, now seen corresponding path program 1 times [2018-12-09 17:58:19,932 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:19,933 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 2 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:19,952 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:20,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:20,076 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:20,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 17:58:20,105 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-09 17:58:20,108 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:58:20,109 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 17:58:20,111 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 17:58:20,119 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 17:58:20,120 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:58:20,121 INFO L87 Difference]: Start difference. First operand 486 states. Second operand 3 states. [2018-12-09 17:58:20,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:20,192 INFO L93 Difference]: Finished difference Result 822 states and 1040 transitions. [2018-12-09 17:58:20,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 17:58:20,194 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-12-09 17:58:20,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:20,203 INFO L225 Difference]: With dead ends: 822 [2018-12-09 17:58:20,203 INFO L226 Difference]: Without dead ends: 331 [2018-12-09 17:58:20,207 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:58:20,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331 states. [2018-12-09 17:58:20,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331 to 331. [2018-12-09 17:58:20,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 331 states. [2018-12-09 17:58:20,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 331 states to 331 states and 401 transitions. [2018-12-09 17:58:20,250 INFO L78 Accepts]: Start accepts. Automaton has 331 states and 401 transitions. Word has length 47 [2018-12-09 17:58:20,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:20,251 INFO L480 AbstractCegarLoop]: Abstraction has 331 states and 401 transitions. [2018-12-09 17:58:20,251 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 17:58:20,252 INFO L276 IsEmpty]: Start isEmpty. Operand 331 states and 401 transitions. [2018-12-09 17:58:20,254 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-12-09 17:58:20,254 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:20,254 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:20,254 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:20,254 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:20,254 INFO L82 PathProgramCache]: Analyzing trace with hash -884307126, now seen corresponding path program 1 times [2018-12-09 17:58:20,255 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:20,255 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 3 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:20,272 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:20,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:20,383 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:20,414 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:20,414 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-09 17:58:20,416 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:58:20,416 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 17:58:20,417 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 17:58:20,418 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 17:58:20,418 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 17:58:20,418 INFO L87 Difference]: Start difference. First operand 331 states and 401 transitions. Second operand 5 states. [2018-12-09 17:58:20,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:20,543 INFO L93 Difference]: Finished difference Result 970 states and 1194 transitions. [2018-12-09 17:58:20,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 17:58:20,543 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2018-12-09 17:58:20,544 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:20,548 INFO L225 Difference]: With dead ends: 970 [2018-12-09 17:58:20,548 INFO L226 Difference]: Without dead ends: 656 [2018-12-09 17:58:20,550 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-09 17:58:20,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 656 states. [2018-12-09 17:58:20,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 656 to 643. [2018-12-09 17:58:20,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 643 states. [2018-12-09 17:58:20,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 643 states to 643 states and 786 transitions. [2018-12-09 17:58:20,611 INFO L78 Accepts]: Start accepts. Automaton has 643 states and 786 transitions. Word has length 70 [2018-12-09 17:58:20,612 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:20,612 INFO L480 AbstractCegarLoop]: Abstraction has 643 states and 786 transitions. [2018-12-09 17:58:20,612 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 17:58:20,612 INFO L276 IsEmpty]: Start isEmpty. Operand 643 states and 786 transitions. [2018-12-09 17:58:20,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-12-09 17:58:20,614 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:20,614 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:20,614 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:20,614 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:20,614 INFO L82 PathProgramCache]: Analyzing trace with hash -1544904286, now seen corresponding path program 1 times [2018-12-09 17:58:20,614 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:20,615 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 4 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:20,631 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:20,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:20,756 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:20,763 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:20,763 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-09 17:58:20,764 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:58:20,765 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 17:58:20,765 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 17:58:20,765 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 17:58:20,765 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:58:20,765 INFO L87 Difference]: Start difference. First operand 643 states and 786 transitions. Second operand 3 states. [2018-12-09 17:58:20,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:20,832 INFO L93 Difference]: Finished difference Result 1516 states and 1857 transitions. [2018-12-09 17:58:20,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 17:58:20,832 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2018-12-09 17:58:20,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:20,835 INFO L225 Difference]: With dead ends: 1516 [2018-12-09 17:58:20,835 INFO L226 Difference]: Without dead ends: 890 [2018-12-09 17:58:20,836 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:58:20,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 890 states. [2018-12-09 17:58:20,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 890 to 887. [2018-12-09 17:58:20,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 887 states. [2018-12-09 17:58:20,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 887 states to 887 states and 1086 transitions. [2018-12-09 17:58:20,863 INFO L78 Accepts]: Start accepts. Automaton has 887 states and 1086 transitions. Word has length 68 [2018-12-09 17:58:20,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:20,864 INFO L480 AbstractCegarLoop]: Abstraction has 887 states and 1086 transitions. [2018-12-09 17:58:20,864 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 17:58:20,864 INFO L276 IsEmpty]: Start isEmpty. Operand 887 states and 1086 transitions. [2018-12-09 17:58:20,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-12-09 17:58:20,865 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:20,865 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:20,865 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:20,865 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:20,865 INFO L82 PathProgramCache]: Analyzing trace with hash -1663745524, now seen corresponding path program 1 times [2018-12-09 17:58:20,865 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:20,866 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 5 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:20,882 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:20,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:20,989 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:21,011 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:21,011 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-09 17:58:21,013 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:58:21,013 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 17:58:21,014 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 17:58:21,014 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 17:58:21,014 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 17:58:21,014 INFO L87 Difference]: Start difference. First operand 887 states and 1086 transitions. Second operand 5 states. [2018-12-09 17:58:21,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:21,108 INFO L93 Difference]: Finished difference Result 1780 states and 2200 transitions. [2018-12-09 17:58:21,109 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 17:58:21,109 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2018-12-09 17:58:21,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:21,111 INFO L225 Difference]: With dead ends: 1780 [2018-12-09 17:58:21,112 INFO L226 Difference]: Without dead ends: 919 [2018-12-09 17:58:21,113 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-09 17:58:21,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states. [2018-12-09 17:58:21,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 895. [2018-12-09 17:58:21,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 895 states. [2018-12-09 17:58:21,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 895 states to 895 states and 1088 transitions. [2018-12-09 17:58:21,141 INFO L78 Accepts]: Start accepts. Automaton has 895 states and 1088 transitions. Word has length 71 [2018-12-09 17:58:21,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:21,141 INFO L480 AbstractCegarLoop]: Abstraction has 895 states and 1088 transitions. [2018-12-09 17:58:21,141 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 17:58:21,141 INFO L276 IsEmpty]: Start isEmpty. Operand 895 states and 1088 transitions. [2018-12-09 17:58:21,142 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-12-09 17:58:21,142 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:21,142 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:21,143 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:21,143 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:21,143 INFO L82 PathProgramCache]: Analyzing trace with hash -1782427673, now seen corresponding path program 1 times [2018-12-09 17:58:21,143 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:21,143 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 6 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:21,168 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:21,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:21,268 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:21,294 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:21,294 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-09 17:58:21,296 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:58:21,296 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 17:58:21,296 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 17:58:21,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 17:58:21,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 17:58:21,297 INFO L87 Difference]: Start difference. First operand 895 states and 1088 transitions. Second operand 5 states. [2018-12-09 17:58:21,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:21,389 INFO L93 Difference]: Finished difference Result 1796 states and 2200 transitions. [2018-12-09 17:58:21,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 17:58:21,389 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 72 [2018-12-09 17:58:21,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:21,393 INFO L225 Difference]: With dead ends: 1796 [2018-12-09 17:58:21,393 INFO L226 Difference]: Without dead ends: 927 [2018-12-09 17:58:21,396 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 68 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-09 17:58:21,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 927 states. [2018-12-09 17:58:21,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 927 to 903. [2018-12-09 17:58:21,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 903 states. [2018-12-09 17:58:21,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 903 states to 903 states and 1090 transitions. [2018-12-09 17:58:21,438 INFO L78 Accepts]: Start accepts. Automaton has 903 states and 1090 transitions. Word has length 72 [2018-12-09 17:58:21,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:21,439 INFO L480 AbstractCegarLoop]: Abstraction has 903 states and 1090 transitions. [2018-12-09 17:58:21,439 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 17:58:21,439 INFO L276 IsEmpty]: Start isEmpty. Operand 903 states and 1090 transitions. [2018-12-09 17:58:21,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-12-09 17:58:21,440 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:21,441 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:21,441 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:21,441 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:21,441 INFO L82 PathProgramCache]: Analyzing trace with hash 1402464713, now seen corresponding path program 1 times [2018-12-09 17:58:21,442 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:21,442 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 7 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:21,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:21,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:21,568 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:21,587 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:21,587 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-09 17:58:21,589 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:58:21,589 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 17:58:21,589 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 17:58:21,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 17:58:21,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 17:58:21,589 INFO L87 Difference]: Start difference. First operand 903 states and 1090 transitions. Second operand 5 states. [2018-12-09 17:58:21,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:21,654 INFO L93 Difference]: Finished difference Result 1707 states and 2078 transitions. [2018-12-09 17:58:21,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 17:58:21,655 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2018-12-09 17:58:21,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:21,657 INFO L225 Difference]: With dead ends: 1707 [2018-12-09 17:58:21,657 INFO L226 Difference]: Without dead ends: 830 [2018-12-09 17:58:21,659 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 69 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-09 17:58:21,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states. [2018-12-09 17:58:21,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 812. [2018-12-09 17:58:21,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2018-12-09 17:58:21,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 974 transitions. [2018-12-09 17:58:21,684 INFO L78 Accepts]: Start accepts. Automaton has 812 states and 974 transitions. Word has length 73 [2018-12-09 17:58:21,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:21,684 INFO L480 AbstractCegarLoop]: Abstraction has 812 states and 974 transitions. [2018-12-09 17:58:21,684 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 17:58:21,684 INFO L276 IsEmpty]: Start isEmpty. Operand 812 states and 974 transitions. [2018-12-09 17:58:21,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-12-09 17:58:21,686 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:21,686 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:21,686 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:21,686 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:21,686 INFO L82 PathProgramCache]: Analyzing trace with hash -1316738903, now seen corresponding path program 1 times [2018-12-09 17:58:21,687 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:21,687 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 8 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:21,712 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:21,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:21,834 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:21,897 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-09 17:58:21,898 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:22,130 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-12-09 17:58:22,133 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 17:58:22,133 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [9] total 13 [2018-12-09 17:58:22,133 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-12-09 17:58:22,133 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-12-09 17:58:22,133 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-12-09 17:58:22,133 INFO L87 Difference]: Start difference. First operand 812 states and 974 transitions. Second operand 13 states. [2018-12-09 17:58:25,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:25,263 INFO L93 Difference]: Finished difference Result 2154 states and 2671 transitions. [2018-12-09 17:58:25,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-12-09 17:58:25,263 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 85 [2018-12-09 17:58:25,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:25,268 INFO L225 Difference]: With dead ends: 2154 [2018-12-09 17:58:25,268 INFO L226 Difference]: Without dead ends: 1368 [2018-12-09 17:58:25,271 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 158 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=152, Invalid=498, Unknown=0, NotChecked=0, Total=650 [2018-12-09 17:58:25,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1368 states. [2018-12-09 17:58:25,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1368 to 1155. [2018-12-09 17:58:25,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1155 states. [2018-12-09 17:58:25,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1155 states to 1155 states and 1392 transitions. [2018-12-09 17:58:25,344 INFO L78 Accepts]: Start accepts. Automaton has 1155 states and 1392 transitions. Word has length 85 [2018-12-09 17:58:25,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:25,344 INFO L480 AbstractCegarLoop]: Abstraction has 1155 states and 1392 transitions. [2018-12-09 17:58:25,344 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-12-09 17:58:25,344 INFO L276 IsEmpty]: Start isEmpty. Operand 1155 states and 1392 transitions. [2018-12-09 17:58:25,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-12-09 17:58:25,346 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:25,346 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:25,346 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:25,346 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:25,346 INFO L82 PathProgramCache]: Analyzing trace with hash 1516400962, now seen corresponding path program 1 times [2018-12-09 17:58:25,347 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:25,347 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 9 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:25,372 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:25,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:25,490 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:25,570 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:25,571 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:25,724 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:25,725 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:58:25,726 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 17:58:25,741 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:25,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:25,812 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:25,818 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:25,818 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:25,941 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:25,957 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-12-09 17:58:25,957 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-12-09 17:58:25,958 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-09 17:58:25,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-09 17:58:25,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-12-09 17:58:25,958 INFO L87 Difference]: Start difference. First operand 1155 states and 1392 transitions. Second operand 14 states. [2018-12-09 17:58:27,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:27,199 INFO L93 Difference]: Finished difference Result 2670 states and 3229 transitions. [2018-12-09 17:58:27,199 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-12-09 17:58:27,199 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 86 [2018-12-09 17:58:27,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:27,204 INFO L225 Difference]: With dead ends: 2670 [2018-12-09 17:58:27,204 INFO L226 Difference]: Without dead ends: 1541 [2018-12-09 17:58:27,206 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 353 GetRequests, 329 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-12-09 17:58:27,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1541 states. [2018-12-09 17:58:27,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1541 to 1472. [2018-12-09 17:58:27,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1472 states. [2018-12-09 17:58:27,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1472 states to 1472 states and 1785 transitions. [2018-12-09 17:58:27,272 INFO L78 Accepts]: Start accepts. Automaton has 1472 states and 1785 transitions. Word has length 86 [2018-12-09 17:58:27,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:27,272 INFO L480 AbstractCegarLoop]: Abstraction has 1472 states and 1785 transitions. [2018-12-09 17:58:27,272 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-09 17:58:27,272 INFO L276 IsEmpty]: Start isEmpty. Operand 1472 states and 1785 transitions. [2018-12-09 17:58:27,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-12-09 17:58:27,274 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:27,274 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:27,274 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:27,274 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:27,274 INFO L82 PathProgramCache]: Analyzing trace with hash -2059129438, now seen corresponding path program 1 times [2018-12-09 17:58:27,275 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:27,275 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 11 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:27,299 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:27,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:27,419 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:27,487 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:27,488 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:27,624 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:27,626 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:58:27,626 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 17:58:27,634 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:27,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:27,708 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:27,713 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:27,713 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:27,816 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:27,831 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-12-09 17:58:27,831 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-12-09 17:58:27,831 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-09 17:58:27,831 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-09 17:58:27,831 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-12-09 17:58:27,832 INFO L87 Difference]: Start difference. First operand 1472 states and 1785 transitions. Second operand 14 states. [2018-12-09 17:58:29,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:29,053 INFO L93 Difference]: Finished difference Result 3304 states and 4019 transitions. [2018-12-09 17:58:29,053 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-12-09 17:58:29,053 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 87 [2018-12-09 17:58:29,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:29,057 INFO L225 Difference]: With dead ends: 3304 [2018-12-09 17:58:29,057 INFO L226 Difference]: Without dead ends: 1858 [2018-12-09 17:58:29,059 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 333 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-12-09 17:58:29,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1858 states. [2018-12-09 17:58:29,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1858 to 1472. [2018-12-09 17:58:29,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1472 states. [2018-12-09 17:58:29,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1472 states to 1472 states and 1785 transitions. [2018-12-09 17:58:29,125 INFO L78 Accepts]: Start accepts. Automaton has 1472 states and 1785 transitions. Word has length 87 [2018-12-09 17:58:29,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:29,126 INFO L480 AbstractCegarLoop]: Abstraction has 1472 states and 1785 transitions. [2018-12-09 17:58:29,126 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-09 17:58:29,126 INFO L276 IsEmpty]: Start isEmpty. Operand 1472 states and 1785 transitions. [2018-12-09 17:58:29,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-12-09 17:58:29,127 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:29,128 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:29,128 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:29,128 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:29,128 INFO L82 PathProgramCache]: Analyzing trace with hash 1854992155, now seen corresponding path program 1 times [2018-12-09 17:58:29,128 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:29,128 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 13 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:29,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:29,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:29,264 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:29,321 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:29,321 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:29,450 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:29,452 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:58:29,452 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 17:58:29,459 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:29,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:29,522 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:29,527 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:29,527 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:29,620 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:29,636 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-12-09 17:58:29,636 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-12-09 17:58:29,636 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-12-09 17:58:29,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-12-09 17:58:29,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-12-09 17:58:29,637 INFO L87 Difference]: Start difference. First operand 1472 states and 1785 transitions. Second operand 14 states. [2018-12-09 17:58:30,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:30,932 INFO L93 Difference]: Finished difference Result 2860 states and 3465 transitions. [2018-12-09 17:58:30,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-12-09 17:58:30,932 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 88 [2018-12-09 17:58:30,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:30,935 INFO L225 Difference]: With dead ends: 2860 [2018-12-09 17:58:30,935 INFO L226 Difference]: Without dead ends: 1414 [2018-12-09 17:58:30,937 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 359 GetRequests, 337 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=115, Invalid=347, Unknown=0, NotChecked=0, Total=462 [2018-12-09 17:58:30,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states. [2018-12-09 17:58:30,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 398. [2018-12-09 17:58:30,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 398 states. [2018-12-09 17:58:30,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 398 states to 398 states and 465 transitions. [2018-12-09 17:58:30,965 INFO L78 Accepts]: Start accepts. Automaton has 398 states and 465 transitions. Word has length 88 [2018-12-09 17:58:30,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:30,965 INFO L480 AbstractCegarLoop]: Abstraction has 398 states and 465 transitions. [2018-12-09 17:58:30,965 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-12-09 17:58:30,965 INFO L276 IsEmpty]: Start isEmpty. Operand 398 states and 465 transitions. [2018-12-09 17:58:30,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-12-09 17:58:30,966 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:30,966 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:30,966 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:30,966 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:30,966 INFO L82 PathProgramCache]: Analyzing trace with hash -1289094802, now seen corresponding path program 1 times [2018-12-09 17:58:30,967 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:30,967 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 15 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:30,983 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:31,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:31,095 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:31,109 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 17:58:31,109 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-09 17:58:31,111 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:58:31,111 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 17:58:31,111 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 17:58:31,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 17:58:31,111 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:58:31,112 INFO L87 Difference]: Start difference. First operand 398 states and 465 transitions. Second operand 3 states. [2018-12-09 17:58:31,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:31,217 INFO L93 Difference]: Finished difference Result 852 states and 1012 transitions. [2018-12-09 17:58:31,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 17:58:31,217 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 97 [2018-12-09 17:58:31,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:31,218 INFO L225 Difference]: With dead ends: 852 [2018-12-09 17:58:31,218 INFO L226 Difference]: Without dead ends: 480 [2018-12-09 17:58:31,219 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:58:31,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states. [2018-12-09 17:58:31,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2018-12-09 17:58:31,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2018-12-09 17:58:31,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 566 transitions. [2018-12-09 17:58:31,244 INFO L78 Accepts]: Start accepts. Automaton has 480 states and 566 transitions. Word has length 97 [2018-12-09 17:58:31,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:31,244 INFO L480 AbstractCegarLoop]: Abstraction has 480 states and 566 transitions. [2018-12-09 17:58:31,245 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 17:58:31,245 INFO L276 IsEmpty]: Start isEmpty. Operand 480 states and 566 transitions. [2018-12-09 17:58:31,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-12-09 17:58:31,245 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:31,246 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:31,246 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:31,246 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:31,246 INFO L82 PathProgramCache]: Analyzing trace with hash -94289413, now seen corresponding path program 1 times [2018-12-09 17:58:31,246 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:31,246 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 16 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:31,270 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:31,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:31,377 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:31,385 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-12-09 17:58:31,385 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-09 17:58:31,386 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:58:31,386 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-12-09 17:58:31,387 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 17:58:31,387 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 17:58:31,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:58:31,387 INFO L87 Difference]: Start difference. First operand 480 states and 566 transitions. Second operand 3 states. [2018-12-09 17:58:31,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:31,504 INFO L93 Difference]: Finished difference Result 1169 states and 1373 transitions. [2018-12-09 17:58:31,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 17:58:31,504 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 114 [2018-12-09 17:58:31,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:31,505 INFO L225 Difference]: With dead ends: 1169 [2018-12-09 17:58:31,505 INFO L226 Difference]: Without dead ends: 715 [2018-12-09 17:58:31,506 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 17:58:31,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 715 states. [2018-12-09 17:58:31,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 715 to 712. [2018-12-09 17:58:31,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 712 states. [2018-12-09 17:58:31,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 712 states to 712 states and 824 transitions. [2018-12-09 17:58:31,543 INFO L78 Accepts]: Start accepts. Automaton has 712 states and 824 transitions. Word has length 114 [2018-12-09 17:58:31,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:31,544 INFO L480 AbstractCegarLoop]: Abstraction has 712 states and 824 transitions. [2018-12-09 17:58:31,544 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 17:58:31,544 INFO L276 IsEmpty]: Start isEmpty. Operand 712 states and 824 transitions. [2018-12-09 17:58:31,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-12-09 17:58:31,544 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:31,545 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:31,545 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:31,545 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:31,545 INFO L82 PathProgramCache]: Analyzing trace with hash -1420932234, now seen corresponding path program 1 times [2018-12-09 17:58:31,545 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:31,545 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 17 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:31,562 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:31,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:31,890 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:31,900 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 17:58:31,901 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-12-09 17:58:31,904 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 17:58:31,904 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 17:58:31,904 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 17:58:31,904 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 17:58:31,904 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 17:58:31,905 INFO L87 Difference]: Start difference. First operand 712 states and 824 transitions. Second operand 4 states. [2018-12-09 17:58:31,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:31,956 INFO L93 Difference]: Finished difference Result 1402 states and 1625 transitions. [2018-12-09 17:58:31,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 17:58:31,957 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 115 [2018-12-09 17:58:31,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:31,958 INFO L225 Difference]: With dead ends: 1402 [2018-12-09 17:58:31,958 INFO L226 Difference]: Without dead ends: 713 [2018-12-09 17:58:31,959 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-12-09 17:58:31,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 713 states. [2018-12-09 17:58:31,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 713 to 713. [2018-12-09 17:58:31,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 713 states. [2018-12-09 17:58:31,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 713 states to 713 states and 825 transitions. [2018-12-09 17:58:31,993 INFO L78 Accepts]: Start accepts. Automaton has 713 states and 825 transitions. Word has length 115 [2018-12-09 17:58:31,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:31,994 INFO L480 AbstractCegarLoop]: Abstraction has 713 states and 825 transitions. [2018-12-09 17:58:31,994 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 17:58:31,994 INFO L276 IsEmpty]: Start isEmpty. Operand 713 states and 825 transitions. [2018-12-09 17:58:31,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-12-09 17:58:31,995 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:31,995 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:31,995 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:31,996 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:31,996 INFO L82 PathProgramCache]: Analyzing trace with hash 732072980, now seen corresponding path program 1 times [2018-12-09 17:58:31,996 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:31,996 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 18 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:32,015 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:32,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:32,329 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:32,348 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 17:58:32,348 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:32,424 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-09 17:58:32,427 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 17:58:32,427 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 17:58:32,435 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 17:58:32,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 17:58:32,523 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 17:58:32,528 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-12-09 17:58:32,528 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 17:58:32,573 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-12-09 17:58:32,588 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-12-09 17:58:32,589 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5] total 8 [2018-12-09 17:58:32,589 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-12-09 17:58:32,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-12-09 17:58:32,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-12-09 17:58:32,590 INFO L87 Difference]: Start difference. First operand 713 states and 825 transitions. Second operand 8 states. [2018-12-09 17:58:32,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 17:58:32,700 INFO L93 Difference]: Finished difference Result 1407 states and 1632 transitions. [2018-12-09 17:58:32,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-12-09 17:58:32,701 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 116 [2018-12-09 17:58:32,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 17:58:32,702 INFO L225 Difference]: With dead ends: 1407 [2018-12-09 17:58:32,702 INFO L226 Difference]: Without dead ends: 716 [2018-12-09 17:58:32,703 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 464 GetRequests, 454 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-12-09 17:58:32,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 716 states. [2018-12-09 17:58:32,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 716 to 716. [2018-12-09 17:58:32,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 716 states. [2018-12-09 17:58:32,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 716 states and 828 transitions. [2018-12-09 17:58:32,735 INFO L78 Accepts]: Start accepts. Automaton has 716 states and 828 transitions. Word has length 116 [2018-12-09 17:58:32,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 17:58:32,735 INFO L480 AbstractCegarLoop]: Abstraction has 716 states and 828 transitions. [2018-12-09 17:58:32,736 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-12-09 17:58:32,736 INFO L276 IsEmpty]: Start isEmpty. Operand 716 states and 828 transitions. [2018-12-09 17:58:32,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-12-09 17:58:32,737 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 17:58:32,737 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 17:58:32,737 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 17:58:32,737 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 17:58:32,737 INFO L82 PathProgramCache]: Analyzing trace with hash 1051230966, now seen corresponding path program 2 times [2018-12-09 17:58:32,737 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-12-09 17:58:32,737 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/cvc4 Starting monitored process 20 with cvc4 --incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --incremental --print-success --lang smt --rewrite-divk [2018-12-09 17:58:32,754 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-12-09 17:58:33,499 ERROR L235 seRefinementStrategy]: Caught known exception: Array theory solver does not yet support write-chains connecting two different constant arrays [2018-12-09 17:58:33,499 INFO L258 seRefinementStrategy]: Advancing trace checker [2018-12-09 17:58:33,499 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9bbe8743-c182-456e-8ef6-af0b2e4623f2/bin-2019/utaipan/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2018-12-09 17:58:33,509 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-12-09 17:58:34,525 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-12-09 17:58:34,525 INFO L250 tOrderPrioritization]: Conjunction of SSA is sat [2018-12-09 17:58:36,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 17:58:36,742 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-09 17:58:36,805 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2018-12-09 17:58:36,842 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-09 17:58:36,843 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time [2018-12-09 17:58:36,843 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-09 17:58:36,843 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-09 17:58:36,843 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device [2018-12-09 17:58:36,843 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-09 17:58:36,843 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm [2018-12-09 17:58:36,843 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-12-09 17:58:36,844 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-09 17:58:36,844 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-09 17:58:36,844 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-09 17:58:36,844 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-12-09 17:58:36,844 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-09 17:58:36,844 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm [2018-12-09 17:58:36,844 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-09 17:58:36,844 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time [2018-12-09 17:58:36,844 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-12-09 17:58:36,845 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,845 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device [2018-12-09 17:58:36,845 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,846 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,847 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,847 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,848 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,849 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,849 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,850 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,850 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,851 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,851 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,852 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,852 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,853 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,853 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,854 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,854 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,855 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,856 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,856 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,857 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,857 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,857 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,857 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,858 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,858 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,858 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,858 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,859 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,859 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,859 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,860 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,860 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,860 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,861 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,861 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,862 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,862 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,862 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,863 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,863 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,863 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,863 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,864 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,864 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,864 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,864 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,864 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,865 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,865 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,866 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,866 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,866 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,867 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,867 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,867 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,868 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,868 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,868 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,869 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,869 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,869 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,869 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,869 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,870 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,870 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,870 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,870 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,870 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,870 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,871 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,871 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,871 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,871 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,872 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,872 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,872 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,872 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,872 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,873 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,873 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,873 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,874 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,874 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,874 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,874 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,874 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,875 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,875 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,875 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,875 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,875 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,876 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,876 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,876 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,876 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,876 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,877 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,877 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,877 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,877 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,877 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,878 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,878 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,878 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,878 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,878 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,878 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,878 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,879 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,879 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,879 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-12-09 17:58:36,879 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,879 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,880 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,880 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,880 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,880 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,881 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,881 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,882 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,882 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,882 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,882 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,883 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,883 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,883 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,884 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,884 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,884 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,885 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,885 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,885 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,885 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,886 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,886 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,886 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,886 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,887 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,887 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,888 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,888 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,888 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,888 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,889 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,889 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,890 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,890 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,890 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,890 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,891 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,891 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,891 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,891 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,892 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,892 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,892 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,892 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,893 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,893 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-12-09 17:58:36,905 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 09.12 05:58:36 BoogieIcfgContainer [2018-12-09 17:58:36,905 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-09 17:58:36,905 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-09 17:58:36,906 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-09 17:58:36,906 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-09 17:58:36,906 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 05:58:19" (3/4) ... [2018-12-09 17:58:36,908 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-12-09 17:58:36,908 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-09 17:58:36,909 INFO L168 Benchmark]: Toolchain (without parser) took 20850.63 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 515.4 MB). Free memory was 936.7 MB in the beginning and 1.2 GB in the end (delta: -250.2 MB). Peak memory consumption was 265.1 MB. Max. memory is 11.5 GB. [2018-12-09 17:58:36,910 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 972.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 17:58:36,910 INFO L168 Benchmark]: CACSL2BoogieTranslator took 743.58 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.4 MB). Free memory was 936.7 MB in the beginning and 1.1 GB in the end (delta: -162.1 MB). Peak memory consumption was 67.0 MB. Max. memory is 11.5 GB. [2018-12-09 17:58:36,910 INFO L168 Benchmark]: Boogie Procedure Inliner took 38.48 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 17:58:36,910 INFO L168 Benchmark]: Boogie Preprocessor took 59.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 13.2 MB). Peak memory consumption was 13.2 MB. Max. memory is 11.5 GB. [2018-12-09 17:58:36,911 INFO L168 Benchmark]: RCFGBuilder took 2934.08 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 954.3 MB in the end (delta: 131.3 MB). Peak memory consumption was 131.3 MB. Max. memory is 11.5 GB. [2018-12-09 17:58:36,911 INFO L168 Benchmark]: TraceAbstraction took 17068.25 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 367.0 MB). Free memory was 947.6 MB in the beginning and 1.2 GB in the end (delta: -239.3 MB). Peak memory consumption was 127.7 MB. Max. memory is 11.5 GB. [2018-12-09 17:58:36,911 INFO L168 Benchmark]: Witness Printer took 3.04 ms. Allocated memory is still 1.5 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 17:58:36,912 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 972.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 743.58 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.4 MB). Free memory was 936.7 MB in the beginning and 1.1 GB in the end (delta: -162.1 MB). Peak memory consumption was 67.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 38.48 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 59.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 13.2 MB). Peak memory consumption was 13.2 MB. Max. memory is 11.5 GB. * RCFGBuilder took 2934.08 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 954.3 MB in the end (delta: 131.3 MB). Peak memory consumption was 131.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 17068.25 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 367.0 MB). Free memory was 947.6 MB in the beginning and 1.2 GB in the end (delta: -239.3 MB). Peak memory consumption was 127.7 MB. Max. memory is 11.5 GB. * Witness Printer took 3.04 ms. Allocated memory is still 1.5 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1664]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of large string literal at line 2219. Possible FailurePath: [L1687] int ldv_irq_1_2 = 0; [L1688] int LDV_IN_INTERRUPT = 1; [L1689] int ldv_irq_1_3 = 0; [L1690] struct platform_device *tegra_rtc_driver_group0 ; [L1691] void *ldv_irq_data_1_1 ; [L1692] int ldv_irq_1_1 = 0; [L1693] int ldv_irq_1_0 = 0; [L1694] int ldv_irq_line_1_3 ; [L1695] void *ldv_irq_data_1_0 ; [L1696] int ldv_state_variable_0 ; [L1697] struct device *tegra_rtc_ops_group1 ; [L1698] int ldv_state_variable_3 ; [L1699] int ldv_irq_line_1_0 ; [L1700] int ldv_state_variable_2 ; [L1701] void *ldv_irq_data_1_3 ; [L1702] int ref_cnt ; [L1703] int ldv_irq_line_1_1 ; [L1704] struct rtc_time *tegra_rtc_ops_group0 ; [L1705] void *ldv_irq_data_1_2 ; [L1706] int ldv_state_variable_1 ; [L1707] int ldv_irq_line_1_2 ; [L1708] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2050-L2052] static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2218-L2219] static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2235] int ldv_retval_2 ; [L2236] int ldv_retval_0 ; [L2238] int ldv_retval_1 ; [L2761] int ldv_init = 0; VAL [\old(LDV_IN_INTERRUPT)=0, \old(ldv_init)=0, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_line_1_0)=0, \old(ldv_irq_line_1_1)=0, \old(ldv_irq_line_1_2)=0, \old(ldv_irq_line_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group2)=null, \old(tegra_rtc_ops_group2)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2390] struct seq_file *ldvarg1 ; [L2391] void *tmp ; [L2392] unsigned int ldvarg0 ; [L2393] unsigned int tmp___0 ; [L2394] pm_message_t ldvarg2 ; [L2395] int tmp___1 ; [L2396] int tmp___2 ; [L2397] int tmp___3 ; [L2398] int tmp___4 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] CALL, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, size=136, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2400] RET, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_zalloc(136U)={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] tmp = ldv_zalloc(136U) [L2401] ldvarg1 = (struct seq_file *)tmp [L2402] tmp___0 = __VERIFIER_nondet_uint() [L2403] ldvarg0 = tmp___0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2404] FCALL ldv_initialize() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2405] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, memset((void *)(& ldvarg2), 0, 4U)={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2406] ldv_state_variable_1 = 1 [L2407] ref_cnt = 0 [L2408] ldv_state_variable_0 = 1 [L2409] ldv_state_variable_3 = 0 [L2410] ldv_state_variable_2 = 0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1] [L2421] COND TRUE ldv_state_variable_0 != 0 [L2422] tmp___2 = __VERIFIER_nondet_int() [L2424] case 0: [L2432] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2433] COND TRUE ldv_state_variable_0 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2434] CALL, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2222] int tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] CALL, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={1:0}, arg1={-1:11}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2842] return __VERIFIER_nondet_int(); [L2224] RET, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe)=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2225] return (tmp); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp=0] [L2434] RET, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_init()=0, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2434] ldv_retval_0 = tegra_rtc_init() [L2435] COND TRUE ldv_retval_0 == 0 [L2436] ldv_state_variable_0 = 3 [L2437] ldv_state_variable_2 = 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2438] CALL ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2355] void *tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] CALL, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, size=624, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2357] RET, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] tmp = ldv_zalloc(624U) [L2358] tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2438] RET ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2441] COND FALSE !(ldv_retval_0 != 0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: [L2566] case 1: [L2576] case 2: [L2596] case 3: [L2606] case 4: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2607] COND TRUE ldv_state_variable_2 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2608] CALL ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2830] return __VERIFIER_nondet_int(); [L2608] RET ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_probe_2()=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2609] ldv_state_variable_2 = 2 [L2610] ref_cnt = ref_cnt + 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2555] COND FALSE !(ldv_state_variable_2 == 4) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2560] COND TRUE ldv_state_variable_2 == 2 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={2:0}, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2561] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2214] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1952] struct tegra_rtc_info *info ; [L1953] void *tmp ; [L1954] unsigned int status ; [L1955] unsigned long sl_irq_flags ; [L1956] u32 __v ; [L1957] u32 __v___0 ; VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_nondet_pointer(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, arg0={0:12}, external_alloc()={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1959] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={0:0}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] tmp = dev_get_drvdata((struct device const *)dev) [L1960] info = (struct tegra_rtc_info *)tmp VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L1961] CALL tegra_rtc_wait_while_busy(dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1835] struct tegra_rtc_info *info ; [L1836] void *tmp ; [L1837] int retries ; [L1838] int tmp___0 ; [L1839] u32 tmp___1 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_nondet_pointer(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, arg0={0:12}, arg0={0:12}, external_alloc()={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1841] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, dev_get_drvdata((struct device const *)dev)={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] tmp = dev_get_drvdata((struct device const *)dev) [L1842] info = (struct tegra_rtc_info *)tmp [L1843] retries = 500 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L1854] CALL, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1825] u32 __v ; [L1826] u32 __v___0 ; [L1828] EXPR info->rtc_base [L1828] EXPR (unsigned int volatile *)info->rtc_base + 4U [L1828] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1829] __v = __v___0 [L1830] return (__v & 1U); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, __v=0, __v___0=0, info={0:0}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1854] RET, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_check_busy(info)=0, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L1854] tmp___1 = tegra_rtc_check_busy(info) [L1855] COND FALSE !(tmp___1 != 0U) [L1859] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, dev={0:12}, dev={0:12}, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___1=0] [L1961] RET tegra_rtc_wait_while_busy(dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={0:0}] [L1962] CALL ldv_spin_lock_check() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2775] COND FALSE !(ldv_init == 1) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2777] CALL ldv_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1664] __VERIFIER_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={1:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={12:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 65 procedures, 488 locations, 1 error locations. UNSAFE Result, 17.0s OverallTime, 15 OverallIterations, 4 TraceHistogramMax, 7.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5825 SDtfs, 6314 SDslu, 13689 SDs, 0 SdLazy, 5132 SolverSat, 918 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2447 GetRequests, 2311 SyntacticMatches, 9 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 1.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1472occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.5s AutomataMinimizationTime, 14 MinimizatonAttempts, 1769 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.5s SsaConstructionTime, 2.5s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 1685 NumberOfCodeBlocks, 1685 NumberOfCodeBlocksAsserted, 20 NumberOfCheckSat, 2378 ConstructedInterpolants, 0 QuantifiedInterpolants, 389916 SizeOfPredicates, 60 NumberOfNonLiveVariables, 9353 ConjunctsInSsa, 138 ConjunctsInUnsatCore, 27 InterpolantComputations, 10 PerfectInterpolantSequences, 355/435 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request...