./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 635dfa2a Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-635dfa2 [2018-12-09 13:29:09,055 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-12-09 13:29:09,055 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-12-09 13:29:09,061 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-12-09 13:29:09,062 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-12-09 13:29:09,062 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-12-09 13:29:09,063 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-12-09 13:29:09,063 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-12-09 13:29:09,064 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-12-09 13:29:09,065 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-12-09 13:29:09,065 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-12-09 13:29:09,065 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-12-09 13:29:09,066 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-12-09 13:29:09,066 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-12-09 13:29:09,066 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-12-09 13:29:09,067 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-12-09 13:29:09,067 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-12-09 13:29:09,068 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-12-09 13:29:09,069 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-12-09 13:29:09,070 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-12-09 13:29:09,070 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-12-09 13:29:09,070 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-12-09 13:29:09,072 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-12-09 13:29:09,072 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-12-09 13:29:09,072 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-12-09 13:29:09,072 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-12-09 13:29:09,073 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-12-09 13:29:09,073 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-12-09 13:29:09,073 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-12-09 13:29:09,074 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-12-09 13:29:09,074 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-12-09 13:29:09,074 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-12-09 13:29:09,074 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-12-09 13:29:09,075 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-12-09 13:29:09,075 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-12-09 13:29:09,075 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-12-09 13:29:09,075 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-12-09 13:29:09,082 INFO L110 SettingsManager]: Loading preferences was successful [2018-12-09 13:29:09,082 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-12-09 13:29:09,083 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-12-09 13:29:09,083 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-12-09 13:29:09,083 INFO L133 SettingsManager]: * User list type=DISABLED [2018-12-09 13:29:09,083 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-12-09 13:29:09,083 INFO L133 SettingsManager]: * Explicit value domain=true [2018-12-09 13:29:09,083 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-12-09 13:29:09,083 INFO L133 SettingsManager]: * Octagon Domain=false [2018-12-09 13:29:09,083 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-12-09 13:29:09,084 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-12-09 13:29:09,084 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-12-09 13:29:09,084 INFO L133 SettingsManager]: * Interval Domain=false [2018-12-09 13:29:09,084 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-12-09 13:29:09,084 INFO L133 SettingsManager]: * sizeof long=4 [2018-12-09 13:29:09,084 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-12-09 13:29:09,084 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-12-09 13:29:09,084 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-12-09 13:29:09,084 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-12-09 13:29:09,085 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-12-09 13:29:09,085 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-12-09 13:29:09,085 INFO L133 SettingsManager]: * sizeof long double=12 [2018-12-09 13:29:09,085 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-12-09 13:29:09,085 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-12-09 13:29:09,085 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-12-09 13:29:09,085 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-12-09 13:29:09,085 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-12-09 13:29:09,085 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-12-09 13:29:09,085 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 13:29:09,086 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-12-09 13:29:09,086 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-12-09 13:29:09,086 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-12-09 13:29:09,086 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-12-09 13:29:09,086 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-12-09 13:29:09,086 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-12-09 13:29:09,086 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-12-09 13:29:09,086 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2018-12-09 13:29:09,103 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-12-09 13:29:09,109 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-12-09 13:29:09,111 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-12-09 13:29:09,112 INFO L271 PluginConnector]: Initializing CDTParser... [2018-12-09 13:29:09,112 INFO L276 PluginConnector]: CDTParser initialized [2018-12-09 13:29:09,112 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-12-09 13:29:09,145 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/data/640a3c7da/07e7d178cc62482eb8e25e5e9c1566e0/FLAG871c80fda [2018-12-09 13:29:09,525 INFO L307 CDTParser]: Found 1 translation units. [2018-12-09 13:29:09,525 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-12-09 13:29:09,530 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/data/640a3c7da/07e7d178cc62482eb8e25e5e9c1566e0/FLAG871c80fda [2018-12-09 13:29:09,538 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/data/640a3c7da/07e7d178cc62482eb8e25e5e9c1566e0 [2018-12-09 13:29:09,540 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-12-09 13:29:09,541 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-12-09 13:29:09,541 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-12-09 13:29:09,541 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-12-09 13:29:09,543 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-12-09 13:29:09,544 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 01:29:09" (1/1) ... [2018-12-09 13:29:09,545 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@706fcb08 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09, skipping insertion in model container [2018-12-09 13:29:09,545 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.12 01:29:09" (1/1) ... [2018-12-09 13:29:09,549 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-12-09 13:29:09,566 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-12-09 13:29:09,677 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 13:29:09,681 INFO L191 MainTranslator]: Completed pre-run [2018-12-09 13:29:09,707 INFO L203 PostProcessor]: Analyzing one entry point: main [2018-12-09 13:29:09,717 INFO L195 MainTranslator]: Completed translation [2018-12-09 13:29:09,717 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09 WrapperNode [2018-12-09 13:29:09,717 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-12-09 13:29:09,718 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-12-09 13:29:09,718 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-12-09 13:29:09,718 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-12-09 13:29:09,723 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09" (1/1) ... [2018-12-09 13:29:09,727 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09" (1/1) ... [2018-12-09 13:29:09,739 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-12-09 13:29:09,740 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-12-09 13:29:09,740 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-12-09 13:29:09,740 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-12-09 13:29:09,746 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09" (1/1) ... [2018-12-09 13:29:09,746 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09" (1/1) ... [2018-12-09 13:29:09,748 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09" (1/1) ... [2018-12-09 13:29:09,748 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09" (1/1) ... [2018-12-09 13:29:09,754 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09" (1/1) ... [2018-12-09 13:29:09,761 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09" (1/1) ... [2018-12-09 13:29:09,762 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09" (1/1) ... [2018-12-09 13:29:09,789 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-12-09 13:29:09,789 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-12-09 13:29:09,789 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-12-09 13:29:09,789 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-12-09 13:29:09,790 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-12-09 13:29:09,823 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-12-09 13:29:09,823 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-12-09 13:29:09,823 INFO L130 BoogieDeclarations]: Found specification of procedure transmit3 [2018-12-09 13:29:09,823 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit3 [2018-12-09 13:29:09,823 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-12-09 13:29:09,823 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-12-09 13:29:09,823 INFO L130 BoogieDeclarations]: Found specification of procedure transmit4 [2018-12-09 13:29:09,823 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit4 [2018-12-09 13:29:09,824 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-12-09 13:29:09,824 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-12-09 13:29:09,824 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-12-09 13:29:09,824 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-12-09 13:29:09,824 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-12-09 13:29:09,824 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-12-09 13:29:09,824 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-12-09 13:29:09,824 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-12-09 13:29:09,824 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-12-09 13:29:09,824 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-12-09 13:29:09,824 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-12-09 13:29:09,824 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-12-09 13:29:09,824 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-12-09 13:29:09,824 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-12-09 13:29:09,824 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit4_triggered [2018-12-09 13:29:09,825 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit4_triggered [2018-12-09 13:29:09,825 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-12-09 13:29:09,825 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-12-09 13:29:09,825 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-12-09 13:29:09,825 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-12-09 13:29:09,825 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-12-09 13:29:09,825 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-12-09 13:29:09,825 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-12-09 13:29:09,825 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-12-09 13:29:09,825 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-12-09 13:29:09,825 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-12-09 13:29:09,825 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-12-09 13:29:09,825 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-12-09 13:29:09,825 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-12-09 13:29:09,825 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-12-09 13:29:09,826 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-12-09 13:29:09,826 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-12-09 13:29:09,826 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-12-09 13:29:09,826 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-12-09 13:29:09,826 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-12-09 13:29:09,826 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-12-09 13:29:09,826 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit3_triggered [2018-12-09 13:29:09,826 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit3_triggered [2018-12-09 13:29:09,826 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-12-09 13:29:09,826 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-12-09 13:29:09,826 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-12-09 13:29:09,826 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-12-09 13:29:09,826 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-12-09 13:29:09,826 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-12-09 13:29:09,826 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-12-09 13:29:09,827 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-12-09 13:29:10,142 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-12-09 13:29:10,142 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-12-09 13:29:10,142 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 01:29:10 BoogieIcfgContainer [2018-12-09 13:29:10,142 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-12-09 13:29:10,143 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-12-09 13:29:10,143 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-12-09 13:29:10,144 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-12-09 13:29:10,145 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 09.12 01:29:09" (1/3) ... [2018-12-09 13:29:10,145 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31995ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 01:29:10, skipping insertion in model container [2018-12-09 13:29:10,145 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.12 01:29:09" (2/3) ... [2018-12-09 13:29:10,145 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31995ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 09.12 01:29:10, skipping insertion in model container [2018-12-09 13:29:10,145 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 01:29:10" (3/3) ... [2018-12-09 13:29:10,146 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.04_false-unreach-call_false-termination.cil.c [2018-12-09 13:29:10,152 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-12-09 13:29:10,157 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-12-09 13:29:10,170 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-12-09 13:29:10,192 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-12-09 13:29:10,192 INFO L383 AbstractCegarLoop]: Hoare is true [2018-12-09 13:29:10,193 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-12-09 13:29:10,193 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-12-09 13:29:10,193 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-12-09 13:29:10,193 INFO L387 AbstractCegarLoop]: Difference is false [2018-12-09 13:29:10,193 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-12-09 13:29:10,193 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-12-09 13:29:10,205 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states. [2018-12-09 13:29:10,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:10,212 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:10,212 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:10,213 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:10,216 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:10,217 INFO L82 PathProgramCache]: Analyzing trace with hash -2019614736, now seen corresponding path program 1 times [2018-12-09 13:29:10,218 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:10,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:10,246 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:10,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:10,246 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:10,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:10,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:10,398 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:10,398 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:10,399 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:10,402 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:10,410 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:10,410 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:10,412 INFO L87 Difference]: Start difference. First operand 229 states. Second operand 5 states. [2018-12-09 13:29:10,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:10,792 INFO L93 Difference]: Finished difference Result 475 states and 713 transitions. [2018-12-09 13:29:10,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:29:10,793 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-09 13:29:10,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:10,803 INFO L225 Difference]: With dead ends: 475 [2018-12-09 13:29:10,803 INFO L226 Difference]: Without dead ends: 256 [2018-12-09 13:29:10,807 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:10,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-12-09 13:29:10,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 220. [2018-12-09 13:29:10,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-09 13:29:10,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 304 transitions. [2018-12-09 13:29:10,857 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 304 transitions. Word has length 120 [2018-12-09 13:29:10,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:10,858 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 304 transitions. [2018-12-09 13:29:10,858 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:10,858 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 304 transitions. [2018-12-09 13:29:10,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:10,861 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:10,861 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:10,861 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:10,861 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:10,862 INFO L82 PathProgramCache]: Analyzing trace with hash 1218621358, now seen corresponding path program 1 times [2018-12-09 13:29:10,862 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:10,862 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:10,862 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:10,863 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:10,863 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:10,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:10,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:10,947 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:10,947 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:10,947 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:10,948 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:10,948 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:10,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:10,948 INFO L87 Difference]: Start difference. First operand 220 states and 304 transitions. Second operand 5 states. [2018-12-09 13:29:11,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:11,218 INFO L93 Difference]: Finished difference Result 454 states and 646 transitions. [2018-12-09 13:29:11,218 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:29:11,218 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-09 13:29:11,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:11,220 INFO L225 Difference]: With dead ends: 454 [2018-12-09 13:29:11,220 INFO L226 Difference]: Without dead ends: 256 [2018-12-09 13:29:11,222 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:11,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-12-09 13:29:11,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 220. [2018-12-09 13:29:11,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-09 13:29:11,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 303 transitions. [2018-12-09 13:29:11,240 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 303 transitions. Word has length 120 [2018-12-09 13:29:11,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:11,240 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 303 transitions. [2018-12-09 13:29:11,240 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:11,240 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 303 transitions. [2018-12-09 13:29:11,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:11,242 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:11,242 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:11,243 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:11,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:11,243 INFO L82 PathProgramCache]: Analyzing trace with hash -1724960720, now seen corresponding path program 1 times [2018-12-09 13:29:11,243 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:11,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:11,244 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:11,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:11,244 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:11,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:11,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:11,327 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:11,328 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:11,328 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:11,328 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:11,328 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:11,328 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:11,328 INFO L87 Difference]: Start difference. First operand 220 states and 303 transitions. Second operand 5 states. [2018-12-09 13:29:11,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:11,607 INFO L93 Difference]: Finished difference Result 452 states and 640 transitions. [2018-12-09 13:29:11,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:29:11,607 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-09 13:29:11,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:11,608 INFO L225 Difference]: With dead ends: 452 [2018-12-09 13:29:11,609 INFO L226 Difference]: Without dead ends: 254 [2018-12-09 13:29:11,609 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:11,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 254 states. [2018-12-09 13:29:11,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 254 to 220. [2018-12-09 13:29:11,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-09 13:29:11,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 302 transitions. [2018-12-09 13:29:11,621 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 302 transitions. Word has length 120 [2018-12-09 13:29:11,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:11,621 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 302 transitions. [2018-12-09 13:29:11,621 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:11,621 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 302 transitions. [2018-12-09 13:29:11,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:11,622 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:11,622 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:11,622 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:11,622 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:11,622 INFO L82 PathProgramCache]: Analyzing trace with hash 951031662, now seen corresponding path program 1 times [2018-12-09 13:29:11,623 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:11,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:11,623 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:11,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:11,623 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:11,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:11,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:11,662 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:11,662 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:11,662 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:11,663 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:11,663 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:11,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:11,663 INFO L87 Difference]: Start difference. First operand 220 states and 302 transitions. Second operand 5 states. [2018-12-09 13:29:11,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:11,894 INFO L93 Difference]: Finished difference Result 450 states and 634 transitions. [2018-12-09 13:29:11,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:29:11,894 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-09 13:29:11,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:11,895 INFO L225 Difference]: With dead ends: 450 [2018-12-09 13:29:11,896 INFO L226 Difference]: Without dead ends: 252 [2018-12-09 13:29:11,896 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:11,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252 states. [2018-12-09 13:29:11,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252 to 220. [2018-12-09 13:29:11,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-09 13:29:11,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 301 transitions. [2018-12-09 13:29:11,908 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 301 transitions. Word has length 120 [2018-12-09 13:29:11,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:11,908 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 301 transitions. [2018-12-09 13:29:11,908 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:11,908 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 301 transitions. [2018-12-09 13:29:11,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:11,909 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:11,909 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:11,910 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:11,910 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:11,910 INFO L82 PathProgramCache]: Analyzing trace with hash 67522672, now seen corresponding path program 1 times [2018-12-09 13:29:11,910 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:11,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:11,911 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:11,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:11,911 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:11,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:11,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:11,978 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:11,978 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:11,978 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:11,979 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:11,979 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:11,979 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:11,979 INFO L87 Difference]: Start difference. First operand 220 states and 301 transitions. Second operand 5 states. [2018-12-09 13:29:12,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:12,283 INFO L93 Difference]: Finished difference Result 471 states and 668 transitions. [2018-12-09 13:29:12,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:29:12,284 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-09 13:29:12,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:12,285 INFO L225 Difference]: With dead ends: 471 [2018-12-09 13:29:12,285 INFO L226 Difference]: Without dead ends: 273 [2018-12-09 13:29:12,285 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:12,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 273 states. [2018-12-09 13:29:12,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 273 to 220. [2018-12-09 13:29:12,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-09 13:29:12,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 300 transitions. [2018-12-09 13:29:12,296 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 300 transitions. Word has length 120 [2018-12-09 13:29:12,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:12,297 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 300 transitions. [2018-12-09 13:29:12,297 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:12,297 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 300 transitions. [2018-12-09 13:29:12,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:12,298 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:12,298 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:12,298 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:12,298 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:12,298 INFO L82 PathProgramCache]: Analyzing trace with hash -1873059342, now seen corresponding path program 1 times [2018-12-09 13:29:12,299 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:12,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:12,299 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:12,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:12,299 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:12,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:12,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:12,342 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:12,343 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:12,343 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:12,343 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:12,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:12,343 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:12,343 INFO L87 Difference]: Start difference. First operand 220 states and 300 transitions. Second operand 5 states. [2018-12-09 13:29:12,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:12,581 INFO L93 Difference]: Finished difference Result 469 states and 662 transitions. [2018-12-09 13:29:12,581 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:29:12,581 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-09 13:29:12,581 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:12,582 INFO L225 Difference]: With dead ends: 469 [2018-12-09 13:29:12,582 INFO L226 Difference]: Without dead ends: 271 [2018-12-09 13:29:12,583 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:12,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states. [2018-12-09 13:29:12,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 220. [2018-12-09 13:29:12,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-09 13:29:12,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 299 transitions. [2018-12-09 13:29:12,601 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 299 transitions. Word has length 120 [2018-12-09 13:29:12,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:12,601 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 299 transitions. [2018-12-09 13:29:12,601 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:12,601 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 299 transitions. [2018-12-09 13:29:12,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:12,602 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:12,603 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:12,603 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:12,603 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:12,603 INFO L82 PathProgramCache]: Analyzing trace with hash 4003888, now seen corresponding path program 1 times [2018-12-09 13:29:12,603 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:12,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:12,604 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:12,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:12,604 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:12,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:12,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:12,655 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:12,655 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:12,655 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:12,655 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:12,655 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:12,656 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:12,656 INFO L87 Difference]: Start difference. First operand 220 states and 299 transitions. Second operand 5 states. [2018-12-09 13:29:12,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:12,899 INFO L93 Difference]: Finished difference Result 467 states and 656 transitions. [2018-12-09 13:29:12,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:29:12,900 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-09 13:29:12,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:12,901 INFO L225 Difference]: With dead ends: 467 [2018-12-09 13:29:12,901 INFO L226 Difference]: Without dead ends: 269 [2018-12-09 13:29:12,901 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:12,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states. [2018-12-09 13:29:12,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 220. [2018-12-09 13:29:12,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-09 13:29:12,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 298 transitions. [2018-12-09 13:29:12,912 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 298 transitions. Word has length 120 [2018-12-09 13:29:12,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:12,912 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 298 transitions. [2018-12-09 13:29:12,912 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:12,912 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 298 transitions. [2018-12-09 13:29:12,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:12,913 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:12,913 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:12,913 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:12,913 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:12,913 INFO L82 PathProgramCache]: Analyzing trace with hash -766729678, now seen corresponding path program 1 times [2018-12-09 13:29:12,913 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:12,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:12,914 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:12,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:12,914 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:12,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:12,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:12,959 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:12,959 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:12,960 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:12,960 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:12,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:12,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:12,960 INFO L87 Difference]: Start difference. First operand 220 states and 298 transitions. Second operand 5 states. [2018-12-09 13:29:13,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:13,189 INFO L93 Difference]: Finished difference Result 465 states and 650 transitions. [2018-12-09 13:29:13,190 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:29:13,190 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 120 [2018-12-09 13:29:13,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:13,191 INFO L225 Difference]: With dead ends: 465 [2018-12-09 13:29:13,191 INFO L226 Difference]: Without dead ends: 267 [2018-12-09 13:29:13,192 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:13,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-12-09 13:29:13,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 220. [2018-12-09 13:29:13,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-12-09 13:29:13,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 297 transitions. [2018-12-09 13:29:13,205 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 297 transitions. Word has length 120 [2018-12-09 13:29:13,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:13,205 INFO L480 AbstractCegarLoop]: Abstraction has 220 states and 297 transitions. [2018-12-09 13:29:13,205 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:13,205 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 297 transitions. [2018-12-09 13:29:13,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:13,206 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:13,206 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:13,206 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:13,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:13,207 INFO L82 PathProgramCache]: Analyzing trace with hash -1761423376, now seen corresponding path program 1 times [2018-12-09 13:29:13,207 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:13,207 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:13,207 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:13,207 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:13,207 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:13,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:13,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:13,245 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:13,245 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 13:29:13,245 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:13,246 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 13:29:13,246 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 13:29:13,246 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:13,246 INFO L87 Difference]: Start difference. First operand 220 states and 297 transitions. Second operand 6 states. [2018-12-09 13:29:13,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:13,281 INFO L93 Difference]: Finished difference Result 436 states and 607 transitions. [2018-12-09 13:29:13,281 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 13:29:13,281 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-09 13:29:13,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:13,283 INFO L225 Difference]: With dead ends: 436 [2018-12-09 13:29:13,283 INFO L226 Difference]: Without dead ends: 239 [2018-12-09 13:29:13,283 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 13:29:13,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-12-09 13:29:13,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 225. [2018-12-09 13:29:13,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225 states. [2018-12-09 13:29:13,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 302 transitions. [2018-12-09 13:29:13,298 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 302 transitions. Word has length 120 [2018-12-09 13:29:13,298 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:13,298 INFO L480 AbstractCegarLoop]: Abstraction has 225 states and 302 transitions. [2018-12-09 13:29:13,298 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 13:29:13,298 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 302 transitions. [2018-12-09 13:29:13,299 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:13,299 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:13,299 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:13,299 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:13,299 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:13,299 INFO L82 PathProgramCache]: Analyzing trace with hash -27318926, now seen corresponding path program 1 times [2018-12-09 13:29:13,299 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:13,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:13,300 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:13,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:13,300 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:13,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:13,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:13,336 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:13,336 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 13:29:13,336 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:13,336 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 13:29:13,336 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 13:29:13,337 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 13:29:13,337 INFO L87 Difference]: Start difference. First operand 225 states and 302 transitions. Second operand 4 states. [2018-12-09 13:29:13,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:13,483 INFO L93 Difference]: Finished difference Result 622 states and 862 transitions. [2018-12-09 13:29:13,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 13:29:13,484 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-12-09 13:29:13,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:13,486 INFO L225 Difference]: With dead ends: 622 [2018-12-09 13:29:13,486 INFO L226 Difference]: Without dead ends: 420 [2018-12-09 13:29:13,487 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 13:29:13,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states. [2018-12-09 13:29:13,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 415. [2018-12-09 13:29:13,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 415 states. [2018-12-09 13:29:13,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 415 states to 415 states and 556 transitions. [2018-12-09 13:29:13,522 INFO L78 Accepts]: Start accepts. Automaton has 415 states and 556 transitions. Word has length 120 [2018-12-09 13:29:13,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:13,522 INFO L480 AbstractCegarLoop]: Abstraction has 415 states and 556 transitions. [2018-12-09 13:29:13,522 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 13:29:13,522 INFO L276 IsEmpty]: Start isEmpty. Operand 415 states and 556 transitions. [2018-12-09 13:29:13,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:13,523 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:13,523 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:13,523 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:13,523 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:13,524 INFO L82 PathProgramCache]: Analyzing trace with hash -512734447, now seen corresponding path program 1 times [2018-12-09 13:29:13,524 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:13,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:13,524 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:13,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:13,525 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:13,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:13,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:13,560 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:13,560 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 13:29:13,561 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:13,561 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 13:29:13,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 13:29:13,561 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:13,561 INFO L87 Difference]: Start difference. First operand 415 states and 556 transitions. Second operand 6 states. [2018-12-09 13:29:13,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:13,626 INFO L93 Difference]: Finished difference Result 823 states and 1130 transitions. [2018-12-09 13:29:13,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 13:29:13,626 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-09 13:29:13,626 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:13,627 INFO L225 Difference]: With dead ends: 823 [2018-12-09 13:29:13,627 INFO L226 Difference]: Without dead ends: 431 [2018-12-09 13:29:13,628 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 13:29:13,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431 states. [2018-12-09 13:29:13,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431 to 420. [2018-12-09 13:29:13,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 420 states. [2018-12-09 13:29:13,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 420 states to 420 states and 560 transitions. [2018-12-09 13:29:13,649 INFO L78 Accepts]: Start accepts. Automaton has 420 states and 560 transitions. Word has length 120 [2018-12-09 13:29:13,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:13,649 INFO L480 AbstractCegarLoop]: Abstraction has 420 states and 560 transitions. [2018-12-09 13:29:13,649 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 13:29:13,649 INFO L276 IsEmpty]: Start isEmpty. Operand 420 states and 560 transitions. [2018-12-09 13:29:13,650 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:13,650 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:13,650 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:13,650 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:13,650 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:13,650 INFO L82 PathProgramCache]: Analyzing trace with hash -1244701873, now seen corresponding path program 1 times [2018-12-09 13:29:13,650 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:13,651 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:13,651 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:13,651 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:13,651 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:13,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:13,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:13,689 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:13,689 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 13:29:13,689 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:13,689 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 13:29:13,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 13:29:13,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 13:29:13,689 INFO L87 Difference]: Start difference. First operand 420 states and 560 transitions. Second operand 4 states. [2018-12-09 13:29:13,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:13,848 INFO L93 Difference]: Finished difference Result 1201 states and 1654 transitions. [2018-12-09 13:29:13,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 13:29:13,848 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-12-09 13:29:13,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:13,850 INFO L225 Difference]: With dead ends: 1201 [2018-12-09 13:29:13,850 INFO L226 Difference]: Without dead ends: 804 [2018-12-09 13:29:13,851 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 13:29:13,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 804 states. [2018-12-09 13:29:13,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 804 to 797. [2018-12-09 13:29:13,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 797 states. [2018-12-09 13:29:13,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 797 states to 797 states and 1060 transitions. [2018-12-09 13:29:13,889 INFO L78 Accepts]: Start accepts. Automaton has 797 states and 1060 transitions. Word has length 120 [2018-12-09 13:29:13,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:13,889 INFO L480 AbstractCegarLoop]: Abstraction has 797 states and 1060 transitions. [2018-12-09 13:29:13,889 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 13:29:13,889 INFO L276 IsEmpty]: Start isEmpty. Operand 797 states and 1060 transitions. [2018-12-09 13:29:13,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:13,890 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:13,890 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:13,890 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:13,890 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:13,890 INFO L82 PathProgramCache]: Analyzing trace with hash -667773232, now seen corresponding path program 1 times [2018-12-09 13:29:13,890 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:13,890 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:13,890 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:13,891 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:13,891 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:13,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:13,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:13,931 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:13,931 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 13:29:13,931 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:13,932 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 13:29:13,932 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 13:29:13,932 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:13,932 INFO L87 Difference]: Start difference. First operand 797 states and 1060 transitions. Second operand 6 states. [2018-12-09 13:29:13,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:13,995 INFO L93 Difference]: Finished difference Result 1597 states and 2175 transitions. [2018-12-09 13:29:13,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 13:29:13,995 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-09 13:29:13,995 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:13,998 INFO L225 Difference]: With dead ends: 1597 [2018-12-09 13:29:13,998 INFO L226 Difference]: Without dead ends: 823 [2018-12-09 13:29:13,999 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 13:29:14,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 823 states. [2018-12-09 13:29:14,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 823 to 807. [2018-12-09 13:29:14,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 807 states. [2018-12-09 13:29:14,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1068 transitions. [2018-12-09 13:29:14,050 INFO L78 Accepts]: Start accepts. Automaton has 807 states and 1068 transitions. Word has length 120 [2018-12-09 13:29:14,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:14,050 INFO L480 AbstractCegarLoop]: Abstraction has 807 states and 1068 transitions. [2018-12-09 13:29:14,050 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 13:29:14,050 INFO L276 IsEmpty]: Start isEmpty. Operand 807 states and 1068 transitions. [2018-12-09 13:29:14,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:14,051 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:14,051 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:14,051 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:14,051 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:14,052 INFO L82 PathProgramCache]: Analyzing trace with hash 593144018, now seen corresponding path program 1 times [2018-12-09 13:29:14,052 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:14,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:14,052 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:14,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:14,052 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:14,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:14,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:14,094 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:14,095 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 13:29:14,095 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:14,095 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 13:29:14,095 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 13:29:14,095 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:14,095 INFO L87 Difference]: Start difference. First operand 807 states and 1068 transitions. Second operand 6 states. [2018-12-09 13:29:14,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:14,168 INFO L93 Difference]: Finished difference Result 1631 states and 2212 transitions. [2018-12-09 13:29:14,169 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 13:29:14,169 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2018-12-09 13:29:14,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:14,173 INFO L225 Difference]: With dead ends: 1631 [2018-12-09 13:29:14,173 INFO L226 Difference]: Without dead ends: 847 [2018-12-09 13:29:14,176 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 13:29:14,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 847 states. [2018-12-09 13:29:14,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 847 to 827. [2018-12-09 13:29:14,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 827 states. [2018-12-09 13:29:14,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 827 states to 827 states and 1088 transitions. [2018-12-09 13:29:14,248 INFO L78 Accepts]: Start accepts. Automaton has 827 states and 1088 transitions. Word has length 120 [2018-12-09 13:29:14,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:14,248 INFO L480 AbstractCegarLoop]: Abstraction has 827 states and 1088 transitions. [2018-12-09 13:29:14,248 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 13:29:14,248 INFO L276 IsEmpty]: Start isEmpty. Operand 827 states and 1088 transitions. [2018-12-09 13:29:14,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-12-09 13:29:14,248 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:14,248 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:14,249 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:14,249 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:14,249 INFO L82 PathProgramCache]: Analyzing trace with hash -1762661232, now seen corresponding path program 1 times [2018-12-09 13:29:14,249 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:14,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:14,249 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:14,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:14,249 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:14,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:14,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:29:14,281 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:14,281 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 13:29:14,281 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:14,281 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 13:29:14,281 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 13:29:14,281 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 13:29:14,281 INFO L87 Difference]: Start difference. First operand 827 states and 1088 transitions. Second operand 4 states. [2018-12-09 13:29:14,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:14,490 INFO L93 Difference]: Finished difference Result 2411 states and 3286 transitions. [2018-12-09 13:29:14,491 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 13:29:14,491 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 120 [2018-12-09 13:29:14,491 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:14,494 INFO L225 Difference]: With dead ends: 2411 [2018-12-09 13:29:14,495 INFO L226 Difference]: Without dead ends: 1607 [2018-12-09 13:29:14,497 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 13:29:14,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1607 states. [2018-12-09 13:29:14,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1607 to 1598. [2018-12-09 13:29:14,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1598 states. [2018-12-09 13:29:14,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1598 states to 1598 states and 2097 transitions. [2018-12-09 13:29:14,571 INFO L78 Accepts]: Start accepts. Automaton has 1598 states and 2097 transitions. Word has length 120 [2018-12-09 13:29:14,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:14,571 INFO L480 AbstractCegarLoop]: Abstraction has 1598 states and 2097 transitions. [2018-12-09 13:29:14,571 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 13:29:14,571 INFO L276 IsEmpty]: Start isEmpty. Operand 1598 states and 2097 transitions. [2018-12-09 13:29:14,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-09 13:29:14,572 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:14,572 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:14,573 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:14,573 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:14,573 INFO L82 PathProgramCache]: Analyzing trace with hash 1599710920, now seen corresponding path program 1 times [2018-12-09 13:29:14,573 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:14,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:14,573 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:14,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:14,573 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:14,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:14,609 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 13:29:14,609 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:14,609 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-12-09 13:29:14,609 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:14,609 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 13:29:14,609 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 13:29:14,609 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:14,609 INFO L87 Difference]: Start difference. First operand 1598 states and 2097 transitions. Second operand 6 states. [2018-12-09 13:29:14,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:14,748 INFO L93 Difference]: Finished difference Result 3201 states and 4303 transitions. [2018-12-09 13:29:14,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 13:29:14,749 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 141 [2018-12-09 13:29:14,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:14,755 INFO L225 Difference]: With dead ends: 3201 [2018-12-09 13:29:14,755 INFO L226 Difference]: Without dead ends: 1626 [2018-12-09 13:29:14,759 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-12-09 13:29:14,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1626 states. [2018-12-09 13:29:14,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1626 to 1618. [2018-12-09 13:29:14,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-09 13:29:14,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2113 transitions. [2018-12-09 13:29:14,844 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2113 transitions. Word has length 141 [2018-12-09 13:29:14,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:14,844 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2113 transitions. [2018-12-09 13:29:14,844 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 13:29:14,844 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2113 transitions. [2018-12-09 13:29:14,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-09 13:29:14,845 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:14,845 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:14,845 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:14,846 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:14,846 INFO L82 PathProgramCache]: Analyzing trace with hash 1801534854, now seen corresponding path program 1 times [2018-12-09 13:29:14,846 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:14,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:14,846 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:14,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:14,846 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:14,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:14,896 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 13:29:14,896 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:14,896 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:14,896 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:14,896 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:14,897 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:14,897 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:14,897 INFO L87 Difference]: Start difference. First operand 1618 states and 2113 transitions. Second operand 5 states. [2018-12-09 13:29:15,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:15,206 INFO L93 Difference]: Finished difference Result 3212 states and 4210 transitions. [2018-12-09 13:29:15,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:29:15,206 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-09 13:29:15,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:15,212 INFO L225 Difference]: With dead ends: 3212 [2018-12-09 13:29:15,212 INFO L226 Difference]: Without dead ends: 1618 [2018-12-09 13:29:15,215 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:15,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-12-09 13:29:15,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-12-09 13:29:15,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-09 13:29:15,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2097 transitions. [2018-12-09 13:29:15,309 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2097 transitions. Word has length 141 [2018-12-09 13:29:15,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:15,309 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2097 transitions. [2018-12-09 13:29:15,309 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:15,309 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2097 transitions. [2018-12-09 13:29:15,310 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-09 13:29:15,310 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:15,310 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:15,311 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:15,311 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:15,311 INFO L82 PathProgramCache]: Analyzing trace with hash -1106647032, now seen corresponding path program 1 times [2018-12-09 13:29:15,311 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:15,311 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:15,311 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:15,311 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:15,311 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:15,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:15,364 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 13:29:15,364 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:15,364 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:15,364 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:15,365 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:15,365 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:15,365 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:15,365 INFO L87 Difference]: Start difference. First operand 1618 states and 2097 transitions. Second operand 5 states. [2018-12-09 13:29:15,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:15,659 INFO L93 Difference]: Finished difference Result 3212 states and 4178 transitions. [2018-12-09 13:29:15,659 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:29:15,659 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-09 13:29:15,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:15,663 INFO L225 Difference]: With dead ends: 3212 [2018-12-09 13:29:15,663 INFO L226 Difference]: Without dead ends: 1618 [2018-12-09 13:29:15,665 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:15,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-12-09 13:29:15,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-12-09 13:29:15,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-09 13:29:15,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2081 transitions. [2018-12-09 13:29:15,737 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2081 transitions. Word has length 141 [2018-12-09 13:29:15,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:15,737 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2081 transitions. [2018-12-09 13:29:15,737 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:15,737 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2081 transitions. [2018-12-09 13:29:15,738 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-09 13:29:15,738 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:15,738 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:15,738 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:15,738 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:15,738 INFO L82 PathProgramCache]: Analyzing trace with hash -230628026, now seen corresponding path program 1 times [2018-12-09 13:29:15,739 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:15,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:15,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:15,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:15,739 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:15,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:15,793 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 13:29:15,793 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:15,793 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:15,793 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:15,794 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:15,794 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:15,794 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:15,794 INFO L87 Difference]: Start difference. First operand 1618 states and 2081 transitions. Second operand 5 states. [2018-12-09 13:29:16,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:16,081 INFO L93 Difference]: Finished difference Result 3212 states and 4146 transitions. [2018-12-09 13:29:16,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:29:16,081 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-09 13:29:16,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:16,087 INFO L225 Difference]: With dead ends: 3212 [2018-12-09 13:29:16,087 INFO L226 Difference]: Without dead ends: 1618 [2018-12-09 13:29:16,090 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:29:16,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states. [2018-12-09 13:29:16,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1618. [2018-12-09 13:29:16,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1618 states. [2018-12-09 13:29:16,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2065 transitions. [2018-12-09 13:29:16,218 INFO L78 Accepts]: Start accepts. Automaton has 1618 states and 2065 transitions. Word has length 141 [2018-12-09 13:29:16,218 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:16,218 INFO L480 AbstractCegarLoop]: Abstraction has 1618 states and 2065 transitions. [2018-12-09 13:29:16,218 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:16,218 INFO L276 IsEmpty]: Start isEmpty. Operand 1618 states and 2065 transitions. [2018-12-09 13:29:16,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-09 13:29:16,219 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:16,220 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:16,220 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:16,220 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:16,220 INFO L82 PathProgramCache]: Analyzing trace with hash 213272648, now seen corresponding path program 1 times [2018-12-09 13:29:16,220 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:16,220 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:16,221 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:16,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:16,221 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:16,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:16,272 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 13:29:16,272 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:16,273 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:16,273 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:16,273 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:16,273 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:16,273 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:16,273 INFO L87 Difference]: Start difference. First operand 1618 states and 2065 transitions. Second operand 5 states. [2018-12-09 13:29:16,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:16,706 INFO L93 Difference]: Finished difference Result 4062 states and 5227 transitions. [2018-12-09 13:29:16,706 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 13:29:16,706 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-09 13:29:16,707 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:16,712 INFO L225 Difference]: With dead ends: 4062 [2018-12-09 13:29:16,712 INFO L226 Difference]: Without dead ends: 2468 [2018-12-09 13:29:16,714 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 13:29:16,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2468 states. [2018-12-09 13:29:16,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2468 to 2324. [2018-12-09 13:29:16,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2324 states. [2018-12-09 13:29:16,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2324 states to 2324 states and 2887 transitions. [2018-12-09 13:29:16,816 INFO L78 Accepts]: Start accepts. Automaton has 2324 states and 2887 transitions. Word has length 141 [2018-12-09 13:29:16,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:16,816 INFO L480 AbstractCegarLoop]: Abstraction has 2324 states and 2887 transitions. [2018-12-09 13:29:16,816 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:16,817 INFO L276 IsEmpty]: Start isEmpty. Operand 2324 states and 2887 transitions. [2018-12-09 13:29:16,818 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-09 13:29:16,818 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:16,818 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:16,818 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:16,819 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:16,819 INFO L82 PathProgramCache]: Analyzing trace with hash 1751612678, now seen corresponding path program 1 times [2018-12-09 13:29:16,819 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:16,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:16,819 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:16,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:16,820 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:16,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:16,857 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 13:29:16,857 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:16,857 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:16,857 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:16,858 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:16,858 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:16,858 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:16,858 INFO L87 Difference]: Start difference. First operand 2324 states and 2887 transitions. Second operand 5 states. [2018-12-09 13:29:17,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:17,373 INFO L93 Difference]: Finished difference Result 5495 states and 7170 transitions. [2018-12-09 13:29:17,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 13:29:17,374 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-09 13:29:17,374 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:17,382 INFO L225 Difference]: With dead ends: 5495 [2018-12-09 13:29:17,382 INFO L226 Difference]: Without dead ends: 3197 [2018-12-09 13:29:17,386 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 13:29:17,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3197 states. [2018-12-09 13:29:17,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3197 to 2836. [2018-12-09 13:29:17,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2836 states. [2018-12-09 13:29:17,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2836 states to 2836 states and 3435 transitions. [2018-12-09 13:29:17,511 INFO L78 Accepts]: Start accepts. Automaton has 2836 states and 3435 transitions. Word has length 141 [2018-12-09 13:29:17,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:17,511 INFO L480 AbstractCegarLoop]: Abstraction has 2836 states and 3435 transitions. [2018-12-09 13:29:17,511 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:17,511 INFO L276 IsEmpty]: Start isEmpty. Operand 2836 states and 3435 transitions. [2018-12-09 13:29:17,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-09 13:29:17,513 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:17,513 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:17,513 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:17,513 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:17,513 INFO L82 PathProgramCache]: Analyzing trace with hash -276973432, now seen corresponding path program 1 times [2018-12-09 13:29:17,513 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:17,514 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:17,514 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:17,514 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:17,514 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:17,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:17,579 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 13:29:17,579 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:17,579 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:17,579 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:17,579 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:17,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:17,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:17,580 INFO L87 Difference]: Start difference. First operand 2836 states and 3435 transitions. Second operand 5 states. [2018-12-09 13:29:18,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:18,077 INFO L93 Difference]: Finished difference Result 6035 states and 7539 transitions. [2018-12-09 13:29:18,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 13:29:18,078 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-09 13:29:18,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:18,088 INFO L225 Difference]: With dead ends: 6035 [2018-12-09 13:29:18,089 INFO L226 Difference]: Without dead ends: 3225 [2018-12-09 13:29:18,094 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 13:29:18,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3225 states. [2018-12-09 13:29:18,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3225 to 3060. [2018-12-09 13:29:18,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3060 states. [2018-12-09 13:29:18,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3060 states to 3060 states and 3641 transitions. [2018-12-09 13:29:18,251 INFO L78 Accepts]: Start accepts. Automaton has 3060 states and 3641 transitions. Word has length 141 [2018-12-09 13:29:18,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:18,251 INFO L480 AbstractCegarLoop]: Abstraction has 3060 states and 3641 transitions. [2018-12-09 13:29:18,251 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:18,251 INFO L276 IsEmpty]: Start isEmpty. Operand 3060 states and 3641 transitions. [2018-12-09 13:29:18,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-09 13:29:18,253 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:18,253 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:18,253 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:18,254 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:18,254 INFO L82 PathProgramCache]: Analyzing trace with hash -758053690, now seen corresponding path program 1 times [2018-12-09 13:29:18,254 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:18,254 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:18,255 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:18,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:18,255 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:18,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:18,297 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-12-09 13:29:18,297 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:18,297 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-12-09 13:29:18,297 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:18,297 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:29:18,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:29:18,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-12-09 13:29:18,298 INFO L87 Difference]: Start difference. First operand 3060 states and 3641 transitions. Second operand 5 states. [2018-12-09 13:29:18,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:18,770 INFO L93 Difference]: Finished difference Result 6473 states and 8022 transitions. [2018-12-09 13:29:18,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-12-09 13:29:18,770 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 141 [2018-12-09 13:29:18,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:18,781 INFO L225 Difference]: With dead ends: 6473 [2018-12-09 13:29:18,782 INFO L226 Difference]: Without dead ends: 3437 [2018-12-09 13:29:18,789 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-12-09 13:29:18,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3437 states. [2018-12-09 13:29:19,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3437 to 3206. [2018-12-09 13:29:19,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3206 states. [2018-12-09 13:29:19,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3206 states to 3206 states and 3739 transitions. [2018-12-09 13:29:19,008 INFO L78 Accepts]: Start accepts. Automaton has 3206 states and 3739 transitions. Word has length 141 [2018-12-09 13:29:19,008 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:19,008 INFO L480 AbstractCegarLoop]: Abstraction has 3206 states and 3739 transitions. [2018-12-09 13:29:19,008 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:29:19,008 INFO L276 IsEmpty]: Start isEmpty. Operand 3206 states and 3739 transitions. [2018-12-09 13:29:19,009 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-12-09 13:29:19,009 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:19,009 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:19,009 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:19,009 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:19,009 INFO L82 PathProgramCache]: Analyzing trace with hash -773572408, now seen corresponding path program 1 times [2018-12-09 13:29:19,009 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:19,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:19,010 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:19,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:19,010 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:19,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:19,031 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 6 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-12-09 13:29:19,031 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:29:19,031 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:29:19,032 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 142 with the following transitions: [2018-12-09 13:29:19,033 INFO L205 CegarAbsIntRunner]: [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [330], [332], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [542], [555], [568], [581], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [696], [697], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:29:19,056 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:29:19,056 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:29:19,219 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 13:29:19,220 INFO L272 AbstractInterpreter]: Visited 110 different actions 110 times. Never merged. Never widened. Performed 971 root evaluator evaluations with a maximum evaluation depth of 3. Performed 971 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 58 variables. [2018-12-09 13:29:19,230 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:19,230 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 13:29:19,397 INFO L227 lantSequenceWeakener]: Weakened 118 states. On average, predicates are now at 69.56% of their original sizes. [2018-12-09 13:29:19,397 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 13:29:20,030 INFO L418 sIntCurrentIteration]: We unified 140 AI predicates to 140 [2018-12-09 13:29:20,030 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 13:29:20,031 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 13:29:20,031 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [46] imperfect sequences [3] total 47 [2018-12-09 13:29:20,031 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:20,032 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-12-09 13:29:20,032 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-12-09 13:29:20,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=414, Invalid=1656, Unknown=0, NotChecked=0, Total=2070 [2018-12-09 13:29:20,033 INFO L87 Difference]: Start difference. First operand 3206 states and 3739 transitions. Second operand 46 states. [2018-12-09 13:29:26,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:26,495 INFO L93 Difference]: Finished difference Result 6513 states and 7626 transitions. [2018-12-09 13:29:26,495 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-12-09 13:29:26,495 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 141 [2018-12-09 13:29:26,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:26,501 INFO L225 Difference]: With dead ends: 6513 [2018-12-09 13:29:26,501 INFO L226 Difference]: Without dead ends: 3322 [2018-12-09 13:29:26,505 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 170 GetRequests, 96 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1530 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1227, Invalid=4473, Unknown=0, NotChecked=0, Total=5700 [2018-12-09 13:29:26,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3322 states. [2018-12-09 13:29:26,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3322 to 3309. [2018-12-09 13:29:26,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3309 states. [2018-12-09 13:29:26,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3309 states to 3309 states and 3847 transitions. [2018-12-09 13:29:26,657 INFO L78 Accepts]: Start accepts. Automaton has 3309 states and 3847 transitions. Word has length 141 [2018-12-09 13:29:26,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:26,657 INFO L480 AbstractCegarLoop]: Abstraction has 3309 states and 3847 transitions. [2018-12-09 13:29:26,658 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-12-09 13:29:26,658 INFO L276 IsEmpty]: Start isEmpty. Operand 3309 states and 3847 transitions. [2018-12-09 13:29:26,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2018-12-09 13:29:26,659 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:26,659 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:26,659 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:26,660 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:26,660 INFO L82 PathProgramCache]: Analyzing trace with hash -1812010618, now seen corresponding path program 1 times [2018-12-09 13:29:26,660 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:26,660 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:26,660 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:26,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:26,661 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:26,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:26,682 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 9 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-12-09 13:29:26,682 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:29:26,682 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:29:26,682 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 146 with the following transitions: [2018-12-09 13:29:26,683 INFO L205 CegarAbsIntRunner]: [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [330], [332], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [565], [568], [572], [578], [581], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [696], [697], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:29:26,685 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:29:26,685 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:29:26,747 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 13:29:26,747 INFO L272 AbstractInterpreter]: Visited 130 different actions 152 times. Merged at 13 different actions 13 times. Never widened. Performed 1404 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1404 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 60 variables. [2018-12-09 13:29:26,749 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:26,749 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 13:29:26,865 INFO L227 lantSequenceWeakener]: Weakened 140 states. On average, predicates are now at 72.97% of their original sizes. [2018-12-09 13:29:26,865 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 13:29:27,486 INFO L418 sIntCurrentIteration]: We unified 144 AI predicates to 144 [2018-12-09 13:29:27,486 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 13:29:27,486 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 13:29:27,487 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [55] imperfect sequences [3] total 56 [2018-12-09 13:29:27,487 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:27,487 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-12-09 13:29:27,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-12-09 13:29:27,488 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=751, Invalid=2219, Unknown=0, NotChecked=0, Total=2970 [2018-12-09 13:29:27,488 INFO L87 Difference]: Start difference. First operand 3309 states and 3847 transitions. Second operand 55 states. [2018-12-09 13:29:43,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:43,872 INFO L93 Difference]: Finished difference Result 24421 states and 30695 transitions. [2018-12-09 13:29:43,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-12-09 13:29:43,872 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 145 [2018-12-09 13:29:43,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:43,907 INFO L225 Difference]: With dead ends: 24421 [2018-12-09 13:29:43,907 INFO L226 Difference]: Without dead ends: 16699 [2018-12-09 13:29:43,928 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 195 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3582 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2359, Invalid=8771, Unknown=0, NotChecked=0, Total=11130 [2018-12-09 13:29:43,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16699 states. [2018-12-09 13:29:44,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16699 to 16217. [2018-12-09 13:29:44,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16217 states. [2018-12-09 13:29:44,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16217 states to 16217 states and 19636 transitions. [2018-12-09 13:29:44,915 INFO L78 Accepts]: Start accepts. Automaton has 16217 states and 19636 transitions. Word has length 145 [2018-12-09 13:29:44,915 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:44,915 INFO L480 AbstractCegarLoop]: Abstraction has 16217 states and 19636 transitions. [2018-12-09 13:29:44,915 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-12-09 13:29:44,915 INFO L276 IsEmpty]: Start isEmpty. Operand 16217 states and 19636 transitions. [2018-12-09 13:29:44,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 208 [2018-12-09 13:29:44,931 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:44,931 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:44,931 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:44,931 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:44,931 INFO L82 PathProgramCache]: Analyzing trace with hash -708564301, now seen corresponding path program 1 times [2018-12-09 13:29:44,931 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:44,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:44,932 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:44,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:44,932 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:44,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:44,971 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-12-09 13:29:44,971 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-12-09 13:29:44,971 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-12-09 13:29:44,971 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:44,971 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 13:29:44,971 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 13:29:44,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 13:29:44,972 INFO L87 Difference]: Start difference. First operand 16217 states and 19636 transitions. Second operand 4 states. [2018-12-09 13:29:45,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:45,915 INFO L93 Difference]: Finished difference Result 31187 states and 38714 transitions. [2018-12-09 13:29:45,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-12-09 13:29:45,916 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 207 [2018-12-09 13:29:45,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:45,944 INFO L225 Difference]: With dead ends: 31187 [2018-12-09 13:29:45,944 INFO L226 Difference]: Without dead ends: 15097 [2018-12-09 13:29:45,969 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-12-09 13:29:45,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15097 states. [2018-12-09 13:29:46,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15097 to 15012. [2018-12-09 13:29:46,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15012 states. [2018-12-09 13:29:46,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15012 states to 15012 states and 17698 transitions. [2018-12-09 13:29:46,835 INFO L78 Accepts]: Start accepts. Automaton has 15012 states and 17698 transitions. Word has length 207 [2018-12-09 13:29:46,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:46,835 INFO L480 AbstractCegarLoop]: Abstraction has 15012 states and 17698 transitions. [2018-12-09 13:29:46,835 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 13:29:46,836 INFO L276 IsEmpty]: Start isEmpty. Operand 15012 states and 17698 transitions. [2018-12-09 13:29:46,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 211 [2018-12-09 13:29:46,846 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:46,846 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:46,846 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:46,847 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:46,847 INFO L82 PathProgramCache]: Analyzing trace with hash -913434924, now seen corresponding path program 1 times [2018-12-09 13:29:46,847 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:46,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:46,847 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:46,848 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:46,848 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:46,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:46,905 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-09 13:29:46,905 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:29:46,905 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:29:46,906 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 211 with the following transitions: [2018-12-09 13:29:46,906 INFO L205 CegarAbsIntRunner]: [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [552], [559], [565], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:29:46,908 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:29:46,909 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:29:46,969 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 13:29:46,969 INFO L272 AbstractInterpreter]: Visited 131 different actions 152 times. Merged at 14 different actions 14 times. Never widened. Performed 1651 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1651 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 60 variables. [2018-12-09 13:29:46,970 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:46,971 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 13:29:47,088 INFO L227 lantSequenceWeakener]: Weakened 146 states. On average, predicates are now at 69.13% of their original sizes. [2018-12-09 13:29:47,088 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 13:29:47,855 INFO L418 sIntCurrentIteration]: We unified 209 AI predicates to 209 [2018-12-09 13:29:47,855 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 13:29:47,855 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 13:29:47,855 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [57] imperfect sequences [6] total 61 [2018-12-09 13:29:47,855 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:29:47,856 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-12-09 13:29:47,856 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-12-09 13:29:47,857 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=791, Invalid=2401, Unknown=0, NotChecked=0, Total=3192 [2018-12-09 13:29:47,857 INFO L87 Difference]: Start difference. First operand 15012 states and 17698 transitions. Second operand 57 states. [2018-12-09 13:29:58,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:29:58,967 INFO L93 Difference]: Finished difference Result 30059 states and 35455 transitions. [2018-12-09 13:29:58,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-12-09 13:29:58,967 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 210 [2018-12-09 13:29:58,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:29:59,003 INFO L225 Difference]: With dead ends: 30059 [2018-12-09 13:29:59,003 INFO L226 Difference]: Without dead ends: 15174 [2018-12-09 13:29:59,020 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 252 GetRequests, 154 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3161 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2346, Invalid=7554, Unknown=0, NotChecked=0, Total=9900 [2018-12-09 13:29:59,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15174 states. [2018-12-09 13:29:59,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15174 to 15153. [2018-12-09 13:29:59,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15153 states. [2018-12-09 13:29:59,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15153 states to 15153 states and 17847 transitions. [2018-12-09 13:29:59,876 INFO L78 Accepts]: Start accepts. Automaton has 15153 states and 17847 transitions. Word has length 210 [2018-12-09 13:29:59,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:29:59,877 INFO L480 AbstractCegarLoop]: Abstraction has 15153 states and 17847 transitions. [2018-12-09 13:29:59,877 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-12-09 13:29:59,877 INFO L276 IsEmpty]: Start isEmpty. Operand 15153 states and 17847 transitions. [2018-12-09 13:29:59,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 214 [2018-12-09 13:29:59,887 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:29:59,887 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:29:59,887 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:29:59,887 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:59,888 INFO L82 PathProgramCache]: Analyzing trace with hash -1170762779, now seen corresponding path program 1 times [2018-12-09 13:29:59,888 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:29:59,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:59,888 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:29:59,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:29:59,888 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:29:59,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:29:59,935 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 11 proven. 8 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-09 13:29:59,935 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:29:59,935 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:29:59,935 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 214 with the following transitions: [2018-12-09 13:29:59,935 INFO L205 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [565], [568], [572], [575], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:29:59,937 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:29:59,937 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:29:59,981 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 13:29:59,981 INFO L272 AbstractInterpreter]: Visited 138 different actions 157 times. Merged at 11 different actions 11 times. Never widened. Performed 1442 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1442 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 1 fixpoints after 1 different actions. Largest state had 60 variables. [2018-12-09 13:29:59,982 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:29:59,982 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 13:30:00,149 INFO L227 lantSequenceWeakener]: Weakened 153 states. On average, predicates are now at 70% of their original sizes. [2018-12-09 13:30:00,149 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 13:30:01,004 INFO L418 sIntCurrentIteration]: We unified 212 AI predicates to 212 [2018-12-09 13:30:01,004 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 13:30:01,004 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 13:30:01,004 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [60] imperfect sequences [4] total 62 [2018-12-09 13:30:01,004 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:30:01,005 INFO L459 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-12-09 13:30:01,005 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-12-09 13:30:01,006 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=774, Invalid=2766, Unknown=0, NotChecked=0, Total=3540 [2018-12-09 13:30:01,006 INFO L87 Difference]: Start difference. First operand 15153 states and 17847 transitions. Second operand 60 states. [2018-12-09 13:30:11,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:30:11,853 INFO L93 Difference]: Finished difference Result 30357 states and 35873 transitions. [2018-12-09 13:30:11,853 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-12-09 13:30:11,853 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 213 [2018-12-09 13:30:11,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:30:11,877 INFO L225 Difference]: With dead ends: 30357 [2018-12-09 13:30:11,878 INFO L226 Difference]: Without dead ends: 15463 [2018-12-09 13:30:11,894 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 252 GetRequests, 154 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2901 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2027, Invalid=7873, Unknown=0, NotChecked=0, Total=9900 [2018-12-09 13:30:11,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15463 states. [2018-12-09 13:30:12,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15463 to 15443. [2018-12-09 13:30:12,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15443 states. [2018-12-09 13:30:12,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15443 states to 15443 states and 18195 transitions. [2018-12-09 13:30:12,777 INFO L78 Accepts]: Start accepts. Automaton has 15443 states and 18195 transitions. Word has length 213 [2018-12-09 13:30:12,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:30:12,777 INFO L480 AbstractCegarLoop]: Abstraction has 15443 states and 18195 transitions. [2018-12-09 13:30:12,778 INFO L481 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-12-09 13:30:12,778 INFO L276 IsEmpty]: Start isEmpty. Operand 15443 states and 18195 transitions. [2018-12-09 13:30:12,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-12-09 13:30:12,787 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:30:12,788 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:30:12,788 INFO L423 AbstractCegarLoop]: === Iteration 29 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:30:12,788 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:30:12,788 INFO L82 PathProgramCache]: Analyzing trace with hash -105925495, now seen corresponding path program 1 times [2018-12-09 13:30:12,788 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:30:12,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:30:12,789 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:30:12,789 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:30:12,789 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:30:12,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:30:12,846 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 10 proven. 3 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-09 13:30:12,846 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:30:12,846 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:30:12,846 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 215 with the following transitions: [2018-12-09 13:30:12,846 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [549], [555], [559], [565], [568], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:30:12,848 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:30:12,848 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:30:12,897 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 13:30:12,897 INFO L272 AbstractInterpreter]: Visited 141 different actions 164 times. Merged at 13 different actions 13 times. Never widened. Performed 1709 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1709 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-12-09 13:30:12,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:30:12,899 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 13:30:13,002 INFO L227 lantSequenceWeakener]: Weakened 149 states. On average, predicates are now at 68.55% of their original sizes. [2018-12-09 13:30:13,002 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 13:30:15,375 INFO L418 sIntCurrentIteration]: We unified 213 AI predicates to 213 [2018-12-09 13:30:15,375 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 13:30:15,376 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 13:30:15,376 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [60] imperfect sequences [4] total 62 [2018-12-09 13:30:15,376 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:30:15,376 INFO L459 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-12-09 13:30:15,377 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-12-09 13:30:15,377 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=635, Invalid=2905, Unknown=0, NotChecked=0, Total=3540 [2018-12-09 13:30:15,377 INFO L87 Difference]: Start difference. First operand 15443 states and 18195 transitions. Second operand 60 states. [2018-12-09 13:30:26,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:30:26,164 INFO L93 Difference]: Finished difference Result 23771 states and 27984 transitions. [2018-12-09 13:30:26,164 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-09 13:30:26,165 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 214 [2018-12-09 13:30:26,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:30:26,191 INFO L225 Difference]: With dead ends: 23771 [2018-12-09 13:30:26,191 INFO L226 Difference]: Without dead ends: 15742 [2018-12-09 13:30:26,206 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 258 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3201 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=1794, Invalid=9126, Unknown=0, NotChecked=0, Total=10920 [2018-12-09 13:30:26,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15742 states. [2018-12-09 13:30:27,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15742 to 15717. [2018-12-09 13:30:27,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15717 states. [2018-12-09 13:30:27,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15717 states to 15717 states and 18521 transitions. [2018-12-09 13:30:27,182 INFO L78 Accepts]: Start accepts. Automaton has 15717 states and 18521 transitions. Word has length 214 [2018-12-09 13:30:27,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:30:27,182 INFO L480 AbstractCegarLoop]: Abstraction has 15717 states and 18521 transitions. [2018-12-09 13:30:27,182 INFO L481 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-12-09 13:30:27,183 INFO L276 IsEmpty]: Start isEmpty. Operand 15717 states and 18521 transitions. [2018-12-09 13:30:27,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-12-09 13:30:27,192 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:30:27,192 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:30:27,192 INFO L423 AbstractCegarLoop]: === Iteration 30 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:30:27,192 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:30:27,192 INFO L82 PathProgramCache]: Analyzing trace with hash 1361264291, now seen corresponding path program 1 times [2018-12-09 13:30:27,192 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:30:27,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:30:27,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:30:27,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:30:27,193 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:30:27,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:30:27,232 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 10 proven. 3 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-09 13:30:27,233 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:30:27,233 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:30:27,233 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 215 with the following transitions: [2018-12-09 13:30:27,233 INFO L205 CegarAbsIntRunner]: [33], [36], [47], [49], [51], [53], [57], [60], [76], [78], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [562], [568], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:30:27,235 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:30:27,235 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:30:27,294 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 13:30:27,295 INFO L272 AbstractInterpreter]: Visited 141 different actions 164 times. Merged at 13 different actions 13 times. Never widened. Performed 1711 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1711 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-12-09 13:30:27,298 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:30:27,298 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 13:30:27,403 INFO L227 lantSequenceWeakener]: Weakened 149 states. On average, predicates are now at 68.56% of their original sizes. [2018-12-09 13:30:27,403 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 13:30:28,301 INFO L418 sIntCurrentIteration]: We unified 213 AI predicates to 213 [2018-12-09 13:30:28,301 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 13:30:28,301 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 13:30:28,301 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [60] imperfect sequences [4] total 62 [2018-12-09 13:30:28,301 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:30:28,301 INFO L459 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-12-09 13:30:28,301 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-12-09 13:30:28,302 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=671, Invalid=2869, Unknown=0, NotChecked=0, Total=3540 [2018-12-09 13:30:28,302 INFO L87 Difference]: Start difference. First operand 15717 states and 18521 transitions. Second operand 60 states. [2018-12-09 13:30:41,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:30:41,998 INFO L93 Difference]: Finished difference Result 23998 states and 28234 transitions. [2018-12-09 13:30:41,998 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-09 13:30:41,998 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 214 [2018-12-09 13:30:41,998 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:30:42,026 INFO L225 Difference]: With dead ends: 23998 [2018-12-09 13:30:42,026 INFO L226 Difference]: Without dead ends: 16168 [2018-12-09 13:30:42,039 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 258 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3264 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1907, Invalid=9013, Unknown=0, NotChecked=0, Total=10920 [2018-12-09 13:30:42,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16168 states. [2018-12-09 13:30:43,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16168 to 16141. [2018-12-09 13:30:43,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16141 states. [2018-12-09 13:30:43,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16141 states to 16141 states and 18992 transitions. [2018-12-09 13:30:43,051 INFO L78 Accepts]: Start accepts. Automaton has 16141 states and 18992 transitions. Word has length 214 [2018-12-09 13:30:43,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:30:43,051 INFO L480 AbstractCegarLoop]: Abstraction has 16141 states and 18992 transitions. [2018-12-09 13:30:43,051 INFO L481 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-12-09 13:30:43,051 INFO L276 IsEmpty]: Start isEmpty. Operand 16141 states and 18992 transitions. [2018-12-09 13:30:43,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 218 [2018-12-09 13:30:43,060 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:30:43,060 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:30:43,060 INFO L423 AbstractCegarLoop]: === Iteration 31 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:30:43,060 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:30:43,060 INFO L82 PathProgramCache]: Analyzing trace with hash -1427190956, now seen corresponding path program 1 times [2018-12-09 13:30:43,060 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:30:43,061 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:30:43,061 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:30:43,061 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:30:43,061 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:30:43,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:30:43,125 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-09 13:30:43,125 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:30:43,125 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:30:43,125 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 218 with the following transitions: [2018-12-09 13:30:43,125 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [565], [572], [575], [578], [585], [588], [600], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:30:43,126 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:30:43,126 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:30:43,196 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 13:30:43,197 INFO L272 AbstractInterpreter]: Visited 142 different actions 214 times. Merged at 18 different actions 34 times. Never widened. Performed 2808 root evaluator evaluations with a maximum evaluation depth of 3. Performed 2808 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 4 fixpoints after 3 different actions. Largest state had 60 variables. [2018-12-09 13:30:43,198 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:30:43,199 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 13:30:43,199 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:30:43,199 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 13:30:43,205 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:30:43,205 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 13:30:43,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:30:43,289 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 13:30:43,325 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 51 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 13:30:43,325 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 13:30:43,446 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-09 13:30:43,465 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-09 13:30:43,466 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [6] total 7 [2018-12-09 13:30:43,466 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:30:43,466 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 13:30:43,466 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 13:30:43,466 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-12-09 13:30:43,466 INFO L87 Difference]: Start difference. First operand 16141 states and 18992 transitions. Second operand 3 states. [2018-12-09 13:30:44,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:30:44,975 INFO L93 Difference]: Finished difference Result 41019 states and 51056 transitions. [2018-12-09 13:30:44,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 13:30:44,975 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 217 [2018-12-09 13:30:44,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:30:45,024 INFO L225 Difference]: With dead ends: 41019 [2018-12-09 13:30:45,024 INFO L226 Difference]: Without dead ends: 26134 [2018-12-09 13:30:45,059 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 440 GetRequests, 431 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-12-09 13:30:45,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26134 states. [2018-12-09 13:30:46,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26134 to 26118. [2018-12-09 13:30:46,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26118 states. [2018-12-09 13:30:46,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26118 states to 26118 states and 31415 transitions. [2018-12-09 13:30:46,699 INFO L78 Accepts]: Start accepts. Automaton has 26118 states and 31415 transitions. Word has length 217 [2018-12-09 13:30:46,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:30:46,699 INFO L480 AbstractCegarLoop]: Abstraction has 26118 states and 31415 transitions. [2018-12-09 13:30:46,700 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 13:30:46,700 INFO L276 IsEmpty]: Start isEmpty. Operand 26118 states and 31415 transitions. [2018-12-09 13:30:46,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 219 [2018-12-09 13:30:46,716 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:30:46,716 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:30:46,716 INFO L423 AbstractCegarLoop]: === Iteration 32 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:30:46,716 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:30:46,716 INFO L82 PathProgramCache]: Analyzing trace with hash -375898583, now seen corresponding path program 1 times [2018-12-09 13:30:46,716 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:30:46,717 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:30:46,717 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:30:46,717 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:30:46,717 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:30:46,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:30:46,777 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-09 13:30:46,778 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:30:46,778 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:30:46,778 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 219 with the following transitions: [2018-12-09 13:30:46,778 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [565], [572], [575], [578], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:30:46,779 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:30:46,779 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:30:46,854 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 13:30:46,854 INFO L272 AbstractInterpreter]: Visited 143 different actions 215 times. Merged at 18 different actions 34 times. Never widened. Performed 2809 root evaluator evaluations with a maximum evaluation depth of 3. Performed 2809 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 4 fixpoints after 3 different actions. Largest state had 60 variables. [2018-12-09 13:30:46,855 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:30:46,855 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 13:30:46,855 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:30:46,855 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 13:30:46,862 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:30:46,862 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 13:30:46,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:30:46,930 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 13:30:46,986 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 47 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-12-09 13:30:46,986 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 13:30:47,099 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2018-12-09 13:30:47,115 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-09 13:30:47,115 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [6, 5] total 10 [2018-12-09 13:30:47,115 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:30:47,115 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-12-09 13:30:47,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-12-09 13:30:47,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-12-09 13:30:47,116 INFO L87 Difference]: Start difference. First operand 26118 states and 31415 transitions. Second operand 5 states. [2018-12-09 13:30:49,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:30:49,216 INFO L93 Difference]: Finished difference Result 42632 states and 52441 transitions. [2018-12-09 13:30:49,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:30:49,216 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 218 [2018-12-09 13:30:49,216 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:30:49,261 INFO L225 Difference]: With dead ends: 42632 [2018-12-09 13:30:49,261 INFO L226 Difference]: Without dead ends: 27807 [2018-12-09 13:30:49,285 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 442 GetRequests, 429 SyntacticMatches, 5 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-12-09 13:30:49,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27807 states. [2018-12-09 13:30:51,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27807 to 27726. [2018-12-09 13:30:51,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27726 states. [2018-12-09 13:30:51,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27726 states to 27726 states and 33745 transitions. [2018-12-09 13:30:51,111 INFO L78 Accepts]: Start accepts. Automaton has 27726 states and 33745 transitions. Word has length 218 [2018-12-09 13:30:51,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:30:51,111 INFO L480 AbstractCegarLoop]: Abstraction has 27726 states and 33745 transitions. [2018-12-09 13:30:51,112 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-12-09 13:30:51,112 INFO L276 IsEmpty]: Start isEmpty. Operand 27726 states and 33745 transitions. [2018-12-09 13:30:51,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 222 [2018-12-09 13:30:51,128 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:30:51,128 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:30:51,128 INFO L423 AbstractCegarLoop]: === Iteration 33 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:30:51,128 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:30:51,128 INFO L82 PathProgramCache]: Analyzing trace with hash 438612538, now seen corresponding path program 1 times [2018-12-09 13:30:51,128 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:30:51,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:30:51,129 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:30:51,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:30:51,129 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:30:51,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:30:51,185 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 11 proven. 8 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-09 13:30:51,185 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:30:51,185 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:30:51,185 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 222 with the following transitions: [2018-12-09 13:30:51,186 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [549], [555], [559], [565], [568], [572], [575], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:30:51,187 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:30:51,187 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:30:51,243 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 13:30:51,243 INFO L272 AbstractInterpreter]: Visited 146 different actions 164 times. Merged at 10 different actions 10 times. Never widened. Performed 1492 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1492 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-12-09 13:30:51,246 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:30:51,246 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 13:30:51,368 INFO L227 lantSequenceWeakener]: Weakened 159 states. On average, predicates are now at 68.9% of their original sizes. [2018-12-09 13:30:51,368 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 13:30:52,344 INFO L418 sIntCurrentIteration]: We unified 220 AI predicates to 220 [2018-12-09 13:30:52,344 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 13:30:52,344 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 13:30:52,344 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [62] imperfect sequences [4] total 64 [2018-12-09 13:30:52,344 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:30:52,345 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-12-09 13:30:52,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-12-09 13:30:52,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=603, Invalid=3179, Unknown=0, NotChecked=0, Total=3782 [2018-12-09 13:30:52,345 INFO L87 Difference]: Start difference. First operand 27726 states and 33745 transitions. Second operand 62 states. [2018-12-09 13:31:07,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:31:07,570 INFO L93 Difference]: Finished difference Result 36754 states and 44718 transitions. [2018-12-09 13:31:07,570 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-09 13:31:07,570 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 221 [2018-12-09 13:31:07,570 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:31:07,623 INFO L225 Difference]: With dead ends: 36754 [2018-12-09 13:31:07,623 INFO L226 Difference]: Without dead ends: 28003 [2018-12-09 13:31:07,646 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 262 GetRequests, 160 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3060 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1621, Invalid=9091, Unknown=0, NotChecked=0, Total=10712 [2018-12-09 13:31:07,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28003 states. [2018-12-09 13:31:09,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28003 to 27986. [2018-12-09 13:31:09,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27986 states. [2018-12-09 13:31:09,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27986 states to 27986 states and 34065 transitions. [2018-12-09 13:31:09,535 INFO L78 Accepts]: Start accepts. Automaton has 27986 states and 34065 transitions. Word has length 221 [2018-12-09 13:31:09,535 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:31:09,535 INFO L480 AbstractCegarLoop]: Abstraction has 27986 states and 34065 transitions. [2018-12-09 13:31:09,535 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-12-09 13:31:09,535 INFO L276 IsEmpty]: Start isEmpty. Operand 27986 states and 34065 transitions. [2018-12-09 13:31:09,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 222 [2018-12-09 13:31:09,551 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:31:09,551 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:31:09,551 INFO L423 AbstractCegarLoop]: === Iteration 34 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:31:09,551 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:31:09,551 INFO L82 PathProgramCache]: Analyzing trace with hash 1279761248, now seen corresponding path program 1 times [2018-12-09 13:31:09,551 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:31:09,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:31:09,552 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:31:09,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:31:09,552 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:31:09,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:31:09,591 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 11 proven. 8 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-09 13:31:09,591 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:31:09,591 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:31:09,591 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 222 with the following transitions: [2018-12-09 13:31:09,591 INFO L205 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [51], [53], [57], [60], [76], [78], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [542], [546], [552], [555], [559], [562], [568], [572], [575], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:31:09,592 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:31:09,592 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:31:09,632 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 13:31:09,632 INFO L272 AbstractInterpreter]: Visited 146 different actions 164 times. Merged at 10 different actions 10 times. Never widened. Performed 1494 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1494 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-12-09 13:31:09,633 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:31:09,633 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 13:31:09,735 INFO L227 lantSequenceWeakener]: Weakened 159 states. On average, predicates are now at 68.91% of their original sizes. [2018-12-09 13:31:09,735 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 13:31:10,724 INFO L418 sIntCurrentIteration]: We unified 220 AI predicates to 220 [2018-12-09 13:31:10,724 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 13:31:10,724 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 13:31:10,724 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [62] imperfect sequences [4] total 64 [2018-12-09 13:31:10,724 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:31:10,724 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-12-09 13:31:10,725 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-12-09 13:31:10,725 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=640, Invalid=3142, Unknown=0, NotChecked=0, Total=3782 [2018-12-09 13:31:10,725 INFO L87 Difference]: Start difference. First operand 27986 states and 34065 transitions. Second operand 62 states. [2018-12-09 13:31:31,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:31:31,186 INFO L93 Difference]: Finished difference Result 36849 states and 44839 transitions. [2018-12-09 13:31:31,186 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-12-09 13:31:31,186 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 221 [2018-12-09 13:31:31,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:31:31,238 INFO L225 Difference]: With dead ends: 36849 [2018-12-09 13:31:31,238 INFO L226 Difference]: Without dead ends: 28325 [2018-12-09 13:31:31,257 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 263 GetRequests, 160 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3205 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1750, Invalid=9170, Unknown=0, NotChecked=0, Total=10920 [2018-12-09 13:31:31,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28325 states. [2018-12-09 13:31:33,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28325 to 28303. [2018-12-09 13:31:33,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28303 states. [2018-12-09 13:31:33,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28303 states to 28303 states and 34442 transitions. [2018-12-09 13:31:33,171 INFO L78 Accepts]: Start accepts. Automaton has 28303 states and 34442 transitions. Word has length 221 [2018-12-09 13:31:33,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:31:33,172 INFO L480 AbstractCegarLoop]: Abstraction has 28303 states and 34442 transitions. [2018-12-09 13:31:33,172 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-12-09 13:31:33,172 INFO L276 IsEmpty]: Start isEmpty. Operand 28303 states and 34442 transitions. [2018-12-09 13:31:33,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 224 [2018-12-09 13:31:33,194 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:31:33,194 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:31:33,195 INFO L423 AbstractCegarLoop]: === Iteration 35 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:31:33,195 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:31:33,195 INFO L82 PathProgramCache]: Analyzing trace with hash -287017233, now seen corresponding path program 1 times [2018-12-09 13:31:33,195 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:31:33,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:31:33,196 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:31:33,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:31:33,196 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:31:33,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:31:33,237 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 16 proven. 5 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-12-09 13:31:33,237 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:31:33,237 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:31:33,237 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 224 with the following transitions: [2018-12-09 13:31:33,238 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [114], [119], [133], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [565], [568], [572], [575], [585], [588], [600], [603], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:31:33,239 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:31:33,239 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:31:33,329 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 13:31:33,329 INFO L272 AbstractInterpreter]: Visited 159 different actions 314 times. Merged at 31 different actions 55 times. Never widened. Performed 3315 root evaluator evaluations with a maximum evaluation depth of 3. Performed 3315 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 8 fixpoints after 5 different actions. Largest state had 60 variables. [2018-12-09 13:31:33,331 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:31:33,331 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 13:31:33,331 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:31:33,331 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 13:31:33,337 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:31:33,337 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 13:31:33,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:31:33,404 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 13:31:33,430 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 73 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-12-09 13:31:33,431 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 13:31:33,510 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-12-09 13:31:33,525 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-09 13:31:33,525 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2018-12-09 13:31:33,525 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:31:33,525 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 13:31:33,525 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 13:31:33,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-12-09 13:31:33,526 INFO L87 Difference]: Start difference. First operand 28303 states and 34442 transitions. Second operand 4 states. [2018-12-09 13:31:35,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:31:35,403 INFO L93 Difference]: Finished difference Result 40618 states and 50723 transitions. [2018-12-09 13:31:35,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:31:35,403 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 223 [2018-12-09 13:31:35,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:31:35,441 INFO L225 Difference]: With dead ends: 40618 [2018-12-09 13:31:35,441 INFO L226 Difference]: Without dead ends: 24248 [2018-12-09 13:31:35,468 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 454 GetRequests, 445 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-12-09 13:31:35,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24248 states. [2018-12-09 13:31:37,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24248 to 23992. [2018-12-09 13:31:37,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23992 states. [2018-12-09 13:31:37,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23992 states to 23992 states and 28992 transitions. [2018-12-09 13:31:37,045 INFO L78 Accepts]: Start accepts. Automaton has 23992 states and 28992 transitions. Word has length 223 [2018-12-09 13:31:37,045 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:31:37,045 INFO L480 AbstractCegarLoop]: Abstraction has 23992 states and 28992 transitions. [2018-12-09 13:31:37,045 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 13:31:37,045 INFO L276 IsEmpty]: Start isEmpty. Operand 23992 states and 28992 transitions. [2018-12-09 13:31:37,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 414 [2018-12-09 13:31:37,067 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:31:37,067 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:31:37,068 INFO L423 AbstractCegarLoop]: === Iteration 36 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:31:37,068 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:31:37,068 INFO L82 PathProgramCache]: Analyzing trace with hash -643358620, now seen corresponding path program 1 times [2018-12-09 13:31:37,068 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:31:37,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:31:37,068 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:31:37,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:31:37,069 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:31:37,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:31:37,157 INFO L134 CoverageAnalysis]: Checked inductivity of 409 backedges. 24 proven. 20 refuted. 0 times theorem prover too weak. 365 trivial. 0 not checked. [2018-12-09 13:31:37,157 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:31:37,157 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:31:37,157 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 414 with the following transitions: [2018-12-09 13:31:37,157 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [529], [533], [539], [542], [546], [549], [555], [559], [562], [572], [575], [585], [588], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-09 13:31:37,159 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:31:37,159 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:31:37,201 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-12-09 13:31:37,201 INFO L272 AbstractInterpreter]: Visited 155 different actions 171 times. Merged at 8 different actions 8 times. Never widened. Performed 1531 root evaluator evaluations with a maximum evaluation depth of 3. Performed 1531 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 2 fixpoints after 2 different actions. Largest state had 60 variables. [2018-12-09 13:31:37,203 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:31:37,203 INFO L401 sIntCurrentIteration]: Generating AbsInt predicates [2018-12-09 13:31:37,331 INFO L227 lantSequenceWeakener]: Weakened 185 states. On average, predicates are now at 65.66% of their original sizes. [2018-12-09 13:31:37,331 INFO L416 sIntCurrentIteration]: Unifying AI predicates [2018-12-09 13:31:38,522 INFO L418 sIntCurrentIteration]: We unified 412 AI predicates to 412 [2018-12-09 13:31:38,522 INFO L427 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-12-09 13:31:38,522 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-12-09 13:31:38,522 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [66] imperfect sequences [8] total 72 [2018-12-09 13:31:38,522 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:31:38,522 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-12-09 13:31:38,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-12-09 13:31:38,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=492, Invalid=3798, Unknown=0, NotChecked=0, Total=4290 [2018-12-09 13:31:38,523 INFO L87 Difference]: Start difference. First operand 23992 states and 28992 transitions. Second operand 66 states. [2018-12-09 13:32:07,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:32:07,111 INFO L93 Difference]: Finished difference Result 37738 states and 45639 transitions. [2018-12-09 13:32:07,111 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-12-09 13:32:07,111 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 413 [2018-12-09 13:32:07,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:32:07,154 INFO L225 Difference]: With dead ends: 37738 [2018-12-09 13:32:07,154 INFO L226 Difference]: Without dead ends: 25176 [2018-12-09 13:32:07,174 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 457 GetRequests, 348 SyntacticMatches, 0 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3738 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1415, Invalid=10795, Unknown=0, NotChecked=0, Total=12210 [2018-12-09 13:32:07,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25176 states. [2018-12-09 13:32:08,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25176 to 25129. [2018-12-09 13:32:08,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25129 states. [2018-12-09 13:32:08,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25129 states to 25129 states and 30388 transitions. [2018-12-09 13:32:08,949 INFO L78 Accepts]: Start accepts. Automaton has 25129 states and 30388 transitions. Word has length 413 [2018-12-09 13:32:08,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:32:08,950 INFO L480 AbstractCegarLoop]: Abstraction has 25129 states and 30388 transitions. [2018-12-09 13:32:08,950 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-12-09 13:32:08,950 INFO L276 IsEmpty]: Start isEmpty. Operand 25129 states and 30388 transitions. [2018-12-09 13:32:08,972 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 451 [2018-12-09 13:32:08,972 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:32:08,972 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:32:08,973 INFO L423 AbstractCegarLoop]: === Iteration 37 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:32:08,973 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:08,973 INFO L82 PathProgramCache]: Analyzing trace with hash -735215562, now seen corresponding path program 1 times [2018-12-09 13:32:08,973 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:32:08,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:08,973 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:08,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:08,974 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:32:08,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:09,064 INFO L134 CoverageAnalysis]: Checked inductivity of 534 backedges. 70 proven. 2 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2018-12-09 13:32:09,064 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:09,064 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:32:09,064 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 451 with the following transitions: [2018-12-09 13:32:09,065 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [343], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [529], [533], [539], [542], [546], [549], [552], [555], [559], [562], [565], [572], [575], [578], [585], [588], [591], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-09 13:32:09,066 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:32:09,066 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:32:09,451 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 13:32:09,451 INFO L272 AbstractInterpreter]: Visited 182 different actions 1278 times. Merged at 49 different actions 243 times. Widened at 1 different actions 1 times. Performed 14853 root evaluator evaluations with a maximum evaluation depth of 3. Performed 14853 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 76 fixpoints after 19 different actions. Largest state had 60 variables. [2018-12-09 13:32:09,454 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:09,454 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 13:32:09,454 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:09,454 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 13:32:09,460 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:09,460 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 13:32:09,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:09,556 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 13:32:09,623 INFO L134 CoverageAnalysis]: Checked inductivity of 534 backedges. 335 proven. 0 refuted. 0 times theorem prover too weak. 199 trivial. 0 not checked. [2018-12-09 13:32:09,623 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 13:32:09,783 INFO L134 CoverageAnalysis]: Checked inductivity of 534 backedges. 84 proven. 15 refuted. 0 times theorem prover too weak. 435 trivial. 0 not checked. [2018-12-09 13:32:09,798 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-09 13:32:09,798 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 6 [2018-12-09 13:32:09,798 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:32:09,799 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 13:32:09,799 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 13:32:09,799 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:32:09,799 INFO L87 Difference]: Start difference. First operand 25129 states and 30388 transitions. Second operand 3 states. [2018-12-09 13:32:12,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:32:12,414 INFO L93 Difference]: Finished difference Result 63331 states and 81144 transitions. [2018-12-09 13:32:12,415 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 13:32:12,415 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 450 [2018-12-09 13:32:12,415 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:32:12,491 INFO L225 Difference]: With dead ends: 63331 [2018-12-09 13:32:12,491 INFO L226 Difference]: Without dead ends: 40478 [2018-12-09 13:32:12,543 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 904 GetRequests, 900 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:32:12,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40478 states. [2018-12-09 13:32:15,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40478 to 38574. [2018-12-09 13:32:15,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38574 states. [2018-12-09 13:32:15,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38574 states to 38574 states and 48792 transitions. [2018-12-09 13:32:15,323 INFO L78 Accepts]: Start accepts. Automaton has 38574 states and 48792 transitions. Word has length 450 [2018-12-09 13:32:15,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:32:15,323 INFO L480 AbstractCegarLoop]: Abstraction has 38574 states and 48792 transitions. [2018-12-09 13:32:15,323 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 13:32:15,323 INFO L276 IsEmpty]: Start isEmpty. Operand 38574 states and 48792 transitions. [2018-12-09 13:32:15,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 491 [2018-12-09 13:32:15,360 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:32:15,360 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:32:15,360 INFO L423 AbstractCegarLoop]: === Iteration 38 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:32:15,360 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:15,361 INFO L82 PathProgramCache]: Analyzing trace with hash 342535070, now seen corresponding path program 1 times [2018-12-09 13:32:15,361 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:32:15,361 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:15,361 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:15,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:15,362 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:32:15,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:15,464 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 38 proven. 26 refuted. 0 times theorem prover too weak. 584 trivial. 0 not checked. [2018-12-09 13:32:15,465 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:15,465 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:32:15,465 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 491 with the following transitions: [2018-12-09 13:32:15,465 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [207], [210], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [296], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [343], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [425], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [468], [484], [486], [488], [497], [499], [507], [510], [511], [512], [521], [524], [527], [529], [533], [536], [539], [542], [546], [549], [555], [559], [562], [565], [572], [575], [578], [585], [588], [591], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-09 13:32:15,466 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:32:15,466 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:32:16,148 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 13:32:16,148 INFO L272 AbstractInterpreter]: Visited 198 different actions 2252 times. Merged at 65 different actions 358 times. Widened at 2 different actions 3 times. Performed 26884 root evaluator evaluations with a maximum evaluation depth of 3. Performed 26884 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 111 fixpoints after 21 different actions. Largest state had 60 variables. [2018-12-09 13:32:16,150 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:16,150 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 13:32:16,150 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:16,150 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 13:32:16,156 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:16,156 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 13:32:16,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:16,261 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 13:32:16,351 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 469 proven. 0 refuted. 0 times theorem prover too weak. 179 trivial. 0 not checked. [2018-12-09 13:32:16,351 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 13:32:16,559 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 135 proven. 0 refuted. 0 times theorem prover too weak. 513 trivial. 0 not checked. [2018-12-09 13:32:16,574 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-12-09 13:32:16,574 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [8] total 10 [2018-12-09 13:32:16,574 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:32:16,574 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 13:32:16,574 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 13:32:16,575 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-12-09 13:32:16,575 INFO L87 Difference]: Start difference. First operand 38574 states and 48792 transitions. Second operand 3 states. [2018-12-09 13:32:19,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:32:19,463 INFO L93 Difference]: Finished difference Result 78903 states and 104090 transitions. [2018-12-09 13:32:19,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 13:32:19,463 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 490 [2018-12-09 13:32:19,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:32:19,545 INFO L225 Difference]: With dead ends: 78903 [2018-12-09 13:32:19,545 INFO L226 Difference]: Without dead ends: 41048 [2018-12-09 13:32:19,638 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 990 GetRequests, 980 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-12-09 13:32:19,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41048 states. [2018-12-09 13:32:22,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41048 to 41042. [2018-12-09 13:32:22,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41042 states. [2018-12-09 13:32:22,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41042 states to 41042 states and 49371 transitions. [2018-12-09 13:32:22,561 INFO L78 Accepts]: Start accepts. Automaton has 41042 states and 49371 transitions. Word has length 490 [2018-12-09 13:32:22,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:32:22,562 INFO L480 AbstractCegarLoop]: Abstraction has 41042 states and 49371 transitions. [2018-12-09 13:32:22,562 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 13:32:22,562 INFO L276 IsEmpty]: Start isEmpty. Operand 41042 states and 49371 transitions. [2018-12-09 13:32:22,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 448 [2018-12-09 13:32:22,591 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:32:22,592 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:32:22,592 INFO L423 AbstractCegarLoop]: === Iteration 39 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:32:22,592 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:22,592 INFO L82 PathProgramCache]: Analyzing trace with hash -203778320, now seen corresponding path program 1 times [2018-12-09 13:32:22,592 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:32:22,593 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:22,593 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:22,593 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:22,593 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:32:22,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:22,687 INFO L134 CoverageAnalysis]: Checked inductivity of 530 backedges. 68 proven. 31 refuted. 0 times theorem prover too weak. 431 trivial. 0 not checked. [2018-12-09 13:32:22,687 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:22,687 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:32:22,687 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 448 with the following transitions: [2018-12-09 13:32:22,687 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [529], [533], [539], [546], [549], [552], [555], [559], [562], [568], [572], [575], [578], [585], [588], [591], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-09 13:32:22,688 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:32:22,689 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:32:22,962 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 13:32:22,962 INFO L272 AbstractInterpreter]: Visited 180 different actions 951 times. Merged at 46 different actions 178 times. Widened at 1 different actions 1 times. Performed 9982 root evaluator evaluations with a maximum evaluation depth of 3. Performed 9982 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 56 fixpoints after 17 different actions. Largest state had 60 variables. [2018-12-09 13:32:22,964 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:22,964 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 13:32:22,964 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:22,964 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 13:32:22,971 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:22,971 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 13:32:23,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:23,071 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 13:32:23,148 INFO L134 CoverageAnalysis]: Checked inductivity of 530 backedges. 303 proven. 0 refuted. 0 times theorem prover too weak. 227 trivial. 0 not checked. [2018-12-09 13:32:23,148 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 13:32:23,337 INFO L134 CoverageAnalysis]: Checked inductivity of 530 backedges. 73 proven. 12 refuted. 0 times theorem prover too weak. 445 trivial. 0 not checked. [2018-12-09 13:32:23,352 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-09 13:32:23,352 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [8, 6] total 12 [2018-12-09 13:32:23,352 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:32:23,353 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-12-09 13:32:23,353 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-12-09 13:32:23,353 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2018-12-09 13:32:23,353 INFO L87 Difference]: Start difference. First operand 41042 states and 49371 transitions. Second operand 6 states. [2018-12-09 13:32:25,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:32:25,045 INFO L93 Difference]: Finished difference Result 61765 states and 74594 transitions. [2018-12-09 13:32:25,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-12-09 13:32:25,045 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 447 [2018-12-09 13:32:25,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:32:25,081 INFO L225 Difference]: With dead ends: 61765 [2018-12-09 13:32:25,081 INFO L226 Difference]: Without dead ends: 21032 [2018-12-09 13:32:25,127 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 906 GetRequests, 888 SyntacticMatches, 6 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2018-12-09 13:32:25,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21032 states. [2018-12-09 13:32:26,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21032 to 19794. [2018-12-09 13:32:26,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19794 states. [2018-12-09 13:32:26,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19794 states to 19794 states and 22585 transitions. [2018-12-09 13:32:26,404 INFO L78 Accepts]: Start accepts. Automaton has 19794 states and 22585 transitions. Word has length 447 [2018-12-09 13:32:26,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:32:26,405 INFO L480 AbstractCegarLoop]: Abstraction has 19794 states and 22585 transitions. [2018-12-09 13:32:26,405 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-12-09 13:32:26,405 INFO L276 IsEmpty]: Start isEmpty. Operand 19794 states and 22585 transitions. [2018-12-09 13:32:26,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 296 [2018-12-09 13:32:26,417 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:32:26,417 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:32:26,417 INFO L423 AbstractCegarLoop]: === Iteration 40 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:32:26,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:26,417 INFO L82 PathProgramCache]: Analyzing trace with hash 734138646, now seen corresponding path program 1 times [2018-12-09 13:32:26,417 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:32:26,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:26,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:26,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:26,418 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:32:26,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:26,481 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-12-09 13:32:26,481 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:26,481 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:32:26,481 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 296 with the following transitions: [2018-12-09 13:32:26,482 INFO L205 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [133], [136], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [533], [539], [546], [549], [552], [559], [562], [572], [575], [585], [588], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [662], [666], [667], [670], [671], [672], [673], [674], [676], [677], [678], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [738], [739], [740] [2018-12-09 13:32:26,483 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:32:26,483 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:32:26,655 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 13:32:26,655 INFO L272 AbstractInterpreter]: Visited 175 different actions 681 times. Merged at 42 different actions 127 times. Never widened. Performed 6585 root evaluator evaluations with a maximum evaluation depth of 3. Performed 6585 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 23 fixpoints after 11 different actions. Largest state had 60 variables. [2018-12-09 13:32:26,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:26,657 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 13:32:26,657 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:26,657 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 13:32:26,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:26,663 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 13:32:26,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:26,737 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 13:32:26,768 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 127 proven. 0 refuted. 0 times theorem prover too weak. 53 trivial. 0 not checked. [2018-12-09 13:32:26,768 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 13:32:26,900 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-12-09 13:32:26,915 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-09 13:32:26,916 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2018-12-09 13:32:26,916 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:32:26,916 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-12-09 13:32:26,916 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-12-09 13:32:26,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-12-09 13:32:26,916 INFO L87 Difference]: Start difference. First operand 19794 states and 22585 transitions. Second operand 4 states. [2018-12-09 13:32:28,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:32:28,636 INFO L93 Difference]: Finished difference Result 35884 states and 41952 transitions. [2018-12-09 13:32:28,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-12-09 13:32:28,636 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 295 [2018-12-09 13:32:28,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:32:28,667 INFO L225 Difference]: With dead ends: 35884 [2018-12-09 13:32:28,668 INFO L226 Difference]: Without dead ends: 21198 [2018-12-09 13:32:28,687 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 598 GetRequests, 591 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-12-09 13:32:28,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21198 states. [2018-12-09 13:32:30,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21198 to 20988. [2018-12-09 13:32:30,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20988 states. [2018-12-09 13:32:30,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20988 states to 20988 states and 24493 transitions. [2018-12-09 13:32:30,080 INFO L78 Accepts]: Start accepts. Automaton has 20988 states and 24493 transitions. Word has length 295 [2018-12-09 13:32:30,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:32:30,080 INFO L480 AbstractCegarLoop]: Abstraction has 20988 states and 24493 transitions. [2018-12-09 13:32:30,080 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-12-09 13:32:30,080 INFO L276 IsEmpty]: Start isEmpty. Operand 20988 states and 24493 transitions. [2018-12-09 13:32:30,095 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 518 [2018-12-09 13:32:30,095 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:32:30,096 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:32:30,096 INFO L423 AbstractCegarLoop]: === Iteration 41 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:32:30,096 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:30,096 INFO L82 PathProgramCache]: Analyzing trace with hash -924058014, now seen corresponding path program 1 times [2018-12-09 13:32:30,096 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:32:30,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:30,097 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:30,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:30,097 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:32:30,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:30,192 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 67 proven. 44 refuted. 0 times theorem prover too weak. 632 trivial. 0 not checked. [2018-12-09 13:32:30,193 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:30,193 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:32:30,193 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 518 with the following transitions: [2018-12-09 13:32:30,193 INFO L205 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [139], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [306], [309], [312], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [343], [345], [350], [355], [360], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [510], [511], [512], [521], [524], [527], [529], [533], [539], [542], [546], [549], [552], [559], [562], [568], [572], [575], [578], [581], [585], [588], [594], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [668], [669], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [696], [697], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-09 13:32:30,194 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:32:30,194 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:32:30,524 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 13:32:30,524 INFO L272 AbstractInterpreter]: Visited 190 different actions 1198 times. Merged at 60 different actions 213 times. Widened at 1 different actions 1 times. Performed 11832 root evaluator evaluations with a maximum evaluation depth of 3. Performed 11832 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 61 fixpoints after 19 different actions. Largest state had 60 variables. [2018-12-09 13:32:30,526 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:30,526 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 13:32:30,526 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:30,526 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 13:32:30,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:30,533 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 13:32:30,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:30,648 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 13:32:30,717 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 389 proven. 0 refuted. 0 times theorem prover too weak. 354 trivial. 0 not checked. [2018-12-09 13:32:30,717 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 13:32:31,030 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 67 proven. 2 refuted. 0 times theorem prover too weak. 674 trivial. 0 not checked. [2018-12-09 13:32:31,045 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-09 13:32:31,046 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5, 4] total 8 [2018-12-09 13:32:31,046 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:32:31,046 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 13:32:31,046 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 13:32:31,046 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-12-09 13:32:31,046 INFO L87 Difference]: Start difference. First operand 20988 states and 24493 transitions. Second operand 3 states. [2018-12-09 13:32:32,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:32:32,855 INFO L93 Difference]: Finished difference Result 45111 states and 53729 transitions. [2018-12-09 13:32:32,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 13:32:32,855 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 517 [2018-12-09 13:32:32,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:32:32,915 INFO L225 Difference]: With dead ends: 45111 [2018-12-09 13:32:32,915 INFO L226 Difference]: Without dead ends: 28341 [2018-12-09 13:32:32,951 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1041 GetRequests, 1034 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-12-09 13:32:32,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28341 states. [2018-12-09 13:32:34,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28341 to 28073. [2018-12-09 13:32:34,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28073 states. [2018-12-09 13:32:34,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28073 states to 28073 states and 32754 transitions. [2018-12-09 13:32:34,909 INFO L78 Accepts]: Start accepts. Automaton has 28073 states and 32754 transitions. Word has length 517 [2018-12-09 13:32:34,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:32:34,910 INFO L480 AbstractCegarLoop]: Abstraction has 28073 states and 32754 transitions. [2018-12-09 13:32:34,910 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 13:32:34,910 INFO L276 IsEmpty]: Start isEmpty. Operand 28073 states and 32754 transitions. [2018-12-09 13:32:34,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 584 [2018-12-09 13:32:34,925 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:32:34,925 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:32:34,925 INFO L423 AbstractCegarLoop]: === Iteration 42 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:32:34,925 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:34,926 INFO L82 PathProgramCache]: Analyzing trace with hash 225695341, now seen corresponding path program 1 times [2018-12-09 13:32:34,926 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:32:34,926 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:34,926 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:34,926 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:34,926 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:32:34,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:35,027 INFO L134 CoverageAnalysis]: Checked inductivity of 998 backedges. 67 proven. 50 refuted. 0 times theorem prover too weak. 881 trivial. 0 not checked. [2018-12-09 13:32:35,027 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:35,027 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:32:35,028 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 584 with the following transitions: [2018-12-09 13:32:35,028 INFO L205 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [139], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [214], [216], [218], [219], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [298], [301], [304], [306], [309], [312], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [343], [345], [350], [353], [355], [360], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [425], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [468], [484], [486], [488], [497], [499], [507], [510], [511], [512], [521], [524], [527], [529], [533], [536], [539], [542], [546], [549], [555], [559], [562], [565], [568], [572], [575], [578], [581], [585], [588], [594], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [649], [652], [657], [662], [666], [667], [668], [669], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [736], [737], [738], [739], [740] [2018-12-09 13:32:35,029 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:32:35,029 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:32:35,972 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 13:32:35,973 INFO L272 AbstractInterpreter]: Visited 238 different actions 3730 times. Merged at 84 different actions 768 times. Widened at 1 different actions 1 times. Performed 31831 root evaluator evaluations with a maximum evaluation depth of 3. Performed 31831 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 222 fixpoints after 29 different actions. Largest state had 60 variables. [2018-12-09 13:32:35,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:35,974 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 13:32:35,974 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:35,974 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 13:32:35,980 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:35,980 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 13:32:36,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:36,095 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 13:32:36,178 INFO L134 CoverageAnalysis]: Checked inductivity of 998 backedges. 564 proven. 0 refuted. 0 times theorem prover too weak. 434 trivial. 0 not checked. [2018-12-09 13:32:36,178 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 13:32:36,433 INFO L134 CoverageAnalysis]: Checked inductivity of 998 backedges. 67 proven. 50 refuted. 0 times theorem prover too weak. 881 trivial. 0 not checked. [2018-12-09 13:32:36,449 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-09 13:32:36,449 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 3 [2018-12-09 13:32:36,449 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:32:36,449 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 13:32:36,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 13:32:36,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 13:32:36,450 INFO L87 Difference]: Start difference. First operand 28073 states and 32754 transitions. Second operand 3 states. [2018-12-09 13:32:37,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:32:37,707 INFO L93 Difference]: Finished difference Result 43112 states and 49994 transitions. [2018-12-09 13:32:37,708 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 13:32:37,708 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 583 [2018-12-09 13:32:37,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:32:37,735 INFO L225 Difference]: With dead ends: 43112 [2018-12-09 13:32:37,735 INFO L226 Difference]: Without dead ends: 16620 [2018-12-09 13:32:37,763 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1168 GetRequests, 1165 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-12-09 13:32:37,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16620 states. [2018-12-09 13:32:38,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16620 to 16269. [2018-12-09 13:32:38,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16269 states. [2018-12-09 13:32:38,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16269 states to 16269 states and 18244 transitions. [2018-12-09 13:32:38,851 INFO L78 Accepts]: Start accepts. Automaton has 16269 states and 18244 transitions. Word has length 583 [2018-12-09 13:32:38,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:32:38,851 INFO L480 AbstractCegarLoop]: Abstraction has 16269 states and 18244 transitions. [2018-12-09 13:32:38,851 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 13:32:38,851 INFO L276 IsEmpty]: Start isEmpty. Operand 16269 states and 18244 transitions. [2018-12-09 13:32:38,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 693 [2018-12-09 13:32:38,860 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:32:38,861 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:32:38,861 INFO L423 AbstractCegarLoop]: === Iteration 43 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:32:38,861 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:38,861 INFO L82 PathProgramCache]: Analyzing trace with hash -1162149116, now seen corresponding path program 1 times [2018-12-09 13:32:38,861 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:32:38,861 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:38,861 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:38,862 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:38,862 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:32:38,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:39,010 INFO L134 CoverageAnalysis]: Checked inductivity of 1566 backedges. 45 proven. 12 refuted. 0 times theorem prover too weak. 1509 trivial. 0 not checked. [2018-12-09 13:32:39,010 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:39,010 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-12-09 13:32:39,010 INFO L203 CegarAbsIntRunner]: Running AI on error trace of length 693 with the following transitions: [2018-12-09 13:32:39,010 INFO L205 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [114], [119], [122], [124], [129], [131], [132], [133], [136], [139], [141], [143], [145], [147], [148], [153], [159], [165], [171], [177], [183], [189], [195], [201], [203], [204], [207], [210], [214], [216], [218], [219], [224], [230], [236], [242], [248], [254], [260], [266], [272], [274], [275], [278], [281], [283], [285], [287], [289], [290], [291], [293], [296], [298], [301], [304], [306], [309], [312], [314], [317], [320], [322], [325], [328], [330], [332], [334], [335], [338], [340], [345], [348], [350], [355], [360], [362], [363], [368], [374], [380], [386], [392], [398], [404], [410], [416], [418], [419], [422], [425], [427], [429], [431], [433], [434], [437], [443], [449], [455], [461], [465], [468], [484], [486], [488], [497], [499], [507], [508], [509], [510], [511], [512], [521], [524], [527], [529], [533], [536], [539], [546], [549], [555], [559], [562], [565], [572], [575], [578], [585], [588], [594], [599], [600], [603], [606], [608], [610], [612], [614], [615], [616], [630], [632], [634], [636], [641], [644], [652], [657], [662], [666], [667], [668], [669], [670], [671], [672], [673], [674], [676], [677], [678], [680], [681], [682], [683], [684], [685], [686], [687], [688], [689], [690], [691], [692], [693], [694], [695], [696], [697], [698], [699], [700], [701], [702], [703], [704], [705], [706], [707], [708], [709], [710], [711], [712], [713], [714], [715], [716], [717], [718], [719], [720], [721], [722], [723], [724], [725], [726], [727], [728], [729], [730], [731], [732], [733], [734], [735], [736], [737], [738], [739], [740] [2018-12-09 13:32:39,011 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-12-09 13:32:39,011 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-12-09 13:32:40,198 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2018-12-09 13:32:40,198 INFO L272 AbstractInterpreter]: Visited 234 different actions 4022 times. Merged at 91 different actions 827 times. Widened at 1 different actions 2 times. Performed 41494 root evaluator evaluations with a maximum evaluation depth of 3. Performed 41494 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Found 227 fixpoints after 28 different actions. Largest state had 60 variables. [2018-12-09 13:32:40,199 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:40,199 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-12-09 13:32:40,199 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-12-09 13:32:40,199 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-12-09 13:32:40,205 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:40,205 INFO L286 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-12-09 13:32:40,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-12-09 13:32:40,344 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-12-09 13:32:40,456 INFO L134 CoverageAnalysis]: Checked inductivity of 1566 backedges. 729 proven. 0 refuted. 0 times theorem prover too weak. 837 trivial. 0 not checked. [2018-12-09 13:32:40,456 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-12-09 13:32:40,784 INFO L134 CoverageAnalysis]: Checked inductivity of 1566 backedges. 86 proven. 101 refuted. 0 times theorem prover too weak. 1379 trivial. 0 not checked. [2018-12-09 13:32:40,800 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-12-09 13:32:40,800 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 6 [2018-12-09 13:32:40,800 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-12-09 13:32:40,801 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-12-09 13:32:40,801 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-12-09 13:32:40,801 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:32:40,801 INFO L87 Difference]: Start difference. First operand 16269 states and 18244 transitions. Second operand 3 states. [2018-12-09 13:32:41,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-12-09 13:32:41,671 INFO L93 Difference]: Finished difference Result 26006 states and 29286 transitions. [2018-12-09 13:32:41,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-12-09 13:32:41,672 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 692 [2018-12-09 13:32:41,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-12-09 13:32:41,684 INFO L225 Difference]: With dead ends: 26006 [2018-12-09 13:32:41,684 INFO L226 Difference]: Without dead ends: 5326 [2018-12-09 13:32:41,704 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1387 GetRequests, 1383 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-12-09 13:32:41,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5326 states. [2018-12-09 13:32:42,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5326 to 4771. [2018-12-09 13:32:42,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4771 states. [2018-12-09 13:32:42,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4771 states to 4771 states and 5232 transitions. [2018-12-09 13:32:42,062 INFO L78 Accepts]: Start accepts. Automaton has 4771 states and 5232 transitions. Word has length 692 [2018-12-09 13:32:42,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-12-09 13:32:42,062 INFO L480 AbstractCegarLoop]: Abstraction has 4771 states and 5232 transitions. [2018-12-09 13:32:42,062 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-12-09 13:32:42,063 INFO L276 IsEmpty]: Start isEmpty. Operand 4771 states and 5232 transitions. [2018-12-09 13:32:42,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 443 [2018-12-09 13:32:42,066 INFO L394 BasicCegarLoop]: Found error trace [2018-12-09 13:32:42,066 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-12-09 13:32:42,067 INFO L423 AbstractCegarLoop]: === Iteration 44 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-12-09 13:32:42,067 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-12-09 13:32:42,067 INFO L82 PathProgramCache]: Analyzing trace with hash 613832725, now seen corresponding path program 1 times [2018-12-09 13:32:42,067 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-12-09 13:32:42,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:42,067 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-12-09 13:32:42,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-12-09 13:32:42,068 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-12-09 13:32:42,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 13:32:42,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-12-09 13:32:42,227 INFO L469 BasicCegarLoop]: Counterexample might be feasible [2018-12-09 13:32:42,361 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 09.12 01:32:42 BoogieIcfgContainer [2018-12-09 13:32:42,361 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-12-09 13:32:42,361 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-12-09 13:32:42,361 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-12-09 13:32:42,361 INFO L276 PluginConnector]: Witness Printer initialized [2018-12-09 13:32:42,362 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.12 01:29:10" (3/4) ... [2018-12-09 13:32:42,364 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-12-09 13:32:42,478 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_143cca89-570e-4203-b093-5036458d059f/bin-2019/utaipan/witness.graphml [2018-12-09 13:32:42,478 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-12-09 13:32:42,479 INFO L168 Benchmark]: Toolchain (without parser) took 212939.03 ms. Allocated memory was 1.0 GB in the beginning and 4.6 GB in the end (delta: 3.6 GB). Free memory was 949.7 MB in the beginning and 954.8 MB in the end (delta: -5.1 MB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. [2018-12-09 13:32:42,480 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 976.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-12-09 13:32:42,480 INFO L168 Benchmark]: CACSL2BoogieTranslator took 176.63 ms. Allocated memory is still 1.0 GB. Free memory was 949.7 MB in the beginning and 933.5 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. [2018-12-09 13:32:42,480 INFO L168 Benchmark]: Boogie Procedure Inliner took 21.67 ms. Allocated memory is still 1.0 GB. Free memory was 933.5 MB in the beginning and 987.4 MB in the end (delta: -54.0 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. [2018-12-09 13:32:42,481 INFO L168 Benchmark]: Boogie Preprocessor took 49.28 ms. Allocated memory is still 1.0 GB. Free memory was 987.4 MB in the beginning and 1.0 GB in the end (delta: -20.0 MB). Peak memory consumption was 8.2 kB. Max. memory is 11.5 GB. [2018-12-09 13:32:42,481 INFO L168 Benchmark]: RCFGBuilder took 352.99 ms. Allocated memory is still 1.0 GB. Free memory was 1.0 GB in the beginning and 957.4 MB in the end (delta: 50.0 MB). Peak memory consumption was 50.0 MB. Max. memory is 11.5 GB. [2018-12-09 13:32:42,481 INFO L168 Benchmark]: TraceAbstraction took 212218.31 ms. Allocated memory was 1.0 GB in the beginning and 4.6 GB in the end (delta: 3.6 GB). Free memory was 957.4 MB in the beginning and 1.1 GB in the end (delta: -135.9 MB). Peak memory consumption was 3.4 GB. Max. memory is 11.5 GB. [2018-12-09 13:32:42,481 INFO L168 Benchmark]: Witness Printer took 117.34 ms. Allocated memory is still 4.6 GB. Free memory was 1.1 GB in the beginning and 954.8 MB in the end (delta: 138.5 MB). Peak memory consumption was 138.5 MB. Max. memory is 11.5 GB. [2018-12-09 13:32:42,482 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 976.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 176.63 ms. Allocated memory is still 1.0 GB. Free memory was 949.7 MB in the beginning and 933.5 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 21.67 ms. Allocated memory is still 1.0 GB. Free memory was 933.5 MB in the beginning and 987.4 MB in the end (delta: -54.0 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 49.28 ms. Allocated memory is still 1.0 GB. Free memory was 987.4 MB in the beginning and 1.0 GB in the end (delta: -20.0 MB). Peak memory consumption was 8.2 kB. Max. memory is 11.5 GB. * RCFGBuilder took 352.99 ms. Allocated memory is still 1.0 GB. Free memory was 1.0 GB in the beginning and 957.4 MB in the end (delta: 50.0 MB). Peak memory consumption was 50.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 212218.31 ms. Allocated memory was 1.0 GB in the beginning and 4.6 GB in the end (delta: 3.6 GB). Free memory was 957.4 MB in the beginning and 1.1 GB in the end (delta: -135.9 MB). Peak memory consumption was 3.4 GB. Max. memory is 11.5 GB. * Witness Printer took 117.34 ms. Allocated memory is still 4.6 GB. Free memory was 1.1 GB in the beginning and 954.8 MB in the end (delta: 138.5 MB). Peak memory consumption was 138.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; VAL [\old(E_1)=21, \old(E_2)=5, \old(E_3)=25, \old(E_4)=11, \old(M_E)=17, \old(m_i)=7, \old(m_pc)=15, \old(m_st)=16, \old(T1_E)=3, \old(t1_i)=19, \old(t1_pc)=9, \old(t1_st)=4, \old(T2_E)=18, \old(t2_i)=6, \old(t2_pc)=10, \old(t2_st)=13, \old(T3_E)=23, \old(t3_i)=24, \old(t3_pc)=8, \old(t3_st)=14, \old(T4_E)=26, \old(t4_i)=20, \old(t4_pc)=22, \old(t4_st)=12, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L811] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L815] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L815] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L816] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L759] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L331] COND TRUE m_i == 1 [L332] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L760] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L492] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L497] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L502] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L761] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L762] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L247] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L266] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L285] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L304] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L762] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L545] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L550] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L555] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L763] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L766] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L769] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L770] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L397] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L90] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L431] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L125] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L445] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L195] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L206] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L208] t4_pc = 1 [L209] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L473] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L425] COND FALSE !(t1_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L439] COND FALSE !(t2_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=0, tmp_ndt_5=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L459] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L467] COND FALSE !(t4_st == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L401] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND TRUE \read(tmp_ndt_1) [L416] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L417] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L49] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L60] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L63] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND TRUE E_1 == 1 [L249] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND TRUE \read(tmp___0) [L614] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L64] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L65] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L68] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L70] m_pc = 1 [L71] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L417] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L431] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L90] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L93] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L109] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND TRUE E_2 == 1 [L268] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND TRUE \read(tmp___1) [L622] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L110] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L111] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L101] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L431] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L445] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L125] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L128] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L144] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND TRUE E_3 == 1 [L287] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND TRUE \read(tmp___2) [L630] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L145] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L146] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L136] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L445] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L459] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L163] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L179] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L180] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L651] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L225] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND TRUE E_4 == 1 [L306] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND TRUE \read(tmp___3) [L638] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L651] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L180] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L181] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L171] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L459] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L473] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L195] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L198] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L214] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 27 procedures, 229 locations, 1 error locations. UNSAFE Result, 212.1s OverallTime, 44 OverallIterations, 8 TraceHistogramMax, 160.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 16385 SDtfs, 29247 SDslu, 65875 SDs, 0 SdLazy, 42989 SolverSat, 8202 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 29.8s Time, PredicateUnifierStatistics: 18 DeclaredPredicates, 10911 GetRequests, 9793 SyntacticMatches, 65 SemanticMatches, 1053 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27736 ImplicationChecksByTransitivity, 19.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=41042occurred in iteration=38, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 4.8s AbstIntTime, 19 AbstIntIterations, 9 AbstIntStrong, 0.9933137762598749 AbsIntWeakeningRatio, 0.600100857286939 AbsIntAvgWeakeningVarsNumRemoved, 18.019162884518405 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 29.4s AutomataMinimizationTime, 43 MinimizatonAttempts, 6973 StatesRemovedByMinimization, 40 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.3s SsaConstructionTime, 0.9s SatisfiabilityAnalysisTime, 4.0s InterpolantComputationTime, 13833 NumberOfCodeBlocks, 13833 NumberOfCodeBlocksAsserted, 54 NumberOfCheckSat, 17460 ConstructedInterpolants, 0 QuantifiedInterpolants, 8197929 SizeOfPredicates, 9 NumberOfNonLiveVariables, 16624 ConjunctsInSsa, 42 ConjunctsInUnsatCore, 63 InterpolantComputations, 36 PerfectInterpolantSequences, 16777/17279 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...