./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/systemc/toy1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 678e0110 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/systemc/toy1.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-678e011 [2019-11-19 21:23:49,351 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-19 21:23:49,354 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-19 21:23:49,374 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-19 21:23:49,375 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-19 21:23:49,377 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-19 21:23:49,380 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-19 21:23:49,391 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-19 21:23:49,396 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-19 21:23:49,401 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-19 21:23:49,403 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-19 21:23:49,405 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-19 21:23:49,405 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-19 21:23:49,408 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-19 21:23:49,410 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-19 21:23:49,411 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-19 21:23:49,413 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-19 21:23:49,414 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-19 21:23:49,417 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-19 21:23:49,422 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-19 21:23:49,426 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-19 21:23:49,430 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-19 21:23:49,433 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-19 21:23:49,436 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-19 21:23:49,439 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-19 21:23:49,440 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-19 21:23:49,440 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-19 21:23:49,442 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-19 21:23:49,443 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-19 21:23:49,444 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-19 21:23:49,444 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-19 21:23:49,445 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-19 21:23:49,446 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-19 21:23:49,447 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-19 21:23:49,449 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-19 21:23:49,449 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-19 21:23:49,450 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-19 21:23:49,450 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-19 21:23:49,451 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-19 21:23:49,452 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-19 21:23:49,454 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-19 21:23:49,455 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-19 21:23:49,477 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-19 21:23:49,477 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-19 21:23:49,479 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-19 21:23:49,479 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-19 21:23:49,479 INFO L138 SettingsManager]: * Use SBE=true [2019-11-19 21:23:49,480 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-19 21:23:49,480 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-19 21:23:49,480 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-19 21:23:49,480 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-19 21:23:49,480 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-19 21:23:49,481 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-19 21:23:49,481 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-19 21:23:49,481 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-19 21:23:49,481 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-19 21:23:49,481 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-19 21:23:49,482 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-19 21:23:49,482 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-19 21:23:49,482 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-19 21:23:49,482 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-19 21:23:49,482 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-19 21:23:49,483 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-19 21:23:49,483 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-19 21:23:49,483 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-19 21:23:49,483 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-19 21:23:49,484 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-19 21:23:49,484 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-19 21:23:49,484 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-19 21:23:49,484 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-19 21:23:49,484 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 [2019-11-19 21:23:49,820 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-19 21:23:49,832 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-19 21:23:49,835 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-19 21:23:49,837 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-19 21:23:49,837 INFO L275 PluginConnector]: CDTParser initialized [2019-11-19 21:23:49,839 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/toy1.cil.c [2019-11-19 21:23:49,927 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d09705bc6/705373a0c6fd47e3a595bd2e93e2b135/FLAG70b72e170 [2019-11-19 21:23:50,420 INFO L306 CDTParser]: Found 1 translation units. [2019-11-19 21:23:50,423 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/toy1.cil.c [2019-11-19 21:23:50,437 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d09705bc6/705373a0c6fd47e3a595bd2e93e2b135/FLAG70b72e170 [2019-11-19 21:23:50,755 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d09705bc6/705373a0c6fd47e3a595bd2e93e2b135 [2019-11-19 21:23:50,758 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-19 21:23:50,760 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-19 21:23:50,761 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-19 21:23:50,761 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-19 21:23:50,765 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-19 21:23:50,765 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 09:23:50" (1/1) ... [2019-11-19 21:23:50,768 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@701c10e5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:50, skipping insertion in model container [2019-11-19 21:23:50,769 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 09:23:50" (1/1) ... [2019-11-19 21:23:50,779 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-19 21:23:50,818 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-19 21:23:51,063 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-19 21:23:51,069 INFO L188 MainTranslator]: Completed pre-run [2019-11-19 21:23:51,216 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-19 21:23:51,236 INFO L192 MainTranslator]: Completed translation [2019-11-19 21:23:51,237 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51 WrapperNode [2019-11-19 21:23:51,237 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-19 21:23:51,238 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-19 21:23:51,238 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-19 21:23:51,238 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-19 21:23:51,246 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51" (1/1) ... [2019-11-19 21:23:51,254 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51" (1/1) ... [2019-11-19 21:23:51,288 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-19 21:23:51,289 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-19 21:23:51,289 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-19 21:23:51,289 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-19 21:23:51,297 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51" (1/1) ... [2019-11-19 21:23:51,297 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51" (1/1) ... [2019-11-19 21:23:51,300 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51" (1/1) ... [2019-11-19 21:23:51,300 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51" (1/1) ... [2019-11-19 21:23:51,306 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51" (1/1) ... [2019-11-19 21:23:51,317 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51" (1/1) ... [2019-11-19 21:23:51,320 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51" (1/1) ... [2019-11-19 21:23:51,325 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-19 21:23:51,326 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-19 21:23:51,326 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-19 21:23:51,326 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-19 21:23:51,327 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-19 21:23:51,390 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-19 21:23:51,390 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-19 21:23:52,099 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-19 21:23:52,103 INFO L285 CfgBuilder]: Removed 28 assume(true) statements. [2019-11-19 21:23:52,104 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 09:23:52 BoogieIcfgContainer [2019-11-19 21:23:52,105 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-19 21:23:52,107 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-19 21:23:52,108 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-19 21:23:52,111 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-19 21:23:52,112 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 19.11 09:23:50" (1/3) ... [2019-11-19 21:23:52,115 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@55b58586 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 19.11 09:23:52, skipping insertion in model container [2019-11-19 21:23:52,116 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 09:23:51" (2/3) ... [2019-11-19 21:23:52,117 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@55b58586 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 19.11 09:23:52, skipping insertion in model container [2019-11-19 21:23:52,117 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 09:23:52" (3/3) ... [2019-11-19 21:23:52,120 INFO L109 eAbstractionObserver]: Analyzing ICFG toy1.cil.c [2019-11-19 21:23:52,131 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-19 21:23:52,140 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-19 21:23:52,152 INFO L249 AbstractCegarLoop]: Starting to check reachability of 2 error locations. [2019-11-19 21:23:52,195 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-19 21:23:52,195 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-19 21:23:52,196 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-19 21:23:52,196 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-19 21:23:52,196 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-19 21:23:52,197 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-19 21:23:52,197 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-19 21:23:52,197 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-19 21:23:52,227 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states. [2019-11-19 21:23:52,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-19 21:23:52,239 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:52,240 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:52,241 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:52,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:52,247 INFO L82 PathProgramCache]: Analyzing trace with hash -895778166, now seen corresponding path program 1 times [2019-11-19 21:23:52,255 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:52,255 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454652768] [2019-11-19 21:23:52,256 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:52,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:52,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:52,467 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454652768] [2019-11-19 21:23:52,468 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:52,468 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:52,470 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635533180] [2019-11-19 21:23:52,476 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:52,476 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:52,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:52,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:52,494 INFO L87 Difference]: Start difference. First operand 129 states. Second operand 3 states. [2019-11-19 21:23:52,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:52,541 INFO L93 Difference]: Finished difference Result 250 states and 461 transitions. [2019-11-19 21:23:52,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:52,543 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-19 21:23:52,544 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:52,555 INFO L225 Difference]: With dead ends: 250 [2019-11-19 21:23:52,555 INFO L226 Difference]: Without dead ends: 125 [2019-11-19 21:23:52,559 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:52,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2019-11-19 21:23:52,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 125. [2019-11-19 21:23:52,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2019-11-19 21:23:52,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 218 transitions. [2019-11-19 21:23:52,619 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 218 transitions. Word has length 36 [2019-11-19 21:23:52,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:52,619 INFO L462 AbstractCegarLoop]: Abstraction has 125 states and 218 transitions. [2019-11-19 21:23:52,619 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:52,620 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 218 transitions. [2019-11-19 21:23:52,621 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-19 21:23:52,622 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:52,622 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:52,622 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:52,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:52,623 INFO L82 PathProgramCache]: Analyzing trace with hash -1597378040, now seen corresponding path program 1 times [2019-11-19 21:23:52,623 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:52,623 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [840462333] [2019-11-19 21:23:52,623 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:52,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:52,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:52,708 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [840462333] [2019-11-19 21:23:52,708 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:52,708 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:52,708 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [418872803] [2019-11-19 21:23:52,710 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:52,711 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:52,711 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:52,711 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:52,711 INFO L87 Difference]: Start difference. First operand 125 states and 218 transitions. Second operand 3 states. [2019-11-19 21:23:52,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:52,767 INFO L93 Difference]: Finished difference Result 240 states and 420 transitions. [2019-11-19 21:23:52,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:52,770 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-19 21:23:52,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:52,772 INFO L225 Difference]: With dead ends: 240 [2019-11-19 21:23:52,773 INFO L226 Difference]: Without dead ends: 125 [2019-11-19 21:23:52,775 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:52,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2019-11-19 21:23:52,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 125. [2019-11-19 21:23:52,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2019-11-19 21:23:52,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 217 transitions. [2019-11-19 21:23:52,791 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 217 transitions. Word has length 36 [2019-11-19 21:23:52,791 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:52,791 INFO L462 AbstractCegarLoop]: Abstraction has 125 states and 217 transitions. [2019-11-19 21:23:52,791 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:52,792 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 217 transitions. [2019-11-19 21:23:52,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-19 21:23:52,794 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:52,794 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:52,794 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:52,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:52,795 INFO L82 PathProgramCache]: Analyzing trace with hash -211174646, now seen corresponding path program 1 times [2019-11-19 21:23:52,795 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:52,796 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970395004] [2019-11-19 21:23:52,796 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:52,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:52,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:52,887 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970395004] [2019-11-19 21:23:52,888 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:52,888 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:52,888 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462157645] [2019-11-19 21:23:52,891 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:52,891 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:52,893 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:52,893 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:52,894 INFO L87 Difference]: Start difference. First operand 125 states and 217 transitions. Second operand 3 states. [2019-11-19 21:23:53,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:53,037 INFO L93 Difference]: Finished difference Result 328 states and 568 transitions. [2019-11-19 21:23:53,039 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:53,039 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-19 21:23:53,040 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:53,042 INFO L225 Difference]: With dead ends: 328 [2019-11-19 21:23:53,043 INFO L226 Difference]: Without dead ends: 214 [2019-11-19 21:23:53,044 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:53,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2019-11-19 21:23:53,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 200. [2019-11-19 21:23:53,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200 states. [2019-11-19 21:23:53,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 335 transitions. [2019-11-19 21:23:53,073 INFO L78 Accepts]: Start accepts. Automaton has 200 states and 335 transitions. Word has length 36 [2019-11-19 21:23:53,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:53,074 INFO L462 AbstractCegarLoop]: Abstraction has 200 states and 335 transitions. [2019-11-19 21:23:53,074 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:53,074 INFO L276 IsEmpty]: Start isEmpty. Operand 200 states and 335 transitions. [2019-11-19 21:23:53,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-19 21:23:53,076 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:53,077 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:53,077 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:53,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:53,078 INFO L82 PathProgramCache]: Analyzing trace with hash 1832431686, now seen corresponding path program 1 times [2019-11-19 21:23:53,078 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:53,079 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700006359] [2019-11-19 21:23:53,079 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:53,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:53,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:53,130 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700006359] [2019-11-19 21:23:53,130 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:53,130 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-19 21:23:53,131 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062063628] [2019-11-19 21:23:53,132 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-19 21:23:53,132 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:53,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-19 21:23:53,133 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-19 21:23:53,133 INFO L87 Difference]: Start difference. First operand 200 states and 335 transitions. Second operand 4 states. [2019-11-19 21:23:53,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:53,302 INFO L93 Difference]: Finished difference Result 542 states and 911 transitions. [2019-11-19 21:23:53,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-19 21:23:53,303 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-19 21:23:53,304 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:53,306 INFO L225 Difference]: With dead ends: 542 [2019-11-19 21:23:53,307 INFO L226 Difference]: Without dead ends: 354 [2019-11-19 21:23:53,309 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-19 21:23:53,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states. [2019-11-19 21:23:53,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 344. [2019-11-19 21:23:53,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 344 states. [2019-11-19 21:23:53,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 344 states to 344 states and 577 transitions. [2019-11-19 21:23:53,336 INFO L78 Accepts]: Start accepts. Automaton has 344 states and 577 transitions. Word has length 36 [2019-11-19 21:23:53,336 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:53,337 INFO L462 AbstractCegarLoop]: Abstraction has 344 states and 577 transitions. [2019-11-19 21:23:53,337 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-19 21:23:53,337 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 577 transitions. [2019-11-19 21:23:53,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-19 21:23:53,340 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:53,340 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:53,340 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:53,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:53,341 INFO L82 PathProgramCache]: Analyzing trace with hash -539307576, now seen corresponding path program 1 times [2019-11-19 21:23:53,341 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:53,342 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508449036] [2019-11-19 21:23:53,342 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:53,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:53,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:53,387 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [508449036] [2019-11-19 21:23:53,387 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:53,388 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-19 21:23:53,388 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [180075041] [2019-11-19 21:23:53,388 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-19 21:23:53,389 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:53,389 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-19 21:23:53,390 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-19 21:23:53,390 INFO L87 Difference]: Start difference. First operand 344 states and 577 transitions. Second operand 4 states. [2019-11-19 21:23:53,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:53,516 INFO L93 Difference]: Finished difference Result 967 states and 1626 transitions. [2019-11-19 21:23:53,517 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-19 21:23:53,517 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-19 21:23:53,518 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:53,522 INFO L225 Difference]: With dead ends: 967 [2019-11-19 21:23:53,522 INFO L226 Difference]: Without dead ends: 636 [2019-11-19 21:23:53,524 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-19 21:23:53,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states. [2019-11-19 21:23:53,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 626. [2019-11-19 21:23:53,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 626 states. [2019-11-19 21:23:53,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 1047 transitions. [2019-11-19 21:23:53,570 INFO L78 Accepts]: Start accepts. Automaton has 626 states and 1047 transitions. Word has length 36 [2019-11-19 21:23:53,570 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:53,570 INFO L462 AbstractCegarLoop]: Abstraction has 626 states and 1047 transitions. [2019-11-19 21:23:53,571 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-19 21:23:53,571 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 1047 transitions. [2019-11-19 21:23:53,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-19 21:23:53,574 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:53,574 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:53,575 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:53,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:53,575 INFO L82 PathProgramCache]: Analyzing trace with hash -477267962, now seen corresponding path program 1 times [2019-11-19 21:23:53,576 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:53,576 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806541493] [2019-11-19 21:23:53,576 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:53,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:53,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:53,622 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806541493] [2019-11-19 21:23:53,623 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:53,623 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-19 21:23:53,623 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [851691236] [2019-11-19 21:23:53,626 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-19 21:23:53,626 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:53,627 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-19 21:23:53,627 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-19 21:23:53,627 INFO L87 Difference]: Start difference. First operand 626 states and 1047 transitions. Second operand 4 states. [2019-11-19 21:23:53,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:53,812 INFO L93 Difference]: Finished difference Result 1903 states and 3163 transitions. [2019-11-19 21:23:53,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-19 21:23:53,813 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-19 21:23:53,813 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:53,824 INFO L225 Difference]: With dead ends: 1903 [2019-11-19 21:23:53,824 INFO L226 Difference]: Without dead ends: 1291 [2019-11-19 21:23:53,826 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-19 21:23:53,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1291 states. [2019-11-19 21:23:53,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1291 to 1281. [2019-11-19 21:23:53,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1281 states. [2019-11-19 21:23:53,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1281 states to 1281 states and 2107 transitions. [2019-11-19 21:23:53,902 INFO L78 Accepts]: Start accepts. Automaton has 1281 states and 2107 transitions. Word has length 36 [2019-11-19 21:23:53,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:53,904 INFO L462 AbstractCegarLoop]: Abstraction has 1281 states and 2107 transitions. [2019-11-19 21:23:53,905 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-19 21:23:53,905 INFO L276 IsEmpty]: Start isEmpty. Operand 1281 states and 2107 transitions. [2019-11-19 21:23:53,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-19 21:23:53,910 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:53,910 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:53,910 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:53,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:53,916 INFO L82 PathProgramCache]: Analyzing trace with hash -336719352, now seen corresponding path program 1 times [2019-11-19 21:23:53,916 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:53,918 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395199046] [2019-11-19 21:23:53,918 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:53,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:54,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:54,024 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395199046] [2019-11-19 21:23:54,024 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:54,025 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:54,025 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596679263] [2019-11-19 21:23:54,026 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:54,026 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:54,026 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:54,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:54,027 INFO L87 Difference]: Start difference. First operand 1281 states and 2107 transitions. Second operand 3 states. [2019-11-19 21:23:54,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:54,167 INFO L93 Difference]: Finished difference Result 2615 states and 4310 transitions. [2019-11-19 21:23:54,168 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:54,168 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-19 21:23:54,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:54,177 INFO L225 Difference]: With dead ends: 2615 [2019-11-19 21:23:54,178 INFO L226 Difference]: Without dead ends: 1391 [2019-11-19 21:23:54,181 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:54,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1391 states. [2019-11-19 21:23:54,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1391 to 1382. [2019-11-19 21:23:54,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1382 states. [2019-11-19 21:23:54,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1382 states to 1382 states and 2266 transitions. [2019-11-19 21:23:54,265 INFO L78 Accepts]: Start accepts. Automaton has 1382 states and 2266 transitions. Word has length 36 [2019-11-19 21:23:54,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:54,265 INFO L462 AbstractCegarLoop]: Abstraction has 1382 states and 2266 transitions. [2019-11-19 21:23:54,265 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:54,266 INFO L276 IsEmpty]: Start isEmpty. Operand 1382 states and 2266 transitions. [2019-11-19 21:23:54,267 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-19 21:23:54,268 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:54,269 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:54,269 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:54,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:54,270 INFO L82 PathProgramCache]: Analyzing trace with hash 952985988, now seen corresponding path program 1 times [2019-11-19 21:23:54,270 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:54,271 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395562103] [2019-11-19 21:23:54,271 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:54,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:54,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:54,347 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395562103] [2019-11-19 21:23:54,347 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:54,347 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-19 21:23:54,348 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765546714] [2019-11-19 21:23:54,350 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-19 21:23:54,350 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:54,350 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-19 21:23:54,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-19 21:23:54,351 INFO L87 Difference]: Start difference. First operand 1382 states and 2266 transitions. Second operand 4 states. [2019-11-19 21:23:54,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:54,529 INFO L93 Difference]: Finished difference Result 2900 states and 4764 transitions. [2019-11-19 21:23:54,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-19 21:23:54,529 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-19 21:23:54,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:54,537 INFO L225 Difference]: With dead ends: 2900 [2019-11-19 21:23:54,538 INFO L226 Difference]: Without dead ends: 1552 [2019-11-19 21:23:54,540 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-19 21:23:54,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1552 states. [2019-11-19 21:23:54,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1552 to 1539. [2019-11-19 21:23:54,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1539 states. [2019-11-19 21:23:54,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1539 states to 1539 states and 2488 transitions. [2019-11-19 21:23:54,616 INFO L78 Accepts]: Start accepts. Automaton has 1539 states and 2488 transitions. Word has length 36 [2019-11-19 21:23:54,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:54,616 INFO L462 AbstractCegarLoop]: Abstraction has 1539 states and 2488 transitions. [2019-11-19 21:23:54,616 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-19 21:23:54,616 INFO L276 IsEmpty]: Start isEmpty. Operand 1539 states and 2488 transitions. [2019-11-19 21:23:54,617 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-19 21:23:54,617 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:54,618 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:54,618 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:54,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:54,618 INFO L82 PathProgramCache]: Analyzing trace with hash -635361914, now seen corresponding path program 1 times [2019-11-19 21:23:54,618 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:54,619 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016344754] [2019-11-19 21:23:54,619 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:54,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:54,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:54,645 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2016344754] [2019-11-19 21:23:54,646 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:54,646 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-19 21:23:54,646 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55013383] [2019-11-19 21:23:54,646 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-19 21:23:54,647 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:54,647 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-19 21:23:54,647 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-19 21:23:54,647 INFO L87 Difference]: Start difference. First operand 1539 states and 2488 transitions. Second operand 4 states. [2019-11-19 21:23:54,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:54,805 INFO L93 Difference]: Finished difference Result 3378 states and 5467 transitions. [2019-11-19 21:23:54,805 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-19 21:23:54,805 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-19 21:23:54,806 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:54,815 INFO L225 Difference]: With dead ends: 3378 [2019-11-19 21:23:54,815 INFO L226 Difference]: Without dead ends: 1885 [2019-11-19 21:23:54,818 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-19 21:23:54,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1885 states. [2019-11-19 21:23:54,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1885 to 1859. [2019-11-19 21:23:54,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1859 states. [2019-11-19 21:23:54,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1859 states to 1859 states and 2968 transitions. [2019-11-19 21:23:54,906 INFO L78 Accepts]: Start accepts. Automaton has 1859 states and 2968 transitions. Word has length 36 [2019-11-19 21:23:54,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:54,906 INFO L462 AbstractCegarLoop]: Abstraction has 1859 states and 2968 transitions. [2019-11-19 21:23:54,906 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-19 21:23:54,906 INFO L276 IsEmpty]: Start isEmpty. Operand 1859 states and 2968 transitions. [2019-11-19 21:23:54,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-19 21:23:54,907 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:54,907 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:54,908 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:54,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:54,908 INFO L82 PathProgramCache]: Analyzing trace with hash -1915225592, now seen corresponding path program 1 times [2019-11-19 21:23:54,908 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:54,908 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176849042] [2019-11-19 21:23:54,909 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:54,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:54,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:54,942 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [176849042] [2019-11-19 21:23:54,943 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:54,943 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:54,943 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083178151] [2019-11-19 21:23:54,943 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:54,944 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:54,944 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:54,944 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:54,944 INFO L87 Difference]: Start difference. First operand 1859 states and 2968 transitions. Second operand 3 states. [2019-11-19 21:23:55,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:55,046 INFO L93 Difference]: Finished difference Result 3335 states and 5328 transitions. [2019-11-19 21:23:55,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:55,047 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-19 21:23:55,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:55,054 INFO L225 Difference]: With dead ends: 3335 [2019-11-19 21:23:55,055 INFO L226 Difference]: Without dead ends: 1504 [2019-11-19 21:23:55,058 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:55,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1504 states. [2019-11-19 21:23:55,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1504 to 1493. [2019-11-19 21:23:55,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1493 states. [2019-11-19 21:23:55,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1493 states to 1493 states and 2352 transitions. [2019-11-19 21:23:55,126 INFO L78 Accepts]: Start accepts. Automaton has 1493 states and 2352 transitions. Word has length 36 [2019-11-19 21:23:55,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:55,127 INFO L462 AbstractCegarLoop]: Abstraction has 1493 states and 2352 transitions. [2019-11-19 21:23:55,127 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:55,127 INFO L276 IsEmpty]: Start isEmpty. Operand 1493 states and 2352 transitions. [2019-11-19 21:23:55,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-19 21:23:55,129 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:55,129 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:55,129 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:55,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:55,130 INFO L82 PathProgramCache]: Analyzing trace with hash -547155332, now seen corresponding path program 1 times [2019-11-19 21:23:55,130 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:55,130 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595616594] [2019-11-19 21:23:55,130 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:55,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:55,156 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:55,156 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1595616594] [2019-11-19 21:23:55,156 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:55,156 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:55,157 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336767141] [2019-11-19 21:23:55,157 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:55,157 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:55,157 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:55,158 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:55,158 INFO L87 Difference]: Start difference. First operand 1493 states and 2352 transitions. Second operand 3 states. [2019-11-19 21:23:55,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:55,275 INFO L93 Difference]: Finished difference Result 3728 states and 5928 transitions. [2019-11-19 21:23:55,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:55,275 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-19 21:23:55,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:55,290 INFO L225 Difference]: With dead ends: 3728 [2019-11-19 21:23:55,290 INFO L226 Difference]: Without dead ends: 2289 [2019-11-19 21:23:55,294 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:55,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2289 states. [2019-11-19 21:23:55,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2289 to 2285. [2019-11-19 21:23:55,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2285 states. [2019-11-19 21:23:55,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2285 states to 2285 states and 3596 transitions. [2019-11-19 21:23:55,422 INFO L78 Accepts]: Start accepts. Automaton has 2285 states and 3596 transitions. Word has length 46 [2019-11-19 21:23:55,422 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:55,422 INFO L462 AbstractCegarLoop]: Abstraction has 2285 states and 3596 transitions. [2019-11-19 21:23:55,422 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:55,422 INFO L276 IsEmpty]: Start isEmpty. Operand 2285 states and 3596 transitions. [2019-11-19 21:23:55,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-19 21:23:55,425 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:55,425 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:55,425 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:55,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:55,426 INFO L82 PathProgramCache]: Analyzing trace with hash -299008838, now seen corresponding path program 1 times [2019-11-19 21:23:55,426 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:55,426 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923283442] [2019-11-19 21:23:55,427 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:55,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:55,445 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-19 21:23:55,446 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923283442] [2019-11-19 21:23:55,446 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:55,446 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:55,447 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1173450414] [2019-11-19 21:23:55,447 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:55,447 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:55,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:55,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:55,448 INFO L87 Difference]: Start difference. First operand 2285 states and 3596 transitions. Second operand 3 states. [2019-11-19 21:23:55,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:55,545 INFO L93 Difference]: Finished difference Result 4472 states and 7066 transitions. [2019-11-19 21:23:55,545 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:55,545 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-19 21:23:55,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:55,557 INFO L225 Difference]: With dead ends: 4472 [2019-11-19 21:23:55,557 INFO L226 Difference]: Without dead ends: 2241 [2019-11-19 21:23:55,561 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:55,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2241 states. [2019-11-19 21:23:55,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2241 to 2241. [2019-11-19 21:23:55,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2241 states. [2019-11-19 21:23:55,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3539 transitions. [2019-11-19 21:23:55,677 INFO L78 Accepts]: Start accepts. Automaton has 2241 states and 3539 transitions. Word has length 46 [2019-11-19 21:23:55,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:55,678 INFO L462 AbstractCegarLoop]: Abstraction has 2241 states and 3539 transitions. [2019-11-19 21:23:55,678 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:55,678 INFO L276 IsEmpty]: Start isEmpty. Operand 2241 states and 3539 transitions. [2019-11-19 21:23:55,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-11-19 21:23:55,681 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:55,681 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:55,681 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:55,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:55,682 INFO L82 PathProgramCache]: Analyzing trace with hash -336670593, now seen corresponding path program 1 times [2019-11-19 21:23:55,682 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:55,682 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229834896] [2019-11-19 21:23:55,682 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:55,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:55,739 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:55,739 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [229834896] [2019-11-19 21:23:55,740 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:55,740 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:55,740 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777101920] [2019-11-19 21:23:55,741 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:55,741 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:55,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:55,742 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:55,743 INFO L87 Difference]: Start difference. First operand 2241 states and 3539 transitions. Second operand 3 states. [2019-11-19 21:23:56,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:56,003 INFO L93 Difference]: Finished difference Result 5761 states and 9163 transitions. [2019-11-19 21:23:56,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:56,003 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-11-19 21:23:56,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:56,022 INFO L225 Difference]: With dead ends: 5761 [2019-11-19 21:23:56,022 INFO L226 Difference]: Without dead ends: 3574 [2019-11-19 21:23:56,027 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:56,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3574 states. [2019-11-19 21:23:56,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3574 to 3570. [2019-11-19 21:23:56,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3570 states. [2019-11-19 21:23:56,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3570 states to 3570 states and 5623 transitions. [2019-11-19 21:23:56,202 INFO L78 Accepts]: Start accepts. Automaton has 3570 states and 5623 transitions. Word has length 47 [2019-11-19 21:23:56,203 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:56,203 INFO L462 AbstractCegarLoop]: Abstraction has 3570 states and 5623 transitions. [2019-11-19 21:23:56,203 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:56,203 INFO L276 IsEmpty]: Start isEmpty. Operand 3570 states and 5623 transitions. [2019-11-19 21:23:56,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-19 21:23:56,206 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:56,206 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:56,206 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:56,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:56,206 INFO L82 PathProgramCache]: Analyzing trace with hash 1825522215, now seen corresponding path program 1 times [2019-11-19 21:23:56,207 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:56,207 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706973707] [2019-11-19 21:23:56,207 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:56,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:56,235 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:56,236 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706973707] [2019-11-19 21:23:56,236 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:56,236 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:56,236 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [170738338] [2019-11-19 21:23:56,237 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:56,237 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:56,237 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:56,237 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:56,238 INFO L87 Difference]: Start difference. First operand 3570 states and 5623 transitions. Second operand 3 states. [2019-11-19 21:23:56,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:56,536 INFO L93 Difference]: Finished difference Result 9081 states and 14487 transitions. [2019-11-19 21:23:56,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:56,536 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-19 21:23:56,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:56,574 INFO L225 Difference]: With dead ends: 9081 [2019-11-19 21:23:56,574 INFO L226 Difference]: Without dead ends: 5569 [2019-11-19 21:23:56,582 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:56,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5569 states. [2019-11-19 21:23:56,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5569 to 5565. [2019-11-19 21:23:56,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5565 states. [2019-11-19 21:23:56,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5565 states to 5565 states and 8840 transitions. [2019-11-19 21:23:56,946 INFO L78 Accepts]: Start accepts. Automaton has 5565 states and 8840 transitions. Word has length 48 [2019-11-19 21:23:56,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:56,946 INFO L462 AbstractCegarLoop]: Abstraction has 5565 states and 8840 transitions. [2019-11-19 21:23:56,946 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:56,947 INFO L276 IsEmpty]: Start isEmpty. Operand 5565 states and 8840 transitions. [2019-11-19 21:23:56,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-19 21:23:56,951 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:56,951 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:56,951 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:56,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:56,952 INFO L82 PathProgramCache]: Analyzing trace with hash 2073668709, now seen corresponding path program 1 times [2019-11-19 21:23:56,952 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:56,952 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509686540] [2019-11-19 21:23:56,952 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:56,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:56,970 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-19 21:23:56,970 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1509686540] [2019-11-19 21:23:56,970 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:56,971 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:56,971 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [75699924] [2019-11-19 21:23:56,971 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:56,971 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:56,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:56,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:56,972 INFO L87 Difference]: Start difference. First operand 5565 states and 8840 transitions. Second operand 3 states. [2019-11-19 21:23:57,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:57,264 INFO L93 Difference]: Finished difference Result 11028 states and 17554 transitions. [2019-11-19 21:23:57,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:57,264 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-19 21:23:57,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:57,289 INFO L225 Difference]: With dead ends: 11028 [2019-11-19 21:23:57,290 INFO L226 Difference]: Without dead ends: 5521 [2019-11-19 21:23:57,299 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:57,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5521 states. [2019-11-19 21:23:57,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5521 to 5521. [2019-11-19 21:23:57,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5521 states. [2019-11-19 21:23:57,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5521 states to 5521 states and 8785 transitions. [2019-11-19 21:23:57,642 INFO L78 Accepts]: Start accepts. Automaton has 5521 states and 8785 transitions. Word has length 48 [2019-11-19 21:23:57,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:57,642 INFO L462 AbstractCegarLoop]: Abstraction has 5521 states and 8785 transitions. [2019-11-19 21:23:57,642 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:57,642 INFO L276 IsEmpty]: Start isEmpty. Operand 5521 states and 8785 transitions. [2019-11-19 21:23:57,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-19 21:23:57,646 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:57,646 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:57,646 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:57,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:57,647 INFO L82 PathProgramCache]: Analyzing trace with hash 963117268, now seen corresponding path program 1 times [2019-11-19 21:23:57,647 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:57,647 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214241537] [2019-11-19 21:23:57,647 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:57,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:57,673 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:57,674 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [214241537] [2019-11-19 21:23:57,674 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:57,674 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:57,674 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418666270] [2019-11-19 21:23:57,675 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:57,675 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:57,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:57,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:57,675 INFO L87 Difference]: Start difference. First operand 5521 states and 8785 transitions. Second operand 3 states. [2019-11-19 21:23:58,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:58,045 INFO L93 Difference]: Finished difference Result 15573 states and 24710 transitions. [2019-11-19 21:23:58,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:58,046 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-19 21:23:58,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:58,069 INFO L225 Difference]: With dead ends: 15573 [2019-11-19 21:23:58,069 INFO L226 Difference]: Without dead ends: 8340 [2019-11-19 21:23:58,081 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:58,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8340 states. [2019-11-19 21:23:58,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8340 to 8340. [2019-11-19 21:23:58,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8340 states. [2019-11-19 21:23:58,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8340 states to 8340 states and 13079 transitions. [2019-11-19 21:23:58,583 INFO L78 Accepts]: Start accepts. Automaton has 8340 states and 13079 transitions. Word has length 49 [2019-11-19 21:23:58,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:58,583 INFO L462 AbstractCegarLoop]: Abstraction has 8340 states and 13079 transitions. [2019-11-19 21:23:58,583 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:58,584 INFO L276 IsEmpty]: Start isEmpty. Operand 8340 states and 13079 transitions. [2019-11-19 21:23:58,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-19 21:23:58,589 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:58,589 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:58,589 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:58,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:58,590 INFO L82 PathProgramCache]: Analyzing trace with hash 1798060104, now seen corresponding path program 1 times [2019-11-19 21:23:58,590 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:58,590 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263284064] [2019-11-19 21:23:58,591 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:58,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:58,621 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:23:58,621 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1263284064] [2019-11-19 21:23:58,621 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:58,622 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:58,622 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605221686] [2019-11-19 21:23:58,622 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:58,622 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:58,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:58,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:58,623 INFO L87 Difference]: Start difference. First operand 8340 states and 13079 transitions. Second operand 3 states. [2019-11-19 21:23:58,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:23:58,952 INFO L93 Difference]: Finished difference Result 17187 states and 26897 transitions. [2019-11-19 21:23:58,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:23:58,952 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2019-11-19 21:23:58,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:23:58,976 INFO L225 Difference]: With dead ends: 17187 [2019-11-19 21:23:58,976 INFO L226 Difference]: Without dead ends: 8883 [2019-11-19 21:23:58,989 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:59,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8883 states. [2019-11-19 21:23:59,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8883 to 8322. [2019-11-19 21:23:59,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8322 states. [2019-11-19 21:23:59,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8322 states to 8322 states and 12796 transitions. [2019-11-19 21:23:59,378 INFO L78 Accepts]: Start accepts. Automaton has 8322 states and 12796 transitions. Word has length 53 [2019-11-19 21:23:59,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:23:59,379 INFO L462 AbstractCegarLoop]: Abstraction has 8322 states and 12796 transitions. [2019-11-19 21:23:59,379 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:23:59,379 INFO L276 IsEmpty]: Start isEmpty. Operand 8322 states and 12796 transitions. [2019-11-19 21:23:59,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-19 21:23:59,386 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:23:59,386 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:23:59,387 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:23:59,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:23:59,387 INFO L82 PathProgramCache]: Analyzing trace with hash -833394239, now seen corresponding path program 1 times [2019-11-19 21:23:59,387 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:23:59,387 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863618989] [2019-11-19 21:23:59,387 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:23:59,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:23:59,421 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-19 21:23:59,421 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863618989] [2019-11-19 21:23:59,421 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:23:59,422 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:23:59,422 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355419625] [2019-11-19 21:23:59,422 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:23:59,422 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:23:59,423 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:23:59,423 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:23:59,423 INFO L87 Difference]: Start difference. First operand 8322 states and 12796 transitions. Second operand 3 states. [2019-11-19 21:24:00,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:00,172 INFO L93 Difference]: Finished difference Result 24654 states and 37995 transitions. [2019-11-19 21:24:00,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:00,173 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-19 21:24:00,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:00,208 INFO L225 Difference]: With dead ends: 24654 [2019-11-19 21:24:00,209 INFO L226 Difference]: Without dead ends: 16335 [2019-11-19 21:24:00,222 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:00,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16335 states. [2019-11-19 21:24:00,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16335 to 16203. [2019-11-19 21:24:00,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16203 states. [2019-11-19 21:24:00,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16203 states to 16203 states and 25040 transitions. [2019-11-19 21:24:00,986 INFO L78 Accepts]: Start accepts. Automaton has 16203 states and 25040 transitions. Word has length 55 [2019-11-19 21:24:00,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:00,987 INFO L462 AbstractCegarLoop]: Abstraction has 16203 states and 25040 transitions. [2019-11-19 21:24:00,987 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:00,987 INFO L276 IsEmpty]: Start isEmpty. Operand 16203 states and 25040 transitions. [2019-11-19 21:24:01,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-19 21:24:01,001 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:01,001 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:01,001 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:01,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:01,002 INFO L82 PathProgramCache]: Analyzing trace with hash -539805076, now seen corresponding path program 1 times [2019-11-19 21:24:01,003 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:01,004 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862765257] [2019-11-19 21:24:01,004 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:01,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:01,068 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:24:01,069 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862765257] [2019-11-19 21:24:01,069 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:01,070 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:01,070 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [584800744] [2019-11-19 21:24:01,072 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:01,072 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:01,073 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:01,073 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:01,073 INFO L87 Difference]: Start difference. First operand 16203 states and 25040 transitions. Second operand 3 states. [2019-11-19 21:24:01,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:01,859 INFO L93 Difference]: Finished difference Result 33061 states and 51038 transitions. [2019-11-19 21:24:01,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:01,859 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-11-19 21:24:01,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:01,908 INFO L225 Difference]: With dead ends: 33061 [2019-11-19 21:24:01,909 INFO L226 Difference]: Without dead ends: 16887 [2019-11-19 21:24:01,943 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:01,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16887 states. [2019-11-19 21:24:02,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16887 to 16823. [2019-11-19 21:24:02,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16823 states. [2019-11-19 21:24:02,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16823 states to 16823 states and 25342 transitions. [2019-11-19 21:24:02,568 INFO L78 Accepts]: Start accepts. Automaton has 16823 states and 25342 transitions. Word has length 86 [2019-11-19 21:24:02,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:02,569 INFO L462 AbstractCegarLoop]: Abstraction has 16823 states and 25342 transitions. [2019-11-19 21:24:02,569 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:02,569 INFO L276 IsEmpty]: Start isEmpty. Operand 16823 states and 25342 transitions. [2019-11-19 21:24:02,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-11-19 21:24:02,580 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:02,580 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:02,581 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:02,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:02,581 INFO L82 PathProgramCache]: Analyzing trace with hash -1404681213, now seen corresponding path program 1 times [2019-11-19 21:24:02,582 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:02,582 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035385678] [2019-11-19 21:24:02,582 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:02,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:02,624 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-19 21:24:02,625 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1035385678] [2019-11-19 21:24:02,625 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:02,626 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-19 21:24:02,626 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400300581] [2019-11-19 21:24:02,626 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-19 21:24:02,627 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:02,627 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-19 21:24:02,627 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-19 21:24:02,627 INFO L87 Difference]: Start difference. First operand 16823 states and 25342 transitions. Second operand 4 states. [2019-11-19 21:24:03,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:03,482 INFO L93 Difference]: Finished difference Result 27813 states and 42042 transitions. [2019-11-19 21:24:03,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-19 21:24:03,482 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 87 [2019-11-19 21:24:03,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:03,516 INFO L225 Difference]: With dead ends: 27813 [2019-11-19 21:24:03,516 INFO L226 Difference]: Without dead ends: 15935 [2019-11-19 21:24:03,527 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-19 21:24:03,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15935 states. [2019-11-19 21:24:04,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15935 to 15811. [2019-11-19 21:24:04,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15811 states. [2019-11-19 21:24:04,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15811 states to 15811 states and 23636 transitions. [2019-11-19 21:24:04,198 INFO L78 Accepts]: Start accepts. Automaton has 15811 states and 23636 transitions. Word has length 87 [2019-11-19 21:24:04,198 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:04,198 INFO L462 AbstractCegarLoop]: Abstraction has 15811 states and 23636 transitions. [2019-11-19 21:24:04,198 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-19 21:24:04,198 INFO L276 IsEmpty]: Start isEmpty. Operand 15811 states and 23636 transitions. [2019-11-19 21:24:04,207 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-11-19 21:24:04,207 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:04,207 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:04,207 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:04,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:04,208 INFO L82 PathProgramCache]: Analyzing trace with hash 1520792899, now seen corresponding path program 1 times [2019-11-19 21:24:04,208 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:04,208 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804619129] [2019-11-19 21:24:04,208 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:04,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:04,241 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:24:04,241 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804619129] [2019-11-19 21:24:04,242 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:04,242 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:04,242 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121046950] [2019-11-19 21:24:04,243 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:04,243 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:04,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:04,244 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:04,244 INFO L87 Difference]: Start difference. First operand 15811 states and 23636 transitions. Second operand 3 states. [2019-11-19 21:24:05,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:05,002 INFO L93 Difference]: Finished difference Result 32391 states and 48370 transitions. [2019-11-19 21:24:05,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:05,002 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 87 [2019-11-19 21:24:05,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:05,038 INFO L225 Difference]: With dead ends: 32391 [2019-11-19 21:24:05,038 INFO L226 Difference]: Without dead ends: 16621 [2019-11-19 21:24:05,048 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:05,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16621 states. [2019-11-19 21:24:05,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16621 to 16541. [2019-11-19 21:24:05,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16541 states. [2019-11-19 21:24:05,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16541 states to 16541 states and 24008 transitions. [2019-11-19 21:24:05,878 INFO L78 Accepts]: Start accepts. Automaton has 16541 states and 24008 transitions. Word has length 87 [2019-11-19 21:24:05,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:05,878 INFO L462 AbstractCegarLoop]: Abstraction has 16541 states and 24008 transitions. [2019-11-19 21:24:05,878 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:05,879 INFO L276 IsEmpty]: Start isEmpty. Operand 16541 states and 24008 transitions. [2019-11-19 21:24:05,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2019-11-19 21:24:05,887 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:05,888 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:05,888 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:05,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:05,888 INFO L82 PathProgramCache]: Analyzing trace with hash -1973365524, now seen corresponding path program 1 times [2019-11-19 21:24:05,889 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:05,889 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523781074] [2019-11-19 21:24:05,889 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:05,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:05,952 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-19 21:24:05,952 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1523781074] [2019-11-19 21:24:05,953 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:05,953 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:05,953 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048711459] [2019-11-19 21:24:05,954 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:05,954 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:05,955 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:05,955 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:05,955 INFO L87 Difference]: Start difference. First operand 16541 states and 24008 transitions. Second operand 3 states. [2019-11-19 21:24:06,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:06,682 INFO L93 Difference]: Finished difference Result 33498 states and 48738 transitions. [2019-11-19 21:24:06,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:06,682 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 88 [2019-11-19 21:24:06,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:06,711 INFO L225 Difference]: With dead ends: 33498 [2019-11-19 21:24:06,711 INFO L226 Difference]: Without dead ends: 17018 [2019-11-19 21:24:06,730 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:06,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17018 states. [2019-11-19 21:24:07,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17018 to 13513. [2019-11-19 21:24:07,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13513 states. [2019-11-19 21:24:07,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13513 states to 13513 states and 18922 transitions. [2019-11-19 21:24:07,604 INFO L78 Accepts]: Start accepts. Automaton has 13513 states and 18922 transitions. Word has length 88 [2019-11-19 21:24:07,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:07,605 INFO L462 AbstractCegarLoop]: Abstraction has 13513 states and 18922 transitions. [2019-11-19 21:24:07,605 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:07,605 INFO L276 IsEmpty]: Start isEmpty. Operand 13513 states and 18922 transitions. [2019-11-19 21:24:07,615 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2019-11-19 21:24:07,615 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:07,616 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:07,616 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:07,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:07,616 INFO L82 PathProgramCache]: Analyzing trace with hash 663253701, now seen corresponding path program 1 times [2019-11-19 21:24:07,617 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:07,617 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140637143] [2019-11-19 21:24:07,617 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:07,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:07,648 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-19 21:24:07,649 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140637143] [2019-11-19 21:24:07,649 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:07,649 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:07,649 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015894788] [2019-11-19 21:24:07,650 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:07,650 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:07,650 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:07,651 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:07,651 INFO L87 Difference]: Start difference. First operand 13513 states and 18922 transitions. Second operand 3 states. [2019-11-19 21:24:08,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:08,068 INFO L93 Difference]: Finished difference Result 24045 states and 33699 transitions. [2019-11-19 21:24:08,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:08,069 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 89 [2019-11-19 21:24:08,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:08,090 INFO L225 Difference]: With dead ends: 24045 [2019-11-19 21:24:08,091 INFO L226 Difference]: Without dead ends: 15655 [2019-11-19 21:24:08,102 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:08,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15655 states. [2019-11-19 21:24:08,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15655 to 15175. [2019-11-19 21:24:08,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15175 states. [2019-11-19 21:24:08,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15175 states to 15175 states and 20753 transitions. [2019-11-19 21:24:08,579 INFO L78 Accepts]: Start accepts. Automaton has 15175 states and 20753 transitions. Word has length 89 [2019-11-19 21:24:08,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:08,579 INFO L462 AbstractCegarLoop]: Abstraction has 15175 states and 20753 transitions. [2019-11-19 21:24:08,579 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:08,580 INFO L276 IsEmpty]: Start isEmpty. Operand 15175 states and 20753 transitions. [2019-11-19 21:24:08,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2019-11-19 21:24:08,593 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:08,593 INFO L410 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:08,594 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:08,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:08,595 INFO L82 PathProgramCache]: Analyzing trace with hash 1690650567, now seen corresponding path program 1 times [2019-11-19 21:24:08,595 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:08,595 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806408291] [2019-11-19 21:24:08,595 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:08,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:08,628 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-19 21:24:08,628 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806408291] [2019-11-19 21:24:08,628 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:08,629 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:08,629 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051120313] [2019-11-19 21:24:08,629 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:08,629 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:08,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:08,630 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:08,630 INFO L87 Difference]: Start difference. First operand 15175 states and 20753 transitions. Second operand 3 states. [2019-11-19 21:24:09,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:09,200 INFO L93 Difference]: Finished difference Result 29588 states and 40424 transitions. [2019-11-19 21:24:09,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:09,201 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 116 [2019-11-19 21:24:09,201 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:09,214 INFO L225 Difference]: With dead ends: 29588 [2019-11-19 21:24:09,214 INFO L226 Difference]: Without dead ends: 15105 [2019-11-19 21:24:09,224 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:09,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15105 states. [2019-11-19 21:24:09,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15105 to 15105. [2019-11-19 21:24:09,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15105 states. [2019-11-19 21:24:09,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15105 states to 15105 states and 20599 transitions. [2019-11-19 21:24:09,650 INFO L78 Accepts]: Start accepts. Automaton has 15105 states and 20599 transitions. Word has length 116 [2019-11-19 21:24:09,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:09,650 INFO L462 AbstractCegarLoop]: Abstraction has 15105 states and 20599 transitions. [2019-11-19 21:24:09,650 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:09,650 INFO L276 IsEmpty]: Start isEmpty. Operand 15105 states and 20599 transitions. [2019-11-19 21:24:09,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-11-19 21:24:09,664 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:09,664 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:09,664 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:09,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:09,665 INFO L82 PathProgramCache]: Analyzing trace with hash -1184080698, now seen corresponding path program 1 times [2019-11-19 21:24:09,665 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:09,665 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221851046] [2019-11-19 21:24:09,665 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:09,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:09,703 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2019-11-19 21:24:09,703 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221851046] [2019-11-19 21:24:09,703 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:09,703 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:09,704 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1457563231] [2019-11-19 21:24:09,704 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:09,704 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:09,704 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:09,704 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:09,705 INFO L87 Difference]: Start difference. First operand 15105 states and 20599 transitions. Second operand 3 states. [2019-11-19 21:24:10,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:10,047 INFO L93 Difference]: Finished difference Result 25662 states and 34928 transitions. [2019-11-19 21:24:10,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:10,048 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 127 [2019-11-19 21:24:10,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:10,057 INFO L225 Difference]: With dead ends: 25662 [2019-11-19 21:24:10,058 INFO L226 Difference]: Without dead ends: 10614 [2019-11-19 21:24:10,067 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:10,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10614 states. [2019-11-19 21:24:10,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10614 to 8646. [2019-11-19 21:24:10,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8646 states. [2019-11-19 21:24:10,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8646 states to 8646 states and 11323 transitions. [2019-11-19 21:24:10,324 INFO L78 Accepts]: Start accepts. Automaton has 8646 states and 11323 transitions. Word has length 127 [2019-11-19 21:24:10,324 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:10,324 INFO L462 AbstractCegarLoop]: Abstraction has 8646 states and 11323 transitions. [2019-11-19 21:24:10,324 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:10,324 INFO L276 IsEmpty]: Start isEmpty. Operand 8646 states and 11323 transitions. [2019-11-19 21:24:10,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2019-11-19 21:24:10,333 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:10,333 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:10,333 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:10,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:10,334 INFO L82 PathProgramCache]: Analyzing trace with hash 762576065, now seen corresponding path program 1 times [2019-11-19 21:24:10,334 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:10,334 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [19757348] [2019-11-19 21:24:10,334 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:10,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:10,384 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 43 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-19 21:24:10,384 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [19757348] [2019-11-19 21:24:10,384 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:10,385 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:10,385 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1766929631] [2019-11-19 21:24:10,386 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:10,386 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:10,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:10,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:10,387 INFO L87 Difference]: Start difference. First operand 8646 states and 11323 transitions. Second operand 3 states. [2019-11-19 21:24:10,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:10,603 INFO L93 Difference]: Finished difference Result 14253 states and 18666 transitions. [2019-11-19 21:24:10,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:10,604 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 128 [2019-11-19 21:24:10,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:10,610 INFO L225 Difference]: With dead ends: 14253 [2019-11-19 21:24:10,611 INFO L226 Difference]: Without dead ends: 6761 [2019-11-19 21:24:10,618 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:10,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6761 states. [2019-11-19 21:24:10,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6761 to 6175. [2019-11-19 21:24:10,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6175 states. [2019-11-19 21:24:10,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6175 states to 6175 states and 7922 transitions. [2019-11-19 21:24:10,861 INFO L78 Accepts]: Start accepts. Automaton has 6175 states and 7922 transitions. Word has length 128 [2019-11-19 21:24:10,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:10,861 INFO L462 AbstractCegarLoop]: Abstraction has 6175 states and 7922 transitions. [2019-11-19 21:24:10,861 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:10,861 INFO L276 IsEmpty]: Start isEmpty. Operand 6175 states and 7922 transitions. [2019-11-19 21:24:10,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-19 21:24:10,867 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:10,867 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:10,867 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:10,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:10,867 INFO L82 PathProgramCache]: Analyzing trace with hash 843157933, now seen corresponding path program 1 times [2019-11-19 21:24:10,868 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:10,868 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242598808] [2019-11-19 21:24:10,868 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:10,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:10,916 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-19 21:24:10,916 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242598808] [2019-11-19 21:24:10,917 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:10,917 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:10,917 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188981121] [2019-11-19 21:24:10,918 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:10,918 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:10,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:10,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:10,918 INFO L87 Difference]: Start difference. First operand 6175 states and 7922 transitions. Second operand 3 states. [2019-11-19 21:24:11,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:11,183 INFO L93 Difference]: Finished difference Result 11963 states and 15332 transitions. [2019-11-19 21:24:11,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:11,184 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2019-11-19 21:24:11,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:11,189 INFO L225 Difference]: With dead ends: 11963 [2019-11-19 21:24:11,189 INFO L226 Difference]: Without dead ends: 6174 [2019-11-19 21:24:11,194 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:11,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6174 states. [2019-11-19 21:24:11,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6174 to 6134. [2019-11-19 21:24:11,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6134 states. [2019-11-19 21:24:11,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6134 states to 6134 states and 7839 transitions. [2019-11-19 21:24:11,420 INFO L78 Accepts]: Start accepts. Automaton has 6134 states and 7839 transitions. Word has length 134 [2019-11-19 21:24:11,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:11,420 INFO L462 AbstractCegarLoop]: Abstraction has 6134 states and 7839 transitions. [2019-11-19 21:24:11,420 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:11,420 INFO L276 IsEmpty]: Start isEmpty. Operand 6134 states and 7839 transitions. [2019-11-19 21:24:11,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-19 21:24:11,424 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:11,424 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:11,424 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:11,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:11,424 INFO L82 PathProgramCache]: Analyzing trace with hash 713131341, now seen corresponding path program 1 times [2019-11-19 21:24:11,425 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:11,425 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561395797] [2019-11-19 21:24:11,425 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:11,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:11,460 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-19 21:24:11,461 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1561395797] [2019-11-19 21:24:11,461 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:11,461 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:11,461 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090371892] [2019-11-19 21:24:11,461 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:11,462 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:11,462 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:11,462 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:11,462 INFO L87 Difference]: Start difference. First operand 6134 states and 7839 transitions. Second operand 3 states. [2019-11-19 21:24:11,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:11,835 INFO L93 Difference]: Finished difference Result 11902 states and 15193 transitions. [2019-11-19 21:24:11,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:11,835 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2019-11-19 21:24:11,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:11,844 INFO L225 Difference]: With dead ends: 11902 [2019-11-19 21:24:11,844 INFO L226 Difference]: Without dead ends: 6144 [2019-11-19 21:24:11,850 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:11,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6144 states. [2019-11-19 21:24:12,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6144 to 6104. [2019-11-19 21:24:12,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6104 states. [2019-11-19 21:24:12,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6104 states to 6104 states and 7768 transitions. [2019-11-19 21:24:12,146 INFO L78 Accepts]: Start accepts. Automaton has 6104 states and 7768 transitions. Word has length 134 [2019-11-19 21:24:12,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:12,146 INFO L462 AbstractCegarLoop]: Abstraction has 6104 states and 7768 transitions. [2019-11-19 21:24:12,146 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:12,146 INFO L276 IsEmpty]: Start isEmpty. Operand 6104 states and 7768 transitions. [2019-11-19 21:24:12,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-19 21:24:12,151 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:12,151 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:12,152 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:12,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:12,152 INFO L82 PathProgramCache]: Analyzing trace with hash -57826629, now seen corresponding path program 1 times [2019-11-19 21:24:12,152 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:12,152 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183411948] [2019-11-19 21:24:12,152 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:12,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:12,195 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-19 21:24:12,196 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183411948] [2019-11-19 21:24:12,196 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:12,196 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:12,196 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686030817] [2019-11-19 21:24:12,196 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:12,197 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:12,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:12,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:12,197 INFO L87 Difference]: Start difference. First operand 6104 states and 7768 transitions. Second operand 3 states. [2019-11-19 21:24:12,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:12,457 INFO L93 Difference]: Finished difference Result 10914 states and 13936 transitions. [2019-11-19 21:24:12,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:12,458 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 137 [2019-11-19 21:24:12,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:12,464 INFO L225 Difference]: With dead ends: 10914 [2019-11-19 21:24:12,464 INFO L226 Difference]: Without dead ends: 5174 [2019-11-19 21:24:12,471 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:12,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5174 states. [2019-11-19 21:24:12,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5174 to 5102. [2019-11-19 21:24:12,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5102 states. [2019-11-19 21:24:12,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5102 states to 5102 states and 6390 transitions. [2019-11-19 21:24:12,701 INFO L78 Accepts]: Start accepts. Automaton has 5102 states and 6390 transitions. Word has length 137 [2019-11-19 21:24:12,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:12,701 INFO L462 AbstractCegarLoop]: Abstraction has 5102 states and 6390 transitions. [2019-11-19 21:24:12,701 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:12,702 INFO L276 IsEmpty]: Start isEmpty. Operand 5102 states and 6390 transitions. [2019-11-19 21:24:12,704 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-19 21:24:12,705 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:12,705 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:12,705 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:12,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:12,705 INFO L82 PathProgramCache]: Analyzing trace with hash -76782736, now seen corresponding path program 1 times [2019-11-19 21:24:12,706 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:12,706 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186540890] [2019-11-19 21:24:12,706 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:12,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:12,757 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2019-11-19 21:24:12,758 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [186540890] [2019-11-19 21:24:12,759 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:12,759 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:12,761 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1195291863] [2019-11-19 21:24:12,762 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:12,762 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:12,762 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:12,763 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:12,763 INFO L87 Difference]: Start difference. First operand 5102 states and 6390 transitions. Second operand 3 states. [2019-11-19 21:24:12,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:12,997 INFO L93 Difference]: Finished difference Result 9187 states and 11545 transitions. [2019-11-19 21:24:12,998 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:12,998 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 137 [2019-11-19 21:24:12,998 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:13,004 INFO L225 Difference]: With dead ends: 9187 [2019-11-19 21:24:13,004 INFO L226 Difference]: Without dead ends: 4126 [2019-11-19 21:24:13,011 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:13,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4126 states. [2019-11-19 21:24:13,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4126 to 4106. [2019-11-19 21:24:13,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4106 states. [2019-11-19 21:24:13,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4106 states to 4106 states and 5057 transitions. [2019-11-19 21:24:13,232 INFO L78 Accepts]: Start accepts. Automaton has 4106 states and 5057 transitions. Word has length 137 [2019-11-19 21:24:13,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:13,232 INFO L462 AbstractCegarLoop]: Abstraction has 4106 states and 5057 transitions. [2019-11-19 21:24:13,232 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:13,232 INFO L276 IsEmpty]: Start isEmpty. Operand 4106 states and 5057 transitions. [2019-11-19 21:24:13,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2019-11-19 21:24:13,236 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:13,236 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:13,237 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:13,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:13,237 INFO L82 PathProgramCache]: Analyzing trace with hash -691267920, now seen corresponding path program 1 times [2019-11-19 21:24:13,237 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:13,237 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766567927] [2019-11-19 21:24:13,238 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:13,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:13,295 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 75 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-11-19 21:24:13,296 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [766567927] [2019-11-19 21:24:13,296 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:13,296 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:13,296 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1302214714] [2019-11-19 21:24:13,296 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:13,297 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:13,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:13,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:13,297 INFO L87 Difference]: Start difference. First operand 4106 states and 5057 transitions. Second operand 3 states. [2019-11-19 21:24:13,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:13,485 INFO L93 Difference]: Finished difference Result 7627 states and 9455 transitions. [2019-11-19 21:24:13,486 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:13,486 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 170 [2019-11-19 21:24:13,486 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:13,491 INFO L225 Difference]: With dead ends: 7627 [2019-11-19 21:24:13,491 INFO L226 Difference]: Without dead ends: 3797 [2019-11-19 21:24:13,494 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:13,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3797 states. [2019-11-19 21:24:13,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3797 to 3568. [2019-11-19 21:24:13,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3568 states. [2019-11-19 21:24:13,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3568 states to 3568 states and 4348 transitions. [2019-11-19 21:24:13,627 INFO L78 Accepts]: Start accepts. Automaton has 3568 states and 4348 transitions. Word has length 170 [2019-11-19 21:24:13,627 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:13,627 INFO L462 AbstractCegarLoop]: Abstraction has 3568 states and 4348 transitions. [2019-11-19 21:24:13,627 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:13,627 INFO L276 IsEmpty]: Start isEmpty. Operand 3568 states and 4348 transitions. [2019-11-19 21:24:13,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 178 [2019-11-19 21:24:13,629 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:13,630 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:13,631 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:13,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:13,631 INFO L82 PathProgramCache]: Analyzing trace with hash 307077909, now seen corresponding path program 1 times [2019-11-19 21:24:13,631 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:13,631 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401178439] [2019-11-19 21:24:13,631 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:13,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:13,672 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-19 21:24:13,673 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1401178439] [2019-11-19 21:24:13,673 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:13,673 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:13,673 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869402431] [2019-11-19 21:24:13,674 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:13,674 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:13,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:13,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:13,675 INFO L87 Difference]: Start difference. First operand 3568 states and 4348 transitions. Second operand 3 states. [2019-11-19 21:24:13,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:13,998 INFO L93 Difference]: Finished difference Result 8940 states and 10936 transitions. [2019-11-19 21:24:13,998 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:13,998 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 177 [2019-11-19 21:24:13,999 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:14,006 INFO L225 Difference]: With dead ends: 8940 [2019-11-19 21:24:14,006 INFO L226 Difference]: Without dead ends: 5648 [2019-11-19 21:24:14,012 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:14,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5648 states. [2019-11-19 21:24:14,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5648 to 5422. [2019-11-19 21:24:14,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5422 states. [2019-11-19 21:24:14,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5422 states to 5422 states and 6526 transitions. [2019-11-19 21:24:14,395 INFO L78 Accepts]: Start accepts. Automaton has 5422 states and 6526 transitions. Word has length 177 [2019-11-19 21:24:14,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:14,396 INFO L462 AbstractCegarLoop]: Abstraction has 5422 states and 6526 transitions. [2019-11-19 21:24:14,396 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:14,396 INFO L276 IsEmpty]: Start isEmpty. Operand 5422 states and 6526 transitions. [2019-11-19 21:24:14,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-19 21:24:14,400 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:14,400 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:14,401 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:14,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:14,401 INFO L82 PathProgramCache]: Analyzing trace with hash -2095538940, now seen corresponding path program 1 times [2019-11-19 21:24:14,401 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:14,401 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45413164] [2019-11-19 21:24:14,401 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:14,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:14,451 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 79 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2019-11-19 21:24:14,451 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45413164] [2019-11-19 21:24:14,451 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:14,451 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:14,451 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248628138] [2019-11-19 21:24:14,452 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:14,452 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:14,452 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:14,452 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:14,452 INFO L87 Difference]: Start difference. First operand 5422 states and 6526 transitions. Second operand 3 states. [2019-11-19 21:24:14,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:14,581 INFO L93 Difference]: Finished difference Result 8854 states and 10720 transitions. [2019-11-19 21:24:14,581 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:14,581 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 180 [2019-11-19 21:24:14,582 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:14,584 INFO L225 Difference]: With dead ends: 8854 [2019-11-19 21:24:14,584 INFO L226 Difference]: Without dead ends: 3708 [2019-11-19 21:24:14,587 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:14,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3708 states. [2019-11-19 21:24:14,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3708 to 3100. [2019-11-19 21:24:14,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3100 states. [2019-11-19 21:24:14,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3100 states to 3100 states and 3693 transitions. [2019-11-19 21:24:14,682 INFO L78 Accepts]: Start accepts. Automaton has 3100 states and 3693 transitions. Word has length 180 [2019-11-19 21:24:14,682 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:14,682 INFO L462 AbstractCegarLoop]: Abstraction has 3100 states and 3693 transitions. [2019-11-19 21:24:14,682 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:14,682 INFO L276 IsEmpty]: Start isEmpty. Operand 3100 states and 3693 transitions. [2019-11-19 21:24:14,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-19 21:24:14,684 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:14,685 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:14,685 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:14,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:14,685 INFO L82 PathProgramCache]: Analyzing trace with hash -1037700862, now seen corresponding path program 1 times [2019-11-19 21:24:14,685 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:14,685 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088079816] [2019-11-19 21:24:14,685 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:14,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:14,749 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 91 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-19 21:24:14,750 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088079816] [2019-11-19 21:24:14,750 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:14,750 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-19 21:24:14,750 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1077482706] [2019-11-19 21:24:14,751 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-19 21:24:14,751 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:14,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-19 21:24:14,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-19 21:24:14,752 INFO L87 Difference]: Start difference. First operand 3100 states and 3693 transitions. Second operand 4 states. [2019-11-19 21:24:14,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:14,888 INFO L93 Difference]: Finished difference Result 4701 states and 5585 transitions. [2019-11-19 21:24:14,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-19 21:24:14,888 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 180 [2019-11-19 21:24:14,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:14,891 INFO L225 Difference]: With dead ends: 4701 [2019-11-19 21:24:14,891 INFO L226 Difference]: Without dead ends: 1877 [2019-11-19 21:24:14,893 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-19 21:24:14,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1877 states. [2019-11-19 21:24:14,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1877 to 1590. [2019-11-19 21:24:14,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1590 states. [2019-11-19 21:24:14,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1590 states to 1590 states and 1853 transitions. [2019-11-19 21:24:14,961 INFO L78 Accepts]: Start accepts. Automaton has 1590 states and 1853 transitions. Word has length 180 [2019-11-19 21:24:14,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:14,961 INFO L462 AbstractCegarLoop]: Abstraction has 1590 states and 1853 transitions. [2019-11-19 21:24:14,961 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-19 21:24:14,961 INFO L276 IsEmpty]: Start isEmpty. Operand 1590 states and 1853 transitions. [2019-11-19 21:24:14,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-11-19 21:24:14,962 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:14,963 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:14,963 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:14,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:14,963 INFO L82 PathProgramCache]: Analyzing trace with hash 1351947795, now seen corresponding path program 1 times [2019-11-19 21:24:14,963 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:14,963 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1379369703] [2019-11-19 21:24:14,963 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:14,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:15,010 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-19 21:24:15,010 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1379369703] [2019-11-19 21:24:15,010 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:15,010 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:15,011 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852500888] [2019-11-19 21:24:15,011 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:15,011 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:15,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:15,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:15,012 INFO L87 Difference]: Start difference. First operand 1590 states and 1853 transitions. Second operand 3 states. [2019-11-19 21:24:15,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:15,119 INFO L93 Difference]: Finished difference Result 4058 states and 4759 transitions. [2019-11-19 21:24:15,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:15,120 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 184 [2019-11-19 21:24:15,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:15,122 INFO L225 Difference]: With dead ends: 4058 [2019-11-19 21:24:15,123 INFO L226 Difference]: Without dead ends: 2438 [2019-11-19 21:24:15,124 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:15,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2438 states. [2019-11-19 21:24:15,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2438 to 2426. [2019-11-19 21:24:15,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2426 states. [2019-11-19 21:24:15,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2426 states to 2426 states and 2829 transitions. [2019-11-19 21:24:15,207 INFO L78 Accepts]: Start accepts. Automaton has 2426 states and 2829 transitions. Word has length 184 [2019-11-19 21:24:15,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:15,207 INFO L462 AbstractCegarLoop]: Abstraction has 2426 states and 2829 transitions. [2019-11-19 21:24:15,207 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:15,207 INFO L276 IsEmpty]: Start isEmpty. Operand 2426 states and 2829 transitions. [2019-11-19 21:24:15,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-11-19 21:24:15,208 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:15,209 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:15,209 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:15,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:15,209 INFO L82 PathProgramCache]: Analyzing trace with hash 1047126543, now seen corresponding path program 1 times [2019-11-19 21:24:15,209 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:15,210 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830750478] [2019-11-19 21:24:15,210 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:15,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:15,265 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 93 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-19 21:24:15,266 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [830750478] [2019-11-19 21:24:15,266 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:15,266 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:15,266 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136708283] [2019-11-19 21:24:15,267 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:15,267 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:15,267 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:15,267 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:15,267 INFO L87 Difference]: Start difference. First operand 2426 states and 2829 transitions. Second operand 3 states. [2019-11-19 21:24:15,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:15,336 INFO L93 Difference]: Finished difference Result 3380 states and 3910 transitions. [2019-11-19 21:24:15,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:15,337 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 184 [2019-11-19 21:24:15,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:15,338 INFO L225 Difference]: With dead ends: 3380 [2019-11-19 21:24:15,338 INFO L226 Difference]: Without dead ends: 1220 [2019-11-19 21:24:15,339 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:15,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1220 states. [2019-11-19 21:24:15,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1220 to 1198. [2019-11-19 21:24:15,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1198 states. [2019-11-19 21:24:15,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1198 states to 1198 states and 1326 transitions. [2019-11-19 21:24:15,379 INFO L78 Accepts]: Start accepts. Automaton has 1198 states and 1326 transitions. Word has length 184 [2019-11-19 21:24:15,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:15,379 INFO L462 AbstractCegarLoop]: Abstraction has 1198 states and 1326 transitions. [2019-11-19 21:24:15,379 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:15,379 INFO L276 IsEmpty]: Start isEmpty. Operand 1198 states and 1326 transitions. [2019-11-19 21:24:15,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2019-11-19 21:24:15,380 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:15,381 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:15,381 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:15,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:15,381 INFO L82 PathProgramCache]: Analyzing trace with hash -1330592792, now seen corresponding path program 1 times [2019-11-19 21:24:15,381 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:15,381 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007119286] [2019-11-19 21:24:15,381 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:15,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:15,427 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 107 trivial. 0 not checked. [2019-11-19 21:24:15,428 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007119286] [2019-11-19 21:24:15,428 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-19 21:24:15,428 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-19 21:24:15,428 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1448543007] [2019-11-19 21:24:15,429 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-19 21:24:15,429 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:15,429 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-19 21:24:15,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:15,430 INFO L87 Difference]: Start difference. First operand 1198 states and 1326 transitions. Second operand 3 states. [2019-11-19 21:24:15,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:15,528 INFO L93 Difference]: Finished difference Result 1202 states and 1331 transitions. [2019-11-19 21:24:15,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-19 21:24:15,528 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 185 [2019-11-19 21:24:15,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:15,530 INFO L225 Difference]: With dead ends: 1202 [2019-11-19 21:24:15,530 INFO L226 Difference]: Without dead ends: 1200 [2019-11-19 21:24:15,532 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-19 21:24:15,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1200 states. [2019-11-19 21:24:15,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1200 to 1200. [2019-11-19 21:24:15,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1200 states. [2019-11-19 21:24:15,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1200 states to 1200 states and 1328 transitions. [2019-11-19 21:24:15,610 INFO L78 Accepts]: Start accepts. Automaton has 1200 states and 1328 transitions. Word has length 185 [2019-11-19 21:24:15,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:15,611 INFO L462 AbstractCegarLoop]: Abstraction has 1200 states and 1328 transitions. [2019-11-19 21:24:15,611 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-19 21:24:15,611 INFO L276 IsEmpty]: Start isEmpty. Operand 1200 states and 1328 transitions. [2019-11-19 21:24:15,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2019-11-19 21:24:15,613 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:15,613 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:15,613 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:15,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:15,614 INFO L82 PathProgramCache]: Analyzing trace with hash -1330591190, now seen corresponding path program 1 times [2019-11-19 21:24:15,614 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:15,614 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444592171] [2019-11-19 21:24:15,615 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:15,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:15,837 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 81 proven. 15 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-19 21:24:15,837 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1444592171] [2019-11-19 21:24:15,838 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1285373175] [2019-11-19 21:24:15,838 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-19 21:24:15,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-19 21:24:15,944 INFO L255 TraceCheckSpWp]: Trace formula consists of 499 conjuncts, 19 conjunts are in the unsatisfiable core [2019-11-19 21:24:15,968 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-19 21:24:16,097 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 81 proven. 15 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-19 21:24:16,098 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-19 21:24:16,098 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2019-11-19 21:24:16,098 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838874129] [2019-11-19 21:24:16,100 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-11-19 21:24:16,100 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-19 21:24:16,101 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-11-19 21:24:16,101 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2019-11-19 21:24:16,101 INFO L87 Difference]: Start difference. First operand 1200 states and 1328 transitions. Second operand 10 states. [2019-11-19 21:24:16,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-19 21:24:16,605 INFO L93 Difference]: Finished difference Result 2336 states and 2602 transitions. [2019-11-19 21:24:16,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-11-19 21:24:16,605 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 185 [2019-11-19 21:24:16,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-19 21:24:16,611 INFO L225 Difference]: With dead ends: 2336 [2019-11-19 21:24:16,611 INFO L226 Difference]: Without dead ends: 1732 [2019-11-19 21:24:16,612 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 206 GetRequests, 188 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=64, Invalid=242, Unknown=0, NotChecked=0, Total=306 [2019-11-19 21:24:16,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1732 states. [2019-11-19 21:24:16,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1732 to 1546. [2019-11-19 21:24:16,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1546 states. [2019-11-19 21:24:16,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1546 states to 1546 states and 1714 transitions. [2019-11-19 21:24:16,772 INFO L78 Accepts]: Start accepts. Automaton has 1546 states and 1714 transitions. Word has length 185 [2019-11-19 21:24:16,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-19 21:24:16,773 INFO L462 AbstractCegarLoop]: Abstraction has 1546 states and 1714 transitions. [2019-11-19 21:24:16,773 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-11-19 21:24:16,773 INFO L276 IsEmpty]: Start isEmpty. Operand 1546 states and 1714 transitions. [2019-11-19 21:24:16,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2019-11-19 21:24:16,775 INFO L402 BasicCegarLoop]: Found error trace [2019-11-19 21:24:16,776 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-19 21:24:16,980 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-19 21:24:16,981 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-19 21:24:16,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-19 21:24:16,982 INFO L82 PathProgramCache]: Analyzing trace with hash 1701344696, now seen corresponding path program 1 times [2019-11-19 21:24:16,982 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-19 21:24:16,982 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267680448] [2019-11-19 21:24:16,982 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-19 21:24:17,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-19 21:24:17,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-19 21:24:17,094 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-19 21:24:17,094 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-19 21:24:17,278 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 19.11 09:24:17 BoogieIcfgContainer [2019-11-19 21:24:17,278 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-19 21:24:17,279 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-19 21:24:17,279 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-19 21:24:17,279 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-19 21:24:17,280 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 09:23:52" (3/4) ... [2019-11-19 21:24:17,282 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-19 21:24:17,549 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-19 21:24:17,549 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-19 21:24:17,554 INFO L168 Benchmark]: Toolchain (without parser) took 26791.65 ms. Allocated memory was 1.0 GB in the beginning and 3.5 GB in the end (delta: 2.4 GB). Free memory was 957.7 MB in the beginning and 1.7 GB in the end (delta: -715.2 MB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. [2019-11-19 21:24:17,554 INFO L168 Benchmark]: CDTParser took 0.28 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-19 21:24:17,555 INFO L168 Benchmark]: CACSL2BoogieTranslator took 476.78 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 156.8 MB). Free memory was 957.7 MB in the beginning and 1.1 GB in the end (delta: -189.1 MB). Peak memory consumption was 27.4 MB. Max. memory is 11.5 GB. [2019-11-19 21:24:17,555 INFO L168 Benchmark]: Boogie Procedure Inliner took 50.44 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-19 21:24:17,556 INFO L168 Benchmark]: Boogie Preprocessor took 36.68 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-19 21:24:17,556 INFO L168 Benchmark]: RCFGBuilder took 779.11 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 43.3 MB). Peak memory consumption was 43.3 MB. Max. memory is 11.5 GB. [2019-11-19 21:24:17,557 INFO L168 Benchmark]: TraceAbstraction took 25171.42 ms. Allocated memory was 1.2 GB in the beginning and 3.5 GB in the end (delta: 2.3 GB). Free memory was 1.1 GB in the beginning and 1.7 GB in the end (delta: -626.3 MB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. [2019-11-19 21:24:17,558 INFO L168 Benchmark]: Witness Printer took 270.66 ms. Allocated memory is still 3.5 GB. Free memory was 1.7 GB in the beginning and 1.7 GB in the end (delta: 50.5 MB). Peak memory consumption was 50.5 MB. Max. memory is 11.5 GB. [2019-11-19 21:24:17,560 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.28 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 476.78 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 156.8 MB). Free memory was 957.7 MB in the beginning and 1.1 GB in the end (delta: -189.1 MB). Peak memory consumption was 27.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 50.44 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 36.68 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 779.11 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 43.3 MB). Peak memory consumption was 43.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 25171.42 ms. Allocated memory was 1.2 GB in the beginning and 3.5 GB in the end (delta: 2.3 GB). Free memory was 1.1 GB in the beginning and 1.7 GB in the end (delta: -626.3 MB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. * Witness Printer took 270.66 ms. Allocated memory is still 3.5 GB. Free memory was 1.7 GB in the beginning and 1.7 GB in the end (delta: 50.5 MB). Peak memory consumption was 50.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L691] int __retres1 ; [L695] e_wl = 2 [L696] e_c = e_wl [L697] e_g = e_c [L698] e_f = e_g [L699] e_e = e_f [L700] wl_pc = 0 [L701] c1_pc = 0 [L702] c2_pc = 0 [L703] wb_pc = 0 [L704] wb_i = 1 [L705] c2_i = wb_i [L706] c1_i = c2_i [L707] wl_i = c1_i [L708] r_i = 0 [L709] c_req_up = 0 [L710] d = 0 [L711] c = 0 [L402] int kernel_st ; [L405] kernel_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L406] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L417] COND TRUE (int )wl_i == 1 [L418] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L422] COND TRUE (int )c1_i == 1 [L423] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L427] COND TRUE (int )c2_i == 1 [L428] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L432] COND TRUE (int )wb_i == 1 [L433] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L437] COND FALSE !((int )r_i == 1) [L440] r_st = 2 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L442] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L447] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L452] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L457] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L462] COND FALSE !((int )e_wl == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L467] COND FALSE !((int )wl_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L475] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L485] COND FALSE !((int )c1_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L494] COND FALSE !((int )c2_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L503] COND FALSE !((int )wb_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L512] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L517] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L522] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L527] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L532] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L537] COND FALSE !((int )e_wl == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L543] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L139] COND TRUE (int )c1_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L150] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L184] COND TRUE (int )c2_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L195] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L229] COND TRUE (int )wb_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L240] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L561] kernel_st = 3 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L577] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L582] COND TRUE (int )e_wl == 0 [L583] e_wl = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L587] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L588] COND TRUE (int )e_wl == 1 [L589] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L605] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L606] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L614] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L615] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L623] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L624] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L632] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L637] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L642] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L647] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L652] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L657] COND TRUE (int )e_wl == 1 [L658] e_wl = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L662] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L543] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L139] COND FALSE !((int )c1_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L142] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L157] COND TRUE ! processed [L158] data += 1 [L159] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L160] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L161] COND TRUE (int )e_g == 1 [L162] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L169] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L150] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L184] COND FALSE !((int )c2_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L187] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] COND TRUE ! processed [L203] data += 1 [L204] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L205] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L206] COND TRUE (int )e_g == 1 [L207] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L214] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L195] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L229] COND FALSE !((int )wb_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L232] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L247] c_t = data [L248] c_req_up = 1 [L249] processed = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L240] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND TRUE (int )c_req_up == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L551] COND TRUE c != c_t [L552] c = c_t [L553] e_c = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L557] c_req_up = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L561] kernel_st = 3 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L577] COND TRUE (int )e_c == 0 [L578] e_c = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L582] COND FALSE !((int )e_wl == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L587] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L595] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L596] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L605] COND TRUE (int )c1_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L606] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L614] COND TRUE (int )c2_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L615] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L623] COND TRUE (int )wb_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L624] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L632] COND TRUE (int )e_c == 1 [L633] r_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L637] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L642] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L647] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L652] COND TRUE (int )e_c == 1 [L653] e_c = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L657] COND FALSE !((int )e_wl == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L665] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L668] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L671] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L674] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L543] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L319] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L349] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L364] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND TRUE (int )r_st == 0 [L381] tmp___3 = __VERIFIER_nondet_int() [L383] COND TRUE \read(tmp___3) [L385] r_st = 1 [L261] d = c [L262] e_e = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L263] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L271] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L272] COND TRUE (int )e_e == 1 [L273] wl_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L281] e_e = 2 [L282] r_st = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L296] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L112] COND TRUE d == t + 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L120] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 129 locations, 2 error locations. Result: UNSAFE, OverallTime: 25.0s, OverallIterations: 39, TraceHistogramMax: 6, AutomataDifference: 12.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 8305 SDtfs, 6676 SDslu, 6853 SDs, 0 SdLazy, 904 SolverSat, 221 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 337 GetRequests, 266 SyntacticMatches, 4 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=16823occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 9.7s AutomataMinimizationTime, 38 MinimizatonAttempts, 9357 StatesRemovedByMinimization, 31 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 1.3s InterpolantComputationTime, 3918 NumberOfCodeBlocks, 3918 NumberOfCodeBlocksAsserted, 40 NumberOfCheckSat, 3693 ConstructedInterpolants, 0 QuantifiedInterpolants, 995189 SizeOfPredicates, 8 NumberOfNonLiveVariables, 499 ConjunctsInSsa, 19 ConjunctsInUnsatCore, 39 InterpolantComputations, 37 PerfectInterpolantSequences, 1373/1403 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...