./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c -s /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2b1be4311b85b6fe57410228c7ae2544fffadecc ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-10-22 08:57:35,261 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-22 08:57:35,262 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-22 08:57:35,272 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-22 08:57:35,272 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-22 08:57:35,273 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-22 08:57:35,274 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-22 08:57:35,275 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-22 08:57:35,277 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-22 08:57:35,277 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-22 08:57:35,278 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-22 08:57:35,279 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-22 08:57:35,279 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-22 08:57:35,280 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-22 08:57:35,280 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-22 08:57:35,281 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-22 08:57:35,282 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-22 08:57:35,282 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-22 08:57:35,284 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-22 08:57:35,285 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-22 08:57:35,286 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-22 08:57:35,287 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-22 08:57:35,288 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-22 08:57:35,289 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-22 08:57:35,290 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-22 08:57:35,291 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-22 08:57:35,291 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-22 08:57:35,291 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-22 08:57:35,292 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-22 08:57:35,293 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-22 08:57:35,293 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-22 08:57:35,293 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-22 08:57:35,294 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-22 08:57:35,294 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-22 08:57:35,295 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-22 08:57:35,295 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-22 08:57:35,296 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-22 08:57:35,296 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-22 08:57:35,296 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-22 08:57:35,297 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-22 08:57:35,298 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-22 08:57:35,298 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-22 08:57:35,309 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-22 08:57:35,310 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-22 08:57:35,311 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-22 08:57:35,311 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-22 08:57:35,311 INFO L138 SettingsManager]: * Use SBE=true [2019-10-22 08:57:35,311 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-22 08:57:35,311 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-22 08:57:35,312 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-22 08:57:35,312 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-22 08:57:35,312 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-22 08:57:35,312 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-22 08:57:35,312 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-22 08:57:35,312 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-22 08:57:35,313 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-22 08:57:35,313 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-22 08:57:35,313 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-22 08:57:35,313 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-22 08:57:35,313 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-22 08:57:35,313 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-22 08:57:35,314 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-22 08:57:35,314 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-22 08:57:35,314 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-22 08:57:35,314 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-22 08:57:35,314 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-22 08:57:35,314 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-22 08:57:35,315 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-22 08:57:35,315 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-22 08:57:35,315 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-22 08:57:35,315 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2b1be4311b85b6fe57410228c7ae2544fffadecc [2019-10-22 08:57:35,338 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-22 08:57:35,348 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-22 08:57:35,350 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-22 08:57:35,352 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-22 08:57:35,352 INFO L275 PluginConnector]: CDTParser initialized [2019-10-22 08:57:35,353 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2019-10-22 08:57:35,396 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/data/34a40bf82/40096a61bbd5487e999aed2000140cf6/FLAG3e4e4c0e0 [2019-10-22 08:57:35,802 INFO L306 CDTParser]: Found 1 translation units. [2019-10-22 08:57:35,806 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2019-10-22 08:57:35,814 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/data/34a40bf82/40096a61bbd5487e999aed2000140cf6/FLAG3e4e4c0e0 [2019-10-22 08:57:35,826 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/data/34a40bf82/40096a61bbd5487e999aed2000140cf6 [2019-10-22 08:57:35,828 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-22 08:57:35,829 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-10-22 08:57:35,830 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-22 08:57:35,830 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-22 08:57:35,833 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-22 08:57:35,834 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 08:57:35" (1/1) ... [2019-10-22 08:57:35,837 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@49c559ad and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:35, skipping insertion in model container [2019-10-22 08:57:35,837 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 08:57:35" (1/1) ... [2019-10-22 08:57:35,844 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-22 08:57:35,885 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-22 08:57:36,240 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 08:57:36,250 INFO L188 MainTranslator]: Completed pre-run [2019-10-22 08:57:36,360 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 08:57:36,380 INFO L192 MainTranslator]: Completed translation [2019-10-22 08:57:36,381 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36 WrapperNode [2019-10-22 08:57:36,381 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-22 08:57:36,382 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-10-22 08:57:36,382 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-10-22 08:57:36,382 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-10-22 08:57:36,391 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36" (1/1) ... [2019-10-22 08:57:36,406 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36" (1/1) ... [2019-10-22 08:57:36,478 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-10-22 08:57:36,478 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-22 08:57:36,478 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-22 08:57:36,478 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-22 08:57:36,488 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36" (1/1) ... [2019-10-22 08:57:36,489 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36" (1/1) ... [2019-10-22 08:57:36,493 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36" (1/1) ... [2019-10-22 08:57:36,494 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36" (1/1) ... [2019-10-22 08:57:36,506 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36" (1/1) ... [2019-10-22 08:57:36,515 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36" (1/1) ... [2019-10-22 08:57:36,519 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36" (1/1) ... [2019-10-22 08:57:36,528 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-22 08:57:36,529 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-22 08:57:36,529 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-22 08:57:36,529 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-22 08:57:36,530 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-22 08:57:36,590 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-22 08:57:36,590 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-22 08:57:37,602 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-22 08:57:37,602 INFO L284 CfgBuilder]: Removed 119 assume(true) statements. [2019-10-22 08:57:37,605 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:57:37 BoogieIcfgContainer [2019-10-22 08:57:37,605 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-22 08:57:37,606 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-22 08:57:37,607 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-22 08:57:37,610 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-22 08:57:37,610 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 22.10 08:57:35" (1/3) ... [2019-10-22 08:57:37,612 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@52e1d074 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.10 08:57:37, skipping insertion in model container [2019-10-22 08:57:37,612 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:57:36" (2/3) ... [2019-10-22 08:57:37,613 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@52e1d074 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.10 08:57:37, skipping insertion in model container [2019-10-22 08:57:37,613 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:57:37" (3/3) ... [2019-10-22 08:57:37,615 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2019-10-22 08:57:37,626 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-22 08:57:37,634 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-10-22 08:57:37,647 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-10-22 08:57:37,683 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-22 08:57:37,683 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-22 08:57:37,684 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-22 08:57:37,684 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-22 08:57:37,684 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-22 08:57:37,685 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-22 08:57:37,685 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-22 08:57:37,685 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-22 08:57:37,713 INFO L276 IsEmpty]: Start isEmpty. Operand 291 states. [2019-10-22 08:57:37,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-10-22 08:57:37,721 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:37,721 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:37,724 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:37,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:37,730 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-10-22 08:57:37,736 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:37,736 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1072570846] [2019-10-22 08:57:37,736 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:37,737 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:37,737 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:37,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:37,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:37,911 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1072570846] [2019-10-22 08:57:37,912 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:37,918 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:57:37,918 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771047437] [2019-10-22 08:57:37,922 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:57:37,923 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:37,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:57:37,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:37,939 INFO L87 Difference]: Start difference. First operand 291 states. Second operand 3 states. [2019-10-22 08:57:38,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:38,020 INFO L93 Difference]: Finished difference Result 568 states and 884 transitions. [2019-10-22 08:57:38,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:57:38,022 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-10-22 08:57:38,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:38,040 INFO L225 Difference]: With dead ends: 568 [2019-10-22 08:57:38,040 INFO L226 Difference]: Without dead ends: 287 [2019-10-22 08:57:38,045 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:38,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2019-10-22 08:57:38,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 287. [2019-10-22 08:57:38,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 287 states. [2019-10-22 08:57:38,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 287 states to 287 states and 409 transitions. [2019-10-22 08:57:38,113 INFO L78 Accepts]: Start accepts. Automaton has 287 states and 409 transitions. Word has length 31 [2019-10-22 08:57:38,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:38,114 INFO L462 AbstractCegarLoop]: Abstraction has 287 states and 409 transitions. [2019-10-22 08:57:38,114 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:57:38,114 INFO L276 IsEmpty]: Start isEmpty. Operand 287 states and 409 transitions. [2019-10-22 08:57:38,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-22 08:57:38,115 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:38,115 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:38,116 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:38,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:38,117 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-10-22 08:57:38,117 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:38,117 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208167435] [2019-10-22 08:57:38,117 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:38,117 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:38,117 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:38,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:38,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:38,275 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1208167435] [2019-10-22 08:57:38,275 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:38,275 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:57:38,275 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [788529714] [2019-10-22 08:57:38,277 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:57:38,277 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:38,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:57:38,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:38,278 INFO L87 Difference]: Start difference. First operand 287 states and 409 transitions. Second operand 3 states. [2019-10-22 08:57:38,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:38,351 INFO L93 Difference]: Finished difference Result 593 states and 853 transitions. [2019-10-22 08:57:38,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:57:38,352 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-10-22 08:57:38,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:38,355 INFO L225 Difference]: With dead ends: 593 [2019-10-22 08:57:38,355 INFO L226 Difference]: Without dead ends: 321 [2019-10-22 08:57:38,357 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:38,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2019-10-22 08:57:38,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 263. [2019-10-22 08:57:38,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 263 states. [2019-10-22 08:57:38,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 263 states to 263 states and 373 transitions. [2019-10-22 08:57:38,382 INFO L78 Accepts]: Start accepts. Automaton has 263 states and 373 transitions. Word has length 42 [2019-10-22 08:57:38,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:38,383 INFO L462 AbstractCegarLoop]: Abstraction has 263 states and 373 transitions. [2019-10-22 08:57:38,383 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:57:38,383 INFO L276 IsEmpty]: Start isEmpty. Operand 263 states and 373 transitions. [2019-10-22 08:57:38,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-22 08:57:38,384 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:38,385 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:38,385 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:38,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:38,386 INFO L82 PathProgramCache]: Analyzing trace with hash -365626229, now seen corresponding path program 1 times [2019-10-22 08:57:38,386 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:38,386 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175080792] [2019-10-22 08:57:38,386 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:38,386 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:38,387 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:38,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:38,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:38,579 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175080792] [2019-10-22 08:57:38,580 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:38,580 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:57:38,580 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [314212606] [2019-10-22 08:57:38,581 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:57:38,581 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:38,581 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:57:38,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:38,582 INFO L87 Difference]: Start difference. First operand 263 states and 373 transitions. Second operand 3 states. [2019-10-22 08:57:38,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:38,643 INFO L93 Difference]: Finished difference Result 736 states and 1054 transitions. [2019-10-22 08:57:38,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:57:38,648 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-10-22 08:57:38,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:38,651 INFO L225 Difference]: With dead ends: 736 [2019-10-22 08:57:38,655 INFO L226 Difference]: Without dead ends: 488 [2019-10-22 08:57:38,657 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:38,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states. [2019-10-22 08:57:38,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 296. [2019-10-22 08:57:38,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 296 states. [2019-10-22 08:57:38,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 296 states to 296 states and 421 transitions. [2019-10-22 08:57:38,697 INFO L78 Accepts]: Start accepts. Automaton has 296 states and 421 transitions. Word has length 49 [2019-10-22 08:57:38,697 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:38,698 INFO L462 AbstractCegarLoop]: Abstraction has 296 states and 421 transitions. [2019-10-22 08:57:38,698 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:57:38,698 INFO L276 IsEmpty]: Start isEmpty. Operand 296 states and 421 transitions. [2019-10-22 08:57:38,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-10-22 08:57:38,701 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:38,702 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:38,702 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:38,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:38,703 INFO L82 PathProgramCache]: Analyzing trace with hash 744745200, now seen corresponding path program 1 times [2019-10-22 08:57:38,704 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:38,704 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421530949] [2019-10-22 08:57:38,704 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:38,704 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:38,705 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:38,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:38,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:38,823 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421530949] [2019-10-22 08:57:38,823 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:38,823 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 08:57:38,824 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741632298] [2019-10-22 08:57:38,824 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 08:57:38,824 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:38,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:57:38,825 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:38,825 INFO L87 Difference]: Start difference. First operand 296 states and 421 transitions. Second operand 5 states. [2019-10-22 08:57:39,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:39,139 INFO L93 Difference]: Finished difference Result 932 states and 1340 transitions. [2019-10-22 08:57:39,139 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 08:57:39,140 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-10-22 08:57:39,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:39,143 INFO L225 Difference]: With dead ends: 932 [2019-10-22 08:57:39,145 INFO L226 Difference]: Without dead ends: 651 [2019-10-22 08:57:39,146 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-10-22 08:57:39,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 651 states. [2019-10-22 08:57:39,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 651 to 382. [2019-10-22 08:57:39,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2019-10-22 08:57:39,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 544 transitions. [2019-10-22 08:57:39,177 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 544 transitions. Word has length 50 [2019-10-22 08:57:39,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:39,180 INFO L462 AbstractCegarLoop]: Abstraction has 382 states and 544 transitions. [2019-10-22 08:57:39,180 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 08:57:39,180 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 544 transitions. [2019-10-22 08:57:39,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-10-22 08:57:39,182 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:39,182 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:39,182 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:39,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:39,183 INFO L82 PathProgramCache]: Analyzing trace with hash 1614483527, now seen corresponding path program 1 times [2019-10-22 08:57:39,183 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:39,183 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518790428] [2019-10-22 08:57:39,184 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:39,184 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:39,184 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:39,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:39,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:39,298 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [518790428] [2019-10-22 08:57:39,298 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:39,298 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 08:57:39,299 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917538624] [2019-10-22 08:57:39,299 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 08:57:39,299 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:39,300 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:57:39,300 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:39,300 INFO L87 Difference]: Start difference. First operand 382 states and 544 transitions. Second operand 5 states. [2019-10-22 08:57:39,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:39,523 INFO L93 Difference]: Finished difference Result 932 states and 1336 transitions. [2019-10-22 08:57:39,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 08:57:39,524 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-10-22 08:57:39,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:39,527 INFO L225 Difference]: With dead ends: 932 [2019-10-22 08:57:39,527 INFO L226 Difference]: Without dead ends: 651 [2019-10-22 08:57:39,529 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-10-22 08:57:39,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 651 states. [2019-10-22 08:57:39,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 651 to 382. [2019-10-22 08:57:39,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2019-10-22 08:57:39,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 542 transitions. [2019-10-22 08:57:39,551 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 542 transitions. Word has length 51 [2019-10-22 08:57:39,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:39,552 INFO L462 AbstractCegarLoop]: Abstraction has 382 states and 542 transitions. [2019-10-22 08:57:39,552 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 08:57:39,552 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 542 transitions. [2019-10-22 08:57:39,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-10-22 08:57:39,559 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:39,559 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:39,560 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:39,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:39,560 INFO L82 PathProgramCache]: Analyzing trace with hash 251892323, now seen corresponding path program 1 times [2019-10-22 08:57:39,560 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:39,560 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040678963] [2019-10-22 08:57:39,561 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:39,561 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:39,561 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:39,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:39,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:39,702 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040678963] [2019-10-22 08:57:39,702 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:39,702 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:57:39,702 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1869711623] [2019-10-22 08:57:39,703 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 08:57:39,703 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:39,703 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:57:39,704 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:39,704 INFO L87 Difference]: Start difference. First operand 382 states and 542 transitions. Second operand 5 states. [2019-10-22 08:57:39,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:39,769 INFO L93 Difference]: Finished difference Result 760 states and 1089 transitions. [2019-10-22 08:57:39,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-22 08:57:39,771 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2019-10-22 08:57:39,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:39,774 INFO L225 Difference]: With dead ends: 760 [2019-10-22 08:57:39,775 INFO L226 Difference]: Without dead ends: 479 [2019-10-22 08:57:39,775 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-10-22 08:57:39,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states. [2019-10-22 08:57:39,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 377. [2019-10-22 08:57:39,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 377 states. [2019-10-22 08:57:39,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 377 states to 377 states and 534 transitions. [2019-10-22 08:57:39,799 INFO L78 Accepts]: Start accepts. Automaton has 377 states and 534 transitions. Word has length 52 [2019-10-22 08:57:39,799 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:39,799 INFO L462 AbstractCegarLoop]: Abstraction has 377 states and 534 transitions. [2019-10-22 08:57:39,800 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 08:57:39,800 INFO L276 IsEmpty]: Start isEmpty. Operand 377 states and 534 transitions. [2019-10-22 08:57:39,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-10-22 08:57:39,801 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:39,801 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:39,801 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:39,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:39,802 INFO L82 PathProgramCache]: Analyzing trace with hash -1519937093, now seen corresponding path program 1 times [2019-10-22 08:57:39,802 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:39,802 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860238431] [2019-10-22 08:57:39,802 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:39,803 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:39,803 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:39,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:39,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:39,992 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [860238431] [2019-10-22 08:57:39,993 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:39,993 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:57:39,993 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1026168212] [2019-10-22 08:57:39,993 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 08:57:39,994 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:39,994 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:57:39,994 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:39,994 INFO L87 Difference]: Start difference. First operand 377 states and 534 transitions. Second operand 5 states. [2019-10-22 08:57:40,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:40,127 INFO L93 Difference]: Finished difference Result 791 states and 1138 transitions. [2019-10-22 08:57:40,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 08:57:40,128 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-10-22 08:57:40,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:40,130 INFO L225 Difference]: With dead ends: 791 [2019-10-22 08:57:40,130 INFO L226 Difference]: Without dead ends: 515 [2019-10-22 08:57:40,131 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-10-22 08:57:40,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 515 states. [2019-10-22 08:57:40,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 515 to 347. [2019-10-22 08:57:40,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 347 states. [2019-10-22 08:57:40,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 347 states to 347 states and 488 transitions. [2019-10-22 08:57:40,152 INFO L78 Accepts]: Start accepts. Automaton has 347 states and 488 transitions. Word has length 56 [2019-10-22 08:57:40,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:40,153 INFO L462 AbstractCegarLoop]: Abstraction has 347 states and 488 transitions. [2019-10-22 08:57:40,153 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 08:57:40,153 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 488 transitions. [2019-10-22 08:57:40,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-22 08:57:40,154 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:40,154 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:40,154 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:40,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:40,155 INFO L82 PathProgramCache]: Analyzing trace with hash 1786376721, now seen corresponding path program 1 times [2019-10-22 08:57:40,155 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:40,155 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841742375] [2019-10-22 08:57:40,156 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:40,156 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:40,156 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:40,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:40,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:40,276 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841742375] [2019-10-22 08:57:40,276 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:40,276 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:57:40,276 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742913507] [2019-10-22 08:57:40,277 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 08:57:40,277 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:40,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:57:40,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:40,278 INFO L87 Difference]: Start difference. First operand 347 states and 488 transitions. Second operand 5 states. [2019-10-22 08:57:40,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:40,407 INFO L93 Difference]: Finished difference Result 884 states and 1260 transitions. [2019-10-22 08:57:40,407 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 08:57:40,407 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 61 [2019-10-22 08:57:40,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:40,410 INFO L225 Difference]: With dead ends: 884 [2019-10-22 08:57:40,410 INFO L226 Difference]: Without dead ends: 638 [2019-10-22 08:57:40,411 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-10-22 08:57:40,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 638 states. [2019-10-22 08:57:40,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 638 to 317. [2019-10-22 08:57:40,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2019-10-22 08:57:40,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 442 transitions. [2019-10-22 08:57:40,434 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 442 transitions. Word has length 61 [2019-10-22 08:57:40,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:40,434 INFO L462 AbstractCegarLoop]: Abstraction has 317 states and 442 transitions. [2019-10-22 08:57:40,435 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 08:57:40,435 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 442 transitions. [2019-10-22 08:57:40,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-10-22 08:57:40,435 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:40,436 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:40,436 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:40,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:40,437 INFO L82 PathProgramCache]: Analyzing trace with hash -1245848025, now seen corresponding path program 1 times [2019-10-22 08:57:40,437 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:40,437 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570914549] [2019-10-22 08:57:40,437 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:40,437 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:40,437 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:40,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:40,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:40,632 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1570914549] [2019-10-22 08:57:40,632 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:40,633 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 08:57:40,633 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984389017] [2019-10-22 08:57:40,633 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 08:57:40,634 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:40,634 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 08:57:40,634 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 08:57:40,635 INFO L87 Difference]: Start difference. First operand 317 states and 442 transitions. Second operand 6 states. [2019-10-22 08:57:40,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:40,873 INFO L93 Difference]: Finished difference Result 1081 states and 1520 transitions. [2019-10-22 08:57:40,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-10-22 08:57:40,874 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-10-22 08:57:40,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:40,877 INFO L225 Difference]: With dead ends: 1081 [2019-10-22 08:57:40,877 INFO L226 Difference]: Without dead ends: 865 [2019-10-22 08:57:40,878 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-10-22 08:57:40,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 865 states. [2019-10-22 08:57:40,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 865 to 356. [2019-10-22 08:57:40,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 356 states. [2019-10-22 08:57:40,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 356 states to 356 states and 496 transitions. [2019-10-22 08:57:40,901 INFO L78 Accepts]: Start accepts. Automaton has 356 states and 496 transitions. Word has length 66 [2019-10-22 08:57:40,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:40,902 INFO L462 AbstractCegarLoop]: Abstraction has 356 states and 496 transitions. [2019-10-22 08:57:40,902 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 08:57:40,902 INFO L276 IsEmpty]: Start isEmpty. Operand 356 states and 496 transitions. [2019-10-22 08:57:40,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-22 08:57:40,902 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:40,903 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:40,903 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:40,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:40,904 INFO L82 PathProgramCache]: Analyzing trace with hash 1591247394, now seen corresponding path program 1 times [2019-10-22 08:57:40,904 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:40,904 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2980571] [2019-10-22 08:57:40,904 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:40,904 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:40,904 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:40,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:40,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:40,957 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2980571] [2019-10-22 08:57:40,957 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:40,957 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:57:40,957 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601314747] [2019-10-22 08:57:40,958 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:57:40,958 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:40,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:57:40,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:40,958 INFO L87 Difference]: Start difference. First operand 356 states and 496 transitions. Second operand 3 states. [2019-10-22 08:57:41,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:41,011 INFO L93 Difference]: Finished difference Result 650 states and 915 transitions. [2019-10-22 08:57:41,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:57:41,011 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-10-22 08:57:41,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:41,013 INFO L225 Difference]: With dead ends: 650 [2019-10-22 08:57:41,013 INFO L226 Difference]: Without dead ends: 434 [2019-10-22 08:57:41,014 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:41,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 434 states. [2019-10-22 08:57:41,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 434 to 352. [2019-10-22 08:57:41,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2019-10-22 08:57:41,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 489 transitions. [2019-10-22 08:57:41,038 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 489 transitions. Word has length 67 [2019-10-22 08:57:41,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:41,038 INFO L462 AbstractCegarLoop]: Abstraction has 352 states and 489 transitions. [2019-10-22 08:57:41,038 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:57:41,039 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 489 transitions. [2019-10-22 08:57:41,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-10-22 08:57:41,039 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:41,040 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:41,040 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:41,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:41,040 INFO L82 PathProgramCache]: Analyzing trace with hash 480130565, now seen corresponding path program 1 times [2019-10-22 08:57:41,041 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:41,041 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371871118] [2019-10-22 08:57:41,041 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:41,041 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:41,041 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:41,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:41,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:41,100 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [371871118] [2019-10-22 08:57:41,100 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:41,100 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 08:57:41,100 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443407106] [2019-10-22 08:57:41,100 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 08:57:41,101 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:41,101 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 08:57:41,101 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 08:57:41,101 INFO L87 Difference]: Start difference. First operand 352 states and 489 transitions. Second operand 4 states. [2019-10-22 08:57:41,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:41,236 INFO L93 Difference]: Finished difference Result 937 states and 1304 transitions. [2019-10-22 08:57:41,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 08:57:41,236 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 70 [2019-10-22 08:57:41,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:41,239 INFO L225 Difference]: With dead ends: 937 [2019-10-22 08:57:41,240 INFO L226 Difference]: Without dead ends: 715 [2019-10-22 08:57:41,240 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:41,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 715 states. [2019-10-22 08:57:41,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 715 to 518. [2019-10-22 08:57:41,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2019-10-22 08:57:41,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 716 transitions. [2019-10-22 08:57:41,280 INFO L78 Accepts]: Start accepts. Automaton has 518 states and 716 transitions. Word has length 70 [2019-10-22 08:57:41,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:41,280 INFO L462 AbstractCegarLoop]: Abstraction has 518 states and 716 transitions. [2019-10-22 08:57:41,280 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 08:57:41,281 INFO L276 IsEmpty]: Start isEmpty. Operand 518 states and 716 transitions. [2019-10-22 08:57:41,281 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-10-22 08:57:41,281 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:41,282 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:41,282 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:41,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:41,283 INFO L82 PathProgramCache]: Analyzing trace with hash -1523824051, now seen corresponding path program 1 times [2019-10-22 08:57:41,284 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:41,284 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236104331] [2019-10-22 08:57:41,284 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:41,284 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:41,284 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:41,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:41,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:41,338 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236104331] [2019-10-22 08:57:41,338 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:41,339 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:57:41,339 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1932376271] [2019-10-22 08:57:41,339 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:57:41,339 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:41,340 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:57:41,340 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:41,340 INFO L87 Difference]: Start difference. First operand 518 states and 716 transitions. Second operand 3 states. [2019-10-22 08:57:41,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:41,415 INFO L93 Difference]: Finished difference Result 1223 states and 1682 transitions. [2019-10-22 08:57:41,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:57:41,416 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-10-22 08:57:41,416 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:41,420 INFO L225 Difference]: With dead ends: 1223 [2019-10-22 08:57:41,420 INFO L226 Difference]: Without dead ends: 852 [2019-10-22 08:57:41,421 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:41,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 852 states. [2019-10-22 08:57:41,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 852 to 579. [2019-10-22 08:57:41,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 579 states. [2019-10-22 08:57:41,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 579 states to 579 states and 793 transitions. [2019-10-22 08:57:41,467 INFO L78 Accepts]: Start accepts. Automaton has 579 states and 793 transitions. Word has length 70 [2019-10-22 08:57:41,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:41,467 INFO L462 AbstractCegarLoop]: Abstraction has 579 states and 793 transitions. [2019-10-22 08:57:41,467 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:57:41,467 INFO L276 IsEmpty]: Start isEmpty. Operand 579 states and 793 transitions. [2019-10-22 08:57:41,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-10-22 08:57:41,468 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:41,468 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:41,469 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:41,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:41,469 INFO L82 PathProgramCache]: Analyzing trace with hash -1383275441, now seen corresponding path program 1 times [2019-10-22 08:57:41,469 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:41,470 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609243634] [2019-10-22 08:57:41,470 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:41,470 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:41,470 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:41,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:41,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:41,540 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [609243634] [2019-10-22 08:57:41,540 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:41,541 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:57:41,541 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566489471] [2019-10-22 08:57:41,541 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:57:41,541 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:41,542 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:57:41,542 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:41,542 INFO L87 Difference]: Start difference. First operand 579 states and 793 transitions. Second operand 3 states. [2019-10-22 08:57:41,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:41,597 INFO L93 Difference]: Finished difference Result 984 states and 1357 transitions. [2019-10-22 08:57:41,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:57:41,597 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-10-22 08:57:41,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:41,600 INFO L225 Difference]: With dead ends: 984 [2019-10-22 08:57:41,600 INFO L226 Difference]: Without dead ends: 544 [2019-10-22 08:57:41,601 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:41,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 544 states. [2019-10-22 08:57:41,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 544 to 544. [2019-10-22 08:57:41,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2019-10-22 08:57:41,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 744 transitions. [2019-10-22 08:57:41,652 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 744 transitions. Word has length 70 [2019-10-22 08:57:41,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:41,652 INFO L462 AbstractCegarLoop]: Abstraction has 544 states and 744 transitions. [2019-10-22 08:57:41,652 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:57:41,653 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 744 transitions. [2019-10-22 08:57:41,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-10-22 08:57:41,654 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:41,654 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:41,654 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:41,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:41,655 INFO L82 PathProgramCache]: Analyzing trace with hash -1837662732, now seen corresponding path program 1 times [2019-10-22 08:57:41,655 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:41,656 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510230210] [2019-10-22 08:57:41,656 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:41,656 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:41,656 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:41,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:41,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:41,812 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510230210] [2019-10-22 08:57:41,813 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:41,813 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 08:57:41,813 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488265584] [2019-10-22 08:57:41,813 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 08:57:41,814 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:41,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 08:57:41,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 08:57:41,814 INFO L87 Difference]: Start difference. First operand 544 states and 744 transitions. Second operand 6 states. [2019-10-22 08:57:42,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:42,189 INFO L93 Difference]: Finished difference Result 1710 states and 2373 transitions. [2019-10-22 08:57:42,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-10-22 08:57:42,190 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-10-22 08:57:42,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:42,194 INFO L225 Difference]: With dead ends: 1710 [2019-10-22 08:57:42,194 INFO L226 Difference]: Without dead ends: 1386 [2019-10-22 08:57:42,196 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-10-22 08:57:42,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1386 states. [2019-10-22 08:57:42,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1386 to 548. [2019-10-22 08:57:42,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 548 states. [2019-10-22 08:57:42,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 548 states to 548 states and 749 transitions. [2019-10-22 08:57:42,244 INFO L78 Accepts]: Start accepts. Automaton has 548 states and 749 transitions. Word has length 71 [2019-10-22 08:57:42,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:42,244 INFO L462 AbstractCegarLoop]: Abstraction has 548 states and 749 transitions. [2019-10-22 08:57:42,245 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 08:57:42,245 INFO L276 IsEmpty]: Start isEmpty. Operand 548 states and 749 transitions. [2019-10-22 08:57:42,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-10-22 08:57:42,245 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:42,246 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:42,246 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:42,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:42,246 INFO L82 PathProgramCache]: Analyzing trace with hash 276642491, now seen corresponding path program 1 times [2019-10-22 08:57:42,247 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:42,247 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807992298] [2019-10-22 08:57:42,247 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:42,247 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:42,248 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:42,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:42,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:42,340 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807992298] [2019-10-22 08:57:42,340 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:42,340 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:57:42,341 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [800078632] [2019-10-22 08:57:42,341 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 08:57:42,341 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:42,341 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:57:42,341 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:42,342 INFO L87 Difference]: Start difference. First operand 548 states and 749 transitions. Second operand 5 states. [2019-10-22 08:57:42,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:42,503 INFO L93 Difference]: Finished difference Result 858 states and 1189 transitions. [2019-10-22 08:57:42,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 08:57:42,504 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2019-10-22 08:57:42,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:42,507 INFO L225 Difference]: With dead ends: 858 [2019-10-22 08:57:42,507 INFO L226 Difference]: Without dead ends: 856 [2019-10-22 08:57:42,508 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-10-22 08:57:42,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 856 states. [2019-10-22 08:57:42,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 856 to 550. [2019-10-22 08:57:42,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 550 states. [2019-10-22 08:57:42,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 751 transitions. [2019-10-22 08:57:42,559 INFO L78 Accepts]: Start accepts. Automaton has 550 states and 751 transitions. Word has length 71 [2019-10-22 08:57:42,559 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:42,559 INFO L462 AbstractCegarLoop]: Abstraction has 550 states and 751 transitions. [2019-10-22 08:57:42,559 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 08:57:42,559 INFO L276 IsEmpty]: Start isEmpty. Operand 550 states and 751 transitions. [2019-10-22 08:57:42,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-10-22 08:57:42,560 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:42,560 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:42,561 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:42,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:42,561 INFO L82 PathProgramCache]: Analyzing trace with hash -66828782, now seen corresponding path program 1 times [2019-10-22 08:57:42,561 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:42,561 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083649294] [2019-10-22 08:57:42,561 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:42,562 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:42,562 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:42,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:42,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:42,670 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083649294] [2019-10-22 08:57:42,671 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:42,674 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 08:57:42,674 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [696283095] [2019-10-22 08:57:42,674 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 08:57:42,675 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:42,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 08:57:42,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 08:57:42,675 INFO L87 Difference]: Start difference. First operand 550 states and 751 transitions. Second operand 6 states. [2019-10-22 08:57:43,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:43,168 INFO L93 Difference]: Finished difference Result 1977 states and 2718 transitions. [2019-10-22 08:57:43,168 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-10-22 08:57:43,169 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-10-22 08:57:43,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:43,174 INFO L225 Difference]: With dead ends: 1977 [2019-10-22 08:57:43,174 INFO L226 Difference]: Without dead ends: 1612 [2019-10-22 08:57:43,175 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-10-22 08:57:43,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1612 states. [2019-10-22 08:57:43,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1612 to 596. [2019-10-22 08:57:43,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 596 states. [2019-10-22 08:57:43,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 596 states and 809 transitions. [2019-10-22 08:57:43,237 INFO L78 Accepts]: Start accepts. Automaton has 596 states and 809 transitions. Word has length 71 [2019-10-22 08:57:43,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:43,237 INFO L462 AbstractCegarLoop]: Abstraction has 596 states and 809 transitions. [2019-10-22 08:57:43,237 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 08:57:43,237 INFO L276 IsEmpty]: Start isEmpty. Operand 596 states and 809 transitions. [2019-10-22 08:57:43,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-10-22 08:57:43,238 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:43,238 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:43,241 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:43,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:43,241 INFO L82 PathProgramCache]: Analyzing trace with hash -624478278, now seen corresponding path program 1 times [2019-10-22 08:57:43,241 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:43,242 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001728935] [2019-10-22 08:57:43,242 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:43,242 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:43,242 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:43,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:43,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:43,366 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001728935] [2019-10-22 08:57:43,366 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:43,367 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 08:57:43,367 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [575190883] [2019-10-22 08:57:43,367 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 08:57:43,367 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:43,368 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 08:57:43,368 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 08:57:43,368 INFO L87 Difference]: Start difference. First operand 596 states and 809 transitions. Second operand 6 states. [2019-10-22 08:57:43,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:43,833 INFO L93 Difference]: Finished difference Result 2304 states and 3151 transitions. [2019-10-22 08:57:43,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-10-22 08:57:43,834 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-10-22 08:57:43,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:43,840 INFO L225 Difference]: With dead ends: 2304 [2019-10-22 08:57:43,840 INFO L226 Difference]: Without dead ends: 1931 [2019-10-22 08:57:43,841 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-10-22 08:57:43,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1931 states. [2019-10-22 08:57:43,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1931 to 674. [2019-10-22 08:57:43,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 674 states. [2019-10-22 08:57:43,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 911 transitions. [2019-10-22 08:57:43,915 INFO L78 Accepts]: Start accepts. Automaton has 674 states and 911 transitions. Word has length 72 [2019-10-22 08:57:43,915 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:43,915 INFO L462 AbstractCegarLoop]: Abstraction has 674 states and 911 transitions. [2019-10-22 08:57:43,915 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 08:57:43,915 INFO L276 IsEmpty]: Start isEmpty. Operand 674 states and 911 transitions. [2019-10-22 08:57:43,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-10-22 08:57:43,918 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:43,918 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:43,919 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:43,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:43,919 INFO L82 PathProgramCache]: Analyzing trace with hash -2046951303, now seen corresponding path program 1 times [2019-10-22 08:57:43,919 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:43,920 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221556260] [2019-10-22 08:57:43,920 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:43,920 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:43,920 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:43,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:44,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:44,010 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221556260] [2019-10-22 08:57:44,034 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:44,034 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 08:57:44,034 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1740142920] [2019-10-22 08:57:44,034 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 08:57:44,034 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:44,034 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 08:57:44,035 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 08:57:44,035 INFO L87 Difference]: Start difference. First operand 674 states and 911 transitions. Second operand 6 states. [2019-10-22 08:57:44,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:44,244 INFO L93 Difference]: Finished difference Result 1500 states and 2090 transitions. [2019-10-22 08:57:44,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-10-22 08:57:44,244 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-10-22 08:57:44,245 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:44,248 INFO L225 Difference]: With dead ends: 1500 [2019-10-22 08:57:44,249 INFO L226 Difference]: Without dead ends: 1110 [2019-10-22 08:57:44,250 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-10-22 08:57:44,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2019-10-22 08:57:44,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 680. [2019-10-22 08:57:44,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 680 states. [2019-10-22 08:57:44,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 917 transitions. [2019-10-22 08:57:44,315 INFO L78 Accepts]: Start accepts. Automaton has 680 states and 917 transitions. Word has length 72 [2019-10-22 08:57:44,315 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:44,316 INFO L462 AbstractCegarLoop]: Abstraction has 680 states and 917 transitions. [2019-10-22 08:57:44,316 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 08:57:44,316 INFO L276 IsEmpty]: Start isEmpty. Operand 680 states and 917 transitions. [2019-10-22 08:57:44,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-10-22 08:57:44,317 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:44,317 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:44,317 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:44,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:44,318 INFO L82 PathProgramCache]: Analyzing trace with hash 778464989, now seen corresponding path program 1 times [2019-10-22 08:57:44,318 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:44,318 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765638071] [2019-10-22 08:57:44,318 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:44,318 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:44,318 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:44,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:44,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:44,375 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765638071] [2019-10-22 08:57:44,375 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:44,375 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:57:44,375 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824006304] [2019-10-22 08:57:44,376 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:57:44,376 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:44,376 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:57:44,376 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:44,376 INFO L87 Difference]: Start difference. First operand 680 states and 917 transitions. Second operand 3 states. [2019-10-22 08:57:44,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:44,491 INFO L93 Difference]: Finished difference Result 1334 states and 1821 transitions. [2019-10-22 08:57:44,492 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:57:44,492 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-10-22 08:57:44,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:44,495 INFO L225 Difference]: With dead ends: 1334 [2019-10-22 08:57:44,495 INFO L226 Difference]: Without dead ends: 875 [2019-10-22 08:57:44,496 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:44,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 875 states. [2019-10-22 08:57:44,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 875 to 659. [2019-10-22 08:57:44,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 659 states. [2019-10-22 08:57:44,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 880 transitions. [2019-10-22 08:57:44,564 INFO L78 Accepts]: Start accepts. Automaton has 659 states and 880 transitions. Word has length 72 [2019-10-22 08:57:44,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:44,564 INFO L462 AbstractCegarLoop]: Abstraction has 659 states and 880 transitions. [2019-10-22 08:57:44,564 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:57:44,564 INFO L276 IsEmpty]: Start isEmpty. Operand 659 states and 880 transitions. [2019-10-22 08:57:44,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-10-22 08:57:44,565 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:44,565 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:44,566 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:44,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:44,566 INFO L82 PathProgramCache]: Analyzing trace with hash 449594347, now seen corresponding path program 1 times [2019-10-22 08:57:44,566 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:44,566 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930803137] [2019-10-22 08:57:44,567 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:44,567 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:44,567 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:44,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:44,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:44,636 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930803137] [2019-10-22 08:57:44,636 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:44,636 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 08:57:44,636 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826038710] [2019-10-22 08:57:44,637 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 08:57:44,637 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:44,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 08:57:44,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 08:57:44,638 INFO L87 Difference]: Start difference. First operand 659 states and 880 transitions. Second operand 4 states. [2019-10-22 08:57:44,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:44,830 INFO L93 Difference]: Finished difference Result 1702 states and 2282 transitions. [2019-10-22 08:57:44,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 08:57:44,831 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-10-22 08:57:44,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:44,835 INFO L225 Difference]: With dead ends: 1702 [2019-10-22 08:57:44,836 INFO L226 Difference]: Without dead ends: 1296 [2019-10-22 08:57:44,837 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:44,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1296 states. [2019-10-22 08:57:44,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1296 to 893. [2019-10-22 08:57:44,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 893 states. [2019-10-22 08:57:44,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 893 states to 893 states and 1191 transitions. [2019-10-22 08:57:44,922 INFO L78 Accepts]: Start accepts. Automaton has 893 states and 1191 transitions. Word has length 73 [2019-10-22 08:57:44,922 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:44,922 INFO L462 AbstractCegarLoop]: Abstraction has 893 states and 1191 transitions. [2019-10-22 08:57:44,923 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 08:57:44,923 INFO L276 IsEmpty]: Start isEmpty. Operand 893 states and 1191 transitions. [2019-10-22 08:57:44,924 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-10-22 08:57:44,924 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:44,924 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:44,925 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:44,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:44,925 INFO L82 PathProgramCache]: Analyzing trace with hash 1828954211, now seen corresponding path program 1 times [2019-10-22 08:57:44,925 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:44,925 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303357611] [2019-10-22 08:57:44,925 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:44,925 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:44,926 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:44,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:44,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:44,979 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303357611] [2019-10-22 08:57:44,980 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:44,980 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:57:44,980 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1043199679] [2019-10-22 08:57:44,980 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:57:44,980 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:44,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:57:44,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:44,981 INFO L87 Difference]: Start difference. First operand 893 states and 1191 transitions. Second operand 3 states. [2019-10-22 08:57:45,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:45,148 INFO L93 Difference]: Finished difference Result 1870 states and 2511 transitions. [2019-10-22 08:57:45,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:57:45,149 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-10-22 08:57:45,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:45,153 INFO L225 Difference]: With dead ends: 1870 [2019-10-22 08:57:45,153 INFO L226 Difference]: Without dead ends: 1281 [2019-10-22 08:57:45,154 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:45,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1281 states. [2019-10-22 08:57:45,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1281 to 849. [2019-10-22 08:57:45,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 849 states. [2019-10-22 08:57:45,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 849 states to 849 states and 1127 transitions. [2019-10-22 08:57:45,243 INFO L78 Accepts]: Start accepts. Automaton has 849 states and 1127 transitions. Word has length 73 [2019-10-22 08:57:45,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:45,243 INFO L462 AbstractCegarLoop]: Abstraction has 849 states and 1127 transitions. [2019-10-22 08:57:45,243 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:57:45,243 INFO L276 IsEmpty]: Start isEmpty. Operand 849 states and 1127 transitions. [2019-10-22 08:57:45,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-10-22 08:57:45,244 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:45,245 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:45,245 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:45,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:45,245 INFO L82 PathProgramCache]: Analyzing trace with hash 1948644571, now seen corresponding path program 1 times [2019-10-22 08:57:45,246 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:45,246 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243586559] [2019-10-22 08:57:45,246 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:45,246 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:45,246 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:45,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:45,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:45,312 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243586559] [2019-10-22 08:57:45,312 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:45,312 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 08:57:45,312 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764795227] [2019-10-22 08:57:45,313 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 08:57:45,313 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:45,313 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 08:57:45,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 08:57:45,313 INFO L87 Difference]: Start difference. First operand 849 states and 1127 transitions. Second operand 4 states. [2019-10-22 08:57:45,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:45,555 INFO L93 Difference]: Finished difference Result 1986 states and 2630 transitions. [2019-10-22 08:57:45,557 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 08:57:45,557 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-10-22 08:57:45,558 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:45,562 INFO L225 Difference]: With dead ends: 1986 [2019-10-22 08:57:45,562 INFO L226 Difference]: Without dead ends: 1426 [2019-10-22 08:57:45,563 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:45,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1426 states. [2019-10-22 08:57:45,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1426 to 1131. [2019-10-22 08:57:45,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1131 states. [2019-10-22 08:57:45,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1131 states to 1131 states and 1491 transitions. [2019-10-22 08:57:45,687 INFO L78 Accepts]: Start accepts. Automaton has 1131 states and 1491 transitions. Word has length 73 [2019-10-22 08:57:45,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:45,687 INFO L462 AbstractCegarLoop]: Abstraction has 1131 states and 1491 transitions. [2019-10-22 08:57:45,687 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 08:57:45,687 INFO L276 IsEmpty]: Start isEmpty. Operand 1131 states and 1491 transitions. [2019-10-22 08:57:45,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-10-22 08:57:45,688 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:45,688 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:45,689 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:45,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:45,693 INFO L82 PathProgramCache]: Analyzing trace with hash 1795806066, now seen corresponding path program 1 times [2019-10-22 08:57:45,694 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:45,694 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408639368] [2019-10-22 08:57:45,694 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:45,694 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:45,694 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:45,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:45,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:45,727 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408639368] [2019-10-22 08:57:45,727 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:45,727 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:57:45,727 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [247500730] [2019-10-22 08:57:45,728 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:57:45,728 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:45,728 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:57:45,728 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:45,728 INFO L87 Difference]: Start difference. First operand 1131 states and 1491 transitions. Second operand 3 states. [2019-10-22 08:57:46,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:46,029 INFO L93 Difference]: Finished difference Result 2794 states and 3673 transitions. [2019-10-22 08:57:46,029 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:57:46,030 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-10-22 08:57:46,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:46,036 INFO L225 Difference]: With dead ends: 2794 [2019-10-22 08:57:46,036 INFO L226 Difference]: Without dead ends: 1896 [2019-10-22 08:57:46,037 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:57:46,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1896 states. [2019-10-22 08:57:46,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1896 to 1133. [2019-10-22 08:57:46,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1133 states. [2019-10-22 08:57:46,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1133 states to 1133 states and 1493 transitions. [2019-10-22 08:57:46,159 INFO L78 Accepts]: Start accepts. Automaton has 1133 states and 1493 transitions. Word has length 74 [2019-10-22 08:57:46,159 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:46,159 INFO L462 AbstractCegarLoop]: Abstraction has 1133 states and 1493 transitions. [2019-10-22 08:57:46,159 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:57:46,160 INFO L276 IsEmpty]: Start isEmpty. Operand 1133 states and 1493 transitions. [2019-10-22 08:57:46,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-10-22 08:57:46,161 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:46,161 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:46,162 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:46,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:46,162 INFO L82 PathProgramCache]: Analyzing trace with hash 230569326, now seen corresponding path program 1 times [2019-10-22 08:57:46,162 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:46,162 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506602271] [2019-10-22 08:57:46,163 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:46,163 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:46,163 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:46,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:46,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:46,241 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [506602271] [2019-10-22 08:57:46,241 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:46,241 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 08:57:46,241 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [206691153] [2019-10-22 08:57:46,242 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 08:57:46,242 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:46,242 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 08:57:46,242 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 08:57:46,243 INFO L87 Difference]: Start difference. First operand 1133 states and 1493 transitions. Second operand 4 states. [2019-10-22 08:57:46,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:46,427 INFO L93 Difference]: Finished difference Result 2365 states and 3103 transitions. [2019-10-22 08:57:46,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 08:57:46,428 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-10-22 08:57:46,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:46,432 INFO L225 Difference]: With dead ends: 2365 [2019-10-22 08:57:46,432 INFO L226 Difference]: Without dead ends: 1287 [2019-10-22 08:57:46,434 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:46,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1287 states. [2019-10-22 08:57:46,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1287 to 946. [2019-10-22 08:57:46,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 946 states. [2019-10-22 08:57:46,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 946 states to 946 states and 1237 transitions. [2019-10-22 08:57:46,542 INFO L78 Accepts]: Start accepts. Automaton has 946 states and 1237 transitions. Word has length 75 [2019-10-22 08:57:46,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:46,542 INFO L462 AbstractCegarLoop]: Abstraction has 946 states and 1237 transitions. [2019-10-22 08:57:46,542 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 08:57:46,542 INFO L276 IsEmpty]: Start isEmpty. Operand 946 states and 1237 transitions. [2019-10-22 08:57:46,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-10-22 08:57:46,543 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:46,543 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:46,544 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:46,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:46,544 INFO L82 PathProgramCache]: Analyzing trace with hash -818028433, now seen corresponding path program 1 times [2019-10-22 08:57:46,544 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:46,544 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91588406] [2019-10-22 08:57:46,544 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:46,544 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:46,545 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:46,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:46,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:46,610 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91588406] [2019-10-22 08:57:46,610 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:46,611 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 08:57:46,611 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184127889] [2019-10-22 08:57:46,611 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 08:57:46,612 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:46,612 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 08:57:46,612 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 08:57:46,612 INFO L87 Difference]: Start difference. First operand 946 states and 1237 transitions. Second operand 4 states. [2019-10-22 08:57:46,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:46,770 INFO L93 Difference]: Finished difference Result 2178 states and 2855 transitions. [2019-10-22 08:57:46,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 08:57:46,770 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 76 [2019-10-22 08:57:46,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:46,774 INFO L225 Difference]: With dead ends: 2178 [2019-10-22 08:57:46,774 INFO L226 Difference]: Without dead ends: 1307 [2019-10-22 08:57:46,776 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:46,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1307 states. [2019-10-22 08:57:46,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1307 to 892. [2019-10-22 08:57:46,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-10-22 08:57:46,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1159 transitions. [2019-10-22 08:57:46,874 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1159 transitions. Word has length 76 [2019-10-22 08:57:46,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:46,875 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1159 transitions. [2019-10-22 08:57:46,875 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 08:57:46,875 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1159 transitions. [2019-10-22 08:57:46,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2019-10-22 08:57:46,877 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:46,877 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:46,877 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:46,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:46,878 INFO L82 PathProgramCache]: Analyzing trace with hash 1542213080, now seen corresponding path program 1 times [2019-10-22 08:57:46,878 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:46,878 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076714615] [2019-10-22 08:57:46,878 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:46,878 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:46,878 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:46,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:47,191 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:47,192 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076714615] [2019-10-22 08:57:47,192 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [273051610] [2019-10-22 08:57:47,192 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:57:47,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:47,378 INFO L256 TraceCheckSpWp]: Trace formula consists of 724 conjuncts, 9 conjunts are in the unsatisfiable core [2019-10-22 08:57:47,390 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 08:57:47,471 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-10-22 08:57:47,471 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-22 08:57:47,471 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-10-22 08:57:47,472 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627920048] [2019-10-22 08:57:47,472 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 08:57:47,472 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:47,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 08:57:47,473 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-10-22 08:57:47,473 INFO L87 Difference]: Start difference. First operand 892 states and 1159 transitions. Second operand 6 states. [2019-10-22 08:57:47,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:47,803 INFO L93 Difference]: Finished difference Result 2720 states and 3672 transitions. [2019-10-22 08:57:47,804 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-10-22 08:57:47,804 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2019-10-22 08:57:47,804 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:47,809 INFO L225 Difference]: With dead ends: 2720 [2019-10-22 08:57:47,814 INFO L226 Difference]: Without dead ends: 1969 [2019-10-22 08:57:47,815 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 117 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-10-22 08:57:47,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1969 states. [2019-10-22 08:57:47,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1969 to 892. [2019-10-22 08:57:47,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-10-22 08:57:47,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1156 transitions. [2019-10-22 08:57:47,924 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1156 transitions. Word has length 120 [2019-10-22 08:57:47,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:47,925 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1156 transitions. [2019-10-22 08:57:47,925 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 08:57:47,925 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1156 transitions. [2019-10-22 08:57:47,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2019-10-22 08:57:47,926 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:47,927 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:48,127 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:57:48,128 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:48,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:48,128 INFO L82 PathProgramCache]: Analyzing trace with hash -1832197229, now seen corresponding path program 1 times [2019-10-22 08:57:48,129 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:48,129 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219812543] [2019-10-22 08:57:48,129 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:48,129 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:48,129 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:48,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:48,377 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:48,378 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [219812543] [2019-10-22 08:57:48,378 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1012420850] [2019-10-22 08:57:48,378 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:57:48,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:48,509 INFO L256 TraceCheckSpWp]: Trace formula consists of 737 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-22 08:57:48,512 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 08:57:48,627 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-10-22 08:57:48,627 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-22 08:57:48,627 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-10-22 08:57:48,627 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1751541495] [2019-10-22 08:57:48,628 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 08:57:48,628 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:48,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 08:57:48,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-10-22 08:57:48,628 INFO L87 Difference]: Start difference. First operand 892 states and 1156 transitions. Second operand 6 states. [2019-10-22 08:57:48,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:48,977 INFO L93 Difference]: Finished difference Result 2447 states and 3267 transitions. [2019-10-22 08:57:48,978 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-10-22 08:57:48,978 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 124 [2019-10-22 08:57:48,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:48,982 INFO L225 Difference]: With dead ends: 2447 [2019-10-22 08:57:48,986 INFO L226 Difference]: Without dead ends: 1696 [2019-10-22 08:57:48,988 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 140 GetRequests, 121 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-10-22 08:57:48,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1696 states. [2019-10-22 08:57:49,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1696 to 892. [2019-10-22 08:57:49,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-10-22 08:57:49,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1153 transitions. [2019-10-22 08:57:49,078 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1153 transitions. Word has length 124 [2019-10-22 08:57:49,078 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:49,078 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1153 transitions. [2019-10-22 08:57:49,078 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 08:57:49,079 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1153 transitions. [2019-10-22 08:57:49,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-10-22 08:57:49,082 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:49,082 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:49,282 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:57:49,283 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:49,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:49,285 INFO L82 PathProgramCache]: Analyzing trace with hash 1668386931, now seen corresponding path program 1 times [2019-10-22 08:57:49,285 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:49,285 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585136256] [2019-10-22 08:57:49,285 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:49,285 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:49,285 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:49,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:49,567 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:49,567 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585136256] [2019-10-22 08:57:49,567 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [639782723] [2019-10-22 08:57:49,568 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:57:49,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:49,713 INFO L256 TraceCheckSpWp]: Trace formula consists of 749 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-22 08:57:49,717 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 08:57:49,792 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-10-22 08:57:49,792 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-22 08:57:49,792 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-10-22 08:57:49,792 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1622551100] [2019-10-22 08:57:49,793 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 08:57:49,793 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:49,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 08:57:49,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-10-22 08:57:49,793 INFO L87 Difference]: Start difference. First operand 892 states and 1153 transitions. Second operand 6 states. [2019-10-22 08:57:50,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:50,233 INFO L93 Difference]: Finished difference Result 2811 states and 3778 transitions. [2019-10-22 08:57:50,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-10-22 08:57:50,233 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 127 [2019-10-22 08:57:50,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:50,238 INFO L225 Difference]: With dead ends: 2811 [2019-10-22 08:57:50,242 INFO L226 Difference]: Without dead ends: 2047 [2019-10-22 08:57:50,244 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2019-10-22 08:57:50,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states. [2019-10-22 08:57:50,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 840. [2019-10-22 08:57:50,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2019-10-22 08:57:50,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1075 transitions. [2019-10-22 08:57:50,338 INFO L78 Accepts]: Start accepts. Automaton has 840 states and 1075 transitions. Word has length 127 [2019-10-22 08:57:50,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:50,338 INFO L462 AbstractCegarLoop]: Abstraction has 840 states and 1075 transitions. [2019-10-22 08:57:50,338 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 08:57:50,338 INFO L276 IsEmpty]: Start isEmpty. Operand 840 states and 1075 transitions. [2019-10-22 08:57:50,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2019-10-22 08:57:50,341 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:50,342 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:50,542 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:57:50,542 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:50,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:50,543 INFO L82 PathProgramCache]: Analyzing trace with hash -1807241978, now seen corresponding path program 1 times [2019-10-22 08:57:50,543 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:50,543 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883581184] [2019-10-22 08:57:50,543 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:50,544 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:50,544 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:50,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:50,730 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:50,730 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883581184] [2019-10-22 08:57:50,731 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [12851648] [2019-10-22 08:57:50,731 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:57:50,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:50,859 INFO L256 TraceCheckSpWp]: Trace formula consists of 750 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-22 08:57:50,862 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 08:57:50,952 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-10-22 08:57:50,953 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-22 08:57:50,953 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [10] total 15 [2019-10-22 08:57:50,954 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231993437] [2019-10-22 08:57:50,954 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 08:57:50,954 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:50,955 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 08:57:50,955 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=181, Unknown=0, NotChecked=0, Total=210 [2019-10-22 08:57:50,955 INFO L87 Difference]: Start difference. First operand 840 states and 1075 transitions. Second operand 6 states. [2019-10-22 08:57:51,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:51,264 INFO L93 Difference]: Finished difference Result 2163 states and 2880 transitions. [2019-10-22 08:57:51,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-10-22 08:57:51,264 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 128 [2019-10-22 08:57:51,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:51,268 INFO L225 Difference]: With dead ends: 2163 [2019-10-22 08:57:51,272 INFO L226 Difference]: Without dead ends: 1478 [2019-10-22 08:57:51,273 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 142 GetRequests, 125 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=48, Invalid=294, Unknown=0, NotChecked=0, Total=342 [2019-10-22 08:57:51,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1478 states. [2019-10-22 08:57:51,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1478 to 840. [2019-10-22 08:57:51,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2019-10-22 08:57:51,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1074 transitions. [2019-10-22 08:57:51,388 INFO L78 Accepts]: Start accepts. Automaton has 840 states and 1074 transitions. Word has length 128 [2019-10-22 08:57:51,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:51,388 INFO L462 AbstractCegarLoop]: Abstraction has 840 states and 1074 transitions. [2019-10-22 08:57:51,389 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 08:57:51,389 INFO L276 IsEmpty]: Start isEmpty. Operand 840 states and 1074 transitions. [2019-10-22 08:57:51,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-10-22 08:57:51,391 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:51,391 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:51,592 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:57:51,592 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:51,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:51,593 INFO L82 PathProgramCache]: Analyzing trace with hash 237584641, now seen corresponding path program 1 times [2019-10-22 08:57:51,593 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:51,593 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940227304] [2019-10-22 08:57:51,593 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:51,594 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:51,594 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:51,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:51,837 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:51,838 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940227304] [2019-10-22 08:57:51,838 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2135635263] [2019-10-22 08:57:51,838 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:57:52,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:52,062 INFO L256 TraceCheckSpWp]: Trace formula consists of 764 conjuncts, 45 conjunts are in the unsatisfiable core [2019-10-22 08:57:52,065 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 08:57:52,320 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:52,320 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-10-22 08:57:52,321 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12] total 17 [2019-10-22 08:57:52,321 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597360793] [2019-10-22 08:57:52,322 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-22 08:57:52,322 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:52,322 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-22 08:57:52,322 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=251, Unknown=0, NotChecked=0, Total=306 [2019-10-22 08:57:52,322 INFO L87 Difference]: Start difference. First operand 840 states and 1074 transitions. Second operand 18 states. [2019-10-22 08:57:55,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:55,262 INFO L93 Difference]: Finished difference Result 3439 states and 4527 transitions. [2019-10-22 08:57:55,262 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2019-10-22 08:57:55,263 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 132 [2019-10-22 08:57:55,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:55,268 INFO L225 Difference]: With dead ends: 3439 [2019-10-22 08:57:55,268 INFO L226 Difference]: Without dead ends: 2760 [2019-10-22 08:57:55,270 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 199 GetRequests, 119 SyntacticMatches, 4 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1942 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1261, Invalid=4745, Unknown=0, NotChecked=0, Total=6006 [2019-10-22 08:57:55,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2760 states. [2019-10-22 08:57:55,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2760 to 1325. [2019-10-22 08:57:55,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1325 states. [2019-10-22 08:57:55,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1325 states to 1325 states and 1715 transitions. [2019-10-22 08:57:55,456 INFO L78 Accepts]: Start accepts. Automaton has 1325 states and 1715 transitions. Word has length 132 [2019-10-22 08:57:55,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:55,457 INFO L462 AbstractCegarLoop]: Abstraction has 1325 states and 1715 transitions. [2019-10-22 08:57:55,457 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-22 08:57:55,457 INFO L276 IsEmpty]: Start isEmpty. Operand 1325 states and 1715 transitions. [2019-10-22 08:57:55,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-10-22 08:57:55,460 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:55,460 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:55,667 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:57:55,668 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:55,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:55,668 INFO L82 PathProgramCache]: Analyzing trace with hash -700555044, now seen corresponding path program 1 times [2019-10-22 08:57:55,668 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:55,668 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2062949832] [2019-10-22 08:57:55,668 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:55,669 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:55,669 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:55,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:55,734 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-10-22 08:57:55,735 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2062949832] [2019-10-22 08:57:55,735 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:55,735 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 08:57:55,735 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1266100139] [2019-10-22 08:57:55,736 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 08:57:55,736 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:55,736 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 08:57:55,736 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 08:57:55,736 INFO L87 Difference]: Start difference. First operand 1325 states and 1715 transitions. Second operand 4 states. [2019-10-22 08:57:56,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:56,141 INFO L93 Difference]: Finished difference Result 3265 states and 4250 transitions. [2019-10-22 08:57:56,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 08:57:56,141 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 133 [2019-10-22 08:57:56,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:56,145 INFO L225 Difference]: With dead ends: 3265 [2019-10-22 08:57:56,145 INFO L226 Difference]: Without dead ends: 2068 [2019-10-22 08:57:56,148 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:56,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2068 states. [2019-10-22 08:57:56,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2068 to 1385. [2019-10-22 08:57:56,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1385 states. [2019-10-22 08:57:56,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1385 states to 1385 states and 1769 transitions. [2019-10-22 08:57:56,343 INFO L78 Accepts]: Start accepts. Automaton has 1385 states and 1769 transitions. Word has length 133 [2019-10-22 08:57:56,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:56,344 INFO L462 AbstractCegarLoop]: Abstraction has 1385 states and 1769 transitions. [2019-10-22 08:57:56,344 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 08:57:56,344 INFO L276 IsEmpty]: Start isEmpty. Operand 1385 states and 1769 transitions. [2019-10-22 08:57:56,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-10-22 08:57:56,347 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:56,347 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:56,347 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:56,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:56,348 INFO L82 PathProgramCache]: Analyzing trace with hash -709461544, now seen corresponding path program 1 times [2019-10-22 08:57:56,348 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:56,348 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971272616] [2019-10-22 08:57:56,348 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:56,348 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:56,348 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:56,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:56,454 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-10-22 08:57:56,455 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [971272616] [2019-10-22 08:57:56,455 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:56,455 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 08:57:56,455 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140864213] [2019-10-22 08:57:56,455 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 08:57:56,456 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:56,456 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:57:56,456 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:56,456 INFO L87 Difference]: Start difference. First operand 1385 states and 1769 transitions. Second operand 5 states. [2019-10-22 08:57:56,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:56,736 INFO L93 Difference]: Finished difference Result 2514 states and 3258 transitions. [2019-10-22 08:57:56,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 08:57:56,737 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 133 [2019-10-22 08:57:56,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:56,740 INFO L225 Difference]: With dead ends: 2514 [2019-10-22 08:57:56,740 INFO L226 Difference]: Without dead ends: 1257 [2019-10-22 08:57:56,742 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:57:56,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1257 states. [2019-10-22 08:57:56,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1257 to 1257. [2019-10-22 08:57:56,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1257 states. [2019-10-22 08:57:56,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1257 states to 1257 states and 1621 transitions. [2019-10-22 08:57:56,927 INFO L78 Accepts]: Start accepts. Automaton has 1257 states and 1621 transitions. Word has length 133 [2019-10-22 08:57:56,927 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:56,927 INFO L462 AbstractCegarLoop]: Abstraction has 1257 states and 1621 transitions. [2019-10-22 08:57:56,927 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 08:57:56,927 INFO L276 IsEmpty]: Start isEmpty. Operand 1257 states and 1621 transitions. [2019-10-22 08:57:56,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-10-22 08:57:56,929 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:56,930 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:56,930 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:56,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:56,930 INFO L82 PathProgramCache]: Analyzing trace with hash 77500617, now seen corresponding path program 1 times [2019-10-22 08:57:56,930 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:56,930 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442387882] [2019-10-22 08:57:56,931 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:56,931 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:56,931 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:56,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:57,017 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2019-10-22 08:57:57,017 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442387882] [2019-10-22 08:57:57,017 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:57:57,017 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 08:57:57,017 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1391541264] [2019-10-22 08:57:57,018 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 08:57:57,018 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:57,018 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 08:57:57,018 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 08:57:57,018 INFO L87 Difference]: Start difference. First operand 1257 states and 1621 transitions. Second operand 6 states. [2019-10-22 08:57:57,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:57,962 INFO L93 Difference]: Finished difference Result 6586 states and 8686 transitions. [2019-10-22 08:57:57,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-10-22 08:57:57,963 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 134 [2019-10-22 08:57:57,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:57,972 INFO L225 Difference]: With dead ends: 6586 [2019-10-22 08:57:57,972 INFO L226 Difference]: Without dead ends: 5510 [2019-10-22 08:57:57,975 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2019-10-22 08:57:57,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5510 states. [2019-10-22 08:57:58,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5510 to 1599. [2019-10-22 08:57:58,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1599 states. [2019-10-22 08:57:58,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1599 states to 1599 states and 2021 transitions. [2019-10-22 08:57:58,221 INFO L78 Accepts]: Start accepts. Automaton has 1599 states and 2021 transitions. Word has length 134 [2019-10-22 08:57:58,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:58,221 INFO L462 AbstractCegarLoop]: Abstraction has 1599 states and 2021 transitions. [2019-10-22 08:57:58,222 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 08:57:58,222 INFO L276 IsEmpty]: Start isEmpty. Operand 1599 states and 2021 transitions. [2019-10-22 08:57:58,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-22 08:57:58,225 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:58,225 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:57:58,225 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:57:58,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:57:58,225 INFO L82 PathProgramCache]: Analyzing trace with hash -825335127, now seen corresponding path program 1 times [2019-10-22 08:57:58,226 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:57:58,226 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367235444] [2019-10-22 08:57:58,226 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:58,226 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:57:58,226 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:57:58,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:58,500 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:57:58,500 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1367235444] [2019-10-22 08:57:58,500 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [564773942] [2019-10-22 08:57:58,501 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:57:58,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:57:58,671 INFO L256 TraceCheckSpWp]: Trace formula consists of 776 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-22 08:57:58,674 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 08:57:58,757 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-10-22 08:57:58,757 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-22 08:57:58,757 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-10-22 08:57:58,757 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537131395] [2019-10-22 08:57:58,758 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 08:57:58,758 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:57:58,759 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 08:57:58,759 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-10-22 08:57:58,759 INFO L87 Difference]: Start difference. First operand 1599 states and 2021 transitions. Second operand 6 states. [2019-10-22 08:57:59,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:57:59,511 INFO L93 Difference]: Finished difference Result 4910 states and 6326 transitions. [2019-10-22 08:57:59,511 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-10-22 08:57:59,511 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2019-10-22 08:57:59,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:57:59,524 INFO L225 Difference]: With dead ends: 4910 [2019-10-22 08:57:59,525 INFO L226 Difference]: Without dead ends: 3472 [2019-10-22 08:57:59,527 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 132 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-10-22 08:57:59,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3472 states. [2019-10-22 08:57:59,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3472 to 1599. [2019-10-22 08:57:59,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1599 states. [2019-10-22 08:57:59,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1599 states to 1599 states and 2019 transitions. [2019-10-22 08:57:59,834 INFO L78 Accepts]: Start accepts. Automaton has 1599 states and 2019 transitions. Word has length 135 [2019-10-22 08:57:59,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:57:59,834 INFO L462 AbstractCegarLoop]: Abstraction has 1599 states and 2019 transitions. [2019-10-22 08:57:59,834 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 08:57:59,834 INFO L276 IsEmpty]: Start isEmpty. Operand 1599 states and 2019 transitions. [2019-10-22 08:57:59,836 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-22 08:57:59,836 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:57:59,837 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:58:00,037 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:58:00,037 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:58:00,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:58:00,038 INFO L82 PathProgramCache]: Analyzing trace with hash -1957396857, now seen corresponding path program 1 times [2019-10-22 08:58:00,038 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:58:00,038 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154861119] [2019-10-22 08:58:00,038 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:58:00,038 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:58:00,038 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:58:00,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:58:00,291 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:58:00,291 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [154861119] [2019-10-22 08:58:00,292 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1421592233] [2019-10-22 08:58:00,292 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:58:00,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:58:00,456 INFO L256 TraceCheckSpWp]: Trace formula consists of 766 conjuncts, 46 conjunts are in the unsatisfiable core [2019-10-22 08:58:00,458 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 08:58:00,751 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:58:00,752 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-10-22 08:58:00,752 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-10-22 08:58:00,752 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [751903988] [2019-10-22 08:58:00,752 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-10-22 08:58:00,752 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:58:00,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-10-22 08:58:00,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2019-10-22 08:58:00,753 INFO L87 Difference]: Start difference. First operand 1599 states and 2019 transitions. Second operand 21 states. [2019-10-22 08:58:02,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:58:02,676 INFO L93 Difference]: Finished difference Result 4391 states and 5566 transitions. [2019-10-22 08:58:02,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-22 08:58:02,677 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 135 [2019-10-22 08:58:02,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:58:02,683 INFO L225 Difference]: With dead ends: 4391 [2019-10-22 08:58:02,683 INFO L226 Difference]: Without dead ends: 2973 [2019-10-22 08:58:02,687 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 185 GetRequests, 121 SyntacticMatches, 4 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 997 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=649, Invalid=3133, Unknown=0, NotChecked=0, Total=3782 [2019-10-22 08:58:02,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2973 states. [2019-10-22 08:58:03,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2973 to 1819. [2019-10-22 08:58:03,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1819 states. [2019-10-22 08:58:03,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1819 states to 1819 states and 2290 transitions. [2019-10-22 08:58:03,035 INFO L78 Accepts]: Start accepts. Automaton has 1819 states and 2290 transitions. Word has length 135 [2019-10-22 08:58:03,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:58:03,035 INFO L462 AbstractCegarLoop]: Abstraction has 1819 states and 2290 transitions. [2019-10-22 08:58:03,035 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-10-22 08:58:03,035 INFO L276 IsEmpty]: Start isEmpty. Operand 1819 states and 2290 transitions. [2019-10-22 08:58:03,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-22 08:58:03,037 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:58:03,037 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:58:03,239 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 08:58:03,239 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:58:03,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:58:03,239 INFO L82 PathProgramCache]: Analyzing trace with hash 470861765, now seen corresponding path program 1 times [2019-10-22 08:58:03,240 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:58:03,240 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114471046] [2019-10-22 08:58:03,240 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:58:03,240 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:58:03,240 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:58:03,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:58:03,332 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2019-10-22 08:58:03,333 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [114471046] [2019-10-22 08:58:03,333 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:58:03,333 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 08:58:03,333 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020285246] [2019-10-22 08:58:03,334 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 08:58:03,334 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:58:03,334 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 08:58:03,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-10-22 08:58:03,334 INFO L87 Difference]: Start difference. First operand 1819 states and 2290 transitions. Second operand 4 states. [2019-10-22 08:58:03,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:58:03,599 INFO L93 Difference]: Finished difference Result 3316 states and 4201 transitions. [2019-10-22 08:58:03,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-22 08:58:03,600 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2019-10-22 08:58:03,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:58:03,602 INFO L225 Difference]: With dead ends: 3316 [2019-10-22 08:58:03,603 INFO L226 Difference]: Without dead ends: 1623 [2019-10-22 08:58:03,605 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-10-22 08:58:03,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1623 states. [2019-10-22 08:58:03,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1623 to 1623. [2019-10-22 08:58:03,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1623 states. [2019-10-22 08:58:03,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1623 states to 1623 states and 2029 transitions. [2019-10-22 08:58:03,861 INFO L78 Accepts]: Start accepts. Automaton has 1623 states and 2029 transitions. Word has length 135 [2019-10-22 08:58:03,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:58:03,861 INFO L462 AbstractCegarLoop]: Abstraction has 1623 states and 2029 transitions. [2019-10-22 08:58:03,861 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 08:58:03,862 INFO L276 IsEmpty]: Start isEmpty. Operand 1623 states and 2029 transitions. [2019-10-22 08:58:03,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-10-22 08:58:03,864 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:58:03,864 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:58:03,864 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:58:03,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:58:03,865 INFO L82 PathProgramCache]: Analyzing trace with hash -1467051729, now seen corresponding path program 1 times [2019-10-22 08:58:03,865 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:58:03,865 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433240455] [2019-10-22 08:58:03,865 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:58:03,865 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:58:03,865 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:58:03,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:58:03,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:58:04,070 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:58:04,070 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-10-22 08:58:04,278 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.10 08:58:04 BoogieIcfgContainer [2019-10-22 08:58:04,280 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-10-22 08:58:04,280 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-10-22 08:58:04,280 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-10-22 08:58:04,280 INFO L275 PluginConnector]: Witness Printer initialized [2019-10-22 08:58:04,281 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:57:37" (3/4) ... [2019-10-22 08:58:04,283 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-10-22 08:58:04,473 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_f62e9d0b-ad93-4cba-8442-bb08a1680cf8/bin/uautomizer/witness.graphml [2019-10-22 08:58:04,476 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-10-22 08:58:04,478 INFO L168 Benchmark]: Toolchain (without parser) took 28648.62 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 799.0 MB). Free memory was 941.7 MB in the beginning and 1.3 GB in the end (delta: -334.5 MB). Peak memory consumption was 464.5 MB. Max. memory is 11.5 GB. [2019-10-22 08:58:04,478 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 966.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-10-22 08:58:04,478 INFO L168 Benchmark]: CACSL2BoogieTranslator took 551.32 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 119.0 MB). Free memory was 940.4 MB in the beginning and 1.1 GB in the end (delta: -162.8 MB). Peak memory consumption was 20.4 MB. Max. memory is 11.5 GB. [2019-10-22 08:58:04,479 INFO L168 Benchmark]: Boogie Procedure Inliner took 96.11 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.5 MB). Peak memory consumption was 5.5 MB. Max. memory is 11.5 GB. [2019-10-22 08:58:04,479 INFO L168 Benchmark]: Boogie Preprocessor took 50.32 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.7 MB). Peak memory consumption was 3.7 MB. Max. memory is 11.5 GB. [2019-10-22 08:58:04,480 INFO L168 Benchmark]: RCFGBuilder took 1076.86 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 91.5 MB). Peak memory consumption was 91.5 MB. Max. memory is 11.5 GB. [2019-10-22 08:58:04,480 INFO L168 Benchmark]: TraceAbstraction took 26673.33 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 680.0 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -320.9 MB). Peak memory consumption was 359.1 MB. Max. memory is 11.5 GB. [2019-10-22 08:58:04,480 INFO L168 Benchmark]: Witness Printer took 196.13 ms. Allocated memory is still 1.8 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 47.1 MB). Peak memory consumption was 47.1 MB. Max. memory is 11.5 GB. [2019-10-22 08:58:04,481 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 966.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 551.32 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 119.0 MB). Free memory was 940.4 MB in the beginning and 1.1 GB in the end (delta: -162.8 MB). Peak memory consumption was 20.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 96.11 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.5 MB). Peak memory consumption was 5.5 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 50.32 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.7 MB). Peak memory consumption was 3.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1076.86 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 91.5 MB). Peak memory consumption was 91.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 26673.33 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 680.0 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -320.9 MB). Peak memory consumption was 359.1 MB. Max. memory is 11.5 GB. * Witness Printer took 196.13 ms. Allocated memory is still 1.8 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 47.1 MB). Peak memory consumption was 47.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 654]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L455] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L577] int c1 ; [L578] int i2 ; [L581] c1 = 0 [L582] side1Failed = __VERIFIER_nondet_bool() [L583] side2Failed = __VERIFIER_nondet_bool() [L584] side1_written = __VERIFIER_nondet_char() [L585] side2_written = __VERIFIER_nondet_char() [L586] side1Failed_History_0 = __VERIFIER_nondet_bool() [L587] side1Failed_History_1 = __VERIFIER_nondet_bool() [L588] side1Failed_History_2 = __VERIFIER_nondet_bool() [L589] side2Failed_History_0 = __VERIFIER_nondet_bool() [L590] side2Failed_History_1 = __VERIFIER_nondet_bool() [L591] side2Failed_History_2 = __VERIFIER_nondet_bool() [L592] active_side_History_0 = __VERIFIER_nondet_char() [L593] active_side_History_1 = __VERIFIER_nondet_char() [L594] active_side_History_2 = __VERIFIER_nondet_char() [L595] manual_selection_History_0 = __VERIFIER_nondet_char() [L596] manual_selection_History_1 = __VERIFIER_nondet_char() [L597] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L598] i2 = init() [L600] cs1_old = nomsg [L601] cs1_new = nomsg [L602] cs2_old = nomsg [L603] cs2_new = nomsg [L604] s1s2_old = nomsg [L605] s1s2_new = nomsg [L606] s1s1_old = nomsg [L607] s1s1_new = nomsg [L608] s2s1_old = nomsg [L609] s2s1_new = nomsg [L610] s2s2_old = nomsg [L611] s2s2_new = nomsg [L612] s1p_old = nomsg [L613] s1p_new = nomsg [L614] s2p_old = nomsg [L615] s2p_new = nomsg [L616] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L485] COND TRUE ! side2Failed [L486] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] tmp___1 = read_side1_failed_history((unsigned char)1) [L494] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L495] tmp___2 = read_side1_failed_history((unsigned char)0) [L496] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] tmp___11 = read_side1_failed_history((unsigned char)1) [L538] COND TRUE ! tmp___11 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L539] tmp___12 = read_side2_failed_history((unsigned char)1) [L540] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L553] tmp___20 = read_active_side_history((unsigned char)2) [L554] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L572] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L652] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L641] i2 ++ VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-128, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-128, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND FALSE !(\read(side1Failed)) [L326] side1 = s1s1_old [L327] s1s1_old = nomsg [L328] side2 = s2s1_old [L329] s2s1_old = nomsg [L330] manual_selection = cs1_old [L331] cs1_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L332] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L335] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L336] COND TRUE (int )side2 != (int )nomsg [L337] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] EXPR next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] s1s1_new = next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new [L357] EXPR next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L357] s1s2_new = next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new [L358] EXPR next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L358] s1p_new = next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new [L359] side1_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND TRUE \read(side2Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] EXPR nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] s2s1_new = nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new [L378] EXPR nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L378] s2s2_new = nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new [L379] EXPR nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L379] s2p_new = nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new [L380] side2_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND TRUE ! side1Failed [L483] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND FALSE !(! tmp___0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND TRUE \read(tmp___7) [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L523] tmp___8 = read_side2_failed_history((unsigned char)1) [L524] COND TRUE ! tmp___8 [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L525] tmp___5 = read_active_side_history((unsigned char)0) [L526] COND TRUE ! ((int )tmp___5 == 2) [L527] return (0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L652] COND TRUE ! arg VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L654] __VERIFIER_error() VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 291 locations, 23 error locations. Result: UNSAFE, OverallTime: 26.5s, OverallIterations: 37, TraceHistogramMax: 2, AutomataDifference: 13.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 15713 SDtfs, 28413 SDslu, 34026 SDs, 0 SdLazy, 5191 SolverSat, 400 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1324 GetRequests, 950 SyntacticMatches, 19 SemanticMatches, 355 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3349 ImplicationChecksByTransitivity, 5.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1819occurred in iteration=35, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 3.5s AutomataMinimizationTime, 36 MinimizatonAttempts, 21934 StatesRemovedByMinimization, 32 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.4s SsaConstructionTime, 1.7s SatisfiabilityAnalysisTime, 4.0s InterpolantComputationTime, 4081 NumberOfCodeBlocks, 4081 NumberOfCodeBlocksAsserted, 44 NumberOfCheckSat, 3902 ConstructedInterpolants, 0 QuantifiedInterpolants, 1566655 SizeOfPredicates, 38 NumberOfNonLiveVariables, 5266 ConjunctsInSsa, 136 ConjunctsInUnsatCore, 43 InterpolantComputations, 34 PerfectInterpolantSequences, 582/673 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...