./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c -s /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 51b120a585d23a491f06d4bb80c2a463453987ac .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-10-22 09:00:17,680 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-22 09:00:17,681 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-22 09:00:17,695 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-22 09:00:17,696 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-22 09:00:17,697 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-22 09:00:17,698 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-22 09:00:17,701 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-22 09:00:17,703 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-22 09:00:17,704 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-22 09:00:17,705 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-22 09:00:17,706 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-22 09:00:17,706 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-22 09:00:17,707 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-22 09:00:17,709 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-22 09:00:17,709 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-22 09:00:17,710 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-22 09:00:17,711 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-22 09:00:17,712 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-22 09:00:17,713 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-22 09:00:17,714 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-22 09:00:17,715 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-22 09:00:17,716 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-22 09:00:17,716 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-22 09:00:17,718 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-22 09:00:17,718 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-22 09:00:17,723 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-22 09:00:17,724 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-22 09:00:17,725 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-22 09:00:17,725 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-22 09:00:17,725 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-22 09:00:17,726 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-22 09:00:17,726 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-22 09:00:17,727 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-22 09:00:17,728 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-22 09:00:17,728 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-22 09:00:17,728 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-22 09:00:17,728 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-22 09:00:17,729 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-22 09:00:17,729 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-22 09:00:17,730 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-22 09:00:17,730 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-22 09:00:17,740 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-22 09:00:17,740 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-22 09:00:17,741 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-22 09:00:17,741 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-22 09:00:17,742 INFO L138 SettingsManager]: * Use SBE=true [2019-10-22 09:00:17,742 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-22 09:00:17,742 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-22 09:00:17,742 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-22 09:00:17,742 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-22 09:00:17,743 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-22 09:00:17,743 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-22 09:00:17,743 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-22 09:00:17,743 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-22 09:00:17,743 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-22 09:00:17,743 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-22 09:00:17,744 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-22 09:00:17,744 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-22 09:00:17,744 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-22 09:00:17,744 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-22 09:00:17,744 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-22 09:00:17,744 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-22 09:00:17,745 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-22 09:00:17,745 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-22 09:00:17,745 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-22 09:00:17,745 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-22 09:00:17,745 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-22 09:00:17,746 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-22 09:00:17,746 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-22 09:00:17,746 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 51b120a585d23a491f06d4bb80c2a463453987ac [2019-10-22 09:00:17,771 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-22 09:00:17,783 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-22 09:00:17,787 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-22 09:00:17,789 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-22 09:00:17,789 INFO L275 PluginConnector]: CDTParser initialized [2019-10-22 09:00:17,790 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2019-10-22 09:00:17,835 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/data/fc280554a/fcb6a8fd6beb4b98abffe071cea327bd/FLAGd72ed2f04 [2019-10-22 09:00:18,260 INFO L306 CDTParser]: Found 1 translation units. [2019-10-22 09:00:18,260 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2019-10-22 09:00:18,268 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/data/fc280554a/fcb6a8fd6beb4b98abffe071cea327bd/FLAGd72ed2f04 [2019-10-22 09:00:18,277 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/data/fc280554a/fcb6a8fd6beb4b98abffe071cea327bd [2019-10-22 09:00:18,280 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-22 09:00:18,282 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-10-22 09:00:18,283 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-22 09:00:18,283 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-22 09:00:18,286 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-22 09:00:18,287 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 09:00:18" (1/1) ... [2019-10-22 09:00:18,289 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3e7d5d03 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18, skipping insertion in model container [2019-10-22 09:00:18,289 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 09:00:18" (1/1) ... [2019-10-22 09:00:18,296 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-22 09:00:18,329 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-22 09:00:18,608 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 09:00:18,619 INFO L188 MainTranslator]: Completed pre-run [2019-10-22 09:00:18,674 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 09:00:18,690 INFO L192 MainTranslator]: Completed translation [2019-10-22 09:00:18,690 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18 WrapperNode [2019-10-22 09:00:18,690 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-22 09:00:18,691 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-10-22 09:00:18,691 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-10-22 09:00:18,691 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-10-22 09:00:18,697 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18" (1/1) ... [2019-10-22 09:00:18,707 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18" (1/1) ... [2019-10-22 09:00:18,751 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-10-22 09:00:18,752 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-22 09:00:18,752 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-22 09:00:18,752 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-22 09:00:18,761 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18" (1/1) ... [2019-10-22 09:00:18,761 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18" (1/1) ... [2019-10-22 09:00:18,765 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18" (1/1) ... [2019-10-22 09:00:18,765 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18" (1/1) ... [2019-10-22 09:00:18,777 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18" (1/1) ... [2019-10-22 09:00:18,794 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18" (1/1) ... [2019-10-22 09:00:18,803 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18" (1/1) ... [2019-10-22 09:00:18,807 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-22 09:00:18,808 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-22 09:00:18,808 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-22 09:00:18,808 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-22 09:00:18,809 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-22 09:00:18,874 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-22 09:00:18,875 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-22 09:00:19,967 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-22 09:00:19,968 INFO L284 CfgBuilder]: Removed 119 assume(true) statements. [2019-10-22 09:00:19,969 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 09:00:19 BoogieIcfgContainer [2019-10-22 09:00:19,969 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-22 09:00:19,970 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-22 09:00:19,970 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-22 09:00:19,973 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-22 09:00:19,974 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 22.10 09:00:18" (1/3) ... [2019-10-22 09:00:19,974 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31ec8c53 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.10 09:00:19, skipping insertion in model container [2019-10-22 09:00:19,975 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:00:18" (2/3) ... [2019-10-22 09:00:19,975 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31ec8c53 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.10 09:00:19, skipping insertion in model container [2019-10-22 09:00:19,975 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 09:00:19" (3/3) ... [2019-10-22 09:00:19,978 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2019-10-22 09:00:19,987 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-22 09:00:19,994 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-10-22 09:00:20,006 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-10-22 09:00:20,038 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-22 09:00:20,038 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-22 09:00:20,038 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-22 09:00:20,038 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-22 09:00:20,039 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-22 09:00:20,039 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-22 09:00:20,039 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-22 09:00:20,039 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-22 09:00:20,067 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states. [2019-10-22 09:00:20,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-10-22 09:00:20,075 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:20,076 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:20,078 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:20,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:20,085 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-10-22 09:00:20,091 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:20,091 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482818170] [2019-10-22 09:00:20,091 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:20,091 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:20,091 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:20,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:20,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:20,275 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482818170] [2019-10-22 09:00:20,276 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:20,277 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:20,277 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428425380] [2019-10-22 09:00:20,282 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:20,282 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:20,294 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:20,294 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:20,296 INFO L87 Difference]: Start difference. First operand 290 states. Second operand 3 states. [2019-10-22 09:00:20,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:20,403 INFO L93 Difference]: Finished difference Result 562 states and 879 transitions. [2019-10-22 09:00:20,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:20,404 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-10-22 09:00:20,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:20,418 INFO L225 Difference]: With dead ends: 562 [2019-10-22 09:00:20,418 INFO L226 Difference]: Without dead ends: 286 [2019-10-22 09:00:20,423 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:20,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states. [2019-10-22 09:00:20,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 286. [2019-10-22 09:00:20,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2019-10-22 09:00:20,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 408 transitions. [2019-10-22 09:00:20,483 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 408 transitions. Word has length 31 [2019-10-22 09:00:20,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:20,483 INFO L462 AbstractCegarLoop]: Abstraction has 286 states and 408 transitions. [2019-10-22 09:00:20,483 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:20,483 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 408 transitions. [2019-10-22 09:00:20,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-22 09:00:20,489 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:20,489 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:20,489 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:20,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:20,491 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-10-22 09:00:20,491 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:20,491 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801922957] [2019-10-22 09:00:20,492 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:20,492 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:20,492 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:20,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:20,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:20,701 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801922957] [2019-10-22 09:00:20,701 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:20,701 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:20,701 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235471044] [2019-10-22 09:00:20,703 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:20,704 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:20,704 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:20,704 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:20,705 INFO L87 Difference]: Start difference. First operand 286 states and 408 transitions. Second operand 3 states. [2019-10-22 09:00:20,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:20,766 INFO L93 Difference]: Finished difference Result 590 states and 850 transitions. [2019-10-22 09:00:20,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:20,766 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-10-22 09:00:20,767 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:20,769 INFO L225 Difference]: With dead ends: 590 [2019-10-22 09:00:20,769 INFO L226 Difference]: Without dead ends: 319 [2019-10-22 09:00:20,770 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:20,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2019-10-22 09:00:20,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 262. [2019-10-22 09:00:20,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 262 states. [2019-10-22 09:00:20,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 372 transitions. [2019-10-22 09:00:20,785 INFO L78 Accepts]: Start accepts. Automaton has 262 states and 372 transitions. Word has length 42 [2019-10-22 09:00:20,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:20,786 INFO L462 AbstractCegarLoop]: Abstraction has 262 states and 372 transitions. [2019-10-22 09:00:20,786 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:20,786 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 372 transitions. [2019-10-22 09:00:20,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-22 09:00:20,787 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:20,787 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:20,788 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:20,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:20,788 INFO L82 PathProgramCache]: Analyzing trace with hash -365626229, now seen corresponding path program 1 times [2019-10-22 09:00:20,788 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:20,788 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553951704] [2019-10-22 09:00:20,789 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:20,789 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:20,789 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:20,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:20,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:20,926 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553951704] [2019-10-22 09:00:20,926 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:20,926 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:20,927 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729856763] [2019-10-22 09:00:20,927 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:20,927 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:20,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:20,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:20,928 INFO L87 Difference]: Start difference. First operand 262 states and 372 transitions. Second operand 3 states. [2019-10-22 09:00:20,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:20,960 INFO L93 Difference]: Finished difference Result 733 states and 1051 transitions. [2019-10-22 09:00:20,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:20,961 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-10-22 09:00:20,961 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:20,963 INFO L225 Difference]: With dead ends: 733 [2019-10-22 09:00:20,963 INFO L226 Difference]: Without dead ends: 486 [2019-10-22 09:00:20,964 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:20,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 486 states. [2019-10-22 09:00:20,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 486 to 295. [2019-10-22 09:00:20,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 295 states. [2019-10-22 09:00:20,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 295 states to 295 states and 420 transitions. [2019-10-22 09:00:20,983 INFO L78 Accepts]: Start accepts. Automaton has 295 states and 420 transitions. Word has length 49 [2019-10-22 09:00:20,984 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:20,984 INFO L462 AbstractCegarLoop]: Abstraction has 295 states and 420 transitions. [2019-10-22 09:00:20,984 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:20,984 INFO L276 IsEmpty]: Start isEmpty. Operand 295 states and 420 transitions. [2019-10-22 09:00:20,985 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-10-22 09:00:20,985 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:20,985 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:20,986 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:20,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:20,986 INFO L82 PathProgramCache]: Analyzing trace with hash 744745200, now seen corresponding path program 1 times [2019-10-22 09:00:20,987 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:20,987 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586539786] [2019-10-22 09:00:20,987 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:20,987 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:20,987 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:21,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:21,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:21,121 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1586539786] [2019-10-22 09:00:21,121 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:21,121 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:00:21,121 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148950616] [2019-10-22 09:00:21,122 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 09:00:21,122 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:21,122 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 09:00:21,122 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:21,122 INFO L87 Difference]: Start difference. First operand 295 states and 420 transitions. Second operand 5 states. [2019-10-22 09:00:21,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:21,388 INFO L93 Difference]: Finished difference Result 929 states and 1337 transitions. [2019-10-22 09:00:21,388 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 09:00:21,389 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-10-22 09:00:21,389 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:21,391 INFO L225 Difference]: With dead ends: 929 [2019-10-22 09:00:21,392 INFO L226 Difference]: Without dead ends: 649 [2019-10-22 09:00:21,392 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-10-22 09:00:21,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 649 states. [2019-10-22 09:00:21,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 649 to 381. [2019-10-22 09:00:21,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 381 states. [2019-10-22 09:00:21,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 543 transitions. [2019-10-22 09:00:21,415 INFO L78 Accepts]: Start accepts. Automaton has 381 states and 543 transitions. Word has length 50 [2019-10-22 09:00:21,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:21,415 INFO L462 AbstractCegarLoop]: Abstraction has 381 states and 543 transitions. [2019-10-22 09:00:21,415 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 09:00:21,415 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 543 transitions. [2019-10-22 09:00:21,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-10-22 09:00:21,416 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:21,417 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:21,417 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:21,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:21,418 INFO L82 PathProgramCache]: Analyzing trace with hash 1614483527, now seen corresponding path program 1 times [2019-10-22 09:00:21,418 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:21,418 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344269007] [2019-10-22 09:00:21,418 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:21,418 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:21,418 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:21,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:21,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:21,503 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344269007] [2019-10-22 09:00:21,504 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:21,504 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:00:21,504 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1942487089] [2019-10-22 09:00:21,504 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 09:00:21,505 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:21,505 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 09:00:21,505 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:21,505 INFO L87 Difference]: Start difference. First operand 381 states and 543 transitions. Second operand 5 states. [2019-10-22 09:00:21,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:21,720 INFO L93 Difference]: Finished difference Result 929 states and 1333 transitions. [2019-10-22 09:00:21,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 09:00:21,721 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-10-22 09:00:21,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:21,725 INFO L225 Difference]: With dead ends: 929 [2019-10-22 09:00:21,727 INFO L226 Difference]: Without dead ends: 649 [2019-10-22 09:00:21,728 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-10-22 09:00:21,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 649 states. [2019-10-22 09:00:21,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 649 to 381. [2019-10-22 09:00:21,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 381 states. [2019-10-22 09:00:21,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 541 transitions. [2019-10-22 09:00:21,749 INFO L78 Accepts]: Start accepts. Automaton has 381 states and 541 transitions. Word has length 51 [2019-10-22 09:00:21,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:21,751 INFO L462 AbstractCegarLoop]: Abstraction has 381 states and 541 transitions. [2019-10-22 09:00:21,751 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 09:00:21,751 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 541 transitions. [2019-10-22 09:00:21,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-10-22 09:00:21,752 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:21,753 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:21,753 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:21,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:21,753 INFO L82 PathProgramCache]: Analyzing trace with hash 251892323, now seen corresponding path program 1 times [2019-10-22 09:00:21,754 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:21,754 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380185427] [2019-10-22 09:00:21,754 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:21,754 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:21,754 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:21,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:21,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:21,889 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [380185427] [2019-10-22 09:00:21,889 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:21,889 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 09:00:21,889 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758568609] [2019-10-22 09:00:21,889 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 09:00:21,890 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:21,890 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 09:00:21,890 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:21,890 INFO L87 Difference]: Start difference. First operand 381 states and 541 transitions. Second operand 5 states. [2019-10-22 09:00:21,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:21,946 INFO L93 Difference]: Finished difference Result 757 states and 1086 transitions. [2019-10-22 09:00:21,947 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-22 09:00:21,947 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2019-10-22 09:00:21,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:21,949 INFO L225 Difference]: With dead ends: 757 [2019-10-22 09:00:21,949 INFO L226 Difference]: Without dead ends: 477 [2019-10-22 09:00:21,950 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-10-22 09:00:21,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 477 states. [2019-10-22 09:00:21,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 477 to 376. [2019-10-22 09:00:21,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 376 states. [2019-10-22 09:00:21,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 376 states to 376 states and 533 transitions. [2019-10-22 09:00:21,997 INFO L78 Accepts]: Start accepts. Automaton has 376 states and 533 transitions. Word has length 52 [2019-10-22 09:00:21,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:21,997 INFO L462 AbstractCegarLoop]: Abstraction has 376 states and 533 transitions. [2019-10-22 09:00:21,997 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 09:00:21,997 INFO L276 IsEmpty]: Start isEmpty. Operand 376 states and 533 transitions. [2019-10-22 09:00:21,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-10-22 09:00:21,998 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:21,998 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:21,999 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:21,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:21,999 INFO L82 PathProgramCache]: Analyzing trace with hash -1519937093, now seen corresponding path program 1 times [2019-10-22 09:00:21,999 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:22,005 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147367713] [2019-10-22 09:00:22,005 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:22,005 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:22,005 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:22,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:22,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:22,134 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147367713] [2019-10-22 09:00:22,134 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:22,135 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 09:00:22,135 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1314823186] [2019-10-22 09:00:22,135 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 09:00:22,135 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:22,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 09:00:22,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:22,136 INFO L87 Difference]: Start difference. First operand 376 states and 533 transitions. Second operand 5 states. [2019-10-22 09:00:22,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:22,237 INFO L93 Difference]: Finished difference Result 788 states and 1135 transitions. [2019-10-22 09:00:22,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:00:22,238 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-10-22 09:00:22,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:22,240 INFO L225 Difference]: With dead ends: 788 [2019-10-22 09:00:22,240 INFO L226 Difference]: Without dead ends: 513 [2019-10-22 09:00:22,240 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-10-22 09:00:22,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 513 states. [2019-10-22 09:00:22,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 513 to 346. [2019-10-22 09:00:22,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 346 states. [2019-10-22 09:00:22,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346 states to 346 states and 487 transitions. [2019-10-22 09:00:22,261 INFO L78 Accepts]: Start accepts. Automaton has 346 states and 487 transitions. Word has length 56 [2019-10-22 09:00:22,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:22,262 INFO L462 AbstractCegarLoop]: Abstraction has 346 states and 487 transitions. [2019-10-22 09:00:22,262 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 09:00:22,262 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 487 transitions. [2019-10-22 09:00:22,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-22 09:00:22,262 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:22,263 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:22,263 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:22,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:22,264 INFO L82 PathProgramCache]: Analyzing trace with hash 1786376721, now seen corresponding path program 1 times [2019-10-22 09:00:22,265 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:22,265 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620414087] [2019-10-22 09:00:22,265 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:22,265 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:22,265 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:22,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:22,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:22,409 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [620414087] [2019-10-22 09:00:22,409 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:22,409 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 09:00:22,410 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069499294] [2019-10-22 09:00:22,410 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 09:00:22,410 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:22,410 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 09:00:22,410 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:22,410 INFO L87 Difference]: Start difference. First operand 346 states and 487 transitions. Second operand 5 states. [2019-10-22 09:00:22,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:22,522 INFO L93 Difference]: Finished difference Result 880 states and 1256 transitions. [2019-10-22 09:00:22,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:00:22,523 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 61 [2019-10-22 09:00:22,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:22,525 INFO L225 Difference]: With dead ends: 880 [2019-10-22 09:00:22,525 INFO L226 Difference]: Without dead ends: 635 [2019-10-22 09:00:22,526 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-10-22 09:00:22,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 635 states. [2019-10-22 09:00:22,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 635 to 316. [2019-10-22 09:00:22,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 316 states. [2019-10-22 09:00:22,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 316 states and 441 transitions. [2019-10-22 09:00:22,545 INFO L78 Accepts]: Start accepts. Automaton has 316 states and 441 transitions. Word has length 61 [2019-10-22 09:00:22,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:22,545 INFO L462 AbstractCegarLoop]: Abstraction has 316 states and 441 transitions. [2019-10-22 09:00:22,545 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 09:00:22,545 INFO L276 IsEmpty]: Start isEmpty. Operand 316 states and 441 transitions. [2019-10-22 09:00:22,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-10-22 09:00:22,546 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:22,546 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:22,547 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:22,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:22,547 INFO L82 PathProgramCache]: Analyzing trace with hash -1245848025, now seen corresponding path program 1 times [2019-10-22 09:00:22,547 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:22,547 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400259511] [2019-10-22 09:00:22,548 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:22,548 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:22,548 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:22,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:22,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:22,715 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [400259511] [2019-10-22 09:00:22,715 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:22,716 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 09:00:22,716 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020024360] [2019-10-22 09:00:22,716 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 09:00:22,716 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:22,717 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 09:00:22,717 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 09:00:22,717 INFO L87 Difference]: Start difference. First operand 316 states and 441 transitions. Second operand 6 states. [2019-10-22 09:00:22,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:22,934 INFO L93 Difference]: Finished difference Result 1074 states and 1513 transitions. [2019-10-22 09:00:22,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-10-22 09:00:22,935 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-10-22 09:00:22,935 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:22,938 INFO L225 Difference]: With dead ends: 1074 [2019-10-22 09:00:22,938 INFO L226 Difference]: Without dead ends: 859 [2019-10-22 09:00:22,938 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-10-22 09:00:22,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 859 states. [2019-10-22 09:00:22,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 859 to 355. [2019-10-22 09:00:22,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 355 states. [2019-10-22 09:00:22,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 355 states to 355 states and 495 transitions. [2019-10-22 09:00:22,962 INFO L78 Accepts]: Start accepts. Automaton has 355 states and 495 transitions. Word has length 66 [2019-10-22 09:00:22,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:22,962 INFO L462 AbstractCegarLoop]: Abstraction has 355 states and 495 transitions. [2019-10-22 09:00:22,962 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 09:00:22,962 INFO L276 IsEmpty]: Start isEmpty. Operand 355 states and 495 transitions. [2019-10-22 09:00:22,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-22 09:00:22,963 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:22,963 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:22,964 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:22,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:22,964 INFO L82 PathProgramCache]: Analyzing trace with hash 1591247394, now seen corresponding path program 1 times [2019-10-22 09:00:22,965 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:22,965 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319578192] [2019-10-22 09:00:22,965 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:22,965 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:22,965 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:22,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:23,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:23,036 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319578192] [2019-10-22 09:00:23,036 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:23,036 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:23,036 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033097526] [2019-10-22 09:00:23,036 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:23,037 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:23,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:23,037 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:23,037 INFO L87 Difference]: Start difference. First operand 355 states and 495 transitions. Second operand 3 states. [2019-10-22 09:00:23,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:23,097 INFO L93 Difference]: Finished difference Result 647 states and 912 transitions. [2019-10-22 09:00:23,098 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:23,098 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-10-22 09:00:23,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:23,099 INFO L225 Difference]: With dead ends: 647 [2019-10-22 09:00:23,100 INFO L226 Difference]: Without dead ends: 432 [2019-10-22 09:00:23,100 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:23,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432 states. [2019-10-22 09:00:23,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432 to 351. [2019-10-22 09:00:23,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 351 states. [2019-10-22 09:00:23,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 351 states to 351 states and 488 transitions. [2019-10-22 09:00:23,123 INFO L78 Accepts]: Start accepts. Automaton has 351 states and 488 transitions. Word has length 67 [2019-10-22 09:00:23,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:23,123 INFO L462 AbstractCegarLoop]: Abstraction has 351 states and 488 transitions. [2019-10-22 09:00:23,123 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:23,124 INFO L276 IsEmpty]: Start isEmpty. Operand 351 states and 488 transitions. [2019-10-22 09:00:23,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-10-22 09:00:23,124 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:23,124 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:23,125 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:23,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:23,125 INFO L82 PathProgramCache]: Analyzing trace with hash 480130565, now seen corresponding path program 1 times [2019-10-22 09:00:23,125 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:23,125 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349459101] [2019-10-22 09:00:23,125 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:23,126 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:23,126 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:23,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:23,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:23,187 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349459101] [2019-10-22 09:00:23,187 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:23,188 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:00:23,188 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [962955625] [2019-10-22 09:00:23,188 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:00:23,188 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:23,188 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:00:23,188 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:00:23,189 INFO L87 Difference]: Start difference. First operand 351 states and 488 transitions. Second operand 4 states. [2019-10-22 09:00:23,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:23,304 INFO L93 Difference]: Finished difference Result 933 states and 1300 transitions. [2019-10-22 09:00:23,304 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:00:23,304 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 70 [2019-10-22 09:00:23,304 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:23,306 INFO L225 Difference]: With dead ends: 933 [2019-10-22 09:00:23,306 INFO L226 Difference]: Without dead ends: 712 [2019-10-22 09:00:23,307 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:23,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 712 states. [2019-10-22 09:00:23,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 712 to 517. [2019-10-22 09:00:23,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 517 states. [2019-10-22 09:00:23,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 517 states to 517 states and 715 transitions. [2019-10-22 09:00:23,339 INFO L78 Accepts]: Start accepts. Automaton has 517 states and 715 transitions. Word has length 70 [2019-10-22 09:00:23,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:23,339 INFO L462 AbstractCegarLoop]: Abstraction has 517 states and 715 transitions. [2019-10-22 09:00:23,339 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:00:23,339 INFO L276 IsEmpty]: Start isEmpty. Operand 517 states and 715 transitions. [2019-10-22 09:00:23,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-10-22 09:00:23,340 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:23,340 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:23,340 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:23,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:23,341 INFO L82 PathProgramCache]: Analyzing trace with hash -1523824051, now seen corresponding path program 1 times [2019-10-22 09:00:23,341 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:23,341 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670715156] [2019-10-22 09:00:23,341 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:23,341 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:23,341 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:23,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:23,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:23,380 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670715156] [2019-10-22 09:00:23,380 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:23,380 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:23,380 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481001431] [2019-10-22 09:00:23,381 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:23,381 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:23,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:23,381 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:23,381 INFO L87 Difference]: Start difference. First operand 517 states and 715 transitions. Second operand 3 states. [2019-10-22 09:00:23,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:23,445 INFO L93 Difference]: Finished difference Result 1220 states and 1679 transitions. [2019-10-22 09:00:23,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:23,445 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-10-22 09:00:23,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:23,448 INFO L225 Difference]: With dead ends: 1220 [2019-10-22 09:00:23,448 INFO L226 Difference]: Without dead ends: 850 [2019-10-22 09:00:23,449 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:23,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 850 states. [2019-10-22 09:00:23,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 850 to 578. [2019-10-22 09:00:23,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 578 states. [2019-10-22 09:00:23,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 578 states to 578 states and 792 transitions. [2019-10-22 09:00:23,493 INFO L78 Accepts]: Start accepts. Automaton has 578 states and 792 transitions. Word has length 70 [2019-10-22 09:00:23,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:23,494 INFO L462 AbstractCegarLoop]: Abstraction has 578 states and 792 transitions. [2019-10-22 09:00:23,494 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:23,494 INFO L276 IsEmpty]: Start isEmpty. Operand 578 states and 792 transitions. [2019-10-22 09:00:23,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-10-22 09:00:23,495 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:23,495 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:23,495 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:23,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:23,496 INFO L82 PathProgramCache]: Analyzing trace with hash -1383275441, now seen corresponding path program 1 times [2019-10-22 09:00:23,496 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:23,496 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160526087] [2019-10-22 09:00:23,496 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:23,496 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:23,496 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:23,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:23,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:23,552 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160526087] [2019-10-22 09:00:23,552 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:23,552 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:23,552 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485572396] [2019-10-22 09:00:23,553 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:23,553 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:23,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:23,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:23,554 INFO L87 Difference]: Start difference. First operand 578 states and 792 transitions. Second operand 3 states. [2019-10-22 09:00:23,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:23,604 INFO L93 Difference]: Finished difference Result 982 states and 1355 transitions. [2019-10-22 09:00:23,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:23,605 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-10-22 09:00:23,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:23,606 INFO L225 Difference]: With dead ends: 982 [2019-10-22 09:00:23,607 INFO L226 Difference]: Without dead ends: 543 [2019-10-22 09:00:23,607 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:23,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2019-10-22 09:00:23,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 543. [2019-10-22 09:00:23,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 543 states. [2019-10-22 09:00:23,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 543 states to 543 states and 743 transitions. [2019-10-22 09:00:23,651 INFO L78 Accepts]: Start accepts. Automaton has 543 states and 743 transitions. Word has length 70 [2019-10-22 09:00:23,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:23,652 INFO L462 AbstractCegarLoop]: Abstraction has 543 states and 743 transitions. [2019-10-22 09:00:23,652 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:23,652 INFO L276 IsEmpty]: Start isEmpty. Operand 543 states and 743 transitions. [2019-10-22 09:00:23,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-10-22 09:00:23,653 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:23,653 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:23,654 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:23,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:23,654 INFO L82 PathProgramCache]: Analyzing trace with hash -1837662732, now seen corresponding path program 1 times [2019-10-22 09:00:23,654 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:23,654 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74673711] [2019-10-22 09:00:23,654 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:23,654 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:23,655 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:23,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:23,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:23,784 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [74673711] [2019-10-22 09:00:23,785 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:23,785 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 09:00:23,804 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [862780609] [2019-10-22 09:00:23,804 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 09:00:23,804 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:23,804 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 09:00:23,804 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 09:00:23,805 INFO L87 Difference]: Start difference. First operand 543 states and 743 transitions. Second operand 6 states. [2019-10-22 09:00:24,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:24,064 INFO L93 Difference]: Finished difference Result 1703 states and 2366 transitions. [2019-10-22 09:00:24,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-10-22 09:00:24,064 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-10-22 09:00:24,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:24,069 INFO L225 Difference]: With dead ends: 1703 [2019-10-22 09:00:24,069 INFO L226 Difference]: Without dead ends: 1380 [2019-10-22 09:00:24,070 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-10-22 09:00:24,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1380 states. [2019-10-22 09:00:24,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1380 to 547. [2019-10-22 09:00:24,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 547 states. [2019-10-22 09:00:24,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 547 states to 547 states and 748 transitions. [2019-10-22 09:00:24,112 INFO L78 Accepts]: Start accepts. Automaton has 547 states and 748 transitions. Word has length 71 [2019-10-22 09:00:24,112 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:24,112 INFO L462 AbstractCegarLoop]: Abstraction has 547 states and 748 transitions. [2019-10-22 09:00:24,112 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 09:00:24,112 INFO L276 IsEmpty]: Start isEmpty. Operand 547 states and 748 transitions. [2019-10-22 09:00:24,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-10-22 09:00:24,113 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:24,113 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:24,113 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:24,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:24,113 INFO L82 PathProgramCache]: Analyzing trace with hash 276642491, now seen corresponding path program 1 times [2019-10-22 09:00:24,114 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:24,114 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1894802611] [2019-10-22 09:00:24,114 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:24,114 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:24,114 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:24,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:24,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:24,195 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1894802611] [2019-10-22 09:00:24,195 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:24,195 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 09:00:24,195 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [604430815] [2019-10-22 09:00:24,195 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 09:00:24,195 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:24,196 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 09:00:24,196 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:24,196 INFO L87 Difference]: Start difference. First operand 547 states and 748 transitions. Second operand 5 states. [2019-10-22 09:00:24,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:24,327 INFO L93 Difference]: Finished difference Result 856 states and 1187 transitions. [2019-10-22 09:00:24,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 09:00:24,328 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2019-10-22 09:00:24,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:24,330 INFO L225 Difference]: With dead ends: 856 [2019-10-22 09:00:24,330 INFO L226 Difference]: Without dead ends: 854 [2019-10-22 09:00:24,331 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-10-22 09:00:24,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 854 states. [2019-10-22 09:00:24,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 854 to 549. [2019-10-22 09:00:24,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 549 states. [2019-10-22 09:00:24,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 549 states and 750 transitions. [2019-10-22 09:00:24,366 INFO L78 Accepts]: Start accepts. Automaton has 549 states and 750 transitions. Word has length 71 [2019-10-22 09:00:24,366 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:24,366 INFO L462 AbstractCegarLoop]: Abstraction has 549 states and 750 transitions. [2019-10-22 09:00:24,366 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 09:00:24,366 INFO L276 IsEmpty]: Start isEmpty. Operand 549 states and 750 transitions. [2019-10-22 09:00:24,367 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-10-22 09:00:24,367 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:24,367 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:24,368 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:24,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:24,368 INFO L82 PathProgramCache]: Analyzing trace with hash -66828782, now seen corresponding path program 1 times [2019-10-22 09:00:24,369 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:24,369 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670003369] [2019-10-22 09:00:24,369 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:24,369 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:24,369 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:24,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:24,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:24,448 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670003369] [2019-10-22 09:00:24,448 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:24,448 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 09:00:24,448 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2142301529] [2019-10-22 09:00:24,449 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 09:00:24,449 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:24,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 09:00:24,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 09:00:24,449 INFO L87 Difference]: Start difference. First operand 549 states and 750 transitions. Second operand 6 states. [2019-10-22 09:00:24,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:24,832 INFO L93 Difference]: Finished difference Result 1970 states and 2711 transitions. [2019-10-22 09:00:24,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-10-22 09:00:24,833 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-10-22 09:00:24,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:24,837 INFO L225 Difference]: With dead ends: 1970 [2019-10-22 09:00:24,837 INFO L226 Difference]: Without dead ends: 1606 [2019-10-22 09:00:24,838 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-10-22 09:00:24,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1606 states. [2019-10-22 09:00:24,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1606 to 595. [2019-10-22 09:00:24,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 595 states. [2019-10-22 09:00:24,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 595 states to 595 states and 808 transitions. [2019-10-22 09:00:24,884 INFO L78 Accepts]: Start accepts. Automaton has 595 states and 808 transitions. Word has length 71 [2019-10-22 09:00:24,884 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:24,884 INFO L462 AbstractCegarLoop]: Abstraction has 595 states and 808 transitions. [2019-10-22 09:00:24,884 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 09:00:24,884 INFO L276 IsEmpty]: Start isEmpty. Operand 595 states and 808 transitions. [2019-10-22 09:00:24,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-10-22 09:00:24,885 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:24,885 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:24,885 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:24,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:24,886 INFO L82 PathProgramCache]: Analyzing trace with hash -624478278, now seen corresponding path program 1 times [2019-10-22 09:00:24,886 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:24,886 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1755604770] [2019-10-22 09:00:24,886 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:24,886 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:24,886 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:24,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:24,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:24,966 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1755604770] [2019-10-22 09:00:24,966 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:24,966 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 09:00:24,967 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368799371] [2019-10-22 09:00:24,967 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 09:00:24,967 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:24,967 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 09:00:24,968 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 09:00:24,968 INFO L87 Difference]: Start difference. First operand 595 states and 808 transitions. Second operand 6 states. [2019-10-22 09:00:25,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:25,350 INFO L93 Difference]: Finished difference Result 2296 states and 3143 transitions. [2019-10-22 09:00:25,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-10-22 09:00:25,350 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-10-22 09:00:25,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:25,356 INFO L225 Difference]: With dead ends: 2296 [2019-10-22 09:00:25,356 INFO L226 Difference]: Without dead ends: 1924 [2019-10-22 09:00:25,358 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-10-22 09:00:25,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1924 states. [2019-10-22 09:00:25,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1924 to 673. [2019-10-22 09:00:25,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 673 states. [2019-10-22 09:00:25,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 673 states to 673 states and 910 transitions. [2019-10-22 09:00:25,435 INFO L78 Accepts]: Start accepts. Automaton has 673 states and 910 transitions. Word has length 72 [2019-10-22 09:00:25,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:25,435 INFO L462 AbstractCegarLoop]: Abstraction has 673 states and 910 transitions. [2019-10-22 09:00:25,436 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 09:00:25,436 INFO L276 IsEmpty]: Start isEmpty. Operand 673 states and 910 transitions. [2019-10-22 09:00:25,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-10-22 09:00:25,438 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:25,438 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:25,439 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:25,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:25,439 INFO L82 PathProgramCache]: Analyzing trace with hash -2046951303, now seen corresponding path program 1 times [2019-10-22 09:00:25,439 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:25,479 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720231492] [2019-10-22 09:00:25,480 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:25,480 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:25,480 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:25,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:25,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:25,535 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720231492] [2019-10-22 09:00:25,535 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:25,535 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 09:00:25,535 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13201824] [2019-10-22 09:00:25,536 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 09:00:25,536 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:25,536 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 09:00:25,536 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 09:00:25,536 INFO L87 Difference]: Start difference. First operand 673 states and 910 transitions. Second operand 6 states. [2019-10-22 09:00:25,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:25,696 INFO L93 Difference]: Finished difference Result 1495 states and 2085 transitions. [2019-10-22 09:00:25,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-10-22 09:00:25,696 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-10-22 09:00:25,697 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:25,700 INFO L225 Difference]: With dead ends: 1495 [2019-10-22 09:00:25,700 INFO L226 Difference]: Without dead ends: 1106 [2019-10-22 09:00:25,701 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-10-22 09:00:25,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1106 states. [2019-10-22 09:00:25,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1106 to 679. [2019-10-22 09:00:25,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 679 states. [2019-10-22 09:00:25,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 679 states to 679 states and 916 transitions. [2019-10-22 09:00:25,755 INFO L78 Accepts]: Start accepts. Automaton has 679 states and 916 transitions. Word has length 72 [2019-10-22 09:00:25,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:25,755 INFO L462 AbstractCegarLoop]: Abstraction has 679 states and 916 transitions. [2019-10-22 09:00:25,755 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 09:00:25,755 INFO L276 IsEmpty]: Start isEmpty. Operand 679 states and 916 transitions. [2019-10-22 09:00:25,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-10-22 09:00:25,756 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:25,756 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:25,757 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:25,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:25,757 INFO L82 PathProgramCache]: Analyzing trace with hash 778464989, now seen corresponding path program 1 times [2019-10-22 09:00:25,757 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:25,757 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198869805] [2019-10-22 09:00:25,757 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:25,758 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:25,758 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:25,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:25,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:25,798 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1198869805] [2019-10-22 09:00:25,798 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:25,798 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:25,798 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992705456] [2019-10-22 09:00:25,798 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:25,799 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:25,799 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:25,799 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:25,799 INFO L87 Difference]: Start difference. First operand 679 states and 916 transitions. Second operand 3 states. [2019-10-22 09:00:25,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:25,895 INFO L93 Difference]: Finished difference Result 1331 states and 1818 transitions. [2019-10-22 09:00:25,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:25,895 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-10-22 09:00:25,896 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:25,898 INFO L225 Difference]: With dead ends: 1331 [2019-10-22 09:00:25,898 INFO L226 Difference]: Without dead ends: 873 [2019-10-22 09:00:25,899 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:25,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 873 states. [2019-10-22 09:00:25,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 873 to 658. [2019-10-22 09:00:25,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 658 states. [2019-10-22 09:00:25,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 879 transitions. [2019-10-22 09:00:25,954 INFO L78 Accepts]: Start accepts. Automaton has 658 states and 879 transitions. Word has length 72 [2019-10-22 09:00:25,955 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:25,955 INFO L462 AbstractCegarLoop]: Abstraction has 658 states and 879 transitions. [2019-10-22 09:00:25,955 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:25,955 INFO L276 IsEmpty]: Start isEmpty. Operand 658 states and 879 transitions. [2019-10-22 09:00:25,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-10-22 09:00:25,956 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:25,956 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:25,956 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:25,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:25,957 INFO L82 PathProgramCache]: Analyzing trace with hash 449594347, now seen corresponding path program 1 times [2019-10-22 09:00:25,957 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:25,957 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333524492] [2019-10-22 09:00:25,957 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:25,957 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:25,957 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:25,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:26,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:26,000 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1333524492] [2019-10-22 09:00:26,000 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:26,000 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:00:26,000 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [660847065] [2019-10-22 09:00:26,001 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:00:26,001 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:26,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:00:26,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:00:26,001 INFO L87 Difference]: Start difference. First operand 658 states and 879 transitions. Second operand 4 states. [2019-10-22 09:00:26,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:26,165 INFO L93 Difference]: Finished difference Result 1698 states and 2278 transitions. [2019-10-22 09:00:26,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:00:26,165 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-10-22 09:00:26,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:26,169 INFO L225 Difference]: With dead ends: 1698 [2019-10-22 09:00:26,169 INFO L226 Difference]: Without dead ends: 1293 [2019-10-22 09:00:26,170 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:26,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1293 states. [2019-10-22 09:00:26,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1293 to 892. [2019-10-22 09:00:26,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-10-22 09:00:26,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1190 transitions. [2019-10-22 09:00:26,239 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1190 transitions. Word has length 73 [2019-10-22 09:00:26,239 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:26,239 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1190 transitions. [2019-10-22 09:00:26,240 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:00:26,240 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1190 transitions. [2019-10-22 09:00:26,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-10-22 09:00:26,240 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:26,241 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:26,241 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:26,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:26,241 INFO L82 PathProgramCache]: Analyzing trace with hash 1828954211, now seen corresponding path program 1 times [2019-10-22 09:00:26,241 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:26,242 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1100279427] [2019-10-22 09:00:26,242 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:26,242 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:26,242 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:26,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:26,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:26,282 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1100279427] [2019-10-22 09:00:26,282 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:26,282 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:26,282 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588977191] [2019-10-22 09:00:26,282 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:26,282 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:26,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:26,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:26,283 INFO L87 Difference]: Start difference. First operand 892 states and 1190 transitions. Second operand 3 states. [2019-10-22 09:00:26,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:26,411 INFO L93 Difference]: Finished difference Result 1867 states and 2508 transitions. [2019-10-22 09:00:26,411 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:26,411 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-10-22 09:00:26,411 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:26,415 INFO L225 Difference]: With dead ends: 1867 [2019-10-22 09:00:26,415 INFO L226 Difference]: Without dead ends: 1279 [2019-10-22 09:00:26,416 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:26,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1279 states. [2019-10-22 09:00:26,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1279 to 848. [2019-10-22 09:00:26,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 848 states. [2019-10-22 09:00:26,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 848 states to 848 states and 1126 transitions. [2019-10-22 09:00:26,484 INFO L78 Accepts]: Start accepts. Automaton has 848 states and 1126 transitions. Word has length 73 [2019-10-22 09:00:26,484 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:26,485 INFO L462 AbstractCegarLoop]: Abstraction has 848 states and 1126 transitions. [2019-10-22 09:00:26,485 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:26,485 INFO L276 IsEmpty]: Start isEmpty. Operand 848 states and 1126 transitions. [2019-10-22 09:00:26,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-10-22 09:00:26,486 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:26,486 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:26,486 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:26,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:26,487 INFO L82 PathProgramCache]: Analyzing trace with hash 1948644571, now seen corresponding path program 1 times [2019-10-22 09:00:26,487 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:26,487 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427779840] [2019-10-22 09:00:26,487 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:26,487 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:26,487 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:26,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:26,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:26,544 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1427779840] [2019-10-22 09:00:26,544 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:26,544 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:00:26,544 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827280543] [2019-10-22 09:00:26,544 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:00:26,544 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:26,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:00:26,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:00:26,545 INFO L87 Difference]: Start difference. First operand 848 states and 1126 transitions. Second operand 4 states. [2019-10-22 09:00:26,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:26,743 INFO L93 Difference]: Finished difference Result 1982 states and 2626 transitions. [2019-10-22 09:00:26,744 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:00:26,745 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-10-22 09:00:26,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:26,748 INFO L225 Difference]: With dead ends: 1982 [2019-10-22 09:00:26,748 INFO L226 Difference]: Without dead ends: 1423 [2019-10-22 09:00:26,749 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:26,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1423 states. [2019-10-22 09:00:26,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1423 to 1130. [2019-10-22 09:00:26,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1130 states. [2019-10-22 09:00:26,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1130 states to 1130 states and 1490 transitions. [2019-10-22 09:00:26,837 INFO L78 Accepts]: Start accepts. Automaton has 1130 states and 1490 transitions. Word has length 73 [2019-10-22 09:00:26,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:26,837 INFO L462 AbstractCegarLoop]: Abstraction has 1130 states and 1490 transitions. [2019-10-22 09:00:26,837 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:00:26,837 INFO L276 IsEmpty]: Start isEmpty. Operand 1130 states and 1490 transitions. [2019-10-22 09:00:26,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-10-22 09:00:26,838 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:26,838 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:26,839 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:26,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:26,842 INFO L82 PathProgramCache]: Analyzing trace with hash 1795806066, now seen corresponding path program 1 times [2019-10-22 09:00:26,842 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:26,842 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886459365] [2019-10-22 09:00:26,842 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:26,842 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:26,842 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:26,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:26,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:26,867 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886459365] [2019-10-22 09:00:26,867 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:26,868 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:26,868 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597581942] [2019-10-22 09:00:26,868 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:26,868 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:26,868 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:26,868 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:26,868 INFO L87 Difference]: Start difference. First operand 1130 states and 1490 transitions. Second operand 3 states. [2019-10-22 09:00:27,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:27,097 INFO L93 Difference]: Finished difference Result 2791 states and 3670 transitions. [2019-10-22 09:00:27,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:27,097 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-10-22 09:00:27,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:27,102 INFO L225 Difference]: With dead ends: 2791 [2019-10-22 09:00:27,102 INFO L226 Difference]: Without dead ends: 1894 [2019-10-22 09:00:27,104 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:27,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1894 states. [2019-10-22 09:00:27,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1894 to 1132. [2019-10-22 09:00:27,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1132 states. [2019-10-22 09:00:27,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1132 states to 1132 states and 1492 transitions. [2019-10-22 09:00:27,197 INFO L78 Accepts]: Start accepts. Automaton has 1132 states and 1492 transitions. Word has length 74 [2019-10-22 09:00:27,197 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:27,197 INFO L462 AbstractCegarLoop]: Abstraction has 1132 states and 1492 transitions. [2019-10-22 09:00:27,197 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:27,197 INFO L276 IsEmpty]: Start isEmpty. Operand 1132 states and 1492 transitions. [2019-10-22 09:00:27,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-10-22 09:00:27,198 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:27,198 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:27,199 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:27,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:27,199 INFO L82 PathProgramCache]: Analyzing trace with hash 230569326, now seen corresponding path program 1 times [2019-10-22 09:00:27,200 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:27,200 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307277683] [2019-10-22 09:00:27,200 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:27,200 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:27,200 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:27,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:27,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:27,254 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307277683] [2019-10-22 09:00:27,254 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:27,254 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:00:27,254 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100312074] [2019-10-22 09:00:27,255 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:00:27,255 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:27,255 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:00:27,255 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:00:27,255 INFO L87 Difference]: Start difference. First operand 1132 states and 1492 transitions. Second operand 4 states. [2019-10-22 09:00:27,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:27,398 INFO L93 Difference]: Finished difference Result 2362 states and 3100 transitions. [2019-10-22 09:00:27,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:00:27,399 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-10-22 09:00:27,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:27,402 INFO L225 Difference]: With dead ends: 2362 [2019-10-22 09:00:27,402 INFO L226 Difference]: Without dead ends: 1285 [2019-10-22 09:00:27,403 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:27,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1285 states. [2019-10-22 09:00:27,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1285 to 945. [2019-10-22 09:00:27,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 945 states. [2019-10-22 09:00:27,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 945 states to 945 states and 1236 transitions. [2019-10-22 09:00:27,490 INFO L78 Accepts]: Start accepts. Automaton has 945 states and 1236 transitions. Word has length 75 [2019-10-22 09:00:27,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:27,490 INFO L462 AbstractCegarLoop]: Abstraction has 945 states and 1236 transitions. [2019-10-22 09:00:27,490 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:00:27,490 INFO L276 IsEmpty]: Start isEmpty. Operand 945 states and 1236 transitions. [2019-10-22 09:00:27,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-10-22 09:00:27,491 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:27,491 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:27,491 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:27,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:27,492 INFO L82 PathProgramCache]: Analyzing trace with hash -818028433, now seen corresponding path program 1 times [2019-10-22 09:00:27,492 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:27,492 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1833034427] [2019-10-22 09:00:27,492 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:27,492 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:27,492 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:27,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:27,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:27,549 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1833034427] [2019-10-22 09:00:27,549 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:27,549 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:00:27,550 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93117004] [2019-10-22 09:00:27,550 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:00:27,550 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:27,550 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:00:27,550 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:00:27,550 INFO L87 Difference]: Start difference. First operand 945 states and 1236 transitions. Second operand 4 states. [2019-10-22 09:00:27,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:27,705 INFO L93 Difference]: Finished difference Result 2175 states and 2852 transitions. [2019-10-22 09:00:27,706 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:00:27,706 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 76 [2019-10-22 09:00:27,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:27,709 INFO L225 Difference]: With dead ends: 2175 [2019-10-22 09:00:27,709 INFO L226 Difference]: Without dead ends: 1305 [2019-10-22 09:00:27,710 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:27,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1305 states. [2019-10-22 09:00:27,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1305 to 891. [2019-10-22 09:00:27,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 891 states. [2019-10-22 09:00:27,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 891 states and 1158 transitions. [2019-10-22 09:00:27,804 INFO L78 Accepts]: Start accepts. Automaton has 891 states and 1158 transitions. Word has length 76 [2019-10-22 09:00:27,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:27,805 INFO L462 AbstractCegarLoop]: Abstraction has 891 states and 1158 transitions. [2019-10-22 09:00:27,805 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:00:27,805 INFO L276 IsEmpty]: Start isEmpty. Operand 891 states and 1158 transitions. [2019-10-22 09:00:27,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2019-10-22 09:00:27,807 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:27,807 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:27,807 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:27,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:27,808 INFO L82 PathProgramCache]: Analyzing trace with hash 231668988, now seen corresponding path program 1 times [2019-10-22 09:00:27,808 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:27,808 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433473346] [2019-10-22 09:00:27,808 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:27,808 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:27,808 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:27,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:28,069 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:28,070 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1433473346] [2019-10-22 09:00:28,070 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1070506682] [2019-10-22 09:00:28,071 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:28,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:28,265 INFO L256 TraceCheckSpWp]: Trace formula consists of 720 conjuncts, 9 conjunts are in the unsatisfiable core [2019-10-22 09:00:28,278 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 09:00:28,349 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-10-22 09:00:28,349 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-22 09:00:28,350 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-10-22 09:00:28,350 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288502322] [2019-10-22 09:00:28,350 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 09:00:28,350 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:28,350 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 09:00:28,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-10-22 09:00:28,351 INFO L87 Difference]: Start difference. First operand 891 states and 1158 transitions. Second operand 6 states. [2019-10-22 09:00:28,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:28,645 INFO L93 Difference]: Finished difference Result 2714 states and 3666 transitions. [2019-10-22 09:00:28,646 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-10-22 09:00:28,646 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 119 [2019-10-22 09:00:28,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:28,655 INFO L225 Difference]: With dead ends: 2714 [2019-10-22 09:00:28,656 INFO L226 Difference]: Without dead ends: 1964 [2019-10-22 09:00:28,657 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 116 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-10-22 09:00:28,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1964 states. [2019-10-22 09:00:28,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1964 to 891. [2019-10-22 09:00:28,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 891 states. [2019-10-22 09:00:28,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 891 states and 1155 transitions. [2019-10-22 09:00:28,748 INFO L78 Accepts]: Start accepts. Automaton has 891 states and 1155 transitions. Word has length 119 [2019-10-22 09:00:28,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:28,748 INFO L462 AbstractCegarLoop]: Abstraction has 891 states and 1155 transitions. [2019-10-22 09:00:28,748 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 09:00:28,748 INFO L276 IsEmpty]: Start isEmpty. Operand 891 states and 1155 transitions. [2019-10-22 09:00:28,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2019-10-22 09:00:28,750 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:28,750 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:28,950 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:28,951 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:28,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:28,951 INFO L82 PathProgramCache]: Analyzing trace with hash -1539750943, now seen corresponding path program 1 times [2019-10-22 09:00:28,952 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:28,952 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300532508] [2019-10-22 09:00:28,952 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:28,952 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:28,952 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:28,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:29,212 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:29,212 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300532508] [2019-10-22 09:00:29,213 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1478440542] [2019-10-22 09:00:29,213 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:29,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:29,351 INFO L256 TraceCheckSpWp]: Trace formula consists of 733 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-22 09:00:29,354 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 09:00:29,444 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-10-22 09:00:29,444 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-22 09:00:29,444 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-10-22 09:00:29,445 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1519819313] [2019-10-22 09:00:29,445 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 09:00:29,445 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:29,445 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 09:00:29,445 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-10-22 09:00:29,445 INFO L87 Difference]: Start difference. First operand 891 states and 1155 transitions. Second operand 6 states. [2019-10-22 09:00:29,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:29,771 INFO L93 Difference]: Finished difference Result 2443 states and 3263 transitions. [2019-10-22 09:00:29,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-10-22 09:00:29,771 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 123 [2019-10-22 09:00:29,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:29,780 INFO L225 Difference]: With dead ends: 2443 [2019-10-22 09:00:29,784 INFO L226 Difference]: Without dead ends: 1693 [2019-10-22 09:00:29,785 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-10-22 09:00:29,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1693 states. [2019-10-22 09:00:29,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1693 to 891. [2019-10-22 09:00:29,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 891 states. [2019-10-22 09:00:29,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 891 states and 1152 transitions. [2019-10-22 09:00:29,878 INFO L78 Accepts]: Start accepts. Automaton has 891 states and 1152 transitions. Word has length 123 [2019-10-22 09:00:29,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:29,878 INFO L462 AbstractCegarLoop]: Abstraction has 891 states and 1152 transitions. [2019-10-22 09:00:29,878 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 09:00:29,878 INFO L276 IsEmpty]: Start isEmpty. Operand 891 states and 1152 transitions. [2019-10-22 09:00:29,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2019-10-22 09:00:29,881 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:29,881 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:30,082 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:30,082 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:30,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:30,082 INFO L82 PathProgramCache]: Analyzing trace with hash 1067023105, now seen corresponding path program 1 times [2019-10-22 09:00:30,083 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:30,083 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937412097] [2019-10-22 09:00:30,083 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:30,083 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:30,083 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:30,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:30,350 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:30,350 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937412097] [2019-10-22 09:00:30,350 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [412485816] [2019-10-22 09:00:30,350 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:30,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:30,499 INFO L256 TraceCheckSpWp]: Trace formula consists of 745 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-22 09:00:30,502 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 09:00:30,583 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-10-22 09:00:30,584 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-22 09:00:30,584 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-10-22 09:00:30,584 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655553828] [2019-10-22 09:00:30,584 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 09:00:30,584 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:30,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 09:00:30,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-10-22 09:00:30,585 INFO L87 Difference]: Start difference. First operand 891 states and 1152 transitions. Second operand 6 states. [2019-10-22 09:00:30,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:30,994 INFO L93 Difference]: Finished difference Result 2805 states and 3772 transitions. [2019-10-22 09:00:30,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-10-22 09:00:30,994 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 126 [2019-10-22 09:00:30,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:30,998 INFO L225 Difference]: With dead ends: 2805 [2019-10-22 09:00:31,002 INFO L226 Difference]: Without dead ends: 2042 [2019-10-22 09:00:31,004 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2019-10-22 09:00:31,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2042 states. [2019-10-22 09:00:31,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2042 to 839. [2019-10-22 09:00:31,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 839 states. [2019-10-22 09:00:31,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 839 states to 839 states and 1074 transitions. [2019-10-22 09:00:31,098 INFO L78 Accepts]: Start accepts. Automaton has 839 states and 1074 transitions. Word has length 126 [2019-10-22 09:00:31,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:31,098 INFO L462 AbstractCegarLoop]: Abstraction has 839 states and 1074 transitions. [2019-10-22 09:00:31,098 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 09:00:31,099 INFO L276 IsEmpty]: Start isEmpty. Operand 839 states and 1074 transitions. [2019-10-22 09:00:31,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-10-22 09:00:31,101 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:31,101 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:31,302 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:31,303 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:31,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:31,304 INFO L82 PathProgramCache]: Analyzing trace with hash -569114610, now seen corresponding path program 1 times [2019-10-22 09:00:31,304 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:31,304 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816906994] [2019-10-22 09:00:31,304 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:31,304 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:31,304 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:31,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:31,483 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:31,483 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816906994] [2019-10-22 09:00:31,484 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1594795601] [2019-10-22 09:00:31,484 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:31,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:31,612 INFO L256 TraceCheckSpWp]: Trace formula consists of 746 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-22 09:00:31,614 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 09:00:31,688 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-10-22 09:00:31,688 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-22 09:00:31,688 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 13 [2019-10-22 09:00:31,688 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [590037668] [2019-10-22 09:00:31,689 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 09:00:31,689 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:31,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 09:00:31,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2019-10-22 09:00:31,689 INFO L87 Difference]: Start difference. First operand 839 states and 1074 transitions. Second operand 6 states. [2019-10-22 09:00:31,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:31,977 INFO L93 Difference]: Finished difference Result 2159 states and 2876 transitions. [2019-10-22 09:00:31,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-10-22 09:00:31,978 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 127 [2019-10-22 09:00:31,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:31,980 INFO L225 Difference]: With dead ends: 2159 [2019-10-22 09:00:31,984 INFO L226 Difference]: Without dead ends: 1475 [2019-10-22 09:00:31,986 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=44, Invalid=228, Unknown=0, NotChecked=0, Total=272 [2019-10-22 09:00:31,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1475 states. [2019-10-22 09:00:32,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1475 to 839. [2019-10-22 09:00:32,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 839 states. [2019-10-22 09:00:32,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 839 states to 839 states and 1073 transitions. [2019-10-22 09:00:32,090 INFO L78 Accepts]: Start accepts. Automaton has 839 states and 1073 transitions. Word has length 127 [2019-10-22 09:00:32,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:32,090 INFO L462 AbstractCegarLoop]: Abstraction has 839 states and 1073 transitions. [2019-10-22 09:00:32,090 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 09:00:32,090 INFO L276 IsEmpty]: Start isEmpty. Operand 839 states and 1073 transitions. [2019-10-22 09:00:32,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-10-22 09:00:32,092 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:32,092 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:32,292 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:32,293 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:32,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:32,293 INFO L82 PathProgramCache]: Analyzing trace with hash -503152461, now seen corresponding path program 1 times [2019-10-22 09:00:32,293 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:32,294 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425220234] [2019-10-22 09:00:32,294 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:32,294 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:32,294 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:32,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:32,498 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:32,499 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425220234] [2019-10-22 09:00:32,499 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1826764681] [2019-10-22 09:00:32,499 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:32,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:32,677 INFO L256 TraceCheckSpWp]: Trace formula consists of 760 conjuncts, 45 conjunts are in the unsatisfiable core [2019-10-22 09:00:32,681 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 09:00:32,982 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:32,982 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-10-22 09:00:32,982 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12] total 17 [2019-10-22 09:00:32,983 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246214446] [2019-10-22 09:00:32,983 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-22 09:00:32,983 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:32,983 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-22 09:00:32,983 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=251, Unknown=0, NotChecked=0, Total=306 [2019-10-22 09:00:32,984 INFO L87 Difference]: Start difference. First operand 839 states and 1073 transitions. Second operand 18 states. [2019-10-22 09:00:35,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:35,633 INFO L93 Difference]: Finished difference Result 3430 states and 4518 transitions. [2019-10-22 09:00:35,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2019-10-22 09:00:35,633 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 131 [2019-10-22 09:00:35,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:35,637 INFO L225 Difference]: With dead ends: 3430 [2019-10-22 09:00:35,638 INFO L226 Difference]: Without dead ends: 2752 [2019-10-22 09:00:35,641 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 118 SyntacticMatches, 4 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1942 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1261, Invalid=4745, Unknown=0, NotChecked=0, Total=6006 [2019-10-22 09:00:35,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2752 states. [2019-10-22 09:00:35,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2752 to 1322. [2019-10-22 09:00:35,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1322 states. [2019-10-22 09:00:35,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1322 states to 1322 states and 1712 transitions. [2019-10-22 09:00:35,816 INFO L78 Accepts]: Start accepts. Automaton has 1322 states and 1712 transitions. Word has length 131 [2019-10-22 09:00:35,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:35,816 INFO L462 AbstractCegarLoop]: Abstraction has 1322 states and 1712 transitions. [2019-10-22 09:00:35,816 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-22 09:00:35,816 INFO L276 IsEmpty]: Start isEmpty. Operand 1322 states and 1712 transitions. [2019-10-22 09:00:35,818 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-10-22 09:00:35,819 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:35,819 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:36,019 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:36,020 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:36,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:36,021 INFO L82 PathProgramCache]: Analyzing trace with hash -1629002450, now seen corresponding path program 1 times [2019-10-22 09:00:36,021 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:36,021 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [356298389] [2019-10-22 09:00:36,021 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:36,021 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:36,021 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:36,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:36,066 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-10-22 09:00:36,066 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [356298389] [2019-10-22 09:00:36,066 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:36,067 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:00:36,067 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [846211792] [2019-10-22 09:00:36,067 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:00:36,068 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:36,068 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:00:36,068 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:00:36,068 INFO L87 Difference]: Start difference. First operand 1322 states and 1712 transitions. Second operand 4 states. [2019-10-22 09:00:36,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:36,428 INFO L93 Difference]: Finished difference Result 3257 states and 4242 transitions. [2019-10-22 09:00:36,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:00:36,428 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 132 [2019-10-22 09:00:36,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:36,431 INFO L225 Difference]: With dead ends: 3257 [2019-10-22 09:00:36,432 INFO L226 Difference]: Without dead ends: 2063 [2019-10-22 09:00:36,433 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:36,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2063 states. [2019-10-22 09:00:36,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2063 to 1382. [2019-10-22 09:00:36,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1382 states. [2019-10-22 09:00:36,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1382 states to 1382 states and 1766 transitions. [2019-10-22 09:00:36,598 INFO L78 Accepts]: Start accepts. Automaton has 1382 states and 1766 transitions. Word has length 132 [2019-10-22 09:00:36,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:36,599 INFO L462 AbstractCegarLoop]: Abstraction has 1382 states and 1766 transitions. [2019-10-22 09:00:36,599 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:00:36,599 INFO L276 IsEmpty]: Start isEmpty. Operand 1382 states and 1766 transitions. [2019-10-22 09:00:36,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-10-22 09:00:36,601 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:36,601 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:36,601 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:36,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:36,602 INFO L82 PathProgramCache]: Analyzing trace with hash 1003109554, now seen corresponding path program 1 times [2019-10-22 09:00:36,602 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:36,603 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1871141323] [2019-10-22 09:00:36,603 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:36,603 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:36,603 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:36,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:36,697 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-10-22 09:00:36,697 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1871141323] [2019-10-22 09:00:36,697 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:36,697 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:00:36,698 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571369561] [2019-10-22 09:00:36,698 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 09:00:36,698 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:36,698 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 09:00:36,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:36,699 INFO L87 Difference]: Start difference. First operand 1382 states and 1766 transitions. Second operand 5 states. [2019-10-22 09:00:36,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:36,916 INFO L93 Difference]: Finished difference Result 2508 states and 3252 transitions. [2019-10-22 09:00:36,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:00:36,917 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-10-22 09:00:36,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:36,919 INFO L225 Difference]: With dead ends: 2508 [2019-10-22 09:00:36,919 INFO L226 Difference]: Without dead ends: 1254 [2019-10-22 09:00:36,920 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:36,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1254 states. [2019-10-22 09:00:37,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1254 to 1254. [2019-10-22 09:00:37,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1254 states. [2019-10-22 09:00:37,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1254 states to 1254 states and 1618 transitions. [2019-10-22 09:00:37,074 INFO L78 Accepts]: Start accepts. Automaton has 1254 states and 1618 transitions. Word has length 132 [2019-10-22 09:00:37,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:37,074 INFO L462 AbstractCegarLoop]: Abstraction has 1254 states and 1618 transitions. [2019-10-22 09:00:37,074 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 09:00:37,074 INFO L276 IsEmpty]: Start isEmpty. Operand 1254 states and 1618 transitions. [2019-10-22 09:00:37,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-10-22 09:00:37,077 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:37,077 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:37,077 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:37,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:37,077 INFO L82 PathProgramCache]: Analyzing trace with hash 1193716731, now seen corresponding path program 1 times [2019-10-22 09:00:37,077 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:37,077 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045383992] [2019-10-22 09:00:37,078 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:37,078 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:37,078 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:37,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:37,145 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2019-10-22 09:00:37,145 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1045383992] [2019-10-22 09:00:37,146 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:37,146 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 09:00:37,146 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508921116] [2019-10-22 09:00:37,146 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 09:00:37,146 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:37,146 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 09:00:37,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-22 09:00:37,147 INFO L87 Difference]: Start difference. First operand 1254 states and 1618 transitions. Second operand 6 states. [2019-10-22 09:00:38,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:38,052 INFO L93 Difference]: Finished difference Result 6564 states and 8664 transitions. [2019-10-22 09:00:38,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-10-22 09:00:38,053 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 133 [2019-10-22 09:00:38,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:38,061 INFO L225 Difference]: With dead ends: 6564 [2019-10-22 09:00:38,061 INFO L226 Difference]: Without dead ends: 5491 [2019-10-22 09:00:38,065 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2019-10-22 09:00:38,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5491 states. [2019-10-22 09:00:38,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5491 to 1596. [2019-10-22 09:00:38,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1596 states. [2019-10-22 09:00:38,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1596 states to 1596 states and 2018 transitions. [2019-10-22 09:00:38,326 INFO L78 Accepts]: Start accepts. Automaton has 1596 states and 2018 transitions. Word has length 133 [2019-10-22 09:00:38,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:38,326 INFO L462 AbstractCegarLoop]: Abstraction has 1596 states and 2018 transitions. [2019-10-22 09:00:38,327 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 09:00:38,327 INFO L276 IsEmpty]: Start isEmpty. Operand 1596 states and 2018 transitions. [2019-10-22 09:00:38,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-10-22 09:00:38,329 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:38,329 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:38,329 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:38,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:38,330 INFO L82 PathProgramCache]: Analyzing trace with hash 2094959115, now seen corresponding path program 1 times [2019-10-22 09:00:38,330 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:38,330 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1924553128] [2019-10-22 09:00:38,330 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:38,330 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:38,330 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:38,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:38,559 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:38,559 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1924553128] [2019-10-22 09:00:38,559 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [739875035] [2019-10-22 09:00:38,559 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:38,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:38,696 INFO L256 TraceCheckSpWp]: Trace formula consists of 772 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-22 09:00:38,698 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 09:00:38,762 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-10-22 09:00:38,763 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-22 09:00:38,763 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-10-22 09:00:38,763 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [549528190] [2019-10-22 09:00:38,763 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-22 09:00:38,764 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:38,764 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-22 09:00:38,764 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-10-22 09:00:38,764 INFO L87 Difference]: Start difference. First operand 1596 states and 2018 transitions. Second operand 6 states. [2019-10-22 09:00:39,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:39,344 INFO L93 Difference]: Finished difference Result 4898 states and 6314 transitions. [2019-10-22 09:00:39,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-10-22 09:00:39,345 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 134 [2019-10-22 09:00:39,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:39,349 INFO L225 Difference]: With dead ends: 4898 [2019-10-22 09:00:39,350 INFO L226 Difference]: Without dead ends: 3463 [2019-10-22 09:00:39,352 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 131 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-10-22 09:00:39,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3463 states. [2019-10-22 09:00:39,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3463 to 1596. [2019-10-22 09:00:39,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1596 states. [2019-10-22 09:00:39,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1596 states to 1596 states and 2016 transitions. [2019-10-22 09:00:39,520 INFO L78 Accepts]: Start accepts. Automaton has 1596 states and 2016 transitions. Word has length 134 [2019-10-22 09:00:39,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:39,520 INFO L462 AbstractCegarLoop]: Abstraction has 1596 states and 2016 transitions. [2019-10-22 09:00:39,520 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-22 09:00:39,520 INFO L276 IsEmpty]: Start isEmpty. Operand 1596 states and 2016 transitions. [2019-10-22 09:00:39,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-10-22 09:00:39,523 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:39,523 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:39,723 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:39,724 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:39,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:39,724 INFO L82 PathProgramCache]: Analyzing trace with hash -1714435691, now seen corresponding path program 1 times [2019-10-22 09:00:39,724 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:39,724 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2072171813] [2019-10-22 09:00:39,724 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:39,724 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:39,725 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:39,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:39,906 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:39,906 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2072171813] [2019-10-22 09:00:39,906 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [609339464] [2019-10-22 09:00:39,906 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:40,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:40,040 INFO L256 TraceCheckSpWp]: Trace formula consists of 762 conjuncts, 46 conjunts are in the unsatisfiable core [2019-10-22 09:00:40,042 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 09:00:40,275 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:40,275 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-10-22 09:00:40,275 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-10-22 09:00:40,276 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28818617] [2019-10-22 09:00:40,276 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-10-22 09:00:40,276 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:40,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-10-22 09:00:40,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2019-10-22 09:00:40,277 INFO L87 Difference]: Start difference. First operand 1596 states and 2016 transitions. Second operand 21 states. [2019-10-22 09:00:42,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:42,087 INFO L93 Difference]: Finished difference Result 4380 states and 5555 transitions. [2019-10-22 09:00:42,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-22 09:00:42,088 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 134 [2019-10-22 09:00:42,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:42,092 INFO L225 Difference]: With dead ends: 4380 [2019-10-22 09:00:42,092 INFO L226 Difference]: Without dead ends: 2965 [2019-10-22 09:00:42,095 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 120 SyntacticMatches, 4 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 997 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=649, Invalid=3133, Unknown=0, NotChecked=0, Total=3782 [2019-10-22 09:00:42,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2965 states. [2019-10-22 09:00:42,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2965 to 1815. [2019-10-22 09:00:42,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1815 states. [2019-10-22 09:00:42,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1815 states to 1815 states and 2286 transitions. [2019-10-22 09:00:42,330 INFO L78 Accepts]: Start accepts. Automaton has 1815 states and 2286 transitions. Word has length 134 [2019-10-22 09:00:42,331 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:42,331 INFO L462 AbstractCegarLoop]: Abstraction has 1815 states and 2286 transitions. [2019-10-22 09:00:42,331 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-10-22 09:00:42,331 INFO L276 IsEmpty]: Start isEmpty. Operand 1815 states and 2286 transitions. [2019-10-22 09:00:42,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-10-22 09:00:42,334 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:42,334 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:42,534 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-22 09:00:42,535 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:42,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:42,535 INFO L82 PathProgramCache]: Analyzing trace with hash 1273389207, now seen corresponding path program 1 times [2019-10-22 09:00:42,535 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:42,535 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37034782] [2019-10-22 09:00:42,535 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:42,535 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:42,535 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:42,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:42,589 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2019-10-22 09:00:42,590 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37034782] [2019-10-22 09:00:42,590 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:42,590 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:00:42,590 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593719964] [2019-10-22 09:00:42,590 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:00:42,590 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:42,591 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:00:42,591 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:00:42,591 INFO L87 Difference]: Start difference. First operand 1815 states and 2286 transitions. Second operand 4 states. [2019-10-22 09:00:42,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:42,783 INFO L93 Difference]: Finished difference Result 3309 states and 4194 transitions. [2019-10-22 09:00:42,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-22 09:00:42,784 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 134 [2019-10-22 09:00:42,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:42,786 INFO L225 Difference]: With dead ends: 3309 [2019-10-22 09:00:42,786 INFO L226 Difference]: Without dead ends: 1620 [2019-10-22 09:00:42,787 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:00:42,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1620 states. [2019-10-22 09:00:42,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1620 to 1620. [2019-10-22 09:00:42,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1620 states. [2019-10-22 09:00:43,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1620 states to 1620 states and 2026 transitions. [2019-10-22 09:00:43,000 INFO L78 Accepts]: Start accepts. Automaton has 1620 states and 2026 transitions. Word has length 134 [2019-10-22 09:00:43,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:43,000 INFO L462 AbstractCegarLoop]: Abstraction has 1620 states and 2026 transitions. [2019-10-22 09:00:43,000 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:00:43,001 INFO L276 IsEmpty]: Start isEmpty. Operand 1620 states and 2026 transitions. [2019-10-22 09:00:43,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-22 09:00:43,002 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:43,003 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:43,003 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:43,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:43,003 INFO L82 PathProgramCache]: Analyzing trace with hash 1769777121, now seen corresponding path program 1 times [2019-10-22 09:00:43,004 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:43,004 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902513270] [2019-10-22 09:00:43,004 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:43,004 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:43,004 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:43,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 09:00:43,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 09:00:43,195 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 09:00:43,195 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-10-22 09:00:43,359 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.10 09:00:43 BoogieIcfgContainer [2019-10-22 09:00:43,359 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-10-22 09:00:43,359 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-10-22 09:00:43,359 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-10-22 09:00:43,360 INFO L275 PluginConnector]: Witness Printer initialized [2019-10-22 09:00:43,360 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 09:00:19" (3/4) ... [2019-10-22 09:00:43,362 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-10-22 09:00:43,530 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_6a5e62df-963a-4e84-8dfd-f7ef725433fe/bin/uautomizer/witness.graphml [2019-10-22 09:00:43,530 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-10-22 09:00:43,532 INFO L168 Benchmark]: Toolchain (without parser) took 25249.44 ms. Allocated memory was 1.0 GB in the beginning and 2.0 GB in the end (delta: 938.0 MB). Free memory was 944.5 MB in the beginning and 751.9 MB in the end (delta: 192.6 MB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. [2019-10-22 09:00:43,532 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 967.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-10-22 09:00:43,533 INFO L168 Benchmark]: CACSL2BoogieTranslator took 407.79 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 113.2 MB). Free memory was 939.1 MB in the beginning and 1.1 GB in the end (delta: -157.2 MB). Peak memory consumption was 17.8 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:43,533 INFO L168 Benchmark]: Boogie Procedure Inliner took 60.67 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:43,533 INFO L168 Benchmark]: Boogie Preprocessor took 55.72 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.8 MB). Peak memory consumption was 1.8 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:43,533 INFO L168 Benchmark]: RCFGBuilder took 1161.38 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 86.9 MB). Peak memory consumption was 86.9 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:43,534 INFO L168 Benchmark]: TraceAbstraction took 23389.04 ms. Allocated memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: 824.7 MB). Free memory was 993.3 MB in the beginning and 797.4 MB in the end (delta: 196.0 MB). Peak memory consumption was 1.0 GB. Max. memory is 11.5 GB. [2019-10-22 09:00:43,534 INFO L168 Benchmark]: Witness Printer took 171.21 ms. Allocated memory is still 2.0 GB. Free memory was 797.4 MB in the beginning and 751.9 MB in the end (delta: 45.4 MB). Peak memory consumption was 45.4 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:43,536 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 967.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 407.79 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 113.2 MB). Free memory was 939.1 MB in the beginning and 1.1 GB in the end (delta: -157.2 MB). Peak memory consumption was 17.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 60.67 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 55.72 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.8 MB). Peak memory consumption was 1.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1161.38 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 86.9 MB). Peak memory consumption was 86.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 23389.04 ms. Allocated memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: 824.7 MB). Free memory was 993.3 MB in the beginning and 797.4 MB in the end (delta: 196.0 MB). Peak memory consumption was 1.0 GB. Max. memory is 11.5 GB. * Witness Printer took 171.21 ms. Allocated memory is still 2.0 GB. Free memory was 797.4 MB in the beginning and 751.9 MB in the end (delta: 45.4 MB). Peak memory consumption was 45.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 653]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L455] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L577] int c1 ; [L578] int i2 ; [L581] c1 = 0 [L582] side1Failed = __VERIFIER_nondet_bool() [L583] side2Failed = __VERIFIER_nondet_bool() [L584] side1_written = __VERIFIER_nondet_char() [L585] side2_written = __VERIFIER_nondet_char() [L586] side1Failed_History_0 = __VERIFIER_nondet_bool() [L587] side1Failed_History_1 = __VERIFIER_nondet_bool() [L588] side1Failed_History_2 = __VERIFIER_nondet_bool() [L589] side2Failed_History_0 = __VERIFIER_nondet_bool() [L590] side2Failed_History_1 = __VERIFIER_nondet_bool() [L591] side2Failed_History_2 = __VERIFIER_nondet_bool() [L592] active_side_History_0 = __VERIFIER_nondet_char() [L593] active_side_History_1 = __VERIFIER_nondet_char() [L594] active_side_History_2 = __VERIFIER_nondet_char() [L595] manual_selection_History_0 = __VERIFIER_nondet_char() [L596] manual_selection_History_1 = __VERIFIER_nondet_char() [L597] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L598] i2 = init() [L600] cs1_old = nomsg [L601] cs1_new = nomsg [L602] cs2_old = nomsg [L603] cs2_new = nomsg [L604] s1s2_old = nomsg [L605] s1s2_new = nomsg [L606] s1s1_old = nomsg [L607] s1s1_new = nomsg [L608] s2s1_old = nomsg [L609] s2s1_new = nomsg [L610] s2s2_old = nomsg [L611] s2s2_new = nomsg [L612] s1p_old = nomsg [L613] s1p_new = nomsg [L614] s2p_old = nomsg [L615] s2p_new = nomsg [L616] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE 1 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L485] COND TRUE ! side2Failed [L486] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] tmp___1 = read_side1_failed_history((unsigned char)1) [L494] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L495] tmp___2 = read_side1_failed_history((unsigned char)0) [L496] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] tmp___11 = read_side1_failed_history((unsigned char)1) [L538] COND TRUE ! tmp___11 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L539] tmp___12 = read_side2_failed_history((unsigned char)1) [L540] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L553] tmp___20 = read_active_side_history((unsigned char)2) [L554] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L572] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L651] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE 1 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND FALSE !(\read(side1Failed)) [L326] side1 = s1s1_old [L327] s1s1_old = nomsg [L328] side2 = s2s1_old [L329] s2s1_old = nomsg [L330] manual_selection = cs1_old [L331] cs1_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L332] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L335] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L336] COND TRUE (int )side2 != (int )nomsg [L337] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] EXPR next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] s1s1_new = next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new [L357] EXPR next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L357] s1s2_new = next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new [L358] EXPR next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L358] s1p_new = next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new [L359] side1_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND TRUE \read(side2Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] EXPR nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] s2s1_new = nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new [L378] EXPR nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L378] s2s2_new = nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new [L379] EXPR nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L379] s2p_new = nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new [L380] side2_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND TRUE ! side1Failed [L483] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND FALSE !(! tmp___0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND TRUE \read(tmp___7) [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L523] tmp___8 = read_side2_failed_history((unsigned char)1) [L524] COND TRUE ! tmp___8 [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L525] tmp___5 = read_active_side_history((unsigned char)0) [L526] COND TRUE ! ((int )tmp___5 == 2) [L527] return (0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L651] COND TRUE ! arg VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L653] __VERIFIER_error() VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 290 locations, 23 error locations. Result: UNSAFE, OverallTime: 23.3s, OverallIterations: 37, TraceHistogramMax: 2, AutomataDifference: 12.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 15650 SDtfs, 27851 SDslu, 35782 SDs, 0 SdLazy, 5608 SolverSat, 397 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1315 GetRequests, 943 SyntacticMatches, 19 SemanticMatches, 353 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3347 ImplicationChecksByTransitivity, 4.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1815occurred in iteration=35, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 2.9s AutomataMinimizationTime, 36 MinimizatonAttempts, 21843 StatesRemovedByMinimization, 32 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.3s SsaConstructionTime, 1.4s SatisfiabilityAnalysisTime, 3.6s InterpolantComputationTime, 4062 NumberOfCodeBlocks, 4062 NumberOfCodeBlocksAsserted, 44 NumberOfCheckSat, 3884 ConstructedInterpolants, 0 QuantifiedInterpolants, 1555146 SizeOfPredicates, 38 NumberOfNonLiveVariables, 5238 ConjunctsInSsa, 136 ConjunctsInUnsatCore, 43 InterpolantComputations, 34 PerfectInterpolantSequences, 576/673 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...