./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/toy2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/toy2.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c8989412e094655bcf4508d76eb9764ed06d0b34 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-10-22 09:02:11,322 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-22 09:02:11,324 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-22 09:02:11,334 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-22 09:02:11,335 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-22 09:02:11,336 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-22 09:02:11,337 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-22 09:02:11,339 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-22 09:02:11,340 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-22 09:02:11,343 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-22 09:02:11,345 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-22 09:02:11,346 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-22 09:02:11,351 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-22 09:02:11,352 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-22 09:02:11,353 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-22 09:02:11,354 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-22 09:02:11,354 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-22 09:02:11,355 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-22 09:02:11,356 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-22 09:02:11,360 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-22 09:02:11,361 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-22 09:02:11,362 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-22 09:02:11,363 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-22 09:02:11,364 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-22 09:02:11,369 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-22 09:02:11,371 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-22 09:02:11,371 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-22 09:02:11,372 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-22 09:02:11,374 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-22 09:02:11,375 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-22 09:02:11,376 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-22 09:02:11,377 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-22 09:02:11,377 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-22 09:02:11,378 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-22 09:02:11,379 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-22 09:02:11,380 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-22 09:02:11,381 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-22 09:02:11,382 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-22 09:02:11,382 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-22 09:02:11,382 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-22 09:02:11,383 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-22 09:02:11,384 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-22 09:02:11,405 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-22 09:02:11,405 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-22 09:02:11,406 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-22 09:02:11,406 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-22 09:02:11,407 INFO L138 SettingsManager]: * Use SBE=true [2019-10-22 09:02:11,407 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-22 09:02:11,407 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-22 09:02:11,407 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-22 09:02:11,407 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-22 09:02:11,407 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-22 09:02:11,407 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-22 09:02:11,408 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-22 09:02:11,408 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-22 09:02:11,408 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-22 09:02:11,408 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-22 09:02:11,408 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-22 09:02:11,408 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-22 09:02:11,408 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-22 09:02:11,408 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-22 09:02:11,409 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-22 09:02:11,411 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-22 09:02:11,411 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-22 09:02:11,411 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-22 09:02:11,411 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-22 09:02:11,411 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-22 09:02:11,412 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-22 09:02:11,412 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-22 09:02:11,412 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-22 09:02:11,412 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c8989412e094655bcf4508d76eb9764ed06d0b34 [2019-10-22 09:02:11,443 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-22 09:02:11,455 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-22 09:02:11,459 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-22 09:02:11,460 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-22 09:02:11,461 INFO L275 PluginConnector]: CDTParser initialized [2019-10-22 09:02:11,461 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/../../sv-benchmarks/c/systemc/toy2.cil.c [2019-10-22 09:02:11,518 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/data/36908576f/bd357fa671a144658622282ad34a3a9f/FLAGc9e17a963 [2019-10-22 09:02:11,968 INFO L306 CDTParser]: Found 1 translation units. [2019-10-22 09:02:11,968 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/sv-benchmarks/c/systemc/toy2.cil.c [2019-10-22 09:02:11,982 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/data/36908576f/bd357fa671a144658622282ad34a3a9f/FLAGc9e17a963 [2019-10-22 09:02:12,482 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/data/36908576f/bd357fa671a144658622282ad34a3a9f [2019-10-22 09:02:12,486 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-22 09:02:12,488 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-10-22 09:02:12,488 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-22 09:02:12,489 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-22 09:02:12,495 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-22 09:02:12,496 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 09:02:12" (1/1) ... [2019-10-22 09:02:12,498 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@668f3393 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12, skipping insertion in model container [2019-10-22 09:02:12,498 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 09:02:12" (1/1) ... [2019-10-22 09:02:12,509 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-22 09:02:12,541 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-22 09:02:12,816 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 09:02:12,823 INFO L188 MainTranslator]: Completed pre-run [2019-10-22 09:02:12,867 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 09:02:12,882 INFO L192 MainTranslator]: Completed translation [2019-10-22 09:02:12,882 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12 WrapperNode [2019-10-22 09:02:12,882 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-22 09:02:12,883 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-10-22 09:02:12,883 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-10-22 09:02:12,883 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-10-22 09:02:12,891 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12" (1/1) ... [2019-10-22 09:02:12,898 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12" (1/1) ... [2019-10-22 09:02:12,921 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-10-22 09:02:12,922 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-22 09:02:12,922 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-22 09:02:12,922 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-22 09:02:12,931 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12" (1/1) ... [2019-10-22 09:02:12,932 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12" (1/1) ... [2019-10-22 09:02:12,934 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12" (1/1) ... [2019-10-22 09:02:12,934 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12" (1/1) ... [2019-10-22 09:02:12,939 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12" (1/1) ... [2019-10-22 09:02:12,947 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12" (1/1) ... [2019-10-22 09:02:12,949 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12" (1/1) ... [2019-10-22 09:02:12,960 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-22 09:02:12,961 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-22 09:02:12,961 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-22 09:02:12,961 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-22 09:02:12,962 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-22 09:02:13,041 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-22 09:02:13,041 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-22 09:02:13,639 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-22 09:02:13,639 INFO L284 CfgBuilder]: Removed 26 assume(true) statements. [2019-10-22 09:02:13,640 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 09:02:13 BoogieIcfgContainer [2019-10-22 09:02:13,641 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-22 09:02:13,642 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-22 09:02:13,642 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-22 09:02:13,645 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-22 09:02:13,645 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 22.10 09:02:12" (1/3) ... [2019-10-22 09:02:13,647 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@65f575aa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.10 09:02:13, skipping insertion in model container [2019-10-22 09:02:13,647 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 09:02:12" (2/3) ... [2019-10-22 09:02:13,647 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@65f575aa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.10 09:02:13, skipping insertion in model container [2019-10-22 09:02:13,653 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 09:02:13" (3/3) ... [2019-10-22 09:02:13,655 INFO L109 eAbstractionObserver]: Analyzing ICFG toy2.cil.c [2019-10-22 09:02:13,681 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-22 09:02:13,689 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-22 09:02:13,709 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-22 09:02:13,759 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-22 09:02:13,759 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-22 09:02:13,759 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-22 09:02:13,759 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-22 09:02:13,759 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-22 09:02:13,759 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-22 09:02:13,759 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-22 09:02:13,759 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-22 09:02:13,787 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states. [2019-10-22 09:02:13,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-10-22 09:02:13,809 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:13,810 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:13,811 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:13,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:13,817 INFO L82 PathProgramCache]: Analyzing trace with hash 1633671955, now seen corresponding path program 1 times [2019-10-22 09:02:13,829 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:13,830 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593240998] [2019-10-22 09:02:13,830 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:13,830 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:13,830 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:13,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:14,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:14,011 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1593240998] [2019-10-22 09:02:14,012 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:14,012 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:14,013 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679199530] [2019-10-22 09:02:14,016 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:14,017 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:14,029 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:14,030 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:14,032 INFO L87 Difference]: Start difference. First operand 125 states. Second operand 3 states. [2019-10-22 09:02:14,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:14,074 INFO L93 Difference]: Finished difference Result 242 states and 449 transitions. [2019-10-22 09:02:14,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:14,075 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-10-22 09:02:14,076 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:14,086 INFO L225 Difference]: With dead ends: 242 [2019-10-22 09:02:14,086 INFO L226 Difference]: Without dead ends: 121 [2019-10-22 09:02:14,090 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:14,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2019-10-22 09:02:14,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 121. [2019-10-22 09:02:14,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2019-10-22 09:02:14,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 213 transitions. [2019-10-22 09:02:14,129 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 213 transitions. Word has length 35 [2019-10-22 09:02:14,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:14,129 INFO L462 AbstractCegarLoop]: Abstraction has 121 states and 213 transitions. [2019-10-22 09:02:14,129 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:14,129 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 213 transitions. [2019-10-22 09:02:14,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-10-22 09:02:14,131 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:14,131 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:14,131 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:14,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:14,131 INFO L82 PathProgramCache]: Analyzing trace with hash 1611039701, now seen corresponding path program 1 times [2019-10-22 09:02:14,132 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:14,132 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953938039] [2019-10-22 09:02:14,132 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:14,132 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:14,132 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:14,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:14,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:14,174 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [953938039] [2019-10-22 09:02:14,174 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:14,174 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:14,174 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71987167] [2019-10-22 09:02:14,176 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:14,176 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:14,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:14,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:14,177 INFO L87 Difference]: Start difference. First operand 121 states and 213 transitions. Second operand 3 states. [2019-10-22 09:02:14,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:14,201 INFO L93 Difference]: Finished difference Result 232 states and 410 transitions. [2019-10-22 09:02:14,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:14,202 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-10-22 09:02:14,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:14,203 INFO L225 Difference]: With dead ends: 232 [2019-10-22 09:02:14,204 INFO L226 Difference]: Without dead ends: 121 [2019-10-22 09:02:14,207 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:14,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2019-10-22 09:02:14,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 121. [2019-10-22 09:02:14,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2019-10-22 09:02:14,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 212 transitions. [2019-10-22 09:02:14,219 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 212 transitions. Word has length 35 [2019-10-22 09:02:14,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:14,219 INFO L462 AbstractCegarLoop]: Abstraction has 121 states and 212 transitions. [2019-10-22 09:02:14,219 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:14,219 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 212 transitions. [2019-10-22 09:02:14,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-10-22 09:02:14,220 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:14,220 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:14,220 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:14,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:14,220 INFO L82 PathProgramCache]: Analyzing trace with hash 1101566611, now seen corresponding path program 1 times [2019-10-22 09:02:14,220 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:14,220 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451685954] [2019-10-22 09:02:14,221 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:14,221 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:14,221 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:14,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:14,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:14,284 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451685954] [2019-10-22 09:02:14,284 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:14,284 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:14,284 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271615400] [2019-10-22 09:02:14,284 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:14,285 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:14,285 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:14,285 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:14,285 INFO L87 Difference]: Start difference. First operand 121 states and 212 transitions. Second operand 3 states. [2019-10-22 09:02:14,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:14,441 INFO L93 Difference]: Finished difference Result 316 states and 553 transitions. [2019-10-22 09:02:14,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:14,441 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-10-22 09:02:14,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:14,443 INFO L225 Difference]: With dead ends: 316 [2019-10-22 09:02:14,443 INFO L226 Difference]: Without dead ends: 206 [2019-10-22 09:02:14,444 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:14,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2019-10-22 09:02:14,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 196. [2019-10-22 09:02:14,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 196 states. [2019-10-22 09:02:14,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 330 transitions. [2019-10-22 09:02:14,465 INFO L78 Accepts]: Start accepts. Automaton has 196 states and 330 transitions. Word has length 35 [2019-10-22 09:02:14,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:14,468 INFO L462 AbstractCegarLoop]: Abstraction has 196 states and 330 transitions. [2019-10-22 09:02:14,468 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:14,468 INFO L276 IsEmpty]: Start isEmpty. Operand 196 states and 330 transitions. [2019-10-22 09:02:14,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-10-22 09:02:14,469 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:14,470 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:14,470 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:14,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:14,470 INFO L82 PathProgramCache]: Analyzing trace with hash 197658071, now seen corresponding path program 1 times [2019-10-22 09:02:14,470 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:14,471 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366915697] [2019-10-22 09:02:14,471 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:14,471 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:14,471 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:14,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:14,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:14,510 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1366915697] [2019-10-22 09:02:14,510 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:14,510 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:02:14,510 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101673691] [2019-10-22 09:02:14,511 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:02:14,511 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:14,511 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:02:14,511 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:02:14,511 INFO L87 Difference]: Start difference. First operand 196 states and 330 transitions. Second operand 4 states. [2019-10-22 09:02:14,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:14,619 INFO L93 Difference]: Finished difference Result 530 states and 896 transitions. [2019-10-22 09:02:14,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:02:14,620 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-10-22 09:02:14,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:14,622 INFO L225 Difference]: With dead ends: 530 [2019-10-22 09:02:14,622 INFO L226 Difference]: Without dead ends: 346 [2019-10-22 09:02:14,623 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:02:14,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346 states. [2019-10-22 09:02:14,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346 to 340. [2019-10-22 09:02:14,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2019-10-22 09:02:14,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 572 transitions. [2019-10-22 09:02:14,652 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 572 transitions. Word has length 35 [2019-10-22 09:02:14,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:14,652 INFO L462 AbstractCegarLoop]: Abstraction has 340 states and 572 transitions. [2019-10-22 09:02:14,652 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:02:14,652 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 572 transitions. [2019-10-22 09:02:14,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-10-22 09:02:14,658 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:14,658 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:14,658 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:14,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:14,658 INFO L82 PathProgramCache]: Analyzing trace with hash 259697685, now seen corresponding path program 1 times [2019-10-22 09:02:14,659 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:14,659 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748504826] [2019-10-22 09:02:14,659 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:14,659 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:14,659 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:14,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:14,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:14,732 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748504826] [2019-10-22 09:02:14,732 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:14,732 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:02:14,732 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806899670] [2019-10-22 09:02:14,733 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:02:14,733 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:14,733 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:02:14,733 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:02:14,734 INFO L87 Difference]: Start difference. First operand 340 states and 572 transitions. Second operand 4 states. [2019-10-22 09:02:14,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:14,830 INFO L93 Difference]: Finished difference Result 955 states and 1611 transitions. [2019-10-22 09:02:14,830 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:02:14,830 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-10-22 09:02:14,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:14,833 INFO L225 Difference]: With dead ends: 955 [2019-10-22 09:02:14,833 INFO L226 Difference]: Without dead ends: 628 [2019-10-22 09:02:14,835 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:02:14,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 628 states. [2019-10-22 09:02:14,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 628 to 622. [2019-10-22 09:02:14,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2019-10-22 09:02:14,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 1042 transitions. [2019-10-22 09:02:14,871 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 1042 transitions. Word has length 35 [2019-10-22 09:02:14,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:14,871 INFO L462 AbstractCegarLoop]: Abstraction has 622 states and 1042 transitions. [2019-10-22 09:02:14,872 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:02:14,872 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 1042 transitions. [2019-10-22 09:02:14,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-10-22 09:02:14,873 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:14,873 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:14,881 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:14,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:14,881 INFO L82 PathProgramCache]: Analyzing trace with hash 400246295, now seen corresponding path program 1 times [2019-10-22 09:02:14,881 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:14,882 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257042023] [2019-10-22 09:02:14,882 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:14,882 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:14,882 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:14,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:14,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:14,944 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257042023] [2019-10-22 09:02:14,944 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:14,944 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:02:14,944 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815493244] [2019-10-22 09:02:14,946 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:02:14,946 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:14,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:02:14,947 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:02:14,947 INFO L87 Difference]: Start difference. First operand 622 states and 1042 transitions. Second operand 4 states. [2019-10-22 09:02:15,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:15,087 INFO L93 Difference]: Finished difference Result 1891 states and 3148 transitions. [2019-10-22 09:02:15,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:02:15,089 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-10-22 09:02:15,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:15,094 INFO L225 Difference]: With dead ends: 1891 [2019-10-22 09:02:15,094 INFO L226 Difference]: Without dead ends: 1283 [2019-10-22 09:02:15,096 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:02:15,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1283 states. [2019-10-22 09:02:15,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1283 to 1277. [2019-10-22 09:02:15,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1277 states. [2019-10-22 09:02:15,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1277 states to 1277 states and 2102 transitions. [2019-10-22 09:02:15,165 INFO L78 Accepts]: Start accepts. Automaton has 1277 states and 2102 transitions. Word has length 35 [2019-10-22 09:02:15,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:15,167 INFO L462 AbstractCegarLoop]: Abstraction has 1277 states and 2102 transitions. [2019-10-22 09:02:15,167 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:02:15,167 INFO L276 IsEmpty]: Start isEmpty. Operand 1277 states and 2102 transitions. [2019-10-22 09:02:15,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-10-22 09:02:15,171 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:15,171 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:15,171 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:15,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:15,172 INFO L82 PathProgramCache]: Analyzing trace with hash 266232789, now seen corresponding path program 1 times [2019-10-22 09:02:15,172 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:15,172 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472484857] [2019-10-22 09:02:15,172 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:15,172 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:15,173 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:15,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:15,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:15,252 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472484857] [2019-10-22 09:02:15,252 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:15,252 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:15,252 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2073233577] [2019-10-22 09:02:15,253 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:15,253 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:15,253 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:15,253 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:15,253 INFO L87 Difference]: Start difference. First operand 1277 states and 2102 transitions. Second operand 3 states. [2019-10-22 09:02:15,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:15,374 INFO L93 Difference]: Finished difference Result 2603 states and 4295 transitions. [2019-10-22 09:02:15,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:15,374 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-10-22 09:02:15,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:15,381 INFO L225 Difference]: With dead ends: 2603 [2019-10-22 09:02:15,381 INFO L226 Difference]: Without dead ends: 1383 [2019-10-22 09:02:15,383 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:15,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1383 states. [2019-10-22 09:02:15,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1383 to 1376. [2019-10-22 09:02:15,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1376 states. [2019-10-22 09:02:15,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1376 states to 1376 states and 2257 transitions. [2019-10-22 09:02:15,440 INFO L78 Accepts]: Start accepts. Automaton has 1376 states and 2257 transitions. Word has length 35 [2019-10-22 09:02:15,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:15,440 INFO L462 AbstractCegarLoop]: Abstraction has 1376 states and 2257 transitions. [2019-10-22 09:02:15,440 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:15,440 INFO L276 IsEmpty]: Start isEmpty. Operand 1376 states and 2257 transitions. [2019-10-22 09:02:15,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-10-22 09:02:15,442 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:15,442 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:15,443 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:15,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:15,443 INFO L82 PathProgramCache]: Analyzing trace with hash -1908921127, now seen corresponding path program 1 times [2019-10-22 09:02:15,443 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:15,443 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789400351] [2019-10-22 09:02:15,443 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:15,444 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:15,444 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:15,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:15,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:15,480 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [789400351] [2019-10-22 09:02:15,481 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:15,481 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:02:15,481 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662104207] [2019-10-22 09:02:15,481 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:02:15,482 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:15,482 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:02:15,482 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:02:15,482 INFO L87 Difference]: Start difference. First operand 1376 states and 2257 transitions. Second operand 4 states. [2019-10-22 09:02:15,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:15,612 INFO L93 Difference]: Finished difference Result 2882 states and 4737 transitions. [2019-10-22 09:02:15,612 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-22 09:02:15,613 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-10-22 09:02:15,613 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:15,618 INFO L225 Difference]: With dead ends: 2882 [2019-10-22 09:02:15,618 INFO L226 Difference]: Without dead ends: 1540 [2019-10-22 09:02:15,620 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:02:15,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1540 states. [2019-10-22 09:02:15,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1540 to 1529. [2019-10-22 09:02:15,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1529 states. [2019-10-22 09:02:15,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1529 states to 1529 states and 2471 transitions. [2019-10-22 09:02:15,708 INFO L78 Accepts]: Start accepts. Automaton has 1529 states and 2471 transitions. Word has length 35 [2019-10-22 09:02:15,708 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:15,708 INFO L462 AbstractCegarLoop]: Abstraction has 1529 states and 2471 transitions. [2019-10-22 09:02:15,708 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:02:15,708 INFO L276 IsEmpty]: Start isEmpty. Operand 1529 states and 2471 transitions. [2019-10-22 09:02:15,709 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-10-22 09:02:15,709 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:15,709 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:15,709 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:15,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:15,710 INFO L82 PathProgramCache]: Analyzing trace with hash 1364977815, now seen corresponding path program 1 times [2019-10-22 09:02:15,710 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:15,710 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083284125] [2019-10-22 09:02:15,710 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:15,710 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:15,710 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:15,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:15,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:15,739 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083284125] [2019-10-22 09:02:15,740 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:15,740 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:02:15,740 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266568545] [2019-10-22 09:02:15,740 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:02:15,741 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:15,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:02:15,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:02:15,741 INFO L87 Difference]: Start difference. First operand 1529 states and 2471 transitions. Second operand 4 states. [2019-10-22 09:02:15,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:15,869 INFO L93 Difference]: Finished difference Result 3348 states and 5416 transitions. [2019-10-22 09:02:15,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-22 09:02:15,870 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-10-22 09:02:15,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:15,876 INFO L225 Difference]: With dead ends: 3348 [2019-10-22 09:02:15,876 INFO L226 Difference]: Without dead ends: 1865 [2019-10-22 09:02:15,879 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:02:15,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1865 states. [2019-10-22 09:02:15,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1865 to 1841. [2019-10-22 09:02:15,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1841 states. [2019-10-22 09:02:15,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1841 states to 1841 states and 2935 transitions. [2019-10-22 09:02:15,949 INFO L78 Accepts]: Start accepts. Automaton has 1841 states and 2935 transitions. Word has length 35 [2019-10-22 09:02:15,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:15,950 INFO L462 AbstractCegarLoop]: Abstraction has 1841 states and 2935 transitions. [2019-10-22 09:02:15,950 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:02:15,950 INFO L276 IsEmpty]: Start isEmpty. Operand 1841 states and 2935 transitions. [2019-10-22 09:02:15,950 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-10-22 09:02:15,950 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:15,951 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:15,951 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:15,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:15,955 INFO L82 PathProgramCache]: Analyzing trace with hash 353860565, now seen corresponding path program 1 times [2019-10-22 09:02:15,956 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:15,956 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014027413] [2019-10-22 09:02:15,956 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:15,956 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:15,956 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:15,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:15,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:15,988 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014027413] [2019-10-22 09:02:15,988 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:15,988 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:15,989 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556263591] [2019-10-22 09:02:15,989 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:15,989 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:15,989 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:15,989 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:15,989 INFO L87 Difference]: Start difference. First operand 1841 states and 2935 transitions. Second operand 3 states. [2019-10-22 09:02:16,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:16,070 INFO L93 Difference]: Finished difference Result 3307 states and 5278 transitions. [2019-10-22 09:02:16,071 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:16,071 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-10-22 09:02:16,071 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:16,077 INFO L225 Difference]: With dead ends: 3307 [2019-10-22 09:02:16,077 INFO L226 Difference]: Without dead ends: 1494 [2019-10-22 09:02:16,080 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:16,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1494 states. [2019-10-22 09:02:16,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1494 to 1483. [2019-10-22 09:02:16,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1483 states. [2019-10-22 09:02:16,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1483 states to 1483 states and 2335 transitions. [2019-10-22 09:02:16,135 INFO L78 Accepts]: Start accepts. Automaton has 1483 states and 2335 transitions. Word has length 35 [2019-10-22 09:02:16,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:16,136 INFO L462 AbstractCegarLoop]: Abstraction has 1483 states and 2335 transitions. [2019-10-22 09:02:16,136 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:16,136 INFO L276 IsEmpty]: Start isEmpty. Operand 1483 states and 2335 transitions. [2019-10-22 09:02:16,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-10-22 09:02:16,137 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:16,138 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:16,138 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:16,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:16,138 INFO L82 PathProgramCache]: Analyzing trace with hash -209495903, now seen corresponding path program 1 times [2019-10-22 09:02:16,138 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:16,138 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619611516] [2019-10-22 09:02:16,138 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:16,139 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:16,139 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:16,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:16,169 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:16,169 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619611516] [2019-10-22 09:02:16,169 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:16,169 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:16,169 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085530099] [2019-10-22 09:02:16,170 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:16,170 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:16,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:16,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:16,170 INFO L87 Difference]: Start difference. First operand 1483 states and 2335 transitions. Second operand 3 states. [2019-10-22 09:02:16,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:16,254 INFO L93 Difference]: Finished difference Result 3698 states and 5877 transitions. [2019-10-22 09:02:16,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:16,255 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2019-10-22 09:02:16,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:16,262 INFO L225 Difference]: With dead ends: 3698 [2019-10-22 09:02:16,262 INFO L226 Difference]: Without dead ends: 2269 [2019-10-22 09:02:16,264 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:16,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2269 states. [2019-10-22 09:02:16,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2269 to 2267. [2019-10-22 09:02:16,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2267 states. [2019-10-22 09:02:16,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2267 states to 2267 states and 3563 transitions. [2019-10-22 09:02:16,347 INFO L78 Accepts]: Start accepts. Automaton has 2267 states and 3563 transitions. Word has length 45 [2019-10-22 09:02:16,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:16,347 INFO L462 AbstractCegarLoop]: Abstraction has 2267 states and 3563 transitions. [2019-10-22 09:02:16,348 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:16,348 INFO L276 IsEmpty]: Start isEmpty. Operand 2267 states and 3563 transitions. [2019-10-22 09:02:16,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-10-22 09:02:16,349 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:16,350 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:16,350 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:16,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:16,350 INFO L82 PathProgramCache]: Analyzing trace with hash 214150819, now seen corresponding path program 1 times [2019-10-22 09:02:16,350 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:16,350 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401076622] [2019-10-22 09:02:16,350 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:16,351 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:16,351 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:16,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:16,373 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-10-22 09:02:16,373 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1401076622] [2019-10-22 09:02:16,374 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:16,374 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:16,374 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007657191] [2019-10-22 09:02:16,374 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:16,374 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:16,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:16,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:16,375 INFO L87 Difference]: Start difference. First operand 2267 states and 3563 transitions. Second operand 3 states. [2019-10-22 09:02:16,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:16,456 INFO L93 Difference]: Finished difference Result 4436 states and 7000 transitions. [2019-10-22 09:02:16,456 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:16,457 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2019-10-22 09:02:16,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:16,464 INFO L225 Difference]: With dead ends: 4436 [2019-10-22 09:02:16,464 INFO L226 Difference]: Without dead ends: 2223 [2019-10-22 09:02:16,467 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:16,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2223 states. [2019-10-22 09:02:16,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2223 to 2223. [2019-10-22 09:02:16,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2223 states. [2019-10-22 09:02:16,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2223 states to 2223 states and 3506 transitions. [2019-10-22 09:02:16,554 INFO L78 Accepts]: Start accepts. Automaton has 2223 states and 3506 transitions. Word has length 45 [2019-10-22 09:02:16,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:16,554 INFO L462 AbstractCegarLoop]: Abstraction has 2223 states and 3506 transitions. [2019-10-22 09:02:16,554 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:16,554 INFO L276 IsEmpty]: Start isEmpty. Operand 2223 states and 3506 transitions. [2019-10-22 09:02:16,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-10-22 09:02:16,556 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:16,556 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:16,556 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:16,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:16,556 INFO L82 PathProgramCache]: Analyzing trace with hash 1700232685, now seen corresponding path program 1 times [2019-10-22 09:02:16,557 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:16,557 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886715971] [2019-10-22 09:02:16,557 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:16,557 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:16,557 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:16,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:16,583 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:16,583 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886715971] [2019-10-22 09:02:16,583 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:16,583 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:16,583 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462769296] [2019-10-22 09:02:16,584 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:16,584 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:16,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:16,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:16,584 INFO L87 Difference]: Start difference. First operand 2223 states and 3506 transitions. Second operand 3 states. [2019-10-22 09:02:16,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:16,758 INFO L93 Difference]: Finished difference Result 5707 states and 9064 transitions. [2019-10-22 09:02:16,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:16,758 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-10-22 09:02:16,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:16,771 INFO L225 Difference]: With dead ends: 5707 [2019-10-22 09:02:16,771 INFO L226 Difference]: Without dead ends: 3538 [2019-10-22 09:02:16,775 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:16,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3538 states. [2019-10-22 09:02:16,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3538 to 3536. [2019-10-22 09:02:16,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3536 states. [2019-10-22 09:02:16,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3536 states to 3536 states and 5558 transitions. [2019-10-22 09:02:16,980 INFO L78 Accepts]: Start accepts. Automaton has 3536 states and 5558 transitions. Word has length 46 [2019-10-22 09:02:16,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:16,980 INFO L462 AbstractCegarLoop]: Abstraction has 3536 states and 5558 transitions. [2019-10-22 09:02:16,980 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:16,980 INFO L276 IsEmpty]: Start isEmpty. Operand 3536 states and 5558 transitions. [2019-10-22 09:02:16,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-10-22 09:02:16,982 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:16,982 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:16,982 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:16,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:16,983 INFO L82 PathProgramCache]: Analyzing trace with hash 1601371510, now seen corresponding path program 1 times [2019-10-22 09:02:16,983 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:16,983 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977887447] [2019-10-22 09:02:16,983 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:16,983 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:16,983 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:16,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:17,021 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:17,022 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977887447] [2019-10-22 09:02:17,022 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:17,022 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:17,022 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1625690372] [2019-10-22 09:02:17,022 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:17,023 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:17,023 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:17,023 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:17,023 INFO L87 Difference]: Start difference. First operand 3536 states and 5558 transitions. Second operand 3 states. [2019-10-22 09:02:17,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:17,280 INFO L93 Difference]: Finished difference Result 8979 states and 14292 transitions. [2019-10-22 09:02:17,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:17,281 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-10-22 09:02:17,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:17,300 INFO L225 Difference]: With dead ends: 8979 [2019-10-22 09:02:17,300 INFO L226 Difference]: Without dead ends: 5501 [2019-10-22 09:02:17,304 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:17,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5501 states. [2019-10-22 09:02:17,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5501 to 5499. [2019-10-22 09:02:17,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5499 states. [2019-10-22 09:02:17,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5499 states to 5499 states and 8711 transitions. [2019-10-22 09:02:17,580 INFO L78 Accepts]: Start accepts. Automaton has 5499 states and 8711 transitions. Word has length 47 [2019-10-22 09:02:17,581 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:17,582 INFO L462 AbstractCegarLoop]: Abstraction has 5499 states and 8711 transitions. [2019-10-22 09:02:17,582 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:17,582 INFO L276 IsEmpty]: Start isEmpty. Operand 5499 states and 8711 transitions. [2019-10-22 09:02:17,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-10-22 09:02:17,585 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:17,585 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:17,585 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:17,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:17,585 INFO L82 PathProgramCache]: Analyzing trace with hash 2025018232, now seen corresponding path program 1 times [2019-10-22 09:02:17,585 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:17,586 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506346432] [2019-10-22 09:02:17,586 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:17,586 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:17,586 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:17,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:17,603 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-10-22 09:02:17,603 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [506346432] [2019-10-22 09:02:17,603 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:17,603 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:17,603 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884552265] [2019-10-22 09:02:17,604 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:17,604 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:17,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:17,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:17,604 INFO L87 Difference]: Start difference. First operand 5499 states and 8711 transitions. Second operand 3 states. [2019-10-22 09:02:17,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:17,830 INFO L93 Difference]: Finished difference Result 10896 states and 17296 transitions. [2019-10-22 09:02:17,830 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:17,830 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-10-22 09:02:17,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:17,862 INFO L225 Difference]: With dead ends: 10896 [2019-10-22 09:02:17,862 INFO L226 Difference]: Without dead ends: 5455 [2019-10-22 09:02:17,868 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:17,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5455 states. [2019-10-22 09:02:18,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5455 to 5455. [2019-10-22 09:02:18,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5455 states. [2019-10-22 09:02:18,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5455 states to 5455 states and 8656 transitions. [2019-10-22 09:02:18,215 INFO L78 Accepts]: Start accepts. Automaton has 5455 states and 8656 transitions. Word has length 47 [2019-10-22 09:02:18,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:18,215 INFO L462 AbstractCegarLoop]: Abstraction has 5455 states and 8656 transitions. [2019-10-22 09:02:18,215 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:18,216 INFO L276 IsEmpty]: Start isEmpty. Operand 5455 states and 8656 transitions. [2019-10-22 09:02:18,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-10-22 09:02:18,219 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:18,219 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:18,219 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:18,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:18,220 INFO L82 PathProgramCache]: Analyzing trace with hash -2129316584, now seen corresponding path program 1 times [2019-10-22 09:02:18,220 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:18,220 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [325823011] [2019-10-22 09:02:18,220 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:18,220 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:18,220 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:18,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:18,244 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:18,244 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [325823011] [2019-10-22 09:02:18,244 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:18,244 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:18,244 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [524126059] [2019-10-22 09:02:18,245 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:18,245 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:18,245 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:18,245 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:18,245 INFO L87 Difference]: Start difference. First operand 5455 states and 8656 transitions. Second operand 3 states. [2019-10-22 09:02:18,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:18,621 INFO L93 Difference]: Finished difference Result 15441 states and 24452 transitions. [2019-10-22 09:02:18,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:18,621 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-10-22 09:02:18,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:18,639 INFO L225 Difference]: With dead ends: 15441 [2019-10-22 09:02:18,639 INFO L226 Difference]: Without dead ends: 8274 [2019-10-22 09:02:18,648 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:18,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8274 states. [2019-10-22 09:02:18,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8274 to 8274. [2019-10-22 09:02:18,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8274 states. [2019-10-22 09:02:18,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8274 states to 8274 states and 12950 transitions. [2019-10-22 09:02:18,976 INFO L78 Accepts]: Start accepts. Automaton has 8274 states and 12950 transitions. Word has length 48 [2019-10-22 09:02:18,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:18,977 INFO L462 AbstractCegarLoop]: Abstraction has 8274 states and 12950 transitions. [2019-10-22 09:02:18,977 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:18,977 INFO L276 IsEmpty]: Start isEmpty. Operand 8274 states and 12950 transitions. [2019-10-22 09:02:18,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-10-22 09:02:18,982 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:18,982 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:18,982 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:18,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:18,983 INFO L82 PathProgramCache]: Analyzing trace with hash -1392856220, now seen corresponding path program 1 times [2019-10-22 09:02:18,983 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:18,983 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532005298] [2019-10-22 09:02:18,983 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:18,983 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:18,983 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:18,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:19,020 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:19,020 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1532005298] [2019-10-22 09:02:19,020 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:19,021 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:19,021 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1657992367] [2019-10-22 09:02:19,021 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:19,021 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:19,021 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:19,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:19,022 INFO L87 Difference]: Start difference. First operand 8274 states and 12950 transitions. Second operand 3 states. [2019-10-22 09:02:19,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:19,380 INFO L93 Difference]: Finished difference Result 17053 states and 26638 transitions. [2019-10-22 09:02:19,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:19,381 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 52 [2019-10-22 09:02:19,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:19,399 INFO L225 Difference]: With dead ends: 17053 [2019-10-22 09:02:19,399 INFO L226 Difference]: Without dead ends: 8815 [2019-10-22 09:02:19,408 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:19,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8815 states. [2019-10-22 09:02:19,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8815 to 8272. [2019-10-22 09:02:19,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8272 states. [2019-10-22 09:02:19,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8272 states to 8272 states and 12699 transitions. [2019-10-22 09:02:19,725 INFO L78 Accepts]: Start accepts. Automaton has 8272 states and 12699 transitions. Word has length 52 [2019-10-22 09:02:19,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:19,725 INFO L462 AbstractCegarLoop]: Abstraction has 8272 states and 12699 transitions. [2019-10-22 09:02:19,725 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:19,725 INFO L276 IsEmpty]: Start isEmpty. Operand 8272 states and 12699 transitions. [2019-10-22 09:02:19,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-10-22 09:02:19,731 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:19,732 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:19,732 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:19,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:19,732 INFO L82 PathProgramCache]: Analyzing trace with hash 1708846795, now seen corresponding path program 1 times [2019-10-22 09:02:19,732 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:19,733 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145259222] [2019-10-22 09:02:19,733 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:19,733 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:19,733 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:19,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:19,749 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-10-22 09:02:19,749 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145259222] [2019-10-22 09:02:19,750 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:19,750 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:19,750 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [353923311] [2019-10-22 09:02:19,750 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:19,750 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:19,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:19,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:19,751 INFO L87 Difference]: Start difference. First operand 8272 states and 12699 transitions. Second operand 3 states. [2019-10-22 09:02:20,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:20,243 INFO L93 Difference]: Finished difference Result 24504 states and 37704 transitions. [2019-10-22 09:02:20,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:20,244 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 54 [2019-10-22 09:02:20,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:20,278 INFO L225 Difference]: With dead ends: 24504 [2019-10-22 09:02:20,279 INFO L226 Difference]: Without dead ends: 16235 [2019-10-22 09:02:20,291 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:20,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16235 states. [2019-10-22 09:02:20,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16235 to 16105. [2019-10-22 09:02:20,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16105 states. [2019-10-22 09:02:20,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16105 states to 16105 states and 24847 transitions. [2019-10-22 09:02:20,930 INFO L78 Accepts]: Start accepts. Automaton has 16105 states and 24847 transitions. Word has length 54 [2019-10-22 09:02:20,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:20,930 INFO L462 AbstractCegarLoop]: Abstraction has 16105 states and 24847 transitions. [2019-10-22 09:02:20,930 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:20,930 INFO L276 IsEmpty]: Start isEmpty. Operand 16105 states and 24847 transitions. [2019-10-22 09:02:20,937 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-10-22 09:02:20,939 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:20,939 INFO L380 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:20,939 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:20,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:20,940 INFO L82 PathProgramCache]: Analyzing trace with hash 194830513, now seen corresponding path program 1 times [2019-10-22 09:02:20,940 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:20,940 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1300389592] [2019-10-22 09:02:20,940 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:20,940 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:20,940 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:20,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:20,983 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:20,984 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1300389592] [2019-10-22 09:02:20,984 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:20,984 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:20,984 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [444039113] [2019-10-22 09:02:20,985 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:20,986 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:20,986 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:20,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:20,986 INFO L87 Difference]: Start difference. First operand 16105 states and 24847 transitions. Second operand 3 states. [2019-10-22 09:02:21,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:21,409 INFO L93 Difference]: Finished difference Result 32865 states and 50652 transitions. [2019-10-22 09:02:21,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:21,409 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-10-22 09:02:21,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:21,442 INFO L225 Difference]: With dead ends: 32865 [2019-10-22 09:02:21,442 INFO L226 Difference]: Without dead ends: 16789 [2019-10-22 09:02:21,586 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:21,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16789 states. [2019-10-22 09:02:22,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16789 to 16725. [2019-10-22 09:02:22,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16725 states. [2019-10-22 09:02:22,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16725 states to 16725 states and 25149 transitions. [2019-10-22 09:02:22,037 INFO L78 Accepts]: Start accepts. Automaton has 16725 states and 25149 transitions. Word has length 85 [2019-10-22 09:02:22,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:22,037 INFO L462 AbstractCegarLoop]: Abstraction has 16725 states and 25149 transitions. [2019-10-22 09:02:22,037 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:22,038 INFO L276 IsEmpty]: Start isEmpty. Operand 16725 states and 25149 transitions. [2019-10-22 09:02:22,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-10-22 09:02:22,045 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:22,045 INFO L380 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:22,046 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:22,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:22,046 INFO L82 PathProgramCache]: Analyzing trace with hash 164482089, now seen corresponding path program 1 times [2019-10-22 09:02:22,046 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:22,046 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336018404] [2019-10-22 09:02:22,046 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:22,046 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:22,047 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:22,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:22,079 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-10-22 09:02:22,080 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336018404] [2019-10-22 09:02:22,080 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:22,080 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:02:22,080 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360548962] [2019-10-22 09:02:22,081 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:02:22,081 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:22,081 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:02:22,081 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:02:22,081 INFO L87 Difference]: Start difference. First operand 16725 states and 25149 transitions. Second operand 4 states. [2019-10-22 09:02:22,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:22,583 INFO L93 Difference]: Finished difference Result 27583 states and 41591 transitions. [2019-10-22 09:02:22,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-22 09:02:22,583 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 86 [2019-10-22 09:02:22,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:22,611 INFO L225 Difference]: With dead ends: 27583 [2019-10-22 09:02:22,612 INFO L226 Difference]: Without dead ends: 15803 [2019-10-22 09:02:22,626 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:02:22,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15803 states. [2019-10-22 09:02:23,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15803 to 15713. [2019-10-22 09:02:23,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15713 states. [2019-10-22 09:02:23,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15713 states to 15713 states and 23443 transitions. [2019-10-22 09:02:23,395 INFO L78 Accepts]: Start accepts. Automaton has 15713 states and 23443 transitions. Word has length 86 [2019-10-22 09:02:23,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:23,396 INFO L462 AbstractCegarLoop]: Abstraction has 15713 states and 23443 transitions. [2019-10-22 09:02:23,396 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:02:23,396 INFO L276 IsEmpty]: Start isEmpty. Operand 15713 states and 23443 transitions. [2019-10-22 09:02:23,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-10-22 09:02:23,401 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:23,401 INFO L380 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:23,402 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:23,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:23,402 INFO L82 PathProgramCache]: Analyzing trace with hash -433884439, now seen corresponding path program 1 times [2019-10-22 09:02:23,402 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:23,402 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364042644] [2019-10-22 09:02:23,402 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:23,402 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:23,403 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:23,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:23,431 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:23,431 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364042644] [2019-10-22 09:02:23,431 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:23,431 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:23,432 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369681764] [2019-10-22 09:02:23,432 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:23,433 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:23,433 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:23,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:23,433 INFO L87 Difference]: Start difference. First operand 15713 states and 23443 transitions. Second operand 3 states. [2019-10-22 09:02:23,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:23,778 INFO L93 Difference]: Finished difference Result 32195 states and 47984 transitions. [2019-10-22 09:02:23,779 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:23,779 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-10-22 09:02:23,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:23,796 INFO L225 Difference]: With dead ends: 32195 [2019-10-22 09:02:23,797 INFO L226 Difference]: Without dead ends: 16523 [2019-10-22 09:02:23,809 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:23,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16523 states. [2019-10-22 09:02:24,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16523 to 16443. [2019-10-22 09:02:24,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16443 states. [2019-10-22 09:02:24,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16443 states to 16443 states and 23815 transitions. [2019-10-22 09:02:24,244 INFO L78 Accepts]: Start accepts. Automaton has 16443 states and 23815 transitions. Word has length 86 [2019-10-22 09:02:24,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:24,245 INFO L462 AbstractCegarLoop]: Abstraction has 16443 states and 23815 transitions. [2019-10-22 09:02:24,245 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:24,245 INFO L276 IsEmpty]: Start isEmpty. Operand 16443 states and 23815 transitions. [2019-10-22 09:02:24,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-10-22 09:02:24,250 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:24,250 INFO L380 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:24,250 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:24,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:24,251 INFO L82 PathProgramCache]: Analyzing trace with hash -1869450223, now seen corresponding path program 1 times [2019-10-22 09:02:24,251 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:24,251 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820255340] [2019-10-22 09:02:24,251 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:24,251 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:24,251 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:24,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:24,290 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:02:24,291 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [820255340] [2019-10-22 09:02:24,291 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:24,291 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:24,291 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074086731] [2019-10-22 09:02:24,291 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:24,291 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:24,291 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:24,292 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:24,292 INFO L87 Difference]: Start difference. First operand 16443 states and 23815 transitions. Second operand 3 states. [2019-10-22 09:02:24,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:24,903 INFO L93 Difference]: Finished difference Result 33302 states and 48352 transitions. [2019-10-22 09:02:24,903 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:24,903 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 87 [2019-10-22 09:02:24,903 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:24,917 INFO L225 Difference]: With dead ends: 33302 [2019-10-22 09:02:24,917 INFO L226 Difference]: Without dead ends: 16920 [2019-10-22 09:02:24,928 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:24,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16920 states. [2019-10-22 09:02:25,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16920 to 13439. [2019-10-22 09:02:25,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13439 states. [2019-10-22 09:02:25,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13439 states to 13439 states and 18777 transitions. [2019-10-22 09:02:25,276 INFO L78 Accepts]: Start accepts. Automaton has 13439 states and 18777 transitions. Word has length 87 [2019-10-22 09:02:25,276 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:25,277 INFO L462 AbstractCegarLoop]: Abstraction has 13439 states and 18777 transitions. [2019-10-22 09:02:25,277 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:25,277 INFO L276 IsEmpty]: Start isEmpty. Operand 13439 states and 18777 transitions. [2019-10-22 09:02:25,281 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2019-10-22 09:02:25,281 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:25,282 INFO L380 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:25,282 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:25,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:25,282 INFO L82 PathProgramCache]: Analyzing trace with hash -2059863225, now seen corresponding path program 1 times [2019-10-22 09:02:25,282 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:25,282 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220675131] [2019-10-22 09:02:25,283 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:25,283 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:25,283 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:25,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:25,318 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-10-22 09:02:25,319 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220675131] [2019-10-22 09:02:25,319 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:25,319 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:25,319 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [616289685] [2019-10-22 09:02:25,319 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:25,319 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:25,320 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:25,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:25,320 INFO L87 Difference]: Start difference. First operand 13439 states and 18777 transitions. Second operand 3 states. [2019-10-22 09:02:25,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:25,688 INFO L93 Difference]: Finished difference Result 23921 states and 33457 transitions. [2019-10-22 09:02:25,689 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:25,689 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 88 [2019-10-22 09:02:25,689 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:25,704 INFO L225 Difference]: With dead ends: 23921 [2019-10-22 09:02:25,704 INFO L226 Difference]: Without dead ends: 15605 [2019-10-22 09:02:25,712 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:25,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15605 states. [2019-10-22 09:02:26,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15605 to 15125. [2019-10-22 09:02:26,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15125 states. [2019-10-22 09:02:26,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15125 states to 15125 states and 20656 transitions. [2019-10-22 09:02:26,393 INFO L78 Accepts]: Start accepts. Automaton has 15125 states and 20656 transitions. Word has length 88 [2019-10-22 09:02:26,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:26,393 INFO L462 AbstractCegarLoop]: Abstraction has 15125 states and 20656 transitions. [2019-10-22 09:02:26,393 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:26,393 INFO L276 IsEmpty]: Start isEmpty. Operand 15125 states and 20656 transitions. [2019-10-22 09:02:26,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2019-10-22 09:02:26,403 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:26,403 INFO L380 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:26,403 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:26,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:26,404 INFO L82 PathProgramCache]: Analyzing trace with hash 1061949686, now seen corresponding path program 1 times [2019-10-22 09:02:26,404 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:26,404 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306076301] [2019-10-22 09:02:26,404 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:26,404 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:26,404 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:26,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:26,433 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-10-22 09:02:26,433 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [306076301] [2019-10-22 09:02:26,433 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:26,433 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:26,433 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [172309757] [2019-10-22 09:02:26,434 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:26,434 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:26,434 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:26,434 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:26,434 INFO L87 Difference]: Start difference. First operand 15125 states and 20656 transitions. Second operand 3 states. [2019-10-22 09:02:26,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:26,759 INFO L93 Difference]: Finished difference Result 29488 states and 40230 transitions. [2019-10-22 09:02:26,759 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:26,759 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 115 [2019-10-22 09:02:26,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:26,770 INFO L225 Difference]: With dead ends: 29488 [2019-10-22 09:02:26,770 INFO L226 Difference]: Without dead ends: 15055 [2019-10-22 09:02:26,777 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:26,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15055 states. [2019-10-22 09:02:27,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15055 to 15055. [2019-10-22 09:02:27,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15055 states. [2019-10-22 09:02:27,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15055 states to 15055 states and 20502 transitions. [2019-10-22 09:02:27,096 INFO L78 Accepts]: Start accepts. Automaton has 15055 states and 20502 transitions. Word has length 115 [2019-10-22 09:02:27,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:27,096 INFO L462 AbstractCegarLoop]: Abstraction has 15055 states and 20502 transitions. [2019-10-22 09:02:27,096 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:27,096 INFO L276 IsEmpty]: Start isEmpty. Operand 15055 states and 20502 transitions. [2019-10-22 09:02:27,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2019-10-22 09:02:27,104 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:27,104 INFO L380 BasicCegarLoop]: trace histogram [5, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:27,104 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:27,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:27,105 INFO L82 PathProgramCache]: Analyzing trace with hash -1410428474, now seen corresponding path program 1 times [2019-10-22 09:02:27,105 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:27,105 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896081526] [2019-10-22 09:02:27,105 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:27,105 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:27,105 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:27,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:27,133 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2019-10-22 09:02:27,134 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896081526] [2019-10-22 09:02:27,134 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:27,134 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:27,134 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919331561] [2019-10-22 09:02:27,134 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:27,135 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:27,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:27,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:27,135 INFO L87 Difference]: Start difference. First operand 15055 states and 20502 transitions. Second operand 3 states. [2019-10-22 09:02:27,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:27,450 INFO L93 Difference]: Finished difference Result 25586 states and 34782 transitions. [2019-10-22 09:02:27,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:27,450 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 126 [2019-10-22 09:02:27,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:27,458 INFO L225 Difference]: With dead ends: 25586 [2019-10-22 09:02:27,458 INFO L226 Difference]: Without dead ends: 10588 [2019-10-22 09:02:27,464 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:27,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10588 states. [2019-10-22 09:02:27,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10588 to 8620. [2019-10-22 09:02:27,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8620 states. [2019-10-22 09:02:27,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8620 states to 8620 states and 11274 transitions. [2019-10-22 09:02:27,924 INFO L78 Accepts]: Start accepts. Automaton has 8620 states and 11274 transitions. Word has length 126 [2019-10-22 09:02:27,924 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:27,924 INFO L462 AbstractCegarLoop]: Abstraction has 8620 states and 11274 transitions. [2019-10-22 09:02:27,924 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:27,925 INFO L276 IsEmpty]: Start isEmpty. Operand 8620 states and 11274 transitions. [2019-10-22 09:02:27,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-10-22 09:02:27,929 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:27,929 INFO L380 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:27,930 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:27,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:27,930 INFO L82 PathProgramCache]: Analyzing trace with hash 314934891, now seen corresponding path program 1 times [2019-10-22 09:02:27,930 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:27,930 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512355646] [2019-10-22 09:02:27,930 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:27,930 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:27,930 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:27,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:27,961 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 43 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-10-22 09:02:27,961 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1512355646] [2019-10-22 09:02:27,961 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:27,961 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:27,961 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556461756] [2019-10-22 09:02:27,962 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:27,962 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:27,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:27,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:27,962 INFO L87 Difference]: Start difference. First operand 8620 states and 11274 transitions. Second operand 3 states. [2019-10-22 09:02:28,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:28,214 INFO L93 Difference]: Finished difference Result 14199 states and 18567 transitions. [2019-10-22 09:02:28,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:28,214 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 127 [2019-10-22 09:02:28,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:28,221 INFO L225 Difference]: With dead ends: 14199 [2019-10-22 09:02:28,221 INFO L226 Difference]: Without dead ends: 6733 [2019-10-22 09:02:28,226 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:28,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6733 states. [2019-10-22 09:02:28,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6733 to 6149. [2019-10-22 09:02:28,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6149 states. [2019-10-22 09:02:28,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6149 states to 6149 states and 7873 transitions. [2019-10-22 09:02:28,407 INFO L78 Accepts]: Start accepts. Automaton has 6149 states and 7873 transitions. Word has length 127 [2019-10-22 09:02:28,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:28,407 INFO L462 AbstractCegarLoop]: Abstraction has 6149 states and 7873 transitions. [2019-10-22 09:02:28,407 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:28,408 INFO L276 IsEmpty]: Start isEmpty. Operand 6149 states and 7873 transitions. [2019-10-22 09:02:28,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-10-22 09:02:28,411 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:28,411 INFO L380 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:28,411 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:28,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:28,412 INFO L82 PathProgramCache]: Analyzing trace with hash -146147841, now seen corresponding path program 1 times [2019-10-22 09:02:28,412 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:28,412 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887513694] [2019-10-22 09:02:28,412 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:28,412 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:28,412 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:28,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:28,448 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-10-22 09:02:28,448 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887513694] [2019-10-22 09:02:28,448 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:28,448 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:28,449 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [150366692] [2019-10-22 09:02:28,449 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:28,449 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:28,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:28,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:28,449 INFO L87 Difference]: Start difference. First operand 6149 states and 7873 transitions. Second operand 3 states. [2019-10-22 09:02:28,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:28,615 INFO L93 Difference]: Finished difference Result 11907 states and 15226 transitions. [2019-10-22 09:02:28,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:28,615 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 133 [2019-10-22 09:02:28,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:28,619 INFO L225 Difference]: With dead ends: 11907 [2019-10-22 09:02:28,619 INFO L226 Difference]: Without dead ends: 6149 [2019-10-22 09:02:28,622 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:28,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6149 states. [2019-10-22 09:02:28,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6149 to 6109. [2019-10-22 09:02:28,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6109 states. [2019-10-22 09:02:28,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6109 states to 6109 states and 7791 transitions. [2019-10-22 09:02:28,753 INFO L78 Accepts]: Start accepts. Automaton has 6109 states and 7791 transitions. Word has length 133 [2019-10-22 09:02:28,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:28,753 INFO L462 AbstractCegarLoop]: Abstraction has 6109 states and 7791 transitions. [2019-10-22 09:02:28,754 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:28,754 INFO L276 IsEmpty]: Start isEmpty. Operand 6109 states and 7791 transitions. [2019-10-22 09:02:28,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-10-22 09:02:28,757 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:28,757 INFO L380 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:28,757 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:28,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:28,757 INFO L82 PathProgramCache]: Analyzing trace with hash 1797709215, now seen corresponding path program 1 times [2019-10-22 09:02:28,758 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:28,758 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805680139] [2019-10-22 09:02:28,758 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:28,758 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:28,758 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:28,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:28,787 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-10-22 09:02:28,787 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805680139] [2019-10-22 09:02:28,787 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:28,787 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:28,787 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1200909323] [2019-10-22 09:02:28,787 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:28,788 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:28,788 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:28,788 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:28,788 INFO L87 Difference]: Start difference. First operand 6109 states and 7791 transitions. Second operand 3 states. [2019-10-22 09:02:29,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:29,015 INFO L93 Difference]: Finished difference Result 11855 states and 15104 transitions. [2019-10-22 09:02:29,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:29,015 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 133 [2019-10-22 09:02:29,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:29,021 INFO L225 Difference]: With dead ends: 11855 [2019-10-22 09:02:29,021 INFO L226 Difference]: Without dead ends: 6118 [2019-10-22 09:02:29,025 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:29,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6118 states. [2019-10-22 09:02:29,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6118 to 6078. [2019-10-22 09:02:29,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6078 states. [2019-10-22 09:02:29,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6078 states to 6078 states and 7719 transitions. [2019-10-22 09:02:29,244 INFO L78 Accepts]: Start accepts. Automaton has 6078 states and 7719 transitions. Word has length 133 [2019-10-22 09:02:29,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:29,244 INFO L462 AbstractCegarLoop]: Abstraction has 6078 states and 7719 transitions. [2019-10-22 09:02:29,244 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:29,244 INFO L276 IsEmpty]: Start isEmpty. Operand 6078 states and 7719 transitions. [2019-10-22 09:02:29,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-10-22 09:02:29,248 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:29,248 INFO L380 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:29,248 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:29,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:29,248 INFO L82 PathProgramCache]: Analyzing trace with hash 282610594, now seen corresponding path program 1 times [2019-10-22 09:02:29,249 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:29,249 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071032018] [2019-10-22 09:02:29,249 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:29,249 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:29,249 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:29,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:29,277 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-10-22 09:02:29,277 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1071032018] [2019-10-22 09:02:29,277 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:29,277 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:29,277 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121577171] [2019-10-22 09:02:29,277 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:29,278 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:29,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:29,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:29,278 INFO L87 Difference]: Start difference. First operand 6078 states and 7719 transitions. Second operand 3 states. [2019-10-22 09:02:29,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:29,463 INFO L93 Difference]: Finished difference Result 10860 states and 13837 transitions. [2019-10-22 09:02:29,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:29,463 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 136 [2019-10-22 09:02:29,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:29,468 INFO L225 Difference]: With dead ends: 10860 [2019-10-22 09:02:29,468 INFO L226 Difference]: Without dead ends: 5146 [2019-10-22 09:02:29,472 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:29,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5146 states. [2019-10-22 09:02:29,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5146 to 5076. [2019-10-22 09:02:29,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5076 states. [2019-10-22 09:02:29,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5076 states to 5076 states and 6341 transitions. [2019-10-22 09:02:29,667 INFO L78 Accepts]: Start accepts. Automaton has 5076 states and 6341 transitions. Word has length 136 [2019-10-22 09:02:29,667 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:29,667 INFO L462 AbstractCegarLoop]: Abstraction has 5076 states and 6341 transitions. [2019-10-22 09:02:29,667 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:29,667 INFO L276 IsEmpty]: Start isEmpty. Operand 5076 states and 6341 transitions. [2019-10-22 09:02:29,670 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-10-22 09:02:29,670 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:29,671 INFO L380 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:29,671 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:29,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:29,671 INFO L82 PathProgramCache]: Analyzing trace with hash -1519116211, now seen corresponding path program 1 times [2019-10-22 09:02:29,671 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:29,671 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197745953] [2019-10-22 09:02:29,672 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:29,672 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:29,672 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:29,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:29,722 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2019-10-22 09:02:29,722 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197745953] [2019-10-22 09:02:29,723 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:29,723 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:29,723 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1223792050] [2019-10-22 09:02:29,723 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:29,723 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:29,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:29,724 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:29,724 INFO L87 Difference]: Start difference. First operand 5076 states and 6341 transitions. Second operand 3 states. [2019-10-22 09:02:29,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:29,934 INFO L93 Difference]: Finished difference Result 9133 states and 11446 transitions. [2019-10-22 09:02:29,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:29,935 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 136 [2019-10-22 09:02:29,935 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:29,939 INFO L225 Difference]: With dead ends: 9133 [2019-10-22 09:02:29,939 INFO L226 Difference]: Without dead ends: 4098 [2019-10-22 09:02:29,943 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:29,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4098 states. [2019-10-22 09:02:30,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4098 to 4080. [2019-10-22 09:02:30,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4080 states. [2019-10-22 09:02:30,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4080 states to 4080 states and 5008 transitions. [2019-10-22 09:02:30,139 INFO L78 Accepts]: Start accepts. Automaton has 4080 states and 5008 transitions. Word has length 136 [2019-10-22 09:02:30,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:30,140 INFO L462 AbstractCegarLoop]: Abstraction has 4080 states and 5008 transitions. [2019-10-22 09:02:30,140 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:30,140 INFO L276 IsEmpty]: Start isEmpty. Operand 4080 states and 5008 transitions. [2019-10-22 09:02:30,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2019-10-22 09:02:30,144 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:30,144 INFO L380 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:30,144 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:30,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:30,145 INFO L82 PathProgramCache]: Analyzing trace with hash -1856914244, now seen corresponding path program 1 times [2019-10-22 09:02:30,145 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:30,145 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678194145] [2019-10-22 09:02:30,145 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:30,145 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:30,146 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:30,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:30,196 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 75 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-10-22 09:02:30,196 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678194145] [2019-10-22 09:02:30,196 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:30,199 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:30,199 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1966005489] [2019-10-22 09:02:30,199 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:30,200 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:30,200 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:30,200 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:30,200 INFO L87 Difference]: Start difference. First operand 4080 states and 5008 transitions. Second operand 3 states. [2019-10-22 09:02:30,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:30,411 INFO L93 Difference]: Finished difference Result 7575 states and 9357 transitions. [2019-10-22 09:02:30,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:30,412 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 169 [2019-10-22 09:02:30,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:30,416 INFO L225 Difference]: With dead ends: 7575 [2019-10-22 09:02:30,416 INFO L226 Difference]: Without dead ends: 3771 [2019-10-22 09:02:30,419 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:30,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3771 states. [2019-10-22 09:02:30,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3771 to 3560. [2019-10-22 09:02:30,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3560 states. [2019-10-22 09:02:30,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3560 states to 3560 states and 4335 transitions. [2019-10-22 09:02:30,773 INFO L78 Accepts]: Start accepts. Automaton has 3560 states and 4335 transitions. Word has length 169 [2019-10-22 09:02:30,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:30,773 INFO L462 AbstractCegarLoop]: Abstraction has 3560 states and 4335 transitions. [2019-10-22 09:02:30,774 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:30,774 INFO L276 IsEmpty]: Start isEmpty. Operand 3560 states and 4335 transitions. [2019-10-22 09:02:30,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-10-22 09:02:30,776 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:30,777 INFO L380 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:30,777 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:30,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:30,777 INFO L82 PathProgramCache]: Analyzing trace with hash 38014472, now seen corresponding path program 1 times [2019-10-22 09:02:30,778 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:30,778 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552916246] [2019-10-22 09:02:30,779 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:30,779 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:30,780 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:30,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:30,815 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-10-22 09:02:30,816 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1552916246] [2019-10-22 09:02:30,816 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:30,816 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:30,816 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1151475546] [2019-10-22 09:02:30,816 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:30,816 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:30,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:30,818 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:30,818 INFO L87 Difference]: Start difference. First operand 3560 states and 4335 transitions. Second operand 3 states. [2019-10-22 09:02:31,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:31,026 INFO L93 Difference]: Finished difference Result 8918 states and 10901 transitions. [2019-10-22 09:02:31,026 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:31,026 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2019-10-22 09:02:31,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:31,031 INFO L225 Difference]: With dead ends: 8918 [2019-10-22 09:02:31,031 INFO L226 Difference]: Without dead ends: 5634 [2019-10-22 09:02:31,034 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:31,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5634 states. [2019-10-22 09:02:31,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5634 to 5414. [2019-10-22 09:02:31,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5414 states. [2019-10-22 09:02:31,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5414 states to 5414 states and 6513 transitions. [2019-10-22 09:02:31,242 INFO L78 Accepts]: Start accepts. Automaton has 5414 states and 6513 transitions. Word has length 176 [2019-10-22 09:02:31,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:31,242 INFO L462 AbstractCegarLoop]: Abstraction has 5414 states and 6513 transitions. [2019-10-22 09:02:31,242 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:31,242 INFO L276 IsEmpty]: Start isEmpty. Operand 5414 states and 6513 transitions. [2019-10-22 09:02:31,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-10-22 09:02:31,246 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:31,247 INFO L380 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:31,247 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:31,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:31,247 INFO L82 PathProgramCache]: Analyzing trace with hash -1974043446, now seen corresponding path program 1 times [2019-10-22 09:02:31,247 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:31,247 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1479753097] [2019-10-22 09:02:31,247 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:31,247 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:31,247 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:31,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:31,283 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 79 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2019-10-22 09:02:31,284 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1479753097] [2019-10-22 09:02:31,284 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:31,284 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:31,284 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1217391694] [2019-10-22 09:02:31,284 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:31,284 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:31,285 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:31,285 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:31,285 INFO L87 Difference]: Start difference. First operand 5414 states and 6513 transitions. Second operand 3 states. [2019-10-22 09:02:31,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:31,442 INFO L93 Difference]: Finished difference Result 8838 states and 10694 transitions. [2019-10-22 09:02:31,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:31,443 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 179 [2019-10-22 09:02:31,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:31,446 INFO L225 Difference]: With dead ends: 8838 [2019-10-22 09:02:31,447 INFO L226 Difference]: Without dead ends: 3700 [2019-10-22 09:02:31,450 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:31,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3700 states. [2019-10-22 09:02:31,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3700 to 3094. [2019-10-22 09:02:31,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3094 states. [2019-10-22 09:02:31,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3094 states to 3094 states and 3684 transitions. [2019-10-22 09:02:31,585 INFO L78 Accepts]: Start accepts. Automaton has 3094 states and 3684 transitions. Word has length 179 [2019-10-22 09:02:31,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:31,586 INFO L462 AbstractCegarLoop]: Abstraction has 3094 states and 3684 transitions. [2019-10-22 09:02:31,586 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:31,586 INFO L276 IsEmpty]: Start isEmpty. Operand 3094 states and 3684 transitions. [2019-10-22 09:02:31,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-10-22 09:02:31,589 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:31,589 INFO L380 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:31,590 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:31,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:31,591 INFO L82 PathProgramCache]: Analyzing trace with hash -831540980, now seen corresponding path program 1 times [2019-10-22 09:02:31,591 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:31,591 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046473170] [2019-10-22 09:02:31,591 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:31,591 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:31,591 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:31,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:31,634 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 91 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-10-22 09:02:31,634 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1046473170] [2019-10-22 09:02:31,634 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:31,634 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-22 09:02:31,634 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854802186] [2019-10-22 09:02:31,635 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-22 09:02:31,635 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:31,635 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-22 09:02:31,635 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-22 09:02:31,635 INFO L87 Difference]: Start difference. First operand 3094 states and 3684 transitions. Second operand 4 states. [2019-10-22 09:02:31,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:31,767 INFO L93 Difference]: Finished difference Result 4689 states and 5567 transitions. [2019-10-22 09:02:31,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-22 09:02:31,768 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 179 [2019-10-22 09:02:31,768 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:31,770 INFO L225 Difference]: With dead ends: 4689 [2019-10-22 09:02:31,770 INFO L226 Difference]: Without dead ends: 1871 [2019-10-22 09:02:31,772 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:02:31,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1871 states. [2019-10-22 09:02:31,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1871 to 1584. [2019-10-22 09:02:31,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1584 states. [2019-10-22 09:02:31,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1584 states to 1584 states and 1844 transitions. [2019-10-22 09:02:31,847 INFO L78 Accepts]: Start accepts. Automaton has 1584 states and 1844 transitions. Word has length 179 [2019-10-22 09:02:31,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:31,847 INFO L462 AbstractCegarLoop]: Abstraction has 1584 states and 1844 transitions. [2019-10-22 09:02:31,847 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-22 09:02:31,847 INFO L276 IsEmpty]: Start isEmpty. Operand 1584 states and 1844 transitions. [2019-10-22 09:02:31,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2019-10-22 09:02:31,849 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:31,850 INFO L380 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:31,850 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:31,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:31,850 INFO L82 PathProgramCache]: Analyzing trace with hash 1681635082, now seen corresponding path program 1 times [2019-10-22 09:02:31,850 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:31,850 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494692838] [2019-10-22 09:02:31,851 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:31,851 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:31,851 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:31,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:31,898 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-10-22 09:02:31,898 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494692838] [2019-10-22 09:02:31,898 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:31,898 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:31,898 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1628882982] [2019-10-22 09:02:31,899 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:31,900 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:31,900 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:31,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:31,900 INFO L87 Difference]: Start difference. First operand 1584 states and 1844 transitions. Second operand 3 states. [2019-10-22 09:02:32,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:32,032 INFO L93 Difference]: Finished difference Result 4040 states and 4732 transitions. [2019-10-22 09:02:32,033 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:32,033 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 183 [2019-10-22 09:02:32,033 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:32,035 INFO L225 Difference]: With dead ends: 4040 [2019-10-22 09:02:32,035 INFO L226 Difference]: Without dead ends: 2426 [2019-10-22 09:02:32,037 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:32,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2426 states. [2019-10-22 09:02:32,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2426 to 2416. [2019-10-22 09:02:32,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2416 states. [2019-10-22 09:02:32,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2416 states to 2416 states and 2812 transitions. [2019-10-22 09:02:32,150 INFO L78 Accepts]: Start accepts. Automaton has 2416 states and 2812 transitions. Word has length 183 [2019-10-22 09:02:32,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:32,150 INFO L462 AbstractCegarLoop]: Abstraction has 2416 states and 2812 transitions. [2019-10-22 09:02:32,150 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:32,150 INFO L276 IsEmpty]: Start isEmpty. Operand 2416 states and 2812 transitions. [2019-10-22 09:02:32,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2019-10-22 09:02:32,152 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:32,153 INFO L380 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:32,153 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:32,153 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:32,153 INFO L82 PathProgramCache]: Analyzing trace with hash 1256160142, now seen corresponding path program 1 times [2019-10-22 09:02:32,153 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:32,153 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280198832] [2019-10-22 09:02:32,154 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:32,154 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:32,154 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:32,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:02:32,196 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 93 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-10-22 09:02:32,197 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280198832] [2019-10-22 09:02:32,197 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:02:32,197 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:02:32,197 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054268901] [2019-10-22 09:02:32,197 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:02:32,197 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:02:32,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:02:32,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:32,198 INFO L87 Difference]: Start difference. First operand 2416 states and 2812 transitions. Second operand 3 states. [2019-10-22 09:02:32,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:02:32,277 INFO L93 Difference]: Finished difference Result 3364 states and 3884 transitions. [2019-10-22 09:02:32,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:02:32,278 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 183 [2019-10-22 09:02:32,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:02:32,279 INFO L225 Difference]: With dead ends: 3364 [2019-10-22 09:02:32,279 INFO L226 Difference]: Without dead ends: 1214 [2019-10-22 09:02:32,281 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:02:32,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states. [2019-10-22 09:02:32,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1192. [2019-10-22 09:02:32,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1192 states. [2019-10-22 09:02:32,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1192 states to 1192 states and 1317 transitions. [2019-10-22 09:02:32,335 INFO L78 Accepts]: Start accepts. Automaton has 1192 states and 1317 transitions. Word has length 183 [2019-10-22 09:02:32,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:02:32,335 INFO L462 AbstractCegarLoop]: Abstraction has 1192 states and 1317 transitions. [2019-10-22 09:02:32,335 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:02:32,335 INFO L276 IsEmpty]: Start isEmpty. Operand 1192 states and 1317 transitions. [2019-10-22 09:02:32,337 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-10-22 09:02:32,337 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:02:32,338 INFO L380 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:02:32,338 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:02:32,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:02:32,338 INFO L82 PathProgramCache]: Analyzing trace with hash 1772258692, now seen corresponding path program 1 times [2019-10-22 09:02:32,338 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:02:32,338 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291608837] [2019-10-22 09:02:32,338 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:32,338 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:02:32,339 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:02:32,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 09:02:32,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 09:02:32,443 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 09:02:32,443 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-10-22 09:02:32,587 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.10 09:02:32 BoogieIcfgContainer [2019-10-22 09:02:32,591 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-10-22 09:02:32,591 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-10-22 09:02:32,591 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-10-22 09:02:32,591 INFO L275 PluginConnector]: Witness Printer initialized [2019-10-22 09:02:32,592 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 09:02:13" (3/4) ... [2019-10-22 09:02:32,594 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-10-22 09:02:32,755 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_bc7da954-be18-41bd-9d49-8f8f9954d811/bin/uautomizer/witness.graphml [2019-10-22 09:02:32,755 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-10-22 09:02:32,759 INFO L168 Benchmark]: Toolchain (without parser) took 20268.91 ms. Allocated memory was 1.0 GB in the beginning and 3.2 GB in the end (delta: 2.2 GB). Free memory was 945.9 MB in the beginning and 1.4 GB in the end (delta: -442.0 MB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. [2019-10-22 09:02:32,760 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 962.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-10-22 09:02:32,760 INFO L168 Benchmark]: CACSL2BoogieTranslator took 394.24 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 126.9 MB). Free memory was 945.9 MB in the beginning and 1.1 GB in the end (delta: -170.8 MB). Peak memory consumption was 22.9 MB. Max. memory is 11.5 GB. [2019-10-22 09:02:32,760 INFO L168 Benchmark]: Boogie Procedure Inliner took 38.52 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-10-22 09:02:32,761 INFO L168 Benchmark]: Boogie Preprocessor took 38.93 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-10-22 09:02:32,761 INFO L168 Benchmark]: RCFGBuilder took 679.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 48.0 MB). Peak memory consumption was 48.0 MB. Max. memory is 11.5 GB. [2019-10-22 09:02:32,761 INFO L168 Benchmark]: TraceAbstraction took 18949.20 ms. Allocated memory was 1.2 GB in the beginning and 3.2 GB in the end (delta: 2.0 GB). Free memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: -384.4 MB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. [2019-10-22 09:02:32,762 INFO L168 Benchmark]: Witness Printer took 163.95 ms. Allocated memory is still 3.2 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 58.5 MB). Peak memory consumption was 58.5 MB. Max. memory is 11.5 GB. [2019-10-22 09:02:32,763 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 962.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 394.24 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 126.9 MB). Free memory was 945.9 MB in the beginning and 1.1 GB in the end (delta: -170.8 MB). Peak memory consumption was 22.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 38.52 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 38.93 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 679.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 48.0 MB). Peak memory consumption was 48.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 18949.20 ms. Allocated memory was 1.2 GB in the beginning and 3.2 GB in the end (delta: 2.0 GB). Free memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: -384.4 MB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. * Witness Printer took 163.95 ms. Allocated memory is still 3.2 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 58.5 MB). Peak memory consumption was 58.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L679] int __retres1 ; [L683] e_wl = 2 [L684] e_c = e_wl [L685] e_g = e_c [L686] e_f = e_g [L687] e_e = e_f [L688] wl_pc = 0 [L689] c1_pc = 0 [L690] c2_pc = 0 [L691] wb_pc = 0 [L692] wb_i = 1 [L693] c2_i = wb_i [L694] c1_i = c2_i [L695] wl_i = c1_i [L696] r_i = 0 [L697] c_req_up = 0 [L698] d = 0 [L699] c = 0 [L390] int kernel_st ; [L393] kernel_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L394] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L405] COND TRUE (int )wl_i == 1 [L406] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L410] COND TRUE (int )c1_i == 1 [L411] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L415] COND TRUE (int )c2_i == 1 [L416] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L420] COND TRUE (int )wb_i == 1 [L421] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L425] COND FALSE !((int )r_i == 1) [L428] r_st = 2 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L430] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L435] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L440] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L445] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L450] COND FALSE !((int )e_wl == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L455] COND FALSE !((int )wl_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L463] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L473] COND FALSE !((int )c1_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L482] COND FALSE !((int )c2_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L491] COND FALSE !((int )wb_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L500] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L505] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L510] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L515] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L520] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L525] COND FALSE !((int )e_wl == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L531] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L127] COND TRUE (int )c1_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L138] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L172] COND TRUE (int )c2_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L183] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L217] COND TRUE (int )wb_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L228] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L537] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L538] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 3 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L565] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L570] COND TRUE (int )e_wl == 0 [L571] e_wl = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L575] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L576] COND TRUE (int )e_wl == 1 [L577] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L593] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L594] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L602] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L603] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L611] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L612] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L620] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L625] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L630] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L635] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L640] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L645] COND TRUE (int )e_wl == 1 [L646] e_wl = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L650] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L531] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L127] COND FALSE !((int )c1_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L130] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L145] COND TRUE ! processed [L146] data += 1 [L147] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L148] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L149] COND TRUE (int )e_g == 1 [L150] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L157] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L138] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L172] COND FALSE !((int )c2_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L175] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L190] COND TRUE ! processed [L191] data += 1 [L192] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L193] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L194] COND TRUE (int )e_g == 1 [L195] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L183] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L217] COND FALSE !((int )wb_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L220] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L235] c_t = data [L236] c_req_up = 1 [L237] processed = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L228] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L537] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L538] COND TRUE (int )c_req_up == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L539] COND TRUE c != c_t [L540] c = c_t [L541] e_c = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L545] c_req_up = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 3 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L565] COND TRUE (int )e_c == 0 [L566] e_c = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L570] COND FALSE !((int )e_wl == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L575] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L583] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L584] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L593] COND TRUE (int )c1_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L594] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L602] COND TRUE (int )c2_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L603] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L611] COND TRUE (int )wb_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L612] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L620] COND TRUE (int )e_c == 1 [L621] r_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L625] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L630] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L635] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L640] COND TRUE (int )e_c == 1 [L641] e_c = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L645] COND FALSE !((int )e_wl == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L650] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L653] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L656] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L659] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L531] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L337] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L352] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND TRUE (int )r_st == 0 [L369] tmp___3 = __VERIFIER_nondet_int() [L371] COND TRUE \read(tmp___3) [L373] r_st = 1 [L249] d = c [L250] e_e = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L251] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L259] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L260] COND TRUE (int )e_e == 1 [L261] wl_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L269] e_e = 2 [L270] r_st = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L284] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 125 locations, 1 error locations. Result: UNSAFE, OverallTime: 18.8s, OverallIterations: 37, TraceHistogramMax: 6, AutomataDifference: 8.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 7566 SDtfs, 5932 SDslu, 4273 SDs, 0 SdLazy, 705 SolverSat, 210 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 128 GetRequests, 76 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=16725occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 8.0s AutomataMinimizationTime, 36 MinimizatonAttempts, 9031 StatesRemovedByMinimization, 30 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 0.8s InterpolantComputationTime, 3325 NumberOfCodeBlocks, 3325 NumberOfCodeBlocksAsserted, 37 NumberOfCheckSat, 3105 ConstructedInterpolants, 0 QuantifiedInterpolants, 546256 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 36 InterpolantComputations, 36 PerfectInterpolantSequences, 1082/1082 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...