./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 447c919af4e106e36f468570351956f4c77293d2 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-10-22 08:59:44,490 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-22 08:59:44,493 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-22 08:59:44,503 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-22 08:59:44,504 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-22 08:59:44,505 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-22 08:59:44,506 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-22 08:59:44,508 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-22 08:59:44,512 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-22 08:59:44,514 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-22 08:59:44,515 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-22 08:59:44,517 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-22 08:59:44,522 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-22 08:59:44,523 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-22 08:59:44,523 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-22 08:59:44,524 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-22 08:59:44,525 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-22 08:59:44,525 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-22 08:59:44,528 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-22 08:59:44,530 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-22 08:59:44,531 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-22 08:59:44,532 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-22 08:59:44,536 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-22 08:59:44,538 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-22 08:59:44,539 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-22 08:59:44,539 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-22 08:59:44,539 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-22 08:59:44,540 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-22 08:59:44,540 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-22 08:59:44,541 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-22 08:59:44,541 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-22 08:59:44,541 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-22 08:59:44,542 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-22 08:59:44,545 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-22 08:59:44,545 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-22 08:59:44,547 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-22 08:59:44,548 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-22 08:59:44,548 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-22 08:59:44,548 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-22 08:59:44,549 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-22 08:59:44,549 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-22 08:59:44,550 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-22 08:59:44,561 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-22 08:59:44,570 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-22 08:59:44,571 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-22 08:59:44,572 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-22 08:59:44,572 INFO L138 SettingsManager]: * Use SBE=true [2019-10-22 08:59:44,572 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-22 08:59:44,572 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-22 08:59:44,572 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-22 08:59:44,572 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-22 08:59:44,573 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-22 08:59:44,573 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-22 08:59:44,573 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-22 08:59:44,573 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-22 08:59:44,573 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-22 08:59:44,573 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-22 08:59:44,573 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-22 08:59:44,574 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-22 08:59:44,574 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-22 08:59:44,574 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-22 08:59:44,575 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-22 08:59:44,576 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-22 08:59:44,576 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-22 08:59:44,576 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-22 08:59:44,576 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-22 08:59:44,576 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-22 08:59:44,576 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-22 08:59:44,577 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-22 08:59:44,577 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-22 08:59:44,577 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 447c919af4e106e36f468570351956f4c77293d2 [2019-10-22 08:59:44,617 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-22 08:59:44,630 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-22 08:59:44,632 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-22 08:59:44,634 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-22 08:59:44,634 INFO L275 PluginConnector]: CDTParser initialized [2019-10-22 08:59:44,635 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-10-22 08:59:44,678 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/data/5aed4e55b/32dd819cc3864181b2f48b1a1b987da9/FLAGcb77f3d55 [2019-10-22 08:59:45,077 INFO L306 CDTParser]: Found 1 translation units. [2019-10-22 08:59:45,078 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-10-22 08:59:45,086 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/data/5aed4e55b/32dd819cc3864181b2f48b1a1b987da9/FLAGcb77f3d55 [2019-10-22 08:59:45,097 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/data/5aed4e55b/32dd819cc3864181b2f48b1a1b987da9 [2019-10-22 08:59:45,103 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-22 08:59:45,104 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-10-22 08:59:45,106 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-22 08:59:45,107 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-22 08:59:45,110 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-22 08:59:45,111 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 08:59:45" (1/1) ... [2019-10-22 08:59:45,113 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4da91b93 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45, skipping insertion in model container [2019-10-22 08:59:45,113 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 08:59:45" (1/1) ... [2019-10-22 08:59:45,122 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-22 08:59:45,155 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-22 08:59:45,466 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 08:59:45,472 INFO L188 MainTranslator]: Completed pre-run [2019-10-22 08:59:45,527 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 08:59:45,553 INFO L192 MainTranslator]: Completed translation [2019-10-22 08:59:45,554 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45 WrapperNode [2019-10-22 08:59:45,554 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-22 08:59:45,555 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-10-22 08:59:45,555 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-10-22 08:59:45,556 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-10-22 08:59:45,564 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45" (1/1) ... [2019-10-22 08:59:45,572 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45" (1/1) ... [2019-10-22 08:59:45,616 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-10-22 08:59:45,617 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-22 08:59:45,617 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-22 08:59:45,617 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-22 08:59:45,631 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45" (1/1) ... [2019-10-22 08:59:45,632 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45" (1/1) ... [2019-10-22 08:59:45,640 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45" (1/1) ... [2019-10-22 08:59:45,641 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45" (1/1) ... [2019-10-22 08:59:45,650 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45" (1/1) ... [2019-10-22 08:59:45,674 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45" (1/1) ... [2019-10-22 08:59:45,678 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45" (1/1) ... [2019-10-22 08:59:45,690 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-22 08:59:45,691 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-22 08:59:45,691 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-22 08:59:45,691 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-22 08:59:45,691 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-22 08:59:45,754 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-22 08:59:45,754 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-22 08:59:46,767 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-22 08:59:46,767 INFO L284 CfgBuilder]: Removed 119 assume(true) statements. [2019-10-22 08:59:46,769 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:59:46 BoogieIcfgContainer [2019-10-22 08:59:46,769 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-22 08:59:46,771 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-22 08:59:46,772 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-22 08:59:46,775 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-22 08:59:46,776 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 22.10 08:59:45" (1/3) ... [2019-10-22 08:59:46,777 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@73a49e9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.10 08:59:46, skipping insertion in model container [2019-10-22 08:59:46,777 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:45" (2/3) ... [2019-10-22 08:59:46,777 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@73a49e9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.10 08:59:46, skipping insertion in model container [2019-10-22 08:59:46,777 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:59:46" (3/3) ... [2019-10-22 08:59:46,779 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.03.cil.c [2019-10-22 08:59:46,789 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-22 08:59:46,805 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-22 08:59:46,817 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-22 08:59:46,849 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-22 08:59:46,849 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-22 08:59:46,849 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-22 08:59:46,849 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-22 08:59:46,855 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-22 08:59:46,855 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-22 08:59:46,855 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-22 08:59:46,855 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-22 08:59:46,881 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states. [2019-10-22 08:59:46,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-22 08:59:46,890 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:46,890 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:46,892 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:46,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:46,899 INFO L82 PathProgramCache]: Analyzing trace with hash -1838342379, now seen corresponding path program 1 times [2019-10-22 08:59:46,907 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:46,907 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1756768980] [2019-10-22 08:59:46,908 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:46,908 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:46,908 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:47,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:47,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:47,058 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1756768980] [2019-10-22 08:59:47,058 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:47,059 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:47,059 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762205116] [2019-10-22 08:59:47,063 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:47,063 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:47,075 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:47,076 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,078 INFO L87 Difference]: Start difference. First operand 276 states. Second operand 3 states. [2019-10-22 08:59:47,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:47,141 INFO L93 Difference]: Finished difference Result 547 states and 857 transitions. [2019-10-22 08:59:47,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:47,143 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-10-22 08:59:47,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:47,155 INFO L225 Difference]: With dead ends: 547 [2019-10-22 08:59:47,155 INFO L226 Difference]: Without dead ends: 272 [2019-10-22 08:59:47,159 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2019-10-22 08:59:47,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 272. [2019-10-22 08:59:47,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 272 states. [2019-10-22 08:59:47,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 272 states to 272 states and 412 transitions. [2019-10-22 08:59:47,213 INFO L78 Accepts]: Start accepts. Automaton has 272 states and 412 transitions. Word has length 61 [2019-10-22 08:59:47,213 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:47,213 INFO L462 AbstractCegarLoop]: Abstraction has 272 states and 412 transitions. [2019-10-22 08:59:47,213 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:47,214 INFO L276 IsEmpty]: Start isEmpty. Operand 272 states and 412 transitions. [2019-10-22 08:59:47,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-22 08:59:47,215 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:47,215 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:47,215 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:47,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:47,216 INFO L82 PathProgramCache]: Analyzing trace with hash 1195707667, now seen corresponding path program 1 times [2019-10-22 08:59:47,216 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:47,216 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142328815] [2019-10-22 08:59:47,216 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,216 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,217 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:47,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:47,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:47,261 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [142328815] [2019-10-22 08:59:47,261 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:47,261 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:47,262 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378647624] [2019-10-22 08:59:47,263 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:47,263 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:47,264 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:47,264 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,264 INFO L87 Difference]: Start difference. First operand 272 states and 412 transitions. Second operand 3 states. [2019-10-22 08:59:47,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:47,348 INFO L93 Difference]: Finished difference Result 730 states and 1104 transitions. [2019-10-22 08:59:47,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:47,349 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-10-22 08:59:47,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:47,352 INFO L225 Difference]: With dead ends: 730 [2019-10-22 08:59:47,352 INFO L226 Difference]: Without dead ends: 466 [2019-10-22 08:59:47,354 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states. [2019-10-22 08:59:47,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 464. [2019-10-22 08:59:47,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-10-22 08:59:47,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 694 transitions. [2019-10-22 08:59:47,392 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 694 transitions. Word has length 61 [2019-10-22 08:59:47,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:47,392 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 694 transitions. [2019-10-22 08:59:47,393 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:47,393 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 694 transitions. [2019-10-22 08:59:47,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-22 08:59:47,394 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:47,394 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:47,397 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:47,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:47,397 INFO L82 PathProgramCache]: Analyzing trace with hash 266288339, now seen corresponding path program 1 times [2019-10-22 08:59:47,397 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:47,398 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052539592] [2019-10-22 08:59:47,398 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,399 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,399 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:47,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:47,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:47,475 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052539592] [2019-10-22 08:59:47,475 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:47,475 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:47,476 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [940281360] [2019-10-22 08:59:47,476 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:47,476 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:47,476 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:47,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,477 INFO L87 Difference]: Start difference. First operand 464 states and 694 transitions. Second operand 3 states. [2019-10-22 08:59:47,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:47,508 INFO L93 Difference]: Finished difference Result 919 states and 1375 transitions. [2019-10-22 08:59:47,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:47,509 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-10-22 08:59:47,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:47,511 INFO L225 Difference]: With dead ends: 919 [2019-10-22 08:59:47,511 INFO L226 Difference]: Without dead ends: 464 [2019-10-22 08:59:47,512 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-10-22 08:59:47,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-10-22 08:59:47,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-10-22 08:59:47,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 686 transitions. [2019-10-22 08:59:47,560 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 686 transitions. Word has length 61 [2019-10-22 08:59:47,560 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:47,561 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 686 transitions. [2019-10-22 08:59:47,561 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:47,561 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 686 transitions. [2019-10-22 08:59:47,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-22 08:59:47,567 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:47,567 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:47,568 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:47,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:47,568 INFO L82 PathProgramCache]: Analyzing trace with hash 710189013, now seen corresponding path program 1 times [2019-10-22 08:59:47,568 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:47,568 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000296901] [2019-10-22 08:59:47,568 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,569 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,569 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:47,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:47,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:47,624 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000296901] [2019-10-22 08:59:47,625 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:47,625 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:47,625 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818884882] [2019-10-22 08:59:47,625 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:47,626 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:47,626 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:47,627 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,627 INFO L87 Difference]: Start difference. First operand 464 states and 686 transitions. Second operand 3 states. [2019-10-22 08:59:47,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:47,665 INFO L93 Difference]: Finished difference Result 918 states and 1358 transitions. [2019-10-22 08:59:47,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:47,666 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-10-22 08:59:47,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:47,668 INFO L225 Difference]: With dead ends: 918 [2019-10-22 08:59:47,669 INFO L226 Difference]: Without dead ends: 464 [2019-10-22 08:59:47,670 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-10-22 08:59:47,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-10-22 08:59:47,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-10-22 08:59:47,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 678 transitions. [2019-10-22 08:59:47,698 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 678 transitions. Word has length 61 [2019-10-22 08:59:47,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:47,699 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 678 transitions. [2019-10-22 08:59:47,699 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:47,699 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 678 transitions. [2019-10-22 08:59:47,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-22 08:59:47,700 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:47,701 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:47,701 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:47,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:47,701 INFO L82 PathProgramCache]: Analyzing trace with hash -1623736427, now seen corresponding path program 1 times [2019-10-22 08:59:47,701 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:47,702 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689569967] [2019-10-22 08:59:47,702 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,704 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,705 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:47,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:47,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:47,752 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1689569967] [2019-10-22 08:59:47,752 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:47,752 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:47,753 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [131921094] [2019-10-22 08:59:47,753 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:47,753 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:47,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:47,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,754 INFO L87 Difference]: Start difference. First operand 464 states and 678 transitions. Second operand 3 states. [2019-10-22 08:59:47,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:47,789 INFO L93 Difference]: Finished difference Result 917 states and 1341 transitions. [2019-10-22 08:59:47,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:47,790 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-10-22 08:59:47,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:47,792 INFO L225 Difference]: With dead ends: 917 [2019-10-22 08:59:47,792 INFO L226 Difference]: Without dead ends: 464 [2019-10-22 08:59:47,793 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-10-22 08:59:47,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-10-22 08:59:47,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-10-22 08:59:47,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 670 transitions. [2019-10-22 08:59:47,813 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 670 transitions. Word has length 61 [2019-10-22 08:59:47,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:47,813 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 670 transitions. [2019-10-22 08:59:47,813 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:47,814 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 670 transitions. [2019-10-22 08:59:47,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-22 08:59:47,815 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:47,815 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:47,815 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:47,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:47,816 INFO L82 PathProgramCache]: Analyzing trace with hash -175003691, now seen corresponding path program 1 times [2019-10-22 08:59:47,816 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:47,816 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797781172] [2019-10-22 08:59:47,816 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,816 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,817 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:47,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:47,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:47,843 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797781172] [2019-10-22 08:59:47,843 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:47,843 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:47,843 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636528024] [2019-10-22 08:59:47,844 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:47,844 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:47,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:47,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,844 INFO L87 Difference]: Start difference. First operand 464 states and 670 transitions. Second operand 3 states. [2019-10-22 08:59:47,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:47,893 INFO L93 Difference]: Finished difference Result 916 states and 1324 transitions. [2019-10-22 08:59:47,893 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:47,894 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-10-22 08:59:47,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:47,895 INFO L225 Difference]: With dead ends: 916 [2019-10-22 08:59:47,895 INFO L226 Difference]: Without dead ends: 464 [2019-10-22 08:59:47,896 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-10-22 08:59:47,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-10-22 08:59:47,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-10-22 08:59:47,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 654 transitions. [2019-10-22 08:59:47,916 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 654 transitions. Word has length 61 [2019-10-22 08:59:47,916 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:47,917 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 654 transitions. [2019-10-22 08:59:47,917 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:47,917 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 654 transitions. [2019-10-22 08:59:47,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-22 08:59:47,918 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:47,918 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:47,918 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:47,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:47,919 INFO L82 PathProgramCache]: Analyzing trace with hash -1945036492, now seen corresponding path program 1 times [2019-10-22 08:59:47,919 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:47,919 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565872435] [2019-10-22 08:59:47,919 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,920 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:47,920 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:47,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:47,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:47,944 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565872435] [2019-10-22 08:59:47,944 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:47,944 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:47,944 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [493990264] [2019-10-22 08:59:47,945 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:47,945 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:47,945 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:47,945 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,946 INFO L87 Difference]: Start difference. First operand 464 states and 654 transitions. Second operand 3 states. [2019-10-22 08:59:47,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:47,995 INFO L93 Difference]: Finished difference Result 914 states and 1289 transitions. [2019-10-22 08:59:47,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:47,996 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-10-22 08:59:47,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:47,997 INFO L225 Difference]: With dead ends: 914 [2019-10-22 08:59:47,997 INFO L226 Difference]: Without dead ends: 464 [2019-10-22 08:59:47,998 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:47,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-10-22 08:59:48,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-10-22 08:59:48,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-10-22 08:59:48,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 638 transitions. [2019-10-22 08:59:48,015 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 638 transitions. Word has length 61 [2019-10-22 08:59:48,015 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:48,016 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 638 transitions. [2019-10-22 08:59:48,016 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:48,016 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 638 transitions. [2019-10-22 08:59:48,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-22 08:59:48,016 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:48,016 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:48,017 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:48,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:48,017 INFO L82 PathProgramCache]: Analyzing trace with hash -1902661357, now seen corresponding path program 1 times [2019-10-22 08:59:48,017 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:48,017 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871287963] [2019-10-22 08:59:48,017 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:48,017 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:48,018 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:48,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:48,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:48,084 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [871287963] [2019-10-22 08:59:48,085 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:48,085 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:48,085 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821771990] [2019-10-22 08:59:48,085 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:48,085 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:48,085 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:48,086 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:48,086 INFO L87 Difference]: Start difference. First operand 464 states and 638 transitions. Second operand 3 states. [2019-10-22 08:59:48,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:48,146 INFO L93 Difference]: Finished difference Result 915 states and 1259 transitions. [2019-10-22 08:59:48,147 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:48,147 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-10-22 08:59:48,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:48,149 INFO L225 Difference]: With dead ends: 915 [2019-10-22 08:59:48,149 INFO L226 Difference]: Without dead ends: 464 [2019-10-22 08:59:48,150 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:48,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-10-22 08:59:48,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-10-22 08:59:48,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-10-22 08:59:48,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 622 transitions. [2019-10-22 08:59:48,173 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 622 transitions. Word has length 61 [2019-10-22 08:59:48,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:48,173 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 622 transitions. [2019-10-22 08:59:48,173 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:48,173 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 622 transitions. [2019-10-22 08:59:48,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-22 08:59:48,175 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:48,175 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:48,176 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:48,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:48,176 INFO L82 PathProgramCache]: Analyzing trace with hash 398161233, now seen corresponding path program 1 times [2019-10-22 08:59:48,176 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:48,176 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809404632] [2019-10-22 08:59:48,176 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:48,177 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:48,177 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:48,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:48,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:48,222 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1809404632] [2019-10-22 08:59:48,222 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:48,222 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:48,223 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94391303] [2019-10-22 08:59:48,223 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:48,223 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:48,224 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:48,224 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:48,224 INFO L87 Difference]: Start difference. First operand 464 states and 622 transitions. Second operand 3 states. [2019-10-22 08:59:48,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:48,338 INFO L93 Difference]: Finished difference Result 1299 states and 1732 transitions. [2019-10-22 08:59:48,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:48,339 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-10-22 08:59:48,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:48,342 INFO L225 Difference]: With dead ends: 1299 [2019-10-22 08:59:48,342 INFO L226 Difference]: Without dead ends: 884 [2019-10-22 08:59:48,343 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:48,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 884 states. [2019-10-22 08:59:48,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 884 to 834. [2019-10-22 08:59:48,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 834 states. [2019-10-22 08:59:48,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 834 states to 834 states and 1099 transitions. [2019-10-22 08:59:48,375 INFO L78 Accepts]: Start accepts. Automaton has 834 states and 1099 transitions. Word has length 61 [2019-10-22 08:59:48,375 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:48,377 INFO L462 AbstractCegarLoop]: Abstraction has 834 states and 1099 transitions. [2019-10-22 08:59:48,377 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:48,377 INFO L276 IsEmpty]: Start isEmpty. Operand 834 states and 1099 transitions. [2019-10-22 08:59:48,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2019-10-22 08:59:48,377 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:48,378 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:48,378 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:48,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:48,378 INFO L82 PathProgramCache]: Analyzing trace with hash -276756042, now seen corresponding path program 1 times [2019-10-22 08:59:48,379 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:48,379 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836867364] [2019-10-22 08:59:48,379 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:48,379 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:48,379 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:48,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:48,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:48,409 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1836867364] [2019-10-22 08:59:48,409 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:48,409 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:48,409 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239250531] [2019-10-22 08:59:48,410 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:48,410 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:48,410 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:48,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:48,411 INFO L87 Difference]: Start difference. First operand 834 states and 1099 transitions. Second operand 3 states. [2019-10-22 08:59:48,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:48,499 INFO L93 Difference]: Finished difference Result 2234 states and 2945 transitions. [2019-10-22 08:59:48,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:48,499 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 62 [2019-10-22 08:59:48,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:48,504 INFO L225 Difference]: With dead ends: 2234 [2019-10-22 08:59:48,504 INFO L226 Difference]: Without dead ends: 1494 [2019-10-22 08:59:48,505 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:48,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1494 states. [2019-10-22 08:59:48,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1494 to 1424. [2019-10-22 08:59:48,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1424 states. [2019-10-22 08:59:48,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1424 states to 1424 states and 1862 transitions. [2019-10-22 08:59:48,559 INFO L78 Accepts]: Start accepts. Automaton has 1424 states and 1862 transitions. Word has length 62 [2019-10-22 08:59:48,559 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:48,560 INFO L462 AbstractCegarLoop]: Abstraction has 1424 states and 1862 transitions. [2019-10-22 08:59:48,560 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:48,560 INFO L276 IsEmpty]: Start isEmpty. Operand 1424 states and 1862 transitions. [2019-10-22 08:59:48,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-22 08:59:48,560 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:48,561 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:48,561 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:48,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:48,561 INFO L82 PathProgramCache]: Analyzing trace with hash -2032591659, now seen corresponding path program 1 times [2019-10-22 08:59:48,561 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:48,561 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8950635] [2019-10-22 08:59:48,561 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:48,562 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:48,562 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:48,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:48,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:48,598 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [8950635] [2019-10-22 08:59:48,599 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:48,599 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:48,599 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977399236] [2019-10-22 08:59:48,599 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:48,599 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:48,599 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:48,600 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:48,600 INFO L87 Difference]: Start difference. First operand 1424 states and 1862 transitions. Second operand 3 states. [2019-10-22 08:59:48,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:48,722 INFO L93 Difference]: Finished difference Result 3972 states and 5180 transitions. [2019-10-22 08:59:48,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:48,722 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-10-22 08:59:48,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:48,730 INFO L225 Difference]: With dead ends: 3972 [2019-10-22 08:59:48,730 INFO L226 Difference]: Without dead ends: 2642 [2019-10-22 08:59:48,733 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:48,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2642 states. [2019-10-22 08:59:48,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2642 to 2560. [2019-10-22 08:59:48,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2560 states. [2019-10-22 08:59:48,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2560 states to 2560 states and 3314 transitions. [2019-10-22 08:59:48,831 INFO L78 Accepts]: Start accepts. Automaton has 2560 states and 3314 transitions. Word has length 63 [2019-10-22 08:59:48,831 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:48,831 INFO L462 AbstractCegarLoop]: Abstraction has 2560 states and 3314 transitions. [2019-10-22 08:59:48,831 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:48,831 INFO L276 IsEmpty]: Start isEmpty. Operand 2560 states and 3314 transitions. [2019-10-22 08:59:48,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-22 08:59:48,832 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:48,832 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:48,833 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:48,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:48,833 INFO L82 PathProgramCache]: Analyzing trace with hash -1324102959, now seen corresponding path program 1 times [2019-10-22 08:59:48,833 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:48,833 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463923630] [2019-10-22 08:59:48,833 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:48,834 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:48,834 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:48,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:48,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:48,849 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1463923630] [2019-10-22 08:59:48,849 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:48,850 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:48,850 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985293413] [2019-10-22 08:59:48,850 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:48,850 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:48,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:48,851 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:48,851 INFO L87 Difference]: Start difference. First operand 2560 states and 3314 transitions. Second operand 3 states. [2019-10-22 08:59:48,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:48,940 INFO L93 Difference]: Finished difference Result 4968 states and 6441 transitions. [2019-10-22 08:59:48,940 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:48,940 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-10-22 08:59:48,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:48,947 INFO L225 Difference]: With dead ends: 4968 [2019-10-22 08:59:48,947 INFO L226 Difference]: Without dead ends: 2474 [2019-10-22 08:59:48,950 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:48,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2474 states. [2019-10-22 08:59:49,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2474 to 2474. [2019-10-22 08:59:49,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2474 states. [2019-10-22 08:59:49,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2474 states to 2474 states and 3208 transitions. [2019-10-22 08:59:49,046 INFO L78 Accepts]: Start accepts. Automaton has 2474 states and 3208 transitions. Word has length 63 [2019-10-22 08:59:49,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:49,047 INFO L462 AbstractCegarLoop]: Abstraction has 2474 states and 3208 transitions. [2019-10-22 08:59:49,047 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:49,047 INFO L276 IsEmpty]: Start isEmpty. Operand 2474 states and 3208 transitions. [2019-10-22 08:59:49,047 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-10-22 08:59:49,047 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:49,048 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:49,048 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:49,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:49,048 INFO L82 PathProgramCache]: Analyzing trace with hash -1607983393, now seen corresponding path program 1 times [2019-10-22 08:59:49,048 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:49,048 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677942309] [2019-10-22 08:59:49,048 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:49,049 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:49,049 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:49,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:49,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:49,090 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [677942309] [2019-10-22 08:59:49,090 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:49,090 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:49,090 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [258488051] [2019-10-22 08:59:49,091 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:49,091 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:49,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:49,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:49,091 INFO L87 Difference]: Start difference. First operand 2474 states and 3208 transitions. Second operand 3 states. [2019-10-22 08:59:49,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:49,327 INFO L93 Difference]: Finished difference Result 7190 states and 9333 transitions. [2019-10-22 08:59:49,328 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:49,328 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2019-10-22 08:59:49,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:49,343 INFO L225 Difference]: With dead ends: 7190 [2019-10-22 08:59:49,343 INFO L226 Difference]: Without dead ends: 4786 [2019-10-22 08:59:49,346 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:49,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4786 states. [2019-10-22 08:59:49,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4786 to 4754. [2019-10-22 08:59:49,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4754 states. [2019-10-22 08:59:49,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4754 states to 4754 states and 6114 transitions. [2019-10-22 08:59:49,512 INFO L78 Accepts]: Start accepts. Automaton has 4754 states and 6114 transitions. Word has length 64 [2019-10-22 08:59:49,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:49,512 INFO L462 AbstractCegarLoop]: Abstraction has 4754 states and 6114 transitions. [2019-10-22 08:59:49,512 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:49,513 INFO L276 IsEmpty]: Start isEmpty. Operand 4754 states and 6114 transitions. [2019-10-22 08:59:49,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2019-10-22 08:59:49,514 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:49,515 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:49,515 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:49,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:49,515 INFO L82 PathProgramCache]: Analyzing trace with hash 93244939, now seen corresponding path program 1 times [2019-10-22 08:59:49,515 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:49,515 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373842317] [2019-10-22 08:59:49,516 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:49,516 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:49,516 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:49,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:49,547 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:49,548 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373842317] [2019-10-22 08:59:49,548 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:49,548 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:49,548 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077755753] [2019-10-22 08:59:49,548 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:49,548 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:49,549 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:49,549 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:49,549 INFO L87 Difference]: Start difference. First operand 4754 states and 6114 transitions. Second operand 3 states. [2019-10-22 08:59:49,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:49,827 INFO L93 Difference]: Finished difference Result 14046 states and 18043 transitions. [2019-10-22 08:59:49,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:49,827 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2019-10-22 08:59:49,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:49,854 INFO L225 Difference]: With dead ends: 14046 [2019-10-22 08:59:49,855 INFO L226 Difference]: Without dead ends: 9384 [2019-10-22 08:59:49,861 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:49,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9384 states. [2019-10-22 08:59:50,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9384 to 9384. [2019-10-22 08:59:50,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9384 states. [2019-10-22 08:59:50,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9384 states to 9384 states and 11994 transitions. [2019-10-22 08:59:50,288 INFO L78 Accepts]: Start accepts. Automaton has 9384 states and 11994 transitions. Word has length 81 [2019-10-22 08:59:50,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:50,289 INFO L462 AbstractCegarLoop]: Abstraction has 9384 states and 11994 transitions. [2019-10-22 08:59:50,289 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:50,289 INFO L276 IsEmpty]: Start isEmpty. Operand 9384 states and 11994 transitions. [2019-10-22 08:59:50,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-10-22 08:59:50,294 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:50,294 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:50,294 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:50,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:50,294 INFO L82 PathProgramCache]: Analyzing trace with hash -447123663, now seen corresponding path program 1 times [2019-10-22 08:59:50,294 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:50,294 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34437486] [2019-10-22 08:59:50,295 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:50,295 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:50,295 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:50,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:50,343 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-10-22 08:59:50,343 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [34437486] [2019-10-22 08:59:50,344 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:50,344 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:50,344 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901178917] [2019-10-22 08:59:50,344 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:50,344 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:50,344 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:50,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:50,345 INFO L87 Difference]: Start difference. First operand 9384 states and 11994 transitions. Second operand 3 states. [2019-10-22 08:59:50,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:50,725 INFO L93 Difference]: Finished difference Result 22768 states and 29084 transitions. [2019-10-22 08:59:50,725 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:50,725 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-10-22 08:59:50,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:50,770 INFO L225 Difference]: With dead ends: 22768 [2019-10-22 08:59:50,770 INFO L226 Difference]: Without dead ends: 13486 [2019-10-22 08:59:50,782 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:50,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13486 states. [2019-10-22 08:59:51,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13486 to 13420. [2019-10-22 08:59:51,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13420 states. [2019-10-22 08:59:51,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13420 states to 13420 states and 17034 transitions. [2019-10-22 08:59:51,298 INFO L78 Accepts]: Start accepts. Automaton has 13420 states and 17034 transitions. Word has length 110 [2019-10-22 08:59:51,298 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:51,298 INFO L462 AbstractCegarLoop]: Abstraction has 13420 states and 17034 transitions. [2019-10-22 08:59:51,298 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:51,298 INFO L276 IsEmpty]: Start isEmpty. Operand 13420 states and 17034 transitions. [2019-10-22 08:59:51,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-10-22 08:59:51,305 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:51,306 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:51,306 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:51,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:51,306 INFO L82 PathProgramCache]: Analyzing trace with hash -2122456675, now seen corresponding path program 1 times [2019-10-22 08:59:51,307 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:51,307 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781645678] [2019-10-22 08:59:51,307 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:51,307 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:51,307 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:51,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:51,340 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-10-22 08:59:51,340 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781645678] [2019-10-22 08:59:51,340 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:51,340 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:51,341 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621196569] [2019-10-22 08:59:51,341 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:51,341 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:51,341 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:51,341 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:51,341 INFO L87 Difference]: Start difference. First operand 13420 states and 17034 transitions. Second operand 3 states. [2019-10-22 08:59:51,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:51,841 INFO L93 Difference]: Finished difference Result 32624 states and 41352 transitions. [2019-10-22 08:59:51,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:51,842 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-10-22 08:59:51,842 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:51,879 INFO L225 Difference]: With dead ends: 32624 [2019-10-22 08:59:51,879 INFO L226 Difference]: Without dead ends: 19278 [2019-10-22 08:59:51,895 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:51,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19278 states. [2019-10-22 08:59:52,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19278 to 19180. [2019-10-22 08:59:52,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19180 states. [2019-10-22 08:59:52,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19180 states to 19180 states and 24146 transitions. [2019-10-22 08:59:52,707 INFO L78 Accepts]: Start accepts. Automaton has 19180 states and 24146 transitions. Word has length 110 [2019-10-22 08:59:52,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:52,707 INFO L462 AbstractCegarLoop]: Abstraction has 19180 states and 24146 transitions. [2019-10-22 08:59:52,707 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:52,707 INFO L276 IsEmpty]: Start isEmpty. Operand 19180 states and 24146 transitions. [2019-10-22 08:59:52,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-10-22 08:59:52,717 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:52,718 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:52,718 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:52,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:52,718 INFO L82 PathProgramCache]: Analyzing trace with hash -4233773, now seen corresponding path program 1 times [2019-10-22 08:59:52,718 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:52,718 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445696806] [2019-10-22 08:59:52,718 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:52,719 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:52,719 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:52,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:52,773 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-10-22 08:59:52,773 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445696806] [2019-10-22 08:59:52,773 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:52,773 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:59:52,773 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848369243] [2019-10-22 08:59:52,774 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 08:59:52,774 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:52,774 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:59:52,775 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:59:52,775 INFO L87 Difference]: Start difference. First operand 19180 states and 24146 transitions. Second operand 5 states. [2019-10-22 08:59:53,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:53,761 INFO L93 Difference]: Finished difference Result 47102 states and 59685 transitions. [2019-10-22 08:59:53,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 08:59:53,762 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-10-22 08:59:53,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:53,804 INFO L225 Difference]: With dead ends: 47102 [2019-10-22 08:59:53,805 INFO L226 Difference]: Without dead ends: 28012 [2019-10-22 08:59:53,824 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-10-22 08:59:53,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28012 states. [2019-10-22 08:59:54,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28012 to 19324. [2019-10-22 08:59:54,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19324 states. [2019-10-22 08:59:54,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19324 states to 19324 states and 23950 transitions. [2019-10-22 08:59:54,561 INFO L78 Accepts]: Start accepts. Automaton has 19324 states and 23950 transitions. Word has length 110 [2019-10-22 08:59:54,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:54,561 INFO L462 AbstractCegarLoop]: Abstraction has 19324 states and 23950 transitions. [2019-10-22 08:59:54,561 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 08:59:54,561 INFO L276 IsEmpty]: Start isEmpty. Operand 19324 states and 23950 transitions. [2019-10-22 08:59:54,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-10-22 08:59:54,574 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:54,574 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:54,575 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:54,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:54,575 INFO L82 PathProgramCache]: Analyzing trace with hash 2012797655, now seen corresponding path program 1 times [2019-10-22 08:59:54,575 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:54,575 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099892497] [2019-10-22 08:59:54,575 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:54,576 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:54,576 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:54,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:54,625 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-10-22 08:59:54,625 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099892497] [2019-10-22 08:59:54,626 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:54,626 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:59:54,626 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [765109685] [2019-10-22 08:59:54,626 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 08:59:54,627 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:54,627 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:59:54,627 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:59:54,628 INFO L87 Difference]: Start difference. First operand 19324 states and 23950 transitions. Second operand 5 states. [2019-10-22 08:59:55,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:55,836 INFO L93 Difference]: Finished difference Result 45442 states and 56677 transitions. [2019-10-22 08:59:55,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 08:59:55,836 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-10-22 08:59:55,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:55,878 INFO L225 Difference]: With dead ends: 45442 [2019-10-22 08:59:55,878 INFO L226 Difference]: Without dead ends: 26232 [2019-10-22 08:59:55,894 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-10-22 08:59:55,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26232 states. [2019-10-22 08:59:56,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26232 to 19420. [2019-10-22 08:59:56,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19420 states. [2019-10-22 08:59:56,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19420 states to 19420 states and 23690 transitions. [2019-10-22 08:59:56,869 INFO L78 Accepts]: Start accepts. Automaton has 19420 states and 23690 transitions. Word has length 110 [2019-10-22 08:59:56,870 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:56,870 INFO L462 AbstractCegarLoop]: Abstraction has 19420 states and 23690 transitions. [2019-10-22 08:59:56,870 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 08:59:56,870 INFO L276 IsEmpty]: Start isEmpty. Operand 19420 states and 23690 transitions. [2019-10-22 08:59:56,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-10-22 08:59:56,878 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:56,878 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:56,879 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:56,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:56,879 INFO L82 PathProgramCache]: Analyzing trace with hash 564093659, now seen corresponding path program 1 times [2019-10-22 08:59:56,879 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:56,879 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253442511] [2019-10-22 08:59:56,879 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:56,879 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:56,879 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:56,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:56,925 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:56,926 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253442511] [2019-10-22 08:59:56,926 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:56,926 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:56,926 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502480592] [2019-10-22 08:59:56,927 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:56,927 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:56,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:56,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:56,928 INFO L87 Difference]: Start difference. First operand 19420 states and 23690 transitions. Second operand 3 states. [2019-10-22 08:59:57,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:57,538 INFO L93 Difference]: Finished difference Result 29198 states and 35739 transitions. [2019-10-22 08:59:57,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:57,539 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-10-22 08:59:57,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:57,573 INFO L225 Difference]: With dead ends: 29198 [2019-10-22 08:59:57,573 INFO L226 Difference]: Without dead ends: 19420 [2019-10-22 08:59:57,584 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:57,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19420 states. [2019-10-22 08:59:58,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19420 to 19350. [2019-10-22 08:59:58,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19350 states. [2019-10-22 08:59:58,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19350 states to 19350 states and 23356 transitions. [2019-10-22 08:59:58,098 INFO L78 Accepts]: Start accepts. Automaton has 19350 states and 23356 transitions. Word has length 110 [2019-10-22 08:59:58,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:58,098 INFO L462 AbstractCegarLoop]: Abstraction has 19350 states and 23356 transitions. [2019-10-22 08:59:58,098 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 08:59:58,098 INFO L276 IsEmpty]: Start isEmpty. Operand 19350 states and 23356 transitions. [2019-10-22 08:59:58,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-10-22 08:59:58,107 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:58,108 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:58,108 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:58,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:58,108 INFO L82 PathProgramCache]: Analyzing trace with hash 770898653, now seen corresponding path program 1 times [2019-10-22 08:59:58,108 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:58,109 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784242254] [2019-10-22 08:59:58,109 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:58,109 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:58,109 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:58,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:58,159 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-10-22 08:59:58,160 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1784242254] [2019-10-22 08:59:58,160 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:58,160 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:59:58,160 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [179503229] [2019-10-22 08:59:58,161 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 08:59:58,161 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:58,161 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:59:58,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:59:58,162 INFO L87 Difference]: Start difference. First operand 19350 states and 23356 transitions. Second operand 5 states. [2019-10-22 08:59:59,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:59,231 INFO L93 Difference]: Finished difference Result 37116 states and 45101 transitions. [2019-10-22 08:59:59,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 08:59:59,232 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2019-10-22 08:59:59,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 08:59:59,260 INFO L225 Difference]: With dead ends: 37116 [2019-10-22 08:59:59,261 INFO L226 Difference]: Without dead ends: 17840 [2019-10-22 08:59:59,273 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-10-22 08:59:59,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17840 states. [2019-10-22 08:59:59,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17840 to 13178. [2019-10-22 08:59:59,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13178 states. [2019-10-22 08:59:59,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13178 states to 13178 states and 15698 transitions. [2019-10-22 08:59:59,747 INFO L78 Accepts]: Start accepts. Automaton has 13178 states and 15698 transitions. Word has length 111 [2019-10-22 08:59:59,747 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 08:59:59,747 INFO L462 AbstractCegarLoop]: Abstraction has 13178 states and 15698 transitions. [2019-10-22 08:59:59,748 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 08:59:59,748 INFO L276 IsEmpty]: Start isEmpty. Operand 13178 states and 15698 transitions. [2019-10-22 08:59:59,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-10-22 08:59:59,754 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 08:59:59,754 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:59,755 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 08:59:59,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:59,755 INFO L82 PathProgramCache]: Analyzing trace with hash 273196097, now seen corresponding path program 1 times [2019-10-22 08:59:59,755 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:59,755 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032717870] [2019-10-22 08:59:59,755 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:59,755 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:59,756 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:59,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:59,785 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:59,786 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032717870] [2019-10-22 08:59:59,786 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:59,786 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:59,786 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455322523] [2019-10-22 08:59:59,787 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 08:59:59,787 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:59,787 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:59,787 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:59,787 INFO L87 Difference]: Start difference. First operand 13178 states and 15698 transitions. Second operand 3 states. [2019-10-22 09:00:00,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:00,108 INFO L93 Difference]: Finished difference Result 21196 states and 25354 transitions. [2019-10-22 09:00:00,109 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:00,109 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-10-22 09:00:00,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:00,126 INFO L225 Difference]: With dead ends: 21196 [2019-10-22 09:00:00,126 INFO L226 Difference]: Without dead ends: 11030 [2019-10-22 09:00:00,135 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:00,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-10-22 09:00:00,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-10-22 09:00:00,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-10-22 09:00:00,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13114 transitions. [2019-10-22 09:00:00,668 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13114 transitions. Word has length 113 [2019-10-22 09:00:00,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:00,668 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13114 transitions. [2019-10-22 09:00:00,668 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:00,668 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13114 transitions. [2019-10-22 09:00:00,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2019-10-22 09:00:00,673 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:00,673 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:00,673 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:00,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:00,674 INFO L82 PathProgramCache]: Analyzing trace with hash 1857340375, now seen corresponding path program 1 times [2019-10-22 09:00:00,674 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:00,674 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706303876] [2019-10-22 09:00:00,674 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:00,675 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:00,675 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:00,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:00,713 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:00,713 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706303876] [2019-10-22 09:00:00,713 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:00,713 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:00,714 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387162570] [2019-10-22 09:00:00,714 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:00,714 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:00,714 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:00,715 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:00,715 INFO L87 Difference]: Start difference. First operand 11026 states and 13114 transitions. Second operand 3 states. [2019-10-22 09:00:01,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:01,006 INFO L93 Difference]: Finished difference Result 20200 states and 24102 transitions. [2019-10-22 09:00:01,007 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:01,007 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 146 [2019-10-22 09:00:01,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:01,022 INFO L225 Difference]: With dead ends: 20200 [2019-10-22 09:00:01,023 INFO L226 Difference]: Without dead ends: 11030 [2019-10-22 09:00:01,030 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:01,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-10-22 09:00:01,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-10-22 09:00:01,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-10-22 09:00:01,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13034 transitions. [2019-10-22 09:00:01,347 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13034 transitions. Word has length 146 [2019-10-22 09:00:01,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:01,348 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13034 transitions. [2019-10-22 09:00:01,348 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:01,348 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13034 transitions. [2019-10-22 09:00:01,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-10-22 09:00:01,354 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:01,354 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:01,355 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:01,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:01,355 INFO L82 PathProgramCache]: Analyzing trace with hash 1216535548, now seen corresponding path program 1 times [2019-10-22 09:00:01,355 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:01,355 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632127244] [2019-10-22 09:00:01,355 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:01,355 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:01,355 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:01,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:01,404 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-10-22 09:00:01,404 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632127244] [2019-10-22 09:00:01,404 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:01,404 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 09:00:01,404 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395179864] [2019-10-22 09:00:01,405 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-22 09:00:01,410 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:01,410 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 09:00:01,410 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 09:00:01,411 INFO L87 Difference]: Start difference. First operand 11026 states and 13034 transitions. Second operand 5 states. [2019-10-22 09:00:02,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:02,289 INFO L93 Difference]: Finished difference Result 35306 states and 41589 transitions. [2019-10-22 09:00:02,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 09:00:02,290 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 176 [2019-10-22 09:00:02,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:02,308 INFO L225 Difference]: With dead ends: 35306 [2019-10-22 09:00:02,309 INFO L226 Difference]: Without dead ends: 24343 [2019-10-22 09:00:02,322 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-10-22 09:00:02,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24343 states. [2019-10-22 09:00:02,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24343 to 11410. [2019-10-22 09:00:02,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-10-22 09:00:02,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13328 transitions. [2019-10-22 09:00:02,945 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13328 transitions. Word has length 176 [2019-10-22 09:00:02,945 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:02,945 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13328 transitions. [2019-10-22 09:00:02,945 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-22 09:00:02,945 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13328 transitions. [2019-10-22 09:00:02,950 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-10-22 09:00:02,951 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:02,951 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:02,951 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:02,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:02,951 INFO L82 PathProgramCache]: Analyzing trace with hash 2104709508, now seen corresponding path program 1 times [2019-10-22 09:00:02,952 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:02,952 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223440847] [2019-10-22 09:00:02,952 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:02,952 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:02,952 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:02,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:03,005 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:03,005 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223440847] [2019-10-22 09:00:03,005 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:03,006 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:03,006 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888730914] [2019-10-22 09:00:03,006 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:03,006 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:03,007 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:03,007 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:03,007 INFO L87 Difference]: Start difference. First operand 11410 states and 13328 transitions. Second operand 3 states. [2019-10-22 09:00:03,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:03,361 INFO L93 Difference]: Finished difference Result 19722 states and 23103 transitions. [2019-10-22 09:00:03,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:03,361 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2019-10-22 09:00:03,362 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:03,370 INFO L225 Difference]: With dead ends: 19722 [2019-10-22 09:00:03,371 INFO L226 Difference]: Without dead ends: 11442 [2019-10-22 09:00:03,378 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:03,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11442 states. [2019-10-22 09:00:03,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11442 to 11410. [2019-10-22 09:00:03,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-10-22 09:00:03,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13120 transitions. [2019-10-22 09:00:03,723 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13120 transitions. Word has length 176 [2019-10-22 09:00:03,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:03,724 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13120 transitions. [2019-10-22 09:00:03,724 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:03,724 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13120 transitions. [2019-10-22 09:00:03,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-10-22 09:00:03,727 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:03,728 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:03,728 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:03,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:03,728 INFO L82 PathProgramCache]: Analyzing trace with hash 251088387, now seen corresponding path program 1 times [2019-10-22 09:00:03,728 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:03,728 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092790909] [2019-10-22 09:00:03,728 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:03,729 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:03,729 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:03,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:03,772 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-10-22 09:00:03,773 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092790909] [2019-10-22 09:00:03,773 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:03,773 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:03,773 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1789328807] [2019-10-22 09:00:03,773 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:03,774 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:03,774 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:03,774 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:03,774 INFO L87 Difference]: Start difference. First operand 11410 states and 13120 transitions. Second operand 3 states. [2019-10-22 09:00:04,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:04,341 INFO L93 Difference]: Finished difference Result 22664 states and 25875 transitions. [2019-10-22 09:00:04,342 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:04,342 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-10-22 09:00:04,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:04,348 INFO L225 Difference]: With dead ends: 22664 [2019-10-22 09:00:04,348 INFO L226 Difference]: Without dead ends: 6788 [2019-10-22 09:00:04,357 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:04,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6788 states. [2019-10-22 09:00:04,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6788 to 6580. [2019-10-22 09:00:04,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-10-22 09:00:04,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7290 transitions. [2019-10-22 09:00:04,669 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7290 transitions. Word has length 178 [2019-10-22 09:00:04,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:04,669 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7290 transitions. [2019-10-22 09:00:04,669 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:04,669 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7290 transitions. [2019-10-22 09:00:04,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-10-22 09:00:04,673 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:04,674 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:04,674 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:04,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:04,674 INFO L82 PathProgramCache]: Analyzing trace with hash -32931800, now seen corresponding path program 1 times [2019-10-22 09:00:04,674 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:04,675 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665923191] [2019-10-22 09:00:04,675 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:04,675 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:04,675 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:04,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 09:00:04,719 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 09:00:04,719 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [665923191] [2019-10-22 09:00:04,719 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 09:00:04,719 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 09:00:04,719 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988892136] [2019-10-22 09:00:04,720 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-22 09:00:04,720 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 09:00:04,720 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 09:00:04,721 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:04,721 INFO L87 Difference]: Start difference. First operand 6580 states and 7290 transitions. Second operand 3 states. [2019-10-22 09:00:05,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 09:00:05,092 INFO L93 Difference]: Finished difference Result 11554 states and 12829 transitions. [2019-10-22 09:00:05,092 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 09:00:05,092 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 180 [2019-10-22 09:00:05,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-22 09:00:05,098 INFO L225 Difference]: With dead ends: 11554 [2019-10-22 09:00:05,098 INFO L226 Difference]: Without dead ends: 6580 [2019-10-22 09:00:05,103 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 09:00:05,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6580 states. [2019-10-22 09:00:05,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6580 to 6580. [2019-10-22 09:00:05,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-10-22 09:00:05,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7212 transitions. [2019-10-22 09:00:05,429 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7212 transitions. Word has length 180 [2019-10-22 09:00:05,430 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-22 09:00:05,430 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7212 transitions. [2019-10-22 09:00:05,430 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-22 09:00:05,430 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7212 transitions. [2019-10-22 09:00:05,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2019-10-22 09:00:05,437 INFO L372 BasicCegarLoop]: Found error trace [2019-10-22 09:00:05,437 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 09:00:05,437 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-22 09:00:05,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 09:00:05,437 INFO L82 PathProgramCache]: Analyzing trace with hash 1382104249, now seen corresponding path program 1 times [2019-10-22 09:00:05,438 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 09:00:05,438 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153247957] [2019-10-22 09:00:05,439 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:05,440 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 09:00:05,440 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 09:00:05,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 09:00:05,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 09:00:05,545 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 09:00:05,545 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-10-22 09:00:05,698 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.10 09:00:05 BoogieIcfgContainer [2019-10-22 09:00:05,700 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-10-22 09:00:05,700 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-10-22 09:00:05,700 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-10-22 09:00:05,701 INFO L275 PluginConnector]: Witness Printer initialized [2019-10-22 09:00:05,701 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:59:46" (3/4) ... [2019-10-22 09:00:05,703 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-10-22 09:00:05,853 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_f3feb620-d7fd-49c9-b0f8-a8267c9dd831/bin/uautomizer/witness.graphml [2019-10-22 09:00:05,853 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-10-22 09:00:05,855 INFO L168 Benchmark]: Toolchain (without parser) took 20750.86 ms. Allocated memory was 1.0 GB in the beginning and 3.8 GB in the end (delta: 2.8 GB). Free memory was 950.1 MB in the beginning and 2.9 GB in the end (delta: -2.0 GB). Peak memory consumption was 826.5 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:05,856 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-10-22 09:00:05,857 INFO L168 Benchmark]: CACSL2BoogieTranslator took 448.63 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 194.0 MB). Free memory was 950.1 MB in the beginning and 1.2 GB in the end (delta: -235.3 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:05,857 INFO L168 Benchmark]: Boogie Procedure Inliner took 61.68 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:05,857 INFO L168 Benchmark]: Boogie Preprocessor took 73.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:05,858 INFO L168 Benchmark]: RCFGBuilder took 1078.50 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 74.6 MB). Peak memory consumption was 74.6 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:05,858 INFO L168 Benchmark]: TraceAbstraction took 18929.20 ms. Allocated memory was 1.2 GB in the beginning and 3.8 GB in the end (delta: 2.6 GB). Free memory was 1.1 GB in the beginning and 3.0 GB in the end (delta: -1.9 GB). Peak memory consumption was 708.9 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:05,858 INFO L168 Benchmark]: Witness Printer took 153.17 ms. Allocated memory is still 3.8 GB. Free memory was 3.0 GB in the beginning and 2.9 GB in the end (delta: 76.0 MB). Peak memory consumption was 76.0 MB. Max. memory is 11.5 GB. [2019-10-22 09:00:05,860 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 448.63 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 194.0 MB). Free memory was 950.1 MB in the beginning and 1.2 GB in the end (delta: -235.3 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 61.68 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 73.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1078.50 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 74.6 MB). Peak memory consumption was 74.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 18929.20 ms. Allocated memory was 1.2 GB in the beginning and 3.8 GB in the end (delta: 2.6 GB). Free memory was 1.1 GB in the beginning and 3.0 GB in the end (delta: -1.9 GB). Peak memory consumption was 708.9 MB. Max. memory is 11.5 GB. * Witness Printer took 153.17 ms. Allocated memory is still 3.8 GB. Free memory was 3.0 GB in the beginning and 2.9 GB in the end (delta: 76.0 MB). Peak memory consumption was 76.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int t3_i ; [L27] int M_E = 2; [L28] int T1_E = 2; [L29] int T2_E = 2; [L30] int T3_E = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L687] int __retres1 ; [L600] m_i = 1 [L601] t1_i = 1 [L602] t2_i = 1 [L603] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L628] int kernel_st ; [L629] int tmp ; [L630] int tmp___0 ; [L634] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L271] COND TRUE m_i == 1 [L272] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L276] COND TRUE t1_i == 1 [L277] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L281] COND TRUE t2_i == 1 [L282] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t3_i == 1 [L287] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L408] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L413] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L418] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L187] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L206] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L225] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L244] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L254] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L451] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L456] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L461] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L642] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L645] kernel_st = 1 [L327] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L84] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L119] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L154] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L165] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L167] t3_pc = 1 [L168] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND TRUE \read(tmp_ndt_1) [L346] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L43] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L54] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L57] E_1 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND TRUE E_1 == 1 [L208] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND TRUE \read(tmp___0) [L509] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L59] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L62] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L64] m_pc = 1 [L65] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L84] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L87] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L103] E_2 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND TRUE E_2 == 1 [L227] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND TRUE \read(tmp___1) [L517] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L105] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L119] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L122] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L138] E_3 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND TRUE E_3 == 1 [L246] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND TRUE \read(tmp___2) [L525] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L140] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L154] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L157] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 276 locations, 1 error locations. Result: UNSAFE, OverallTime: 18.8s, OverallIterations: 27, TraceHistogramMax: 2, AutomataDifference: 9.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 10884 SDtfs, 10117 SDslu, 7643 SDs, 0 SdLazy, 500 SolverSat, 248 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 92 GetRequests, 50 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=19420occurred in iteration=18, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 7.5s AutomataMinimizationTime, 26 MinimizatonAttempts, 33813 StatesRemovedByMinimization, 16 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.6s InterpolantComputationTime, 2694 NumberOfCodeBlocks, 2694 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 2486 ConstructedInterpolants, 0 QuantifiedInterpolants, 403400 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 26 InterpolantComputations, 26 PerfectInterpolantSequences, 228/228 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...