./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0c244c639ec9718adcbacffa967b748c52a23cd0 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-10-22 08:59:30,368 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-22 08:59:30,369 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-22 08:59:30,378 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-22 08:59:30,378 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-22 08:59:30,379 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-22 08:59:30,381 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-22 08:59:30,382 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-22 08:59:30,384 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-22 08:59:30,384 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-22 08:59:30,385 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-22 08:59:30,386 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-22 08:59:30,387 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-22 08:59:30,387 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-22 08:59:30,388 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-22 08:59:30,389 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-22 08:59:30,389 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-22 08:59:30,390 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-22 08:59:30,392 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-22 08:59:30,393 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-22 08:59:30,394 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-22 08:59:30,395 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-22 08:59:30,396 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-22 08:59:30,397 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-22 08:59:30,399 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-22 08:59:30,399 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-22 08:59:30,399 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-22 08:59:30,400 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-22 08:59:30,401 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-22 08:59:30,401 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-22 08:59:30,402 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-22 08:59:30,402 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-22 08:59:30,403 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-22 08:59:30,404 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-22 08:59:30,404 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-22 08:59:30,405 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-22 08:59:30,405 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-22 08:59:30,405 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-22 08:59:30,405 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-22 08:59:30,406 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-22 08:59:30,406 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-22 08:59:30,407 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-10-22 08:59:30,420 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-22 08:59:30,420 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-22 08:59:30,421 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-22 08:59:30,421 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-22 08:59:30,421 INFO L138 SettingsManager]: * Use SBE=true [2019-10-22 08:59:30,421 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-10-22 08:59:30,421 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-10-22 08:59:30,422 INFO L138 SettingsManager]: * Use old map elimination=false [2019-10-22 08:59:30,422 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-10-22 08:59:30,422 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-10-22 08:59:30,422 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-10-22 08:59:30,422 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-22 08:59:30,422 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-22 08:59:30,423 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-10-22 08:59:30,423 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-22 08:59:30,423 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-22 08:59:30,423 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-22 08:59:30,424 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-10-22 08:59:30,424 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-10-22 08:59:30,424 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-10-22 08:59:30,424 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-22 08:59:30,424 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-22 08:59:30,424 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-10-22 08:59:30,425 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-22 08:59:30,425 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-10-22 08:59:30,425 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-22 08:59:30,425 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-22 08:59:30,425 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-10-22 08:59:30,426 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-22 08:59:30,426 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-22 08:59:30,426 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-10-22 08:59:30,427 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-10-22 08:59:30,427 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0c244c639ec9718adcbacffa967b748c52a23cd0 [2019-10-22 08:59:30,455 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-22 08:59:30,466 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-22 08:59:30,469 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-22 08:59:30,470 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-22 08:59:30,471 INFO L275 PluginConnector]: CDTParser initialized [2019-10-22 08:59:30,471 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.02.cil.c [2019-10-22 08:59:30,529 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/data/3223e78da/e8a981b3936d4c67a1a84e447bce07d9/FLAG17e4f23b0 [2019-10-22 08:59:30,906 INFO L306 CDTParser]: Found 1 translation units. [2019-10-22 08:59:30,907 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/sv-benchmarks/c/systemc/transmitter.02.cil.c [2019-10-22 08:59:30,915 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/data/3223e78da/e8a981b3936d4c67a1a84e447bce07d9/FLAG17e4f23b0 [2019-10-22 08:59:30,928 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/data/3223e78da/e8a981b3936d4c67a1a84e447bce07d9 [2019-10-22 08:59:30,930 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-22 08:59:30,931 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-10-22 08:59:30,932 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-22 08:59:30,932 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-22 08:59:30,936 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-22 08:59:30,936 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 08:59:30" (1/1) ... [2019-10-22 08:59:30,939 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@525ba5f0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:30, skipping insertion in model container [2019-10-22 08:59:30,939 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 08:59:30" (1/1) ... [2019-10-22 08:59:30,946 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-22 08:59:30,977 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-22 08:59:31,202 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 08:59:31,208 INFO L188 MainTranslator]: Completed pre-run [2019-10-22 08:59:31,242 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 08:59:31,259 INFO L192 MainTranslator]: Completed translation [2019-10-22 08:59:31,259 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31 WrapperNode [2019-10-22 08:59:31,259 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-22 08:59:31,260 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-10-22 08:59:31,260 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-10-22 08:59:31,260 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-10-22 08:59:31,269 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31" (1/1) ... [2019-10-22 08:59:31,281 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31" (1/1) ... [2019-10-22 08:59:31,309 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-10-22 08:59:31,309 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-22 08:59:31,309 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-22 08:59:31,310 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-22 08:59:31,318 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31" (1/1) ... [2019-10-22 08:59:31,319 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31" (1/1) ... [2019-10-22 08:59:31,321 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31" (1/1) ... [2019-10-22 08:59:31,322 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31" (1/1) ... [2019-10-22 08:59:31,329 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31" (1/1) ... [2019-10-22 08:59:31,338 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31" (1/1) ... [2019-10-22 08:59:31,340 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31" (1/1) ... [2019-10-22 08:59:31,343 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-22 08:59:31,344 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-22 08:59:31,344 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-22 08:59:31,344 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-22 08:59:31,345 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:31,420 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-22 08:59:31,420 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-22 08:59:32,020 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-22 08:59:32,020 INFO L284 CfgBuilder]: Removed 94 assume(true) statements. [2019-10-22 08:59:32,021 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:59:32 BoogieIcfgContainer [2019-10-22 08:59:32,021 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-22 08:59:32,022 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-10-22 08:59:32,022 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-10-22 08:59:32,026 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-10-22 08:59:32,027 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-10-22 08:59:32,027 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.10 08:59:30" (1/3) ... [2019-10-22 08:59:32,028 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2e8f183 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.10 08:59:32, skipping insertion in model container [2019-10-22 08:59:32,028 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-10-22 08:59:32,028 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:59:31" (2/3) ... [2019-10-22 08:59:32,029 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2e8f183 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.10 08:59:32, skipping insertion in model container [2019-10-22 08:59:32,029 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-10-22 08:59:32,029 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:59:32" (3/3) ... [2019-10-22 08:59:32,030 INFO L371 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2019-10-22 08:59:32,111 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-10-22 08:59:32,111 INFO L357 BuchiCegarLoop]: Hoare is false [2019-10-22 08:59:32,112 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-10-22 08:59:32,112 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-22 08:59:32,119 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-22 08:59:32,119 INFO L361 BuchiCegarLoop]: Difference is false [2019-10-22 08:59:32,120 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-22 08:59:32,120 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-10-22 08:59:32,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states. [2019-10-22 08:59:32,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 150 [2019-10-22 08:59:32,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:32,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:32,211 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:32,211 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:32,211 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-10-22 08:59:32,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states. [2019-10-22 08:59:32,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 150 [2019-10-22 08:59:32,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:32,220 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:32,222 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:32,222 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:32,234 INFO L791 eck$LassoCheckResult]: Stem: 157#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 13#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 184#L481true havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 130#L204true assume !(1 == ~m_i~0);~m_st~0 := 2; 185#L211-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 54#L216-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 71#L221-1true assume !(0 == ~M_E~0); 180#L324-1true assume !(0 == ~T1_E~0); 18#L329-1true assume !(0 == ~T2_E~0); 68#L334-1true assume !(0 == ~E_1~0); 99#L339-1true assume !(0 == ~E_2~0); 146#L344-1true havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 122#L146true assume !(1 == ~m_pc~0); 116#L146-2true is_master_triggered_~__retres1~0 := 0; 123#L157true is_master_triggered_#res := is_master_triggered_~__retres1~0; 47#L158true activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 44#L395true assume !(0 != activate_threads_~tmp~1); 14#L395-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 141#L165true assume 1 == ~t1_pc~0; 69#L166true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 142#L176true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 70#L177true activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 50#L403true assume !(0 != activate_threads_~tmp___0~0); 55#L403-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 176#L184true assume !(1 == ~t2_pc~0); 172#L184-2true is_transmit2_triggered_~__retres1~2 := 0; 177#L195true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 110#L196true activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 80#L411true assume !(0 != activate_threads_~tmp___1~0); 63#L411-2true assume !(1 == ~M_E~0); 178#L357-1true assume !(1 == ~T1_E~0); 15#L362-1true assume !(1 == ~T2_E~0); 64#L367-1true assume !(1 == ~E_1~0); 95#L372-1true assume !(1 == ~E_2~0); 107#L518-1true [2019-10-22 08:59:32,235 INFO L793 eck$LassoCheckResult]: Loop: 107#L518-1true assume !false; 22#L519true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 19#L299true assume false; 136#L314true start_simulation_~kernel_st~0 := 2; 129#L204-1true start_simulation_~kernel_st~0 := 3; 181#L324-2true assume 0 == ~M_E~0;~M_E~0 := 1; 186#L324-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 25#L329-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 74#L334-3true assume 0 == ~E_1~0;~E_1~0 := 1; 105#L339-3true assume !(0 == ~E_2~0); 152#L344-3true havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 92#L146-9true assume 1 == ~m_pc~0; 34#L147-3true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 113#L157-3true is_master_triggered_#res := is_master_triggered_~__retres1~0; 35#L158-3true activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6#L395-9true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11#L395-11true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 121#L165-9true assume !(1 == ~t1_pc~0); 114#L165-11true is_transmit1_triggered_~__retres1~1 := 0; 162#L176-3true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 85#L177-3true activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 48#L403-9true assume !(0 != activate_threads_~tmp___0~0); 21#L403-11true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 140#L184-9true assume 1 == ~t2_pc~0; 98#L185-3true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 171#L195-3true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 100#L196-3true activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 52#L411-9true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 59#L411-11true assume 1 == ~M_E~0;~M_E~0 := 2; 182#L357-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 23#L362-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 72#L367-3true assume !(1 == ~E_1~0); 103#L372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 150#L377-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 127#L234-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 87#L251-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5#L252-1true start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 115#L537true assume !(0 == start_simulation_~tmp~3); 118#L537-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 125#L234-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 109#L251-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3#L252-2true stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 183#L492true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 76#L499true stop_simulation_#res := stop_simulation_~__retres2~0; 190#L500true start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 175#L550true assume !(0 != start_simulation_~tmp___0~1); 107#L518-1true [2019-10-22 08:59:32,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:32,244 INFO L82 PathProgramCache]: Analyzing trace with hash 1765217540, now seen corresponding path program 1 times [2019-10-22 08:59:32,252 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:32,252 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131873083] [2019-10-22 08:59:32,252 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,252 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,252 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:32,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:32,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:32,401 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1131873083] [2019-10-22 08:59:32,402 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:32,402 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:32,402 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [324520438] [2019-10-22 08:59:32,407 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:59:32,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:32,407 INFO L82 PathProgramCache]: Analyzing trace with hash 1231104429, now seen corresponding path program 1 times [2019-10-22 08:59:32,407 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:32,408 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035907589] [2019-10-22 08:59:32,408 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,408 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,408 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:32,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:32,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:32,428 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2035907589] [2019-10-22 08:59:32,428 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:32,428 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:32,428 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452569913] [2019-10-22 08:59:32,430 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:32,430 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:32,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:32,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:32,450 INFO L87 Difference]: Start difference. First operand 191 states. Second operand 3 states. [2019-10-22 08:59:32,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:32,478 INFO L93 Difference]: Finished difference Result 191 states and 286 transitions. [2019-10-22 08:59:32,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:32,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191 states and 286 transitions. [2019-10-22 08:59:32,485 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2019-10-22 08:59:32,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191 states to 186 states and 281 transitions. [2019-10-22 08:59:32,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2019-10-22 08:59:32,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2019-10-22 08:59:32,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 281 transitions. [2019-10-22 08:59:32,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:32,494 INFO L688 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2019-10-22 08:59:32,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 281 transitions. [2019-10-22 08:59:32,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2019-10-22 08:59:32,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2019-10-22 08:59:32,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 281 transitions. [2019-10-22 08:59:32,530 INFO L711 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2019-10-22 08:59:32,530 INFO L591 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2019-10-22 08:59:32,530 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-10-22 08:59:32,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 281 transitions. [2019-10-22 08:59:32,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2019-10-22 08:59:32,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:32,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:32,534 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:32,534 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:32,534 INFO L791 eck$LassoCheckResult]: Stem: 573#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 413#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 414#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 569#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 570#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 481#L216-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 482#L221-1 assume !(0 == ~M_E~0); 508#L324-1 assume !(0 == ~T1_E~0); 427#L329-1 assume !(0 == ~T2_E~0); 428#L334-1 assume !(0 == ~E_1~0); 503#L339-1 assume !(0 == ~E_2~0); 543#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 563#L146 assume !(1 == ~m_pc~0); 469#L146-2 is_master_triggered_~__retres1~0 := 0; 470#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 471#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 467#L395 assume !(0 != activate_threads_~tmp~1); 415#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 416#L165 assume 1 == ~t1_pc~0; 504#L166 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 505#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 507#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 474#L403 assume !(0 != activate_threads_~tmp___0~0); 475#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 483#L184 assume !(1 == ~t2_pc~0); 556#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 555#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 557#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 521#L411 assume !(0 != activate_threads_~tmp___1~0); 494#L411-2 assume !(1 == ~M_E~0); 495#L357-1 assume !(1 == ~T1_E~0); 417#L362-1 assume !(1 == ~T2_E~0); 418#L367-1 assume !(1 == ~E_1~0); 499#L372-1 assume !(1 == ~E_2~0); 538#L518-1 [2019-10-22 08:59:32,534 INFO L793 eck$LassoCheckResult]: Loop: 538#L518-1 assume !false; 434#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 406#L299 assume !false; 429#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 530#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 490#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 399#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 400#L266 assume !(0 != eval_~tmp~0); 420#L314 start_simulation_~kernel_st~0 := 2; 566#L204-1 start_simulation_~kernel_st~0 := 3; 567#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 576#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 435#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 436#L334-3 assume 0 == ~E_1~0;~E_1~0 := 1; 510#L339-3 assume !(0 == ~E_2~0); 552#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 531#L146-9 assume !(1 == ~m_pc~0); 448#L146-11 is_master_triggered_~__retres1~0 := 0; 447#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 449#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 397#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 398#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 410#L165-9 assume 1 == ~t1_pc~0; 522#L166-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 523#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 525#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 472#L403-9 assume !(0 != activate_threads_~tmp___0~0); 425#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 426#L184-9 assume 1 == ~t2_pc~0; 539#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 540#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 542#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 476#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 477#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 488#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 430#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 431#L367-3 assume !(1 == ~E_1~0); 509#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 548#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 565#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 485#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 395#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 396#L537 assume !(0 == start_simulation_~tmp~3); 559#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 561#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 479#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 391#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 392#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 512#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 513#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 575#L550 assume !(0 != start_simulation_~tmp___0~1); 538#L518-1 [2019-10-22 08:59:32,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:32,535 INFO L82 PathProgramCache]: Analyzing trace with hash 1063617666, now seen corresponding path program 1 times [2019-10-22 08:59:32,538 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:32,539 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [701901975] [2019-10-22 08:59:32,539 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,539 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,539 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:32,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:32,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:32,569 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [701901975] [2019-10-22 08:59:32,569 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:32,569 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:32,570 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1870106235] [2019-10-22 08:59:32,570 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:59:32,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:32,570 INFO L82 PathProgramCache]: Analyzing trace with hash -1036257152, now seen corresponding path program 1 times [2019-10-22 08:59:32,571 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:32,571 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741268878] [2019-10-22 08:59:32,571 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,571 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,571 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:32,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:32,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:32,662 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1741268878] [2019-10-22 08:59:32,662 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:32,662 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:32,662 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306601710] [2019-10-22 08:59:32,663 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:32,663 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:32,663 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:32,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:32,664 INFO L87 Difference]: Start difference. First operand 186 states and 281 transitions. cyclomatic complexity: 96 Second operand 3 states. [2019-10-22 08:59:32,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:32,687 INFO L93 Difference]: Finished difference Result 186 states and 280 transitions. [2019-10-22 08:59:32,690 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:32,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 280 transitions. [2019-10-22 08:59:32,692 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2019-10-22 08:59:32,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 186 states and 280 transitions. [2019-10-22 08:59:32,694 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2019-10-22 08:59:32,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2019-10-22 08:59:32,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 280 transitions. [2019-10-22 08:59:32,696 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:32,696 INFO L688 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2019-10-22 08:59:32,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 280 transitions. [2019-10-22 08:59:32,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2019-10-22 08:59:32,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2019-10-22 08:59:32,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 280 transitions. [2019-10-22 08:59:32,705 INFO L711 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2019-10-22 08:59:32,705 INFO L591 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2019-10-22 08:59:32,705 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-10-22 08:59:32,705 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 280 transitions. [2019-10-22 08:59:32,707 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2019-10-22 08:59:32,707 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:32,707 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:32,708 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:32,708 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:32,709 INFO L791 eck$LassoCheckResult]: Stem: 952#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 792#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 793#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 947#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 948#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 860#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 861#L221-1 assume !(0 == ~M_E~0); 887#L324-1 assume !(0 == ~T1_E~0); 802#L329-1 assume !(0 == ~T2_E~0); 803#L334-1 assume !(0 == ~E_1~0); 882#L339-1 assume !(0 == ~E_2~0); 921#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 942#L146 assume !(1 == ~m_pc~0); 848#L146-2 is_master_triggered_~__retres1~0 := 0; 849#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 850#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 845#L395 assume !(0 != activate_threads_~tmp~1); 794#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 795#L165 assume 1 == ~t1_pc~0; 883#L166 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 884#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 886#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 852#L403 assume !(0 != activate_threads_~tmp___0~0); 853#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 862#L184 assume !(1 == ~t2_pc~0); 935#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 934#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 936#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 898#L411 assume !(0 != activate_threads_~tmp___1~0); 873#L411-2 assume !(1 == ~M_E~0); 874#L357-1 assume !(1 == ~T1_E~0); 796#L362-1 assume !(1 == ~T2_E~0); 797#L367-1 assume !(1 == ~E_1~0); 875#L372-1 assume !(1 == ~E_2~0); 915#L518-1 [2019-10-22 08:59:32,709 INFO L793 eck$LassoCheckResult]: Loop: 915#L518-1 assume !false; 809#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 785#L299 assume !false; 804#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 908#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 869#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 778#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 779#L266 assume !(0 != eval_~tmp~0); 799#L314 start_simulation_~kernel_st~0 := 2; 945#L204-1 start_simulation_~kernel_st~0 := 3; 946#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 955#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 814#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 815#L334-3 assume 0 == ~E_1~0;~E_1~0 := 1; 889#L339-3 assume !(0 == ~E_2~0); 931#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 910#L146-9 assume 1 == ~m_pc~0; 825#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 826#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 828#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 776#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 777#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 789#L165-9 assume 1 == ~t1_pc~0; 901#L166-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 902#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 904#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 851#L403-9 assume !(0 != activate_threads_~tmp___0~0); 807#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 808#L184-9 assume 1 == ~t2_pc~0; 918#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 919#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 922#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 855#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 856#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 867#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 810#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 811#L367-3 assume !(1 == ~E_1~0); 888#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 927#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 944#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 864#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 774#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 775#L537 assume !(0 == start_simulation_~tmp~3); 938#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 940#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 858#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 770#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 771#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 891#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 892#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 954#L550 assume !(0 != start_simulation_~tmp___0~1); 915#L518-1 [2019-10-22 08:59:32,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:32,709 INFO L82 PathProgramCache]: Analyzing trace with hash -322585728, now seen corresponding path program 1 times [2019-10-22 08:59:32,709 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:32,709 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118356644] [2019-10-22 08:59:32,710 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,710 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,710 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:32,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:32,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:32,755 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2118356644] [2019-10-22 08:59:32,755 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:32,755 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:32,755 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1440918164] [2019-10-22 08:59:32,756 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:59:32,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:32,756 INFO L82 PathProgramCache]: Analyzing trace with hash -2087706241, now seen corresponding path program 1 times [2019-10-22 08:59:32,756 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:32,756 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736754900] [2019-10-22 08:59:32,757 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,757 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,757 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:32,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:32,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:32,816 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736754900] [2019-10-22 08:59:32,816 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:32,816 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:32,816 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1009316487] [2019-10-22 08:59:32,817 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:32,817 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:32,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:32,817 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:32,817 INFO L87 Difference]: Start difference. First operand 186 states and 280 transitions. cyclomatic complexity: 95 Second operand 3 states. [2019-10-22 08:59:32,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:32,876 INFO L93 Difference]: Finished difference Result 309 states and 459 transitions. [2019-10-22 08:59:32,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:32,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 309 states and 459 transitions. [2019-10-22 08:59:32,879 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 271 [2019-10-22 08:59:32,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 309 states to 309 states and 459 transitions. [2019-10-22 08:59:32,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 309 [2019-10-22 08:59:32,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 309 [2019-10-22 08:59:32,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309 states and 459 transitions. [2019-10-22 08:59:32,884 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:32,884 INFO L688 BuchiCegarLoop]: Abstraction has 309 states and 459 transitions. [2019-10-22 08:59:32,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309 states and 459 transitions. [2019-10-22 08:59:32,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309 to 307. [2019-10-22 08:59:32,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 307 states. [2019-10-22 08:59:32,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 457 transitions. [2019-10-22 08:59:32,896 INFO L711 BuchiCegarLoop]: Abstraction has 307 states and 457 transitions. [2019-10-22 08:59:32,896 INFO L591 BuchiCegarLoop]: Abstraction has 307 states and 457 transitions. [2019-10-22 08:59:32,896 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-10-22 08:59:32,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307 states and 457 transitions. [2019-10-22 08:59:32,898 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 269 [2019-10-22 08:59:32,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:32,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:32,899 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:32,899 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:32,900 INFO L791 eck$LassoCheckResult]: Stem: 1460#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1294#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1295#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1451#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 1452#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1361#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1362#L221-1 assume !(0 == ~M_E~0); 1385#L324-1 assume !(0 == ~T1_E~0); 1309#L329-1 assume !(0 == ~T2_E~0); 1310#L334-1 assume !(0 == ~E_1~0); 1383#L339-1 assume !(0 == ~E_2~0); 1421#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1445#L146 assume !(1 == ~m_pc~0); 1349#L146-2 is_master_triggered_~__retres1~0 := 0; 1350#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1351#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1347#L395 assume !(0 != activate_threads_~tmp~1); 1298#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1299#L165 assume !(1 == ~t1_pc~0); 1456#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 1457#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1384#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1354#L403 assume !(0 != activate_threads_~tmp___0~0); 1355#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1363#L184 assume !(1 == ~t2_pc~0); 1436#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 1435#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1437#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1399#L411 assume !(0 != activate_threads_~tmp___1~0); 1374#L411-2 assume !(1 == ~M_E~0); 1375#L357-1 assume !(1 == ~T1_E~0); 1300#L362-1 assume !(1 == ~T2_E~0); 1301#L367-1 assume !(1 == ~E_1~0); 1379#L372-1 assume !(1 == ~E_2~0); 1416#L518-1 [2019-10-22 08:59:32,900 INFO L793 eck$LassoCheckResult]: Loop: 1416#L518-1 assume !false; 1315#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1287#L299 assume !false; 1304#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1407#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1370#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1280#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1281#L266 assume !(0 != eval_~tmp~0); 1297#L314 start_simulation_~kernel_st~0 := 2; 1448#L204-1 start_simulation_~kernel_st~0 := 3; 1449#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1465#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1316#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1317#L334-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1387#L339-3 assume !(0 == ~E_2~0); 1431#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1409#L146-9 assume !(1 == ~m_pc~0); 1329#L146-11 is_master_triggered_~__retres1~0 := 0; 1328#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1330#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1278#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1279#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1291#L165-9 assume !(1 == ~t1_pc~0); 1444#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 1578#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1577#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1576#L403-9 assume !(0 != activate_threads_~tmp___0~0); 1575#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1574#L184-9 assume 1 == ~t2_pc~0; 1571#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1569#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1567#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1565#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1563#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 1560#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1558#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1556#L367-3 assume !(1 == ~E_1~0); 1425#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1426#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1447#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1365#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1276#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 1277#L537 assume !(0 == start_simulation_~tmp~3); 1439#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1549#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1433#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1272#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 1273#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1389#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 1390#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 1463#L550 assume !(0 != start_simulation_~tmp___0~1); 1416#L518-1 [2019-10-22 08:59:32,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:32,900 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 1 times [2019-10-22 08:59:32,900 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:32,901 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099533940] [2019-10-22 08:59:32,901 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,901 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,901 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:32,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:32,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:32,950 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:32,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:32,952 INFO L82 PathProgramCache]: Analyzing trace with hash -2007931839, now seen corresponding path program 1 times [2019-10-22 08:59:32,952 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:32,953 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265241833] [2019-10-22 08:59:32,953 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,953 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:32,953 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:32,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:33,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:33,009 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265241833] [2019-10-22 08:59:33,009 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:33,009 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:33,009 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116579795] [2019-10-22 08:59:33,010 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:33,010 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:33,010 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:33,010 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:33,010 INFO L87 Difference]: Start difference. First operand 307 states and 457 transitions. cyclomatic complexity: 152 Second operand 3 states. [2019-10-22 08:59:33,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:33,088 INFO L93 Difference]: Finished difference Result 453 states and 669 transitions. [2019-10-22 08:59:33,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:33,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 453 states and 669 transitions. [2019-10-22 08:59:33,093 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 390 [2019-10-22 08:59:33,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 453 states to 453 states and 669 transitions. [2019-10-22 08:59:33,103 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 453 [2019-10-22 08:59:33,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 453 [2019-10-22 08:59:33,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 453 states and 669 transitions. [2019-10-22 08:59:33,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:33,110 INFO L688 BuchiCegarLoop]: Abstraction has 453 states and 669 transitions. [2019-10-22 08:59:33,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 453 states and 669 transitions. [2019-10-22 08:59:33,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 453 to 451. [2019-10-22 08:59:33,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 451 states. [2019-10-22 08:59:33,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 451 states to 451 states and 667 transitions. [2019-10-22 08:59:33,131 INFO L711 BuchiCegarLoop]: Abstraction has 451 states and 667 transitions. [2019-10-22 08:59:33,132 INFO L591 BuchiCegarLoop]: Abstraction has 451 states and 667 transitions. [2019-10-22 08:59:33,132 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-10-22 08:59:33,132 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 451 states and 667 transitions. [2019-10-22 08:59:33,134 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 388 [2019-10-22 08:59:33,134 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:33,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:33,138 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:33,139 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:33,140 INFO L791 eck$LassoCheckResult]: Stem: 2231#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2060#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2061#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2220#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 2221#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2129#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2130#L221-1 assume !(0 == ~M_E~0); 2153#L324-1 assume !(0 == ~T1_E~0); 2070#L329-1 assume !(0 == ~T2_E~0); 2071#L334-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2150#L339-1 assume !(0 == ~E_2~0); 2189#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2213#L146 assume !(1 == ~m_pc~0); 2117#L146-2 is_master_triggered_~__retres1~0 := 0; 2118#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2119#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2114#L395 assume !(0 != activate_threads_~tmp~1); 2062#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2063#L165 assume !(1 == ~t1_pc~0); 2226#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 2227#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2152#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2121#L403 assume !(0 != activate_threads_~tmp___0~0); 2122#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2131#L184 assume !(1 == ~t2_pc~0); 2203#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 2202#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2204#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2166#L411 assume !(0 != activate_threads_~tmp___1~0); 2142#L411-2 assume !(1 == ~M_E~0); 2143#L357-1 assume !(1 == ~T1_E~0); 2064#L362-1 assume !(1 == ~T2_E~0); 2065#L367-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2144#L372-1 assume !(1 == ~E_2~0); 2183#L518-1 [2019-10-22 08:59:33,140 INFO L793 eck$LassoCheckResult]: Loop: 2183#L518-1 assume !false; 2077#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2053#L299 assume !false; 2072#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2176#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2175#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2046#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2047#L266 assume !(0 != eval_~tmp~0); 2067#L314 start_simulation_~kernel_st~0 := 2; 2218#L204-1 start_simulation_~kernel_st~0 := 3; 2219#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2241#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2082#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2083#L334-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2156#L339-3 assume !(0 == ~E_2~0); 2199#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2178#L146-9 assume !(1 == ~m_pc~0); 2096#L146-11 is_master_triggered_~__retres1~0 := 0; 2095#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2097#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2044#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2045#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2057#L165-9 assume !(1 == ~t1_pc~0); 2206#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 2207#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2172#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2120#L403-9 assume !(0 != activate_threads_~tmp___0~0); 2075#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2076#L184-9 assume 1 == ~t2_pc~0; 2186#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2187#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2190#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2124#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2125#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 2136#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2078#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2079#L367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2154#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2194#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2217#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2133#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2042#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 2043#L537 assume !(0 == start_simulation_~tmp~3); 2208#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2215#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2127#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2038#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 2039#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2159#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 2160#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 2238#L550 assume !(0 != start_simulation_~tmp___0~1); 2183#L518-1 [2019-10-22 08:59:33,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:33,140 INFO L82 PathProgramCache]: Analyzing trace with hash 713469919, now seen corresponding path program 1 times [2019-10-22 08:59:33,140 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:33,140 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [759416323] [2019-10-22 08:59:33,141 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,141 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,141 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:33,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:33,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:33,164 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [759416323] [2019-10-22 08:59:33,164 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:33,164 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:33,165 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088231979] [2019-10-22 08:59:33,165 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:59:33,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:33,165 INFO L82 PathProgramCache]: Analyzing trace with hash -728068161, now seen corresponding path program 1 times [2019-10-22 08:59:33,165 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:33,165 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493883460] [2019-10-22 08:59:33,166 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,166 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,166 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:33,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:33,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:33,283 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493883460] [2019-10-22 08:59:33,283 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:33,283 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-10-22 08:59:33,283 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184993549] [2019-10-22 08:59:33,283 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:33,284 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:33,284 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:33,284 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:33,284 INFO L87 Difference]: Start difference. First operand 451 states and 667 transitions. cyclomatic complexity: 218 Second operand 3 states. [2019-10-22 08:59:33,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:33,320 INFO L93 Difference]: Finished difference Result 307 states and 445 transitions. [2019-10-22 08:59:33,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:33,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 307 states and 445 transitions. [2019-10-22 08:59:33,323 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 269 [2019-10-22 08:59:33,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 307 states to 307 states and 445 transitions. [2019-10-22 08:59:33,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 307 [2019-10-22 08:59:33,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 307 [2019-10-22 08:59:33,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 307 states and 445 transitions. [2019-10-22 08:59:33,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:33,326 INFO L688 BuchiCegarLoop]: Abstraction has 307 states and 445 transitions. [2019-10-22 08:59:33,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307 states and 445 transitions. [2019-10-22 08:59:33,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307 to 307. [2019-10-22 08:59:33,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 307 states. [2019-10-22 08:59:33,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 445 transitions. [2019-10-22 08:59:33,338 INFO L711 BuchiCegarLoop]: Abstraction has 307 states and 445 transitions. [2019-10-22 08:59:33,338 INFO L591 BuchiCegarLoop]: Abstraction has 307 states and 445 transitions. [2019-10-22 08:59:33,338 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-10-22 08:59:33,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307 states and 445 transitions. [2019-10-22 08:59:33,341 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 269 [2019-10-22 08:59:33,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:33,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:33,342 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:33,342 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:33,342 INFO L791 eck$LassoCheckResult]: Stem: 3002#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2833#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2834#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2990#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 2991#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2902#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2903#L221-1 assume !(0 == ~M_E~0); 2926#L324-1 assume !(0 == ~T1_E~0); 2849#L329-1 assume !(0 == ~T2_E~0); 2850#L334-1 assume !(0 == ~E_1~0); 2924#L339-1 assume !(0 == ~E_2~0); 2960#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2983#L146 assume !(1 == ~m_pc~0); 2890#L146-2 is_master_triggered_~__retres1~0 := 0; 2891#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2892#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2888#L395 assume !(0 != activate_threads_~tmp~1); 2837#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2838#L165 assume !(1 == ~t1_pc~0); 2997#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 2998#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2925#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2895#L403 assume !(0 != activate_threads_~tmp___0~0); 2896#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2904#L184 assume !(1 == ~t2_pc~0); 2973#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 2972#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2974#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2938#L411 assume !(0 != activate_threads_~tmp___1~0); 2916#L411-2 assume !(1 == ~M_E~0); 2917#L357-1 assume !(1 == ~T1_E~0); 2839#L362-1 assume !(1 == ~T2_E~0); 2840#L367-1 assume !(1 == ~E_1~0); 2920#L372-1 assume !(1 == ~E_2~0); 2955#L518-1 [2019-10-22 08:59:33,343 INFO L793 eck$LassoCheckResult]: Loop: 2955#L518-1 assume !false; 2855#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2826#L299 assume !false; 2844#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2946#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2945#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2819#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2820#L266 assume !(0 != eval_~tmp~0); 2836#L314 start_simulation_~kernel_st~0 := 2; 2987#L204-1 start_simulation_~kernel_st~0 := 3; 2988#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3006#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2856#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2857#L334-3 assume !(0 == ~E_1~0); 2928#L339-3 assume !(0 == ~E_2~0); 2969#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2948#L146-9 assume 1 == ~m_pc~0; 2868#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2869#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2871#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2817#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2818#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2830#L165-9 assume !(1 == ~t1_pc~0); 2982#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 3057#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3056#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3055#L403-9 assume !(0 != activate_threads_~tmp___0~0); 3054#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2996#L184-9 assume 1 == ~t2_pc~0; 2956#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2957#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2959#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2897#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2898#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 3048#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3047#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3046#L367-3 assume !(1 == ~E_1~0); 3045#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3044#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3043#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3040#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3039#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 2977#L537 assume !(0 == start_simulation_~tmp~3); 2978#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2980#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2900#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2811#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 2812#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2930#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 2931#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 3005#L550 assume !(0 != start_simulation_~tmp___0~1); 2955#L518-1 [2019-10-22 08:59:33,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:33,343 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 2 times [2019-10-22 08:59:33,343 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:33,343 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466719399] [2019-10-22 08:59:33,344 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,344 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,344 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:33,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:33,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:33,381 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:33,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:33,388 INFO L82 PathProgramCache]: Analyzing trace with hash 206227070, now seen corresponding path program 1 times [2019-10-22 08:59:33,388 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:33,388 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545380607] [2019-10-22 08:59:33,388 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,388 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,389 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:33,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:33,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:33,475 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545380607] [2019-10-22 08:59:33,476 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:33,476 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-10-22 08:59:33,476 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677658580] [2019-10-22 08:59:33,476 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:33,476 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:33,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-10-22 08:59:33,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-10-22 08:59:33,477 INFO L87 Difference]: Start difference. First operand 307 states and 445 transitions. cyclomatic complexity: 140 Second operand 11 states. [2019-10-22 08:59:33,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:33,632 INFO L93 Difference]: Finished difference Result 511 states and 726 transitions. [2019-10-22 08:59:33,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-10-22 08:59:33,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 511 states and 726 transitions. [2019-10-22 08:59:33,636 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 471 [2019-10-22 08:59:33,638 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 511 states to 511 states and 726 transitions. [2019-10-22 08:59:33,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 511 [2019-10-22 08:59:33,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 511 [2019-10-22 08:59:33,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 511 states and 726 transitions. [2019-10-22 08:59:33,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:33,640 INFO L688 BuchiCegarLoop]: Abstraction has 511 states and 726 transitions. [2019-10-22 08:59:33,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 511 states and 726 transitions. [2019-10-22 08:59:33,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 511 to 313. [2019-10-22 08:59:33,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 313 states. [2019-10-22 08:59:33,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 313 states to 313 states and 451 transitions. [2019-10-22 08:59:33,648 INFO L711 BuchiCegarLoop]: Abstraction has 313 states and 451 transitions. [2019-10-22 08:59:33,648 INFO L591 BuchiCegarLoop]: Abstraction has 313 states and 451 transitions. [2019-10-22 08:59:33,648 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-10-22 08:59:33,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 313 states and 451 transitions. [2019-10-22 08:59:33,650 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 275 [2019-10-22 08:59:33,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:33,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:33,651 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:33,651 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:33,652 INFO L791 eck$LassoCheckResult]: Stem: 3850#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3674#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3675#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3832#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 3833#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3742#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3743#L221-1 assume !(0 == ~M_E~0); 3766#L324-1 assume !(0 == ~T1_E~0); 3684#L329-1 assume !(0 == ~T2_E~0); 3685#L334-1 assume !(0 == ~E_1~0); 3764#L339-1 assume !(0 == ~E_2~0); 3799#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3825#L146 assume !(1 == ~m_pc~0); 3729#L146-2 is_master_triggered_~__retres1~0 := 0; 3730#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3731#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3726#L395 assume !(0 != activate_threads_~tmp~1); 3676#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3677#L165 assume !(1 == ~t1_pc~0); 3843#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 3844#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3765#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3734#L403 assume !(0 != activate_threads_~tmp___0~0); 3735#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3744#L184 assume !(1 == ~t2_pc~0); 3815#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 3814#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3816#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3777#L411 assume !(0 != activate_threads_~tmp___1~0); 3756#L411-2 assume !(1 == ~M_E~0); 3757#L357-1 assume !(1 == ~T1_E~0); 3678#L362-1 assume !(1 == ~T2_E~0); 3679#L367-1 assume !(1 == ~E_1~0); 3758#L372-1 assume !(1 == ~E_2~0); 3793#L518-1 [2019-10-22 08:59:33,652 INFO L793 eck$LassoCheckResult]: Loop: 3793#L518-1 assume !false; 3691#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 3666#L299 assume !false; 3686#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3786#L234 assume !(0 == ~m_st~0); 3849#L238 assume !(0 == ~t1_st~0); 3887#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 3886#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3884#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3873#L266 assume !(0 != eval_~tmp~0); 3874#L314 start_simulation_~kernel_st~0 := 2; 3881#L204-1 start_simulation_~kernel_st~0 := 3; 3880#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3879#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3878#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3877#L334-3 assume !(0 == ~E_1~0); 3876#L339-3 assume !(0 == ~E_2~0); 3875#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3872#L146-9 assume !(1 == ~m_pc~0); 3870#L146-11 is_master_triggered_~__retres1~0 := 0; 3869#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3868#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3867#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3670#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3671#L165-9 assume !(1 == ~t1_pc~0); 3824#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 3853#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3854#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3732#L403-9 assume !(0 != activate_threads_~tmp___0~0); 3733#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3840#L184-9 assume 1 == ~t2_pc~0; 3841#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3857#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3858#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3737#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3738#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 3863#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3864#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3767#L367-3 assume !(1 == ~E_1~0); 3768#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3846#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3829#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3746#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3655#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 3656#L537 assume !(0 == start_simulation_~tmp~3); 3819#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3827#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3740#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3651#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 3652#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3771#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 3772#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 3860#L550 assume !(0 != start_simulation_~tmp___0~1); 3793#L518-1 [2019-10-22 08:59:33,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:33,652 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 3 times [2019-10-22 08:59:33,653 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:33,653 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280044657] [2019-10-22 08:59:33,653 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,653 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,653 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:33,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:33,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:33,667 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:33,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:33,667 INFO L82 PathProgramCache]: Analyzing trace with hash 805723206, now seen corresponding path program 1 times [2019-10-22 08:59:33,668 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:33,668 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533049300] [2019-10-22 08:59:33,668 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,668 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,668 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:33,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:33,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:33,717 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533049300] [2019-10-22 08:59:33,718 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:33,718 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-10-22 08:59:33,718 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [426702880] [2019-10-22 08:59:33,718 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:33,719 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:33,719 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-10-22 08:59:33,719 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2019-10-22 08:59:33,719 INFO L87 Difference]: Start difference. First operand 313 states and 451 transitions. cyclomatic complexity: 140 Second operand 8 states. [2019-10-22 08:59:33,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:33,846 INFO L93 Difference]: Finished difference Result 912 states and 1302 transitions. [2019-10-22 08:59:33,846 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-10-22 08:59:33,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 912 states and 1302 transitions. [2019-10-22 08:59:33,851 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 868 [2019-10-22 08:59:33,855 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 912 states to 912 states and 1302 transitions. [2019-10-22 08:59:33,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 912 [2019-10-22 08:59:33,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 912 [2019-10-22 08:59:33,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 912 states and 1302 transitions. [2019-10-22 08:59:33,858 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:33,858 INFO L688 BuchiCegarLoop]: Abstraction has 912 states and 1302 transitions. [2019-10-22 08:59:33,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 912 states and 1302 transitions. [2019-10-22 08:59:33,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 912 to 319. [2019-10-22 08:59:33,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 319 states. [2019-10-22 08:59:33,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319 states to 319 states and 457 transitions. [2019-10-22 08:59:33,866 INFO L711 BuchiCegarLoop]: Abstraction has 319 states and 457 transitions. [2019-10-22 08:59:33,866 INFO L591 BuchiCegarLoop]: Abstraction has 319 states and 457 transitions. [2019-10-22 08:59:33,866 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-10-22 08:59:33,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 319 states and 457 transitions. [2019-10-22 08:59:33,868 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 281 [2019-10-22 08:59:33,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:33,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:33,869 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:33,870 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:33,870 INFO L791 eck$LassoCheckResult]: Stem: 5099#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4918#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4919#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5081#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 5082#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4986#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4987#L221-1 assume !(0 == ~M_E~0); 5011#L324-1 assume !(0 == ~T1_E~0); 4932#L329-1 assume !(0 == ~T2_E~0); 4933#L334-1 assume !(0 == ~E_1~0); 5009#L339-1 assume !(0 == ~E_2~0); 5047#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5073#L146 assume !(1 == ~m_pc~0); 4973#L146-2 is_master_triggered_~__retres1~0 := 0; 4974#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4975#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4971#L395 assume !(0 != activate_threads_~tmp~1); 4921#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4922#L165 assume !(1 == ~t1_pc~0); 5090#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 5091#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5010#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4979#L403 assume !(0 != activate_threads_~tmp___0~0); 4980#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4988#L184 assume !(1 == ~t2_pc~0); 5062#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 5061#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5063#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5025#L411 assume !(0 != activate_threads_~tmp___1~0); 5001#L411-2 assume !(1 == ~M_E~0); 5002#L357-1 assume !(1 == ~T1_E~0); 4923#L362-1 assume !(1 == ~T2_E~0); 4924#L367-1 assume !(1 == ~E_1~0); 5005#L372-1 assume !(1 == ~E_2~0); 5042#L518-1 [2019-10-22 08:59:33,870 INFO L793 eck$LassoCheckResult]: Loop: 5042#L518-1 assume !false; 4936#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4911#L299 assume !false; 4931#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5033#L234 assume !(0 == ~m_st~0); 5132#L238 assume !(0 == ~t1_st~0); 5092#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 5093#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5143#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5142#L266 assume !(0 != eval_~tmp~0); 5084#L314 start_simulation_~kernel_st~0 := 2; 5078#L204-1 start_simulation_~kernel_st~0 := 3; 5079#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5108#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4940#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4941#L334-3 assume !(0 == ~E_1~0); 5122#L339-3 assume !(0 == ~E_2~0); 5121#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5120#L146-9 assume !(1 == ~m_pc~0); 5118#L146-11 is_master_triggered_~__retres1~0 := 0; 5117#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4954#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4902#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4903#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4915#L165-9 assume !(1 == ~t1_pc~0); 5066#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 5067#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5028#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5029#L403-9 assume !(0 != activate_threads_~tmp___0~0); 4929#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4930#L184-9 assume 1 == ~t2_pc~0; 5043#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5044#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5046#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4981#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4982#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 5109#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5110#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5012#L367-3 assume !(1 == ~E_1~0); 5013#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5051#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5174#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5171#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5170#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 5068#L537 assume !(0 == start_simulation_~tmp~3); 5069#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5071#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5138#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5139#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 5157#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5017#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 5018#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 5106#L550 assume !(0 != start_simulation_~tmp___0~1); 5042#L518-1 [2019-10-22 08:59:33,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:33,870 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 4 times [2019-10-22 08:59:33,871 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:33,871 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709623176] [2019-10-22 08:59:33,871 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,871 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,871 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:33,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:33,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:33,884 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:33,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:33,884 INFO L82 PathProgramCache]: Analyzing trace with hash 805663624, now seen corresponding path program 1 times [2019-10-22 08:59:33,885 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:33,885 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378090918] [2019-10-22 08:59:33,885 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,885 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:33,885 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:33,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:33,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:33,932 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1378090918] [2019-10-22 08:59:33,932 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:33,933 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:59:33,933 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1649578742] [2019-10-22 08:59:33,933 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:33,933 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:33,933 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:59:33,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:59:33,934 INFO L87 Difference]: Start difference. First operand 319 states and 457 transitions. cyclomatic complexity: 140 Second operand 5 states. [2019-10-22 08:59:34,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:34,049 INFO L93 Difference]: Finished difference Result 861 states and 1217 transitions. [2019-10-22 08:59:34,050 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 08:59:34,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 861 states and 1217 transitions. [2019-10-22 08:59:34,056 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 780 [2019-10-22 08:59:34,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 861 states to 861 states and 1217 transitions. [2019-10-22 08:59:34,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 861 [2019-10-22 08:59:34,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 861 [2019-10-22 08:59:34,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 861 states and 1217 transitions. [2019-10-22 08:59:34,063 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:34,063 INFO L688 BuchiCegarLoop]: Abstraction has 861 states and 1217 transitions. [2019-10-22 08:59:34,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 861 states and 1217 transitions. [2019-10-22 08:59:34,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 861 to 343. [2019-10-22 08:59:34,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 343 states. [2019-10-22 08:59:34,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 343 states to 343 states and 481 transitions. [2019-10-22 08:59:34,073 INFO L711 BuchiCegarLoop]: Abstraction has 343 states and 481 transitions. [2019-10-22 08:59:34,073 INFO L591 BuchiCegarLoop]: Abstraction has 343 states and 481 transitions. [2019-10-22 08:59:34,073 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-10-22 08:59:34,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 343 states and 481 transitions. [2019-10-22 08:59:34,075 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 302 [2019-10-22 08:59:34,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:34,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:34,076 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:34,076 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:34,076 INFO L791 eck$LassoCheckResult]: Stem: 6297#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6111#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6112#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6283#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 6284#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6181#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6182#L221-1 assume !(0 == ~M_E~0); 6204#L324-1 assume !(0 == ~T1_E~0); 6120#L329-1 assume !(0 == ~T2_E~0); 6121#L334-1 assume !(0 == ~E_1~0); 6202#L339-1 assume !(0 == ~E_2~0); 6243#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6275#L146 assume !(1 == ~m_pc~0); 6168#L146-2 is_master_triggered_~__retres1~0 := 0; 6268#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6276#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6165#L395 assume !(0 != activate_threads_~tmp~1); 6113#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6114#L165 assume !(1 == ~t1_pc~0); 6291#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 6292#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6203#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6173#L403 assume !(0 != activate_threads_~tmp___0~0); 6174#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6183#L184 assume !(1 == ~t2_pc~0); 6257#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 6256#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6258#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6215#L411 assume !(0 != activate_threads_~tmp___1~0); 6194#L411-2 assume !(1 == ~M_E~0); 6195#L357-1 assume !(1 == ~T1_E~0); 6115#L362-1 assume !(1 == ~T2_E~0); 6116#L367-1 assume !(1 == ~E_1~0); 6196#L372-1 assume !(1 == ~E_2~0); 6235#L518-1 [2019-10-22 08:59:34,076 INFO L793 eck$LassoCheckResult]: Loop: 6235#L518-1 assume !false; 6127#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6104#L299 assume !false; 6122#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6223#L234 assume !(0 == ~m_st~0); 6189#L238 assume !(0 == ~t1_st~0); 6191#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 6294#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6418#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6417#L266 assume !(0 != eval_~tmp~0); 6288#L314 start_simulation_~kernel_st~0 := 2; 6281#L204-1 start_simulation_~kernel_st~0 := 3; 6282#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6306#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6307#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6206#L334-3 assume !(0 == ~E_1~0); 6207#L339-3 assume !(0 == ~E_2~0); 6253#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6295#L146-9 assume 1 == ~m_pc~0; 6144#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6145#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6263#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6348#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6096#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6108#L165-9 assume !(1 == ~t1_pc~0); 6264#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 6265#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6220#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6172#L403-9 assume !(0 != activate_threads_~tmp___0~0); 6125#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6126#L184-9 assume 1 == ~t2_pc~0; 6240#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6241#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6244#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6176#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6177#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 6188#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6128#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6129#L367-3 assume !(1 == ~E_1~0); 6205#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6248#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6280#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6185#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6093#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 6094#L537 assume !(0 == start_simulation_~tmp~3); 6266#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6271#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6179#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6089#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 6090#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6209#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 6210#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 6304#L550 assume !(0 != start_simulation_~tmp___0~1); 6235#L518-1 [2019-10-22 08:59:34,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:34,077 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 5 times [2019-10-22 08:59:34,077 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:34,077 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070350585] [2019-10-22 08:59:34,077 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:34,077 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:34,092 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:34,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:34,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:34,108 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:34,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:34,109 INFO L82 PathProgramCache]: Analyzing trace with hash -245785465, now seen corresponding path program 1 times [2019-10-22 08:59:34,109 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:34,109 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190461180] [2019-10-22 08:59:34,109 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:34,109 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:34,109 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:34,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:34,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:34,136 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:34,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:34,137 INFO L82 PathProgramCache]: Analyzing trace with hash 1118136617, now seen corresponding path program 1 times [2019-10-22 08:59:34,137 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:34,137 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177102341] [2019-10-22 08:59:34,137 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:34,137 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:34,138 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:34,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:34,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:34,170 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1177102341] [2019-10-22 08:59:34,170 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:34,170 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:34,170 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760005748] [2019-10-22 08:59:34,467 WARN L191 SmtUtils]: Spent 292.00 ms on a formula simplification. DAG size of input: 113 DAG size of output: 100 [2019-10-22 08:59:34,587 INFO L210 LassoAnalysis]: Preferences: [2019-10-22 08:59:34,587 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2019-10-22 08:59:34,588 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-10-22 08:59:34,588 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2019-10-22 08:59:34,588 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2019-10-22 08:59:34,588 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:34,588 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2019-10-22 08:59:34,588 INFO L130 ssoRankerPreferences]: Path of dumped script: [2019-10-22 08:59:34,588 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration9_Loop [2019-10-22 08:59:34,588 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2019-10-22 08:59:34,588 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-10-22 08:59:34,611 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,634 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,637 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,643 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,646 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,647 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,650 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,652 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,657 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,662 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,665 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,669 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,671 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,679 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,685 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,687 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,689 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,691 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,694 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,696 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,698 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,700 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,705 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,708 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,711 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,718 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,721 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,726 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,728 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,733 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,735 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,741 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:34,745 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,101 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-10-22 08:59:35,103 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:35,116 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-10-22 08:59:35,116 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-10-22 08:59:35,128 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-10-22 08:59:35,139 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_~__retres1~3=1, ULTIMATE.start_stop_simulation_~tmp~2=1, ULTIMATE.start_exists_runnable_thread_#res=1} Honda state: {ULTIMATE.start_exists_runnable_thread_~__retres1~3=1, ULTIMATE.start_stop_simulation_~tmp~2=1, ULTIMATE.start_exists_runnable_thread_#res=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:35,159 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-10-22 08:59:35,160 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-10-22 08:59:35,176 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-10-22 08:59:35,176 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:35,200 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-10-22 08:59:35,200 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-10-22 08:59:35,228 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-10-22 08:59:35,228 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0=1, ULTIMATE.start_is_transmit2_triggered_#res=1, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=1} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0=1, ULTIMATE.start_is_transmit2_triggered_#res=1, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-10-22 08:59:35,238 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-10-22 08:59:35,238 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:35,242 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-10-22 08:59:35,243 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-10-22 08:59:35,250 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-10-22 08:59:35,250 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:35,254 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-10-22 08:59:35,255 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret5=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret5=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-10-22 08:59:35,265 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-10-22 08:59:35,265 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:35,270 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-10-22 08:59:35,270 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=-8} Honda state: {~t1_pc~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:35,321 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-10-22 08:59:35,322 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-10-22 08:59:35,326 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-10-22 08:59:35,327 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret9=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret9=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-10-22 08:59:35,341 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-10-22 08:59:35,341 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:35,346 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-10-22 08:59:35,346 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_1~0=3} Honda state: {~E_1~0=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-10-22 08:59:35,357 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-10-22 08:59:35,357 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-10-22 08:59:35,371 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-10-22 08:59:35,371 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:35,396 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-10-22 08:59:35,399 INFO L210 LassoAnalysis]: Preferences: [2019-10-22 08:59:35,399 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2019-10-22 08:59:35,400 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-10-22 08:59:35,400 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2019-10-22 08:59:35,400 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2019-10-22 08:59:35,400 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:59:35,400 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2019-10-22 08:59:35,400 INFO L130 ssoRankerPreferences]: Path of dumped script: [2019-10-22 08:59:35,400 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration9_Loop [2019-10-22 08:59:35,401 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2019-10-22 08:59:35,401 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-10-22 08:59:35,404 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,416 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,418 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,420 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,425 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,428 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,432 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,434 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,439 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,441 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,448 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,458 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,460 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,462 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,469 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,472 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,473 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,476 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,482 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,485 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,488 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,493 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,497 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,499 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,502 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,504 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,513 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,518 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,520 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,526 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,528 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,538 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,543 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-10-22 08:59:35,911 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-10-22 08:59:35,924 INFO L489 LassoAnalysis]: Using template 'affine'. [2019-10-22 08:59:35,925 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-10-22 08:59:35,927 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-10-22 08:59:35,928 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-10-22 08:59:35,929 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-10-22 08:59:35,929 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-10-22 08:59:35,929 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-10-22 08:59:35,932 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-10-22 08:59:35,932 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-10-22 08:59:35,935 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-10-22 08:59:35,937 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-10-22 08:59:35,938 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-10-22 08:59:35,938 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-10-22 08:59:35,938 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-10-22 08:59:35,939 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-10-22 08:59:35,939 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-10-22 08:59:35,939 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-10-22 08:59:35,940 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-10-22 08:59:35,943 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-10-22 08:59:35,944 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-10-22 08:59:35,944 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-10-22 08:59:35,944 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-10-22 08:59:35,945 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-10-22 08:59:35,945 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-10-22 08:59:35,945 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-10-22 08:59:35,945 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-10-22 08:59:35,946 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-10-22 08:59:35,946 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-10-22 08:59:35,947 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-10-22 08:59:35,948 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-10-22 08:59:35,948 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-10-22 08:59:35,948 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-10-22 08:59:35,948 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-10-22 08:59:35,949 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-10-22 08:59:35,949 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-10-22 08:59:35,949 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-10-22 08:59:35,953 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-10-22 08:59:35,954 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-10-22 08:59:35,954 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-10-22 08:59:35,955 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-10-22 08:59:35,955 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-10-22 08:59:35,955 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-10-22 08:59:35,955 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-10-22 08:59:35,956 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-10-22 08:59:35,956 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-10-22 08:59:35,957 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-10-22 08:59:35,957 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-10-22 08:59:35,957 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-10-22 08:59:35,958 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-10-22 08:59:35,958 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-10-22 08:59:35,958 INFO L203 nArgumentSynthesizer]: 2 loop disjuncts [2019-10-22 08:59:35,958 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-10-22 08:59:35,960 INFO L400 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-10-22 08:59:35,960 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-10-22 08:59:35,961 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-10-22 08:59:35,962 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-10-22 08:59:35,963 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-10-22 08:59:35,964 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-10-22 08:59:35,964 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-10-22 08:59:35,964 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-10-22 08:59:35,965 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-10-22 08:59:35,965 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-10-22 08:59:35,966 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-10-22 08:59:35,966 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-10-22 08:59:35,967 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-10-22 08:59:35,968 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-10-22 08:59:35,968 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-10-22 08:59:35,968 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-10-22 08:59:35,969 INFO L203 nArgumentSynthesizer]: 2 loop disjuncts [2019-10-22 08:59:35,969 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-10-22 08:59:35,970 INFO L400 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-10-22 08:59:35,977 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-10-22 08:59:35,978 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-10-22 08:59:35,978 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-10-22 08:59:35,979 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-10-22 08:59:35,979 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-10-22 08:59:35,979 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-10-22 08:59:35,979 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-10-22 08:59:35,979 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-10-22 08:59:35,980 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-10-22 08:59:35,980 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-10-22 08:59:35,980 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-10-22 08:59:35,981 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-10-22 08:59:35,981 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-10-22 08:59:35,981 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-10-22 08:59:35,982 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-10-22 08:59:35,982 INFO L203 nArgumentSynthesizer]: 2 loop disjuncts [2019-10-22 08:59:35,982 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-10-22 08:59:35,982 INFO L400 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-10-22 08:59:35,983 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-10-22 08:59:35,987 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-10-22 08:59:35,990 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-10-22 08:59:35,991 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-10-22 08:59:35,991 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-10-22 08:59:35,991 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-10-22 08:59:35,991 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-10-22 08:59:35,992 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-10-22 08:59:35,992 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-10-22 08:59:35,992 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-10-22 08:59:35,994 INFO L419 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-10-22 08:59:35,997 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-10-22 08:59:35,998 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2019-10-22 08:59:36,000 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-10-22 08:59:36,000 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-10-22 08:59:36,000 INFO L510 LassoAnalysis]: Proved termination. [2019-10-22 08:59:36,001 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2019-10-22 08:59:36,003 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-10-22 08:59:36,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:36,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:36,051 INFO L256 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-22 08:59:36,053 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 08:59:36,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:36,090 INFO L256 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 4 conjunts are in the unsatisfiable core [2019-10-22 08:59:36,092 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-22 08:59:36,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:36,131 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2019-10-22 08:59:36,132 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 343 states and 481 transitions. cyclomatic complexity: 140 Second operand 5 states. [2019-10-22 08:59:36,245 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 343 states and 481 transitions. cyclomatic complexity: 140. Second operand 5 states. Result 1151 states and 1620 transitions. Complement of second has 5 states. [2019-10-22 08:59:36,245 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-10-22 08:59:36,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2019-10-22 08:59:36,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 450 transitions. [2019-10-22 08:59:36,248 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 450 transitions. Stem has 34 letters. Loop has 53 letters. [2019-10-22 08:59:36,250 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-10-22 08:59:36,251 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 450 transitions. Stem has 87 letters. Loop has 53 letters. [2019-10-22 08:59:36,252 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-10-22 08:59:36,252 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 450 transitions. Stem has 34 letters. Loop has 106 letters. [2019-10-22 08:59:36,257 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-10-22 08:59:36,257 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1151 states and 1620 transitions. [2019-10-22 08:59:36,285 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 849 [2019-10-22 08:59:36,293 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1151 states to 1151 states and 1620 transitions. [2019-10-22 08:59:36,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 895 [2019-10-22 08:59:36,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 900 [2019-10-22 08:59:36,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1151 states and 1620 transitions. [2019-10-22 08:59:36,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-10-22 08:59:36,294 INFO L688 BuchiCegarLoop]: Abstraction has 1151 states and 1620 transitions. [2019-10-22 08:59:36,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1151 states and 1620 transitions. [2019-10-22 08:59:36,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1151 to 842. [2019-10-22 08:59:36,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 842 states. [2019-10-22 08:59:36,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 842 states to 842 states and 1185 transitions. [2019-10-22 08:59:36,318 INFO L711 BuchiCegarLoop]: Abstraction has 842 states and 1185 transitions. [2019-10-22 08:59:36,319 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:36,319 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:36,319 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:36,319 INFO L87 Difference]: Start difference. First operand 842 states and 1185 transitions. Second operand 3 states. [2019-10-22 08:59:36,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:36,356 INFO L93 Difference]: Finished difference Result 1384 states and 1899 transitions. [2019-10-22 08:59:36,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:36,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1384 states and 1899 transitions. [2019-10-22 08:59:36,364 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 922 [2019-10-22 08:59:36,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1384 states to 1384 states and 1899 transitions. [2019-10-22 08:59:36,370 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 970 [2019-10-22 08:59:36,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 970 [2019-10-22 08:59:36,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1384 states and 1899 transitions. [2019-10-22 08:59:36,372 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-10-22 08:59:36,372 INFO L688 BuchiCegarLoop]: Abstraction has 1384 states and 1899 transitions. [2019-10-22 08:59:36,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1384 states and 1899 transitions. [2019-10-22 08:59:36,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1384 to 1285. [2019-10-22 08:59:36,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1285 states. [2019-10-22 08:59:36,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1285 states to 1285 states and 1773 transitions. [2019-10-22 08:59:36,393 INFO L711 BuchiCegarLoop]: Abstraction has 1285 states and 1773 transitions. [2019-10-22 08:59:36,393 INFO L591 BuchiCegarLoop]: Abstraction has 1285 states and 1773 transitions. [2019-10-22 08:59:36,393 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-10-22 08:59:36,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1285 states and 1773 transitions. [2019-10-22 08:59:36,397 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 856 [2019-10-22 08:59:36,398 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:36,398 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:36,398 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:36,399 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:36,399 INFO L791 eck$LassoCheckResult]: Stem: 10449#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 10137#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10138#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10422#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 10423#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10250#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10251#L221-1 assume !(0 == ~M_E~0); 10290#L324-1 assume !(0 == ~T1_E~0); 10149#L329-1 assume !(0 == ~T2_E~0); 10150#L334-1 assume !(0 == ~E_1~0); 10288#L339-1 assume !(0 == ~E_2~0); 10356#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10410#L146 assume !(1 == ~m_pc~0); 10230#L146-2 is_master_triggered_~__retres1~0 := 0; 10400#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10232#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 10226#L395 assume !(0 != activate_threads_~tmp~1); 10139#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10140#L165 assume !(1 == ~t1_pc~0); 10435#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 10436#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10289#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10236#L403 assume !(0 != activate_threads_~tmp___0~0); 10237#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10252#L184 assume !(1 == ~t2_pc~0); 10384#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 10383#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10387#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10309#L411 assume !(0 != activate_threads_~tmp___1~0); 10275#L411-2 assume !(1 == ~M_E~0); 10276#L357-1 assume !(1 == ~T1_E~0); 10141#L362-1 assume !(1 == ~T2_E~0); 10142#L367-1 assume !(1 == ~E_1~0); 10277#L372-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10344#L518-1 [2019-10-22 08:59:36,399 INFO L793 eck$LassoCheckResult]: Loop: 10344#L518-1 assume !false; 11007#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 11006#L299 assume !false; 11005#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11004#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10777#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11003#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 11002#L266 assume 0 != eval_~tmp~0; 11001#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 10818#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 10999#L37 assume !(0 == ~m_pc~0); 10996#L40 assume 1 == ~m_pc~0; 10924#L41 assume !false; 10819#L57 ~m_pc~0 := 1;~m_st~0 := 2; 10801#L271 assume !(0 == ~t1_st~0); 10787#L285 assume !(0 == ~t2_st~0); 10782#L299 assume !false; 10780#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10776#L234 assume !(0 == ~m_st~0); 10774#L238 assume !(0 == ~t1_st~0); 10770#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 10768#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10766#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 10762#L266 assume !(0 != eval_~tmp~0); 10760#L314 start_simulation_~kernel_st~0 := 2; 10758#L204-1 start_simulation_~kernel_st~0 := 3; 10755#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10750#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10751#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10293#L334-3 assume !(0 == ~E_1~0); 10294#L339-3 assume !(0 == ~E_2~0); 10378#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10444#L146-9 assume 1 == ~m_pc~0; 10992#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 10991#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10990#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 10989#L395-9 assume !(0 != activate_threads_~tmp~1); 10106#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10911#L165-9 assume !(1 == ~t1_pc~0); 10908#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 10906#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10904#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10902#L403-9 assume !(0 != activate_threads_~tmp___0~0); 10900#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10898#L184-9 assume 1 == ~t2_pc~0; 10894#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10891#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10887#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10884#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10881#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 10878#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10875#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10871#L367-3 assume !(1 == ~E_1~0); 10868#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10865#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10861#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10862#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10921#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 10914#L537 assume !(0 == start_simulation_~tmp~3); 10915#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11021#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10840#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11020#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 11019#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11018#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 11017#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 11015#L550 assume !(0 != start_simulation_~tmp___0~1); 10344#L518-1 [2019-10-22 08:59:36,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:36,399 INFO L82 PathProgramCache]: Analyzing trace with hash 854018589, now seen corresponding path program 1 times [2019-10-22 08:59:36,400 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:36,400 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751899675] [2019-10-22 08:59:36,400 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,400 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,400 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:36,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:36,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:36,432 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [751899675] [2019-10-22 08:59:36,433 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:36,433 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-10-22 08:59:36,433 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [301240235] [2019-10-22 08:59:36,433 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:59:36,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:36,433 INFO L82 PathProgramCache]: Analyzing trace with hash 1097849957, now seen corresponding path program 1 times [2019-10-22 08:59:36,434 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:36,434 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [155852715] [2019-10-22 08:59:36,434 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,434 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,434 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:36,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:36,479 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-22 08:59:36,479 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [155852715] [2019-10-22 08:59:36,480 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:36,480 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-22 08:59:36,480 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [225108810] [2019-10-22 08:59:36,480 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:36,480 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:36,480 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:36,481 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:36,481 INFO L87 Difference]: Start difference. First operand 1285 states and 1773 transitions. cyclomatic complexity: 494 Second operand 3 states. [2019-10-22 08:59:36,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:36,506 INFO L93 Difference]: Finished difference Result 1285 states and 1726 transitions. [2019-10-22 08:59:36,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:36,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1285 states and 1726 transitions. [2019-10-22 08:59:36,512 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 856 [2019-10-22 08:59:36,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1285 states to 1285 states and 1726 transitions. [2019-10-22 08:59:36,518 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 904 [2019-10-22 08:59:36,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 904 [2019-10-22 08:59:36,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1285 states and 1726 transitions. [2019-10-22 08:59:36,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-10-22 08:59:36,520 INFO L688 BuchiCegarLoop]: Abstraction has 1285 states and 1726 transitions. [2019-10-22 08:59:36,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1285 states and 1726 transitions. [2019-10-22 08:59:36,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1285 to 1285. [2019-10-22 08:59:36,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1285 states. [2019-10-22 08:59:36,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1285 states to 1285 states and 1726 transitions. [2019-10-22 08:59:36,538 INFO L711 BuchiCegarLoop]: Abstraction has 1285 states and 1726 transitions. [2019-10-22 08:59:36,539 INFO L591 BuchiCegarLoop]: Abstraction has 1285 states and 1726 transitions. [2019-10-22 08:59:36,539 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-10-22 08:59:36,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1285 states and 1726 transitions. [2019-10-22 08:59:36,544 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 856 [2019-10-22 08:59:36,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:36,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:36,545 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:36,550 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:36,550 INFO L791 eck$LassoCheckResult]: Stem: 13025#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 12715#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12716#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12994#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 12995#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12833#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12834#L221-1 assume !(0 == ~M_E~0); 12871#L324-1 assume !(0 == ~T1_E~0); 12741#L329-1 assume !(0 == ~T2_E~0); 12742#L334-1 assume !(0 == ~E_1~0); 12869#L339-1 assume !(0 == ~E_2~0); 12930#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12981#L146 assume !(1 == ~m_pc~0); 12813#L146-2 is_master_triggered_~__retres1~0 := 0; 12972#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13054#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 12811#L395 assume !(0 != activate_threads_~tmp~1); 12721#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12722#L165 assume !(1 == ~t1_pc~0); 13006#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 13009#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12870#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 12821#L403 assume !(0 != activate_threads_~tmp___0~0); 12822#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12835#L184 assume !(1 == ~t2_pc~0); 12955#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 13036#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12956#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12892#L411 assume !(0 != activate_threads_~tmp___1~0); 12856#L411-2 assume !(1 == ~M_E~0); 12857#L357-1 assume !(1 == ~T1_E~0); 12723#L362-1 assume !(1 == ~T2_E~0); 12724#L367-1 assume !(1 == ~E_1~0); 12862#L372-1 assume !(1 == ~E_2~0); 12922#L518-1 assume !false; 12743#L519 [2019-10-22 08:59:36,550 INFO L793 eck$LassoCheckResult]: Loop: 12743#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 12701#L299 assume !false; 12730#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12905#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13748#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13746#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 13744#L266 assume 0 != eval_~tmp~0; 13672#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 12693#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 12694#L37 assume !(0 == ~m_pc~0); 12705#L40 assume 1 == ~m_pc~0; 12706#L41 assume !false; 13016#L57 ~m_pc~0 := 1;~m_st~0 := 2; 13052#L271 assume !(0 == ~t1_st~0); 13735#L285 assume !(0 == ~t2_st~0); 13822#L299 assume !false; 13820#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13819#L234 assume !(0 == ~m_st~0); 12847#L238 assume !(0 == ~t1_st~0); 12849#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 13010#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13957#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 13956#L266 assume !(0 != eval_~tmp~0); 12998#L314 start_simulation_~kernel_st~0 := 2; 12988#L204-1 start_simulation_~kernel_st~0 := 3; 12989#L324-2 assume !(0 == ~M_E~0); 13042#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13795#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13793#L334-3 assume !(0 == ~E_1~0); 13792#L339-3 assume !(0 == ~E_2~0); 13015#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12912#L146-9 assume 1 == ~m_pc~0; 12771#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 12772#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13930#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 13928#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13925#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13923#L165-9 assume !(1 == ~t1_pc~0); 13922#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 13921#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13920#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 13919#L403-9 assume !(0 != activate_threads_~tmp___0~0); 13918#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13917#L184-9 assume !(1 == ~t2_pc~0); 13915#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 13914#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13912#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 13911#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13910#L411-11 assume !(1 == ~M_E~0); 13909#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13908#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13907#L367-3 assume !(1 == ~E_1~0); 13904#L372-3 assume !(1 == ~E_2~0); 13902#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12985#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12903#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12681#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 12682#L537 assume !(0 == start_simulation_~tmp~3); 12969#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12973#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12952#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12673#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 12674#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12880#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 12881#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 13039#L550 assume !(0 != start_simulation_~tmp___0~1); 12950#L518-1 assume !false; 12743#L519 [2019-10-22 08:59:36,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:36,551 INFO L82 PathProgramCache]: Analyzing trace with hash 704772710, now seen corresponding path program 1 times [2019-10-22 08:59:36,551 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:36,551 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [921321132] [2019-10-22 08:59:36,551 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,551 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,551 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:36,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:36,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:36,565 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:36,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:36,567 INFO L82 PathProgramCache]: Analyzing trace with hash -1284606298, now seen corresponding path program 1 times [2019-10-22 08:59:36,567 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:36,567 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145509814] [2019-10-22 08:59:36,567 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,568 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,568 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:36,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:36,605 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-22 08:59:36,605 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145509814] [2019-10-22 08:59:36,606 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:36,606 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:59:36,606 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [911820953] [2019-10-22 08:59:36,606 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:36,606 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:36,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:59:36,607 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:59:36,607 INFO L87 Difference]: Start difference. First operand 1285 states and 1726 transitions. cyclomatic complexity: 447 Second operand 5 states. [2019-10-22 08:59:36,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:36,669 INFO L93 Difference]: Finished difference Result 1905 states and 2543 transitions. [2019-10-22 08:59:36,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 08:59:36,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1905 states and 2543 transitions. [2019-10-22 08:59:36,679 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1268 [2019-10-22 08:59:36,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1905 states to 1905 states and 2543 transitions. [2019-10-22 08:59:36,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1316 [2019-10-22 08:59:36,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1316 [2019-10-22 08:59:36,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1905 states and 2543 transitions. [2019-10-22 08:59:36,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-10-22 08:59:36,689 INFO L688 BuchiCegarLoop]: Abstraction has 1905 states and 2543 transitions. [2019-10-22 08:59:36,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1905 states and 2543 transitions. [2019-10-22 08:59:36,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1905 to 1303. [2019-10-22 08:59:36,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1303 states. [2019-10-22 08:59:36,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1303 states to 1303 states and 1721 transitions. [2019-10-22 08:59:36,710 INFO L711 BuchiCegarLoop]: Abstraction has 1303 states and 1721 transitions. [2019-10-22 08:59:36,710 INFO L591 BuchiCegarLoop]: Abstraction has 1303 states and 1721 transitions. [2019-10-22 08:59:36,710 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-10-22 08:59:36,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1303 states and 1721 transitions. [2019-10-22 08:59:36,714 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 868 [2019-10-22 08:59:36,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:36,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:36,715 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:36,715 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:36,716 INFO L791 eck$LassoCheckResult]: Stem: 16248#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 15920#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 15921#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16209#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 16210#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16033#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16034#L221-1 assume !(0 == ~M_E~0); 16074#L324-1 assume !(0 == ~T1_E~0); 15932#L329-1 assume !(0 == ~T2_E~0); 15933#L334-1 assume !(0 == ~E_1~0); 16072#L339-1 assume !(0 == ~E_2~0); 16136#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16193#L146 assume !(1 == ~m_pc~0); 16013#L146-2 is_master_triggered_~__retres1~0 := 0; 16183#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16194#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 16008#L395 assume !(0 != activate_threads_~tmp~1); 15922#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15923#L165 assume !(1 == ~t1_pc~0); 16219#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 16220#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16073#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 16019#L403 assume !(0 != activate_threads_~tmp___0~0); 16020#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16035#L184 assume !(1 == ~t2_pc~0); 16165#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 16267#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16169#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 16093#L411 assume !(0 != activate_threads_~tmp___1~0); 16058#L411-2 assume !(1 == ~M_E~0); 16059#L357-1 assume !(1 == ~T1_E~0); 15924#L362-1 assume !(1 == ~T2_E~0); 15925#L367-1 assume !(1 == ~E_1~0); 16060#L372-1 assume !(1 == ~E_2~0); 16128#L518-1 assume !false; 16386#L519 [2019-10-22 08:59:36,716 INFO L793 eck$LassoCheckResult]: Loop: 16386#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 16737#L299 assume !false; 16735#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16733#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 16640#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16729#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 16727#L266 assume 0 != eval_~tmp~0; 16725#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 16671#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 16721#L37 assume !(0 == ~m_pc~0); 16694#L40 assume 1 == ~m_pc~0; 16692#L41 assume !false; 16672#L57 ~m_pc~0 := 1;~m_st~0 := 2; 16669#L271 assume !(0 == ~t1_st~0); 16653#L285 assume !(0 == ~t2_st~0); 16644#L299 assume !false; 16642#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16639#L234 assume !(0 == ~m_st~0); 16636#L238 assume !(0 == ~t1_st~0); 16633#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 16630#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16628#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 16625#L266 assume !(0 != eval_~tmp~0); 16622#L314 start_simulation_~kernel_st~0 := 2; 16620#L204-1 start_simulation_~kernel_st~0 := 3; 16618#L324-2 assume !(0 == ~M_E~0); 16616#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16614#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16612#L334-3 assume !(0 == ~E_1~0); 16610#L339-3 assume !(0 == ~E_2~0); 16608#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16606#L146-9 assume 1 == ~m_pc~0; 16603#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 16600#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16598#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 16595#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16592#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16590#L165-9 assume !(1 == ~t1_pc~0); 16588#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 16586#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16584#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 16582#L403-9 assume !(0 != activate_threads_~tmp___0~0); 16580#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16578#L184-9 assume !(1 == ~t2_pc~0); 16574#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 16572#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16570#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 16568#L411-9 assume !(0 != activate_threads_~tmp___1~0); 16566#L411-11 assume !(1 == ~M_E~0); 16557#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16558#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16814#L367-3 assume !(1 == ~E_1~0); 16812#L372-3 assume !(1 == ~E_2~0); 16541#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16538#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 16519#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16520#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 16795#L537 assume !(0 == start_simulation_~tmp~3); 16793#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16791#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 16745#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16782#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 16780#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16778#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 16761#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 16760#L550 assume !(0 != start_simulation_~tmp___0~1); 16759#L518-1 assume !false; 16386#L519 [2019-10-22 08:59:36,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:36,716 INFO L82 PathProgramCache]: Analyzing trace with hash 704772710, now seen corresponding path program 2 times [2019-10-22 08:59:36,716 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:36,718 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552269603] [2019-10-22 08:59:36,720 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,720 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,720 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:36,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:36,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:36,730 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:36,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:36,735 INFO L82 PathProgramCache]: Analyzing trace with hash -2102254748, now seen corresponding path program 1 times [2019-10-22 08:59:36,736 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:36,736 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464919641] [2019-10-22 08:59:36,736 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,736 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,736 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:36,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:36,762 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-22 08:59:36,762 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464919641] [2019-10-22 08:59:36,762 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:36,762 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:36,762 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029590666] [2019-10-22 08:59:36,762 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:36,763 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:36,763 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:36,764 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:36,764 INFO L87 Difference]: Start difference. First operand 1303 states and 1721 transitions. cyclomatic complexity: 424 Second operand 3 states. [2019-10-22 08:59:36,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:36,808 INFO L93 Difference]: Finished difference Result 2056 states and 2675 transitions. [2019-10-22 08:59:36,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:36,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2056 states and 2675 transitions. [2019-10-22 08:59:36,817 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1244 [2019-10-22 08:59:36,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2056 states to 1964 states and 2561 transitions. [2019-10-22 08:59:36,826 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1335 [2019-10-22 08:59:36,827 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1335 [2019-10-22 08:59:36,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1964 states and 2561 transitions. [2019-10-22 08:59:36,828 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-10-22 08:59:36,828 INFO L688 BuchiCegarLoop]: Abstraction has 1964 states and 2561 transitions. [2019-10-22 08:59:36,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1964 states and 2561 transitions. [2019-10-22 08:59:36,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1964 to 1956. [2019-10-22 08:59:36,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1956 states. [2019-10-22 08:59:36,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1956 states to 1956 states and 2551 transitions. [2019-10-22 08:59:36,855 INFO L711 BuchiCegarLoop]: Abstraction has 1956 states and 2551 transitions. [2019-10-22 08:59:36,855 INFO L591 BuchiCegarLoop]: Abstraction has 1956 states and 2551 transitions. [2019-10-22 08:59:36,855 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-10-22 08:59:36,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1956 states and 2551 transitions. [2019-10-22 08:59:36,862 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1238 [2019-10-22 08:59:36,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:36,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:36,862 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:36,863 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:36,863 INFO L791 eck$LassoCheckResult]: Stem: 19593#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 19284#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 19285#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19563#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 19564#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19392#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19393#L221-1 assume 0 == ~M_E~0;~M_E~0 := 1; 19430#L324-1 assume !(0 == ~T1_E~0); 19297#L329-1 assume !(0 == ~T2_E~0); 19298#L334-1 assume !(0 == ~E_1~0); 19428#L339-1 assume !(0 == ~E_2~0); 19648#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19645#L146 assume !(1 == ~m_pc~0); 19646#L146-2 is_master_triggered_~__retres1~0 := 0; 19647#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19644#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 19369#L395 assume !(0 != activate_threads_~tmp~1); 19286#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19287#L165 assume !(1 == ~t1_pc~0); 19575#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 19633#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19632#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 19631#L403 assume !(0 != activate_threads_~tmp___0~0); 19630#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19612#L184 assume !(1 == ~t2_pc~0); 19518#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 19613#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19520#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 19450#L411 assume !(0 != activate_threads_~tmp___1~0); 19415#L411-2 assume 1 == ~M_E~0;~M_E~0 := 2; 19416#L357-1 assume !(1 == ~T1_E~0); 19288#L362-1 assume !(1 == ~T2_E~0); 19289#L367-1 assume !(1 == ~E_1~0); 19417#L372-1 assume !(1 == ~E_2~0); 19484#L518-1 assume !false; 20095#L519 [2019-10-22 08:59:36,863 INFO L793 eck$LassoCheckResult]: Loop: 20095#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 20916#L299 assume !false; 20914#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 20912#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 20876#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 20909#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 20907#L266 assume 0 != eval_~tmp~0; 20905#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 20889#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 20900#L37 assume !(0 == ~m_pc~0); 20893#L40 assume 1 == ~m_pc~0; 20891#L41 assume !false; 20890#L57 ~m_pc~0 := 1;~m_st~0 := 2; 20887#L271 assume !(0 == ~t1_st~0); 20882#L285 assume !(0 == ~t2_st~0); 20878#L299 assume !false; 20877#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 20875#L234 assume !(0 == ~m_st~0); 20874#L238 assume !(0 == ~t1_st~0); 20872#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 20871#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 20870#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 20868#L266 assume !(0 != eval_~tmp~0); 20867#L314 start_simulation_~kernel_st~0 := 2; 20865#L204-1 start_simulation_~kernel_st~0 := 3; 20840#L324-2 assume !(0 == ~M_E~0); 20839#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20838#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20837#L334-3 assume !(0 == ~E_1~0); 20836#L339-3 assume !(0 == ~E_2~0); 20835#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20834#L146-9 assume !(1 == ~m_pc~0); 20831#L146-11 is_master_triggered_~__retres1~0 := 0; 20830#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20829#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 20828#L395-9 assume !(0 != activate_threads_~tmp~1); 20826#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19545#L165-9 assume !(1 == ~t1_pc~0); 19546#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 20866#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20864#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 20863#L403-9 assume !(0 != activate_threads_~tmp___0~0); 20862#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20861#L184-9 assume !(1 == ~t2_pc~0); 20859#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 20858#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20856#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 20853#L411-9 assume !(0 != activate_threads_~tmp___1~0); 19403#L411-11 assume !(1 == ~M_E~0); 19404#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19618#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19432#L367-3 assume !(1 == ~E_1~0); 19433#L372-3 assume !(1 == ~E_2~0); 19504#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 19582#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 19555#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 20857#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 20854#L537 assume !(0 == start_simulation_~tmp~3); 20855#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 20942#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 20940#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 20938#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 20937#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 20936#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 20935#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 20934#L550 assume !(0 != start_simulation_~tmp___0~1); 20933#L518-1 assume !false; 20095#L519 [2019-10-22 08:59:36,863 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:36,863 INFO L82 PathProgramCache]: Analyzing trace with hash -738688986, now seen corresponding path program 1 times [2019-10-22 08:59:36,863 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:36,864 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947018404] [2019-10-22 08:59:36,864 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,864 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,864 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:36,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:36,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:36,874 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947018404] [2019-10-22 08:59:36,874 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:36,874 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:36,874 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952642056] [2019-10-22 08:59:36,874 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:59:36,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:36,875 INFO L82 PathProgramCache]: Analyzing trace with hash 702655553, now seen corresponding path program 1 times [2019-10-22 08:59:36,875 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:36,875 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955481126] [2019-10-22 08:59:36,875 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,875 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,875 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:36,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:36,890 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:36,891 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955481126] [2019-10-22 08:59:36,891 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:36,891 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:36,891 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257278969] [2019-10-22 08:59:36,891 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:36,891 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:36,892 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:36,892 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:36,892 INFO L87 Difference]: Start difference. First operand 1956 states and 2551 transitions. cyclomatic complexity: 603 Second operand 3 states. [2019-10-22 08:59:36,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:36,913 INFO L93 Difference]: Finished difference Result 1117 states and 1430 transitions. [2019-10-22 08:59:36,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:36,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1117 states and 1430 transitions. [2019-10-22 08:59:36,918 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 750 [2019-10-22 08:59:36,921 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1117 states to 795 states and 1017 transitions. [2019-10-22 08:59:36,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 795 [2019-10-22 08:59:36,922 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 795 [2019-10-22 08:59:36,922 INFO L73 IsDeterministic]: Start isDeterministic. Operand 795 states and 1017 transitions. [2019-10-22 08:59:36,923 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:36,923 INFO L688 BuchiCegarLoop]: Abstraction has 795 states and 1017 transitions. [2019-10-22 08:59:36,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 795 states and 1017 transitions. [2019-10-22 08:59:36,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 795 to 472. [2019-10-22 08:59:36,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2019-10-22 08:59:36,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 600 transitions. [2019-10-22 08:59:36,931 INFO L711 BuchiCegarLoop]: Abstraction has 472 states and 600 transitions. [2019-10-22 08:59:36,931 INFO L591 BuchiCegarLoop]: Abstraction has 472 states and 600 transitions. [2019-10-22 08:59:36,931 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-10-22 08:59:36,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 472 states and 600 transitions. [2019-10-22 08:59:36,932 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 432 [2019-10-22 08:59:36,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:36,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:36,933 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:36,933 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:36,933 INFO L791 eck$LassoCheckResult]: Stem: 22522#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 22345#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 22346#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 22502#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 22503#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22409#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22410#L221-1 assume !(0 == ~M_E~0); 22434#L324-1 assume !(0 == ~T1_E~0); 22354#L329-1 assume !(0 == ~T2_E~0); 22355#L334-1 assume !(0 == ~E_1~0); 22432#L339-1 assume !(0 == ~E_2~0); 22470#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22496#L146 assume !(1 == ~m_pc~0); 22398#L146-2 is_master_triggered_~__retres1~0 := 0; 22490#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22399#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 22395#L395 assume !(0 != activate_threads_~tmp~1); 22347#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22348#L165 assume !(1 == ~t1_pc~0); 22512#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 22513#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22433#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 22401#L403 assume !(0 != activate_threads_~tmp___0~0); 22402#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22411#L184 assume !(1 == ~t2_pc~0); 22482#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 22534#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22484#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 22446#L411 assume !(0 != activate_threads_~tmp___1~0); 22424#L411-2 assume !(1 == ~M_E~0); 22425#L357-1 assume !(1 == ~T1_E~0); 22349#L362-1 assume !(1 == ~T2_E~0); 22350#L367-1 assume !(1 == ~E_1~0); 22426#L372-1 assume !(1 == ~E_2~0); 22465#L518-1 [2019-10-22 08:59:36,933 INFO L793 eck$LassoCheckResult]: Loop: 22465#L518-1 assume !false; 22361#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 22337#L299 assume !false; 22356#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22457#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22676#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22672#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 22601#L266 assume 0 != eval_~tmp~0; 22600#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 22599#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 22596#L37 assume !(0 == ~m_pc~0); 22597#L40 assume 1 == ~m_pc~0; 22436#L41 assume !false; 22542#L57 ~m_pc~0 := 1;~m_st~0 := 2; 22543#L271 assume !(0 == ~t1_st~0); 22637#L285 assume !(0 == ~t2_st~0); 22777#L299 assume !false; 22776#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22775#L234 assume !(0 == ~m_st~0); 22418#L238 assume !(0 == ~t1_st~0); 22420#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 22516#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22609#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 22606#L266 assume !(0 != eval_~tmp~0); 22603#L314 start_simulation_~kernel_st~0 := 2; 22602#L204-1 start_simulation_~kernel_st~0 := 3; 22598#L324-2 assume !(0 == ~M_E~0); 22595#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22593#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22591#L334-3 assume !(0 == ~E_1~0); 22590#L339-3 assume !(0 == ~E_2~0); 22582#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22575#L146-9 assume !(1 == ~m_pc~0); 22569#L146-11 is_master_triggered_~__retres1~0 := 0; 22563#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22558#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 22552#L395-9 assume !(0 != activate_threads_~tmp~1); 22341#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22342#L165-9 assume !(1 == ~t1_pc~0); 22495#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 22729#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22728#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 22727#L403-9 assume !(0 != activate_threads_~tmp___0~0); 22726#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22725#L184-9 assume !(1 == ~t2_pc~0); 22723#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 22721#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22719#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 22718#L411-9 assume !(0 != activate_threads_~tmp___1~0); 22416#L411-11 assume !(1 == ~M_E~0); 22417#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22362#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22363#L367-3 assume !(1 == ~E_1~0); 22435#L372-3 assume !(1 == ~E_2~0); 22476#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22499#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22455#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22326#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 22327#L537 assume !(0 == start_simulation_~tmp~3); 22488#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22492#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22483#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22322#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 22323#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22439#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 22440#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 22535#L550 assume !(0 != start_simulation_~tmp___0~1); 22465#L518-1 [2019-10-22 08:59:36,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:36,934 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 6 times [2019-10-22 08:59:36,934 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:36,934 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122655732] [2019-10-22 08:59:36,934 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,934 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,934 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:36,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:36,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:36,943 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:36,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:36,944 INFO L82 PathProgramCache]: Analyzing trace with hash -1341279001, now seen corresponding path program 2 times [2019-10-22 08:59:36,944 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:36,944 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229073055] [2019-10-22 08:59:36,944 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,944 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:36,944 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:36,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:36,960 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:36,960 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229073055] [2019-10-22 08:59:36,960 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:36,960 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:36,960 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588341322] [2019-10-22 08:59:36,961 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:36,961 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:36,961 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:36,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:36,961 INFO L87 Difference]: Start difference. First operand 472 states and 600 transitions. cyclomatic complexity: 130 Second operand 3 states. [2019-10-22 08:59:36,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:36,982 INFO L93 Difference]: Finished difference Result 587 states and 737 transitions. [2019-10-22 08:59:36,983 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:36,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 587 states and 737 transitions. [2019-10-22 08:59:36,985 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 431 [2019-10-22 08:59:36,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 587 states to 587 states and 737 transitions. [2019-10-22 08:59:36,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 587 [2019-10-22 08:59:36,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 587 [2019-10-22 08:59:36,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 587 states and 737 transitions. [2019-10-22 08:59:36,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:36,989 INFO L688 BuchiCegarLoop]: Abstraction has 587 states and 737 transitions. [2019-10-22 08:59:36,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 587 states and 737 transitions. [2019-10-22 08:59:36,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 587 to 546. [2019-10-22 08:59:36,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 546 states. [2019-10-22 08:59:36,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 691 transitions. [2019-10-22 08:59:36,996 INFO L711 BuchiCegarLoop]: Abstraction has 546 states and 691 transitions. [2019-10-22 08:59:36,997 INFO L591 BuchiCegarLoop]: Abstraction has 546 states and 691 transitions. [2019-10-22 08:59:36,997 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-10-22 08:59:36,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 691 transitions. [2019-10-22 08:59:36,998 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 431 [2019-10-22 08:59:36,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:36,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:36,999 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:36,999 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:37,000 INFO L791 eck$LassoCheckResult]: Stem: 23594#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 23409#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 23410#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 23572#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 23573#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23475#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23476#L221-1 assume !(0 == ~M_E~0); 23499#L324-1 assume !(0 == ~T1_E~0); 23419#L329-1 assume !(0 == ~T2_E~0); 23420#L334-1 assume !(0 == ~E_1~0); 23497#L339-1 assume !(0 == ~E_2~0); 23535#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23564#L146 assume 1 == ~m_pc~0; 23462#L147 assume !(1 == ~M_E~0); 23463#L146-2 is_master_triggered_~__retres1~0 := 0; 23557#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23464#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 23460#L395 assume !(0 != activate_threads_~tmp~1); 23411#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23412#L165 assume !(1 == ~t1_pc~0); 23583#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 23584#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23498#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 23467#L403 assume !(0 != activate_threads_~tmp___0~0); 23468#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23844#L184 assume !(1 == ~t2_pc~0); 23843#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 23842#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23841#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 23840#L411 assume !(0 != activate_threads_~tmp___1~0); 23839#L411-2 assume !(1 == ~M_E~0); 23837#L357-1 assume !(1 == ~T1_E~0); 23836#L362-1 assume !(1 == ~T2_E~0); 23835#L367-1 assume !(1 == ~E_1~0); 23827#L372-1 assume !(1 == ~E_2~0); 23826#L518-1 [2019-10-22 08:59:37,000 INFO L793 eck$LassoCheckResult]: Loop: 23826#L518-1 assume !false; 23818#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 23816#L299 assume !false; 23814#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 23810#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 23742#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 23807#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 23805#L266 assume 0 != eval_~tmp~0; 23802#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 23755#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 23439#L37 assume !(0 == ~m_pc~0); 23440#L40 assume 1 == ~m_pc~0; 23768#L41 assume !false; 23610#L57 ~m_pc~0 := 1;~m_st~0 := 2; 23611#L271 assume !(0 == ~t1_st~0); 23748#L285 assume !(0 == ~t2_st~0); 23744#L299 assume !false; 23743#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 23741#L234 assume !(0 == ~m_st~0); 23484#L238 assume !(0 == ~t1_st~0); 23486#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 23635#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 23633#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 23629#L266 assume !(0 != eval_~tmp~0); 23577#L314 start_simulation_~kernel_st~0 := 2; 23570#L204-1 start_simulation_~kernel_st~0 := 3; 23571#L324-2 assume !(0 == ~M_E~0); 23621#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23620#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23619#L334-3 assume !(0 == ~E_1~0); 23618#L339-3 assume !(0 == ~E_2~0); 23617#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23616#L146-9 assume 1 == ~m_pc~0; 23443#L147-3 assume !(1 == ~M_E~0); 23444#L146-11 is_master_triggered_~__retres1~0 := 0; 23522#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23553#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 23393#L395-9 assume !(0 != activate_threads_~tmp~1); 23394#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23405#L165-9 assume !(1 == ~t1_pc~0); 23563#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 23596#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23514#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 23465#L403-9 assume !(0 != activate_threads_~tmp___0~0); 23466#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23582#L184-9 assume !(1 == ~t2_pc~0); 23534#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 23723#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23721#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 23719#L411-9 assume !(0 != activate_threads_~tmp___1~0); 23716#L411-11 assume !(1 == ~M_E~0); 23714#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23710#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23707#L367-3 assume !(1 == ~E_1~0); 23704#L372-3 assume !(1 == ~E_2~0); 23590#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 23569#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 23517#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 23518#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 23856#L537 assume !(0 == start_simulation_~tmp~3); 23848#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 23834#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 23833#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 23832#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 23831#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 23830#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 23829#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 23828#L550 assume !(0 != start_simulation_~tmp___0~1); 23826#L518-1 [2019-10-22 08:59:37,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,000 INFO L82 PathProgramCache]: Analyzing trace with hash -1293822236, now seen corresponding path program 1 times [2019-10-22 08:59:37,000 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,000 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498418059] [2019-10-22 08:59:37,000 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,000 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,001 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:37,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:37,011 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498418059] [2019-10-22 08:59:37,011 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:37,011 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:37,011 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1682819527] [2019-10-22 08:59:37,012 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:59:37,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,012 INFO L82 PathProgramCache]: Analyzing trace with hash 1081139466, now seen corresponding path program 1 times [2019-10-22 08:59:37,012 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,012 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240565473] [2019-10-22 08:59:37,012 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,012 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,012 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:37,031 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-10-22 08:59:37,031 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240565473] [2019-10-22 08:59:37,031 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:37,031 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:37,032 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1068577335] [2019-10-22 08:59:37,032 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:59:37,032 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:37,032 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:37,032 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:37,032 INFO L87 Difference]: Start difference. First operand 546 states and 691 transitions. cyclomatic complexity: 149 Second operand 3 states. [2019-10-22 08:59:37,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:37,048 INFO L93 Difference]: Finished difference Result 525 states and 660 transitions. [2019-10-22 08:59:37,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:37,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 525 states and 660 transitions. [2019-10-22 08:59:37,050 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 431 [2019-10-22 08:59:37,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 525 states to 525 states and 660 transitions. [2019-10-22 08:59:37,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 525 [2019-10-22 08:59:37,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 525 [2019-10-22 08:59:37,053 INFO L73 IsDeterministic]: Start isDeterministic. Operand 525 states and 660 transitions. [2019-10-22 08:59:37,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:37,054 INFO L688 BuchiCegarLoop]: Abstraction has 525 states and 660 transitions. [2019-10-22 08:59:37,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states and 660 transitions. [2019-10-22 08:59:37,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 521. [2019-10-22 08:59:37,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 521 states. [2019-10-22 08:59:37,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 656 transitions. [2019-10-22 08:59:37,060 INFO L711 BuchiCegarLoop]: Abstraction has 521 states and 656 transitions. [2019-10-22 08:59:37,060 INFO L591 BuchiCegarLoop]: Abstraction has 521 states and 656 transitions. [2019-10-22 08:59:37,060 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-10-22 08:59:37,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 521 states and 656 transitions. [2019-10-22 08:59:37,062 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 431 [2019-10-22 08:59:37,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:37,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:37,062 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:37,062 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:37,063 INFO L791 eck$LassoCheckResult]: Stem: 24667#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 24487#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24488#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 24642#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 24643#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24546#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24547#L221-1 assume !(0 == ~M_E~0); 24569#L324-1 assume !(0 == ~T1_E~0); 24497#L329-1 assume !(0 == ~T2_E~0); 24498#L334-1 assume !(0 == ~E_1~0); 24567#L339-1 assume !(0 == ~E_2~0); 24606#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24634#L146 assume !(1 == ~m_pc~0); 24628#L146-2 is_master_triggered_~__retres1~0 := 0; 24629#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24536#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 24534#L395 assume !(0 != activate_threads_~tmp~1); 24489#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24490#L165 assume !(1 == ~t1_pc~0); 24652#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 24653#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24568#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 24538#L403 assume !(0 != activate_threads_~tmp___0~0); 24539#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24548#L184 assume !(1 == ~t2_pc~0); 24619#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 24675#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24621#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 24582#L411 assume !(0 != activate_threads_~tmp___1~0); 24559#L411-2 assume !(1 == ~M_E~0); 24560#L357-1 assume !(1 == ~T1_E~0); 24491#L362-1 assume !(1 == ~T2_E~0); 24492#L367-1 assume !(1 == ~E_1~0); 24561#L372-1 assume !(1 == ~E_2~0); 24600#L518-1 assume !false; 24731#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 24725#L299 [2019-10-22 08:59:37,063 INFO L793 eck$LassoCheckResult]: Loop: 24725#L299 assume !false; 24723#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 24721#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 24718#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 24716#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 24715#L266 assume 0 != eval_~tmp~0; 24713#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 24710#L274 assume !(0 != eval_~tmp_ndt_1~0); 24711#L271 assume !(0 == ~t1_st~0); 24734#L285 assume !(0 == ~t2_st~0); 24725#L299 [2019-10-22 08:59:37,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,063 INFO L82 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 1 times [2019-10-22 08:59:37,063 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,064 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233974318] [2019-10-22 08:59:37,064 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,064 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,064 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,073 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:37,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,073 INFO L82 PathProgramCache]: Analyzing trace with hash -1206180399, now seen corresponding path program 1 times [2019-10-22 08:59:37,073 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,073 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992902473] [2019-10-22 08:59:37,074 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,074 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,074 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,079 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:37,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,079 INFO L82 PathProgramCache]: Analyzing trace with hash 202160337, now seen corresponding path program 1 times [2019-10-22 08:59:37,079 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,079 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61496095] [2019-10-22 08:59:37,079 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,080 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,080 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:37,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:37,095 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61496095] [2019-10-22 08:59:37,095 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:37,095 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:37,095 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [508078772] [2019-10-22 08:59:37,137 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:37,137 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:37,137 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:37,137 INFO L87 Difference]: Start difference. First operand 521 states and 656 transitions. cyclomatic complexity: 139 Second operand 3 states. [2019-10-22 08:59:37,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:37,174 INFO L93 Difference]: Finished difference Result 919 states and 1138 transitions. [2019-10-22 08:59:37,174 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:37,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 919 states and 1138 transitions. [2019-10-22 08:59:37,177 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 660 [2019-10-22 08:59:37,181 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 919 states to 919 states and 1138 transitions. [2019-10-22 08:59:37,181 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 919 [2019-10-22 08:59:37,182 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 919 [2019-10-22 08:59:37,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 919 states and 1138 transitions. [2019-10-22 08:59:37,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:37,183 INFO L688 BuchiCegarLoop]: Abstraction has 919 states and 1138 transitions. [2019-10-22 08:59:37,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states and 1138 transitions. [2019-10-22 08:59:37,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 880. [2019-10-22 08:59:37,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 880 states. [2019-10-22 08:59:37,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 880 states to 880 states and 1090 transitions. [2019-10-22 08:59:37,196 INFO L711 BuchiCegarLoop]: Abstraction has 880 states and 1090 transitions. [2019-10-22 08:59:37,196 INFO L591 BuchiCegarLoop]: Abstraction has 880 states and 1090 transitions. [2019-10-22 08:59:37,196 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-10-22 08:59:37,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 880 states and 1090 transitions. [2019-10-22 08:59:37,199 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 621 [2019-10-22 08:59:37,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:37,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:37,199 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:37,199 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:37,200 INFO L791 eck$LassoCheckResult]: Stem: 26125#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 25934#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 25935#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26095#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 26096#L211-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 25996#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25997#L221-1 assume !(0 == ~M_E~0); 26018#L324-1 assume !(0 == ~T1_E~0); 25943#L329-1 assume !(0 == ~T2_E~0); 25944#L334-1 assume !(0 == ~E_1~0); 26016#L339-1 assume !(0 == ~E_2~0); 26057#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26567#L146 assume !(1 == ~m_pc~0); 26566#L146-2 is_master_triggered_~__retres1~0 := 0; 26565#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25984#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 25985#L395 assume !(0 != activate_threads_~tmp~1); 26564#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26563#L165 assume !(1 == ~t1_pc~0); 26133#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 26134#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26562#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 26561#L403 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25990#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25998#L184 assume !(1 == ~t2_pc~0); 26138#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 26139#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26554#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 26031#L411 assume !(0 != activate_threads_~tmp___1~0); 26008#L411-2 assume !(1 == ~M_E~0); 26009#L357-1 assume !(1 == ~T1_E~0); 25938#L362-1 assume !(1 == ~T2_E~0); 25939#L367-1 assume !(1 == ~E_1~0); 26010#L372-1 assume !(1 == ~E_2~0); 26541#L518-1 assume !false; 26536#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 26533#L299 [2019-10-22 08:59:37,200 INFO L793 eck$LassoCheckResult]: Loop: 26533#L299 assume !false; 26368#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 26369#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 26361#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 26362#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 26357#L266 assume 0 != eval_~tmp~0; 26358#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 26350#L274 assume !(0 != eval_~tmp_ndt_1~0); 26348#L271 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 26345#L288 assume !(0 != eval_~tmp_ndt_2~0); 26346#L285 assume !(0 == ~t2_st~0); 26533#L299 [2019-10-22 08:59:37,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,200 INFO L82 PathProgramCache]: Analyzing trace with hash 1658994561, now seen corresponding path program 1 times [2019-10-22 08:59:37,200 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,200 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099126318] [2019-10-22 08:59:37,200 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,200 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,201 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:37,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:37,217 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099126318] [2019-10-22 08:59:37,217 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:37,217 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:59:37,218 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1486450420] [2019-10-22 08:59:37,218 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:59:37,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,218 INFO L82 PathProgramCache]: Analyzing trace with hash 1263010541, now seen corresponding path program 1 times [2019-10-22 08:59:37,218 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,218 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598944488] [2019-10-22 08:59:37,218 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,218 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,219 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,223 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:37,273 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:37,274 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:37,274 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:37,274 INFO L87 Difference]: Start difference. First operand 880 states and 1090 transitions. cyclomatic complexity: 216 Second operand 3 states. [2019-10-22 08:59:37,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:37,279 INFO L93 Difference]: Finished difference Result 567 states and 706 transitions. [2019-10-22 08:59:37,279 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:37,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 567 states and 706 transitions. [2019-10-22 08:59:37,282 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 453 [2019-10-22 08:59:37,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 567 states to 567 states and 706 transitions. [2019-10-22 08:59:37,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 567 [2019-10-22 08:59:37,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 567 [2019-10-22 08:59:37,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 567 states and 706 transitions. [2019-10-22 08:59:37,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:37,285 INFO L688 BuchiCegarLoop]: Abstraction has 567 states and 706 transitions. [2019-10-22 08:59:37,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states and 706 transitions. [2019-10-22 08:59:37,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 567. [2019-10-22 08:59:37,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 567 states. [2019-10-22 08:59:37,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 567 states to 567 states and 706 transitions. [2019-10-22 08:59:37,293 INFO L711 BuchiCegarLoop]: Abstraction has 567 states and 706 transitions. [2019-10-22 08:59:37,293 INFO L591 BuchiCegarLoop]: Abstraction has 567 states and 706 transitions. [2019-10-22 08:59:37,293 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-10-22 08:59:37,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 567 states and 706 transitions. [2019-10-22 08:59:37,295 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 453 [2019-10-22 08:59:37,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:37,295 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:37,295 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:37,296 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:37,296 INFO L791 eck$LassoCheckResult]: Stem: 27569#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 27388#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 27389#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27545#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 27546#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27450#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27451#L221-1 assume !(0 == ~M_E~0); 27471#L324-1 assume !(0 == ~T1_E~0); 27398#L329-1 assume !(0 == ~T2_E~0); 27399#L334-1 assume !(0 == ~E_1~0); 27469#L339-1 assume !(0 == ~E_2~0); 27506#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27536#L146 assume !(1 == ~m_pc~0); 27529#L146-2 is_master_triggered_~__retres1~0 := 0; 27530#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27440#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 27438#L395 assume !(0 != activate_threads_~tmp~1); 27390#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27391#L165 assume !(1 == ~t1_pc~0); 27555#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 27556#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27470#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 27443#L403 assume !(0 != activate_threads_~tmp___0~0); 27444#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27452#L184 assume !(1 == ~t2_pc~0); 27521#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 27575#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27523#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 27483#L411 assume !(0 != activate_threads_~tmp___1~0); 27461#L411-2 assume !(1 == ~M_E~0); 27462#L357-1 assume !(1 == ~T1_E~0); 27392#L362-1 assume !(1 == ~T2_E~0); 27393#L367-1 assume !(1 == ~E_1~0); 27463#L372-1 assume !(1 == ~E_2~0); 27501#L518-1 assume !false; 27825#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 27822#L299 [2019-10-22 08:59:37,296 INFO L793 eck$LassoCheckResult]: Loop: 27822#L299 assume !false; 27819#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 27815#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 27809#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 27806#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 27803#L266 assume 0 != eval_~tmp~0; 27799#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 27797#L274 assume !(0 != eval_~tmp_ndt_1~0); 27798#L271 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 27832#L288 assume !(0 != eval_~tmp_ndt_2~0); 27828#L285 assume !(0 == ~t2_st~0); 27822#L299 [2019-10-22 08:59:37,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,296 INFO L82 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 2 times [2019-10-22 08:59:37,296 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,296 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429773249] [2019-10-22 08:59:37,296 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,297 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,297 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,306 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:37,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,307 INFO L82 PathProgramCache]: Analyzing trace with hash 1263010541, now seen corresponding path program 2 times [2019-10-22 08:59:37,307 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,307 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774021541] [2019-10-22 08:59:37,307 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,307 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,307 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,313 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:37,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,314 INFO L82 PathProgramCache]: Analyzing trace with hash 1971900397, now seen corresponding path program 1 times [2019-10-22 08:59:37,314 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,314 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930357764] [2019-10-22 08:59:37,314 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,314 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,314 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:59:37,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:59:37,333 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930357764] [2019-10-22 08:59:37,333 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:59:37,333 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:59:37,333 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928593265] [2019-10-22 08:59:37,377 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:59:37,378 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:59:37,378 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:59:37,378 INFO L87 Difference]: Start difference. First operand 567 states and 706 transitions. cyclomatic complexity: 143 Second operand 3 states. [2019-10-22 08:59:37,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:59:37,398 INFO L93 Difference]: Finished difference Result 947 states and 1164 transitions. [2019-10-22 08:59:37,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:59:37,399 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 947 states and 1164 transitions. [2019-10-22 08:59:37,402 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 756 [2019-10-22 08:59:37,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 947 states to 947 states and 1164 transitions. [2019-10-22 08:59:37,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 947 [2019-10-22 08:59:37,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 947 [2019-10-22 08:59:37,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 947 states and 1164 transitions. [2019-10-22 08:59:37,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:59:37,411 INFO L688 BuchiCegarLoop]: Abstraction has 947 states and 1164 transitions. [2019-10-22 08:59:37,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 947 states and 1164 transitions. [2019-10-22 08:59:37,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 947 to 947. [2019-10-22 08:59:37,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 947 states. [2019-10-22 08:59:37,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 947 states to 947 states and 1164 transitions. [2019-10-22 08:59:37,422 INFO L711 BuchiCegarLoop]: Abstraction has 947 states and 1164 transitions. [2019-10-22 08:59:37,422 INFO L591 BuchiCegarLoop]: Abstraction has 947 states and 1164 transitions. [2019-10-22 08:59:37,422 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-10-22 08:59:37,422 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 947 states and 1164 transitions. [2019-10-22 08:59:37,425 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 756 [2019-10-22 08:59:37,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:59:37,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:59:37,426 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:37,426 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:59:37,426 INFO L791 eck$LassoCheckResult]: Stem: 29091#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 28909#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28910#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 29069#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 29070#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28971#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28972#L221-1 assume !(0 == ~M_E~0); 28993#L324-1 assume !(0 == ~T1_E~0); 28918#L329-1 assume !(0 == ~T2_E~0); 28919#L334-1 assume !(0 == ~E_1~0); 28991#L339-1 assume !(0 == ~E_2~0); 29032#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29061#L146 assume !(1 == ~m_pc~0); 29055#L146-2 is_master_triggered_~__retres1~0 := 0; 29056#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28961#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 28959#L395 assume !(0 != activate_threads_~tmp~1); 28911#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28912#L165 assume !(1 == ~t1_pc~0); 29076#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 29079#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28992#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 28964#L403 assume !(0 != activate_threads_~tmp___0~0); 28965#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28973#L184 assume !(1 == ~t2_pc~0); 29047#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 29098#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29048#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 29006#L411 assume !(0 != activate_threads_~tmp___1~0); 28983#L411-2 assume !(1 == ~M_E~0); 28984#L357-1 assume !(1 == ~T1_E~0); 28913#L362-1 assume !(1 == ~T2_E~0); 28914#L367-1 assume !(1 == ~E_1~0); 28985#L372-1 assume !(1 == ~E_2~0); 29027#L518-1 assume !false; 29757#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 29104#L299 [2019-10-22 08:59:37,426 INFO L793 eck$LassoCheckResult]: Loop: 29104#L299 assume !false; 29754#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 29752#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 29750#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 29748#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 29747#L266 assume 0 != eval_~tmp~0; 29746#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 29744#L274 assume !(0 != eval_~tmp_ndt_1~0); 29745#L271 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 28916#L288 assume !(0 != eval_~tmp_ndt_2~0); 28901#L285 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 28902#L302 assume !(0 != eval_~tmp_ndt_3~0); 29104#L299 [2019-10-22 08:59:37,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,426 INFO L82 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 3 times [2019-10-22 08:59:37,427 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,427 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113278076] [2019-10-22 08:59:37,427 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,427 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,427 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,437 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:37,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,440 INFO L82 PathProgramCache]: Analyzing trace with hash 498620433, now seen corresponding path program 1 times [2019-10-22 08:59:37,440 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,440 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105461810] [2019-10-22 08:59:37,440 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,440 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,440 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,448 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:37,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:59:37,449 INFO L82 PathProgramCache]: Analyzing trace with hash 999369489, now seen corresponding path program 1 times [2019-10-22 08:59:37,449 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:59:37,449 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873209538] [2019-10-22 08:59:37,449 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,449 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:59:37,449 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:59:37,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:59:37,462 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:59:37,685 WARN L191 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 66 [2019-10-22 08:59:37,763 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 22.10 08:59:37 BoogieIcfgContainer [2019-10-22 08:59:37,765 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-10-22 08:59:37,765 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-10-22 08:59:37,766 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-10-22 08:59:37,766 INFO L275 PluginConnector]: Witness Printer initialized [2019-10-22 08:59:37,766 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:59:32" (3/4) ... [2019-10-22 08:59:37,769 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-10-22 08:59:37,826 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_ad1ae25c-4bff-4b10-add3-f49b9dc46ee2/bin/uautomizer/witness.graphml [2019-10-22 08:59:37,828 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-10-22 08:59:37,829 INFO L168 Benchmark]: Toolchain (without parser) took 6898.30 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 313.0 MB). Free memory was 951.2 MB in the beginning and 889.7 MB in the end (delta: 61.5 MB). Peak memory consumption was 374.5 MB. Max. memory is 11.5 GB. [2019-10-22 08:59:37,830 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 967.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-10-22 08:59:37,831 INFO L168 Benchmark]: CACSL2BoogieTranslator took 327.71 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 184.0 MB). Free memory was 951.2 MB in the beginning and 1.2 GB in the end (delta: -224.5 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. [2019-10-22 08:59:37,831 INFO L168 Benchmark]: Boogie Procedure Inliner took 48.98 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2019-10-22 08:59:37,831 INFO L168 Benchmark]: Boogie Preprocessor took 34.35 ms. Allocated memory is still 1.2 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-10-22 08:59:37,831 INFO L168 Benchmark]: RCFGBuilder took 677.47 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 57.7 MB). Peak memory consumption was 57.7 MB. Max. memory is 11.5 GB. [2019-10-22 08:59:37,832 INFO L168 Benchmark]: BuchiAutomizer took 5742.91 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 129.0 MB). Free memory was 1.1 GB in the beginning and 892.7 MB in the end (delta: 218.7 MB). Peak memory consumption was 347.6 MB. Max. memory is 11.5 GB. [2019-10-22 08:59:37,832 INFO L168 Benchmark]: Witness Printer took 62.99 ms. Allocated memory is still 1.3 GB. Free memory was 892.7 MB in the beginning and 889.7 MB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 11.5 GB. [2019-10-22 08:59:37,833 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 967.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 327.71 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 184.0 MB). Free memory was 951.2 MB in the beginning and 1.2 GB in the end (delta: -224.5 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 48.98 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 34.35 ms. Allocated memory is still 1.2 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 677.47 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 57.7 MB). Peak memory consumption was 57.7 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 5742.91 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 129.0 MB). Free memory was 1.1 GB in the beginning and 892.7 MB in the end (delta: 218.7 MB). Peak memory consumption was 347.6 MB. Max. memory is 11.5 GB. * Witness Printer took 62.99 ms. Allocated memory is still 1.3 GB. Free memory was 892.7 MB in the beginning and 889.7 MB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 19 terminating modules (18 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * M_E + 1 and consists of 3 locations. 18 modules have a trivial ranking function, the largest among these consists of 11 locations. The remainder module has 947 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.6s and 19 iterations. TraceHistogramMax:2. Analysis of lassos took 3.7s. Construction of modules took 0.5s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 3. Minimization of det autom 14. Minimization of nondet autom 5. Automata minimization 0.2s AutomataMinimizationTime, 19 MinimizatonAttempts, 2738 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 1956 states and ocurred in iteration 12. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 5834 SDtfs, 5467 SDslu, 8352 SDs, 0 SdLazy, 517 SolverSat, 165 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.5s Time LassoAnalysisResults: nont1 unkn0 SFLI7 SFLT0 conc2 concLT1 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital116 mio100 ax100 hnf100 lsp9 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 4ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 8 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.2s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 261]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2b78a463=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6808068a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3515939d=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7f4d9d87=0, kernel_st=1, __retres1=0, tmp___0=0, t2_st=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4a8cc084=0, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c4ca944=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5e1bee1=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5e536260=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@ea2ef00=0, t1_st=0, \result=0, t2_pc=0, m_st=0, tmp___1=0, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 261]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int m_i ; [L22] int t1_i ; [L23] int t2_i ; [L24] int M_E = 2; [L25] int T1_E = 2; [L26] int T2_E = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; [L563] int __retres1 ; [L477] m_i = 1 [L478] t1_i = 1 [L479] t2_i = 1 [L504] int kernel_st ; [L505] int tmp ; [L506] int tmp___0 ; [L510] kernel_st = 0 [L211] COND TRUE m_i == 1 [L212] m_st = 0 [L216] COND TRUE t1_i == 1 [L217] t1_st = 0 [L221] COND TRUE t2_i == 1 [L222] t2_st = 0 [L324] COND FALSE !(M_E == 0) [L329] COND FALSE !(T1_E == 0) [L334] COND FALSE !(T2_E == 0) [L339] COND FALSE !(E_1 == 0) [L344] COND FALSE !(E_2 == 0) [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; [L143] int __retres1 ; [L146] COND FALSE !(m_pc == 1) [L156] __retres1 = 0 [L158] return (__retres1); [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) [L162] int __retres1 ; [L165] COND FALSE !(t1_pc == 1) [L175] __retres1 = 0 [L177] return (__retres1); [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) [L181] int __retres1 ; [L184] COND FALSE !(t2_pc == 1) [L194] __retres1 = 0 [L196] return (__retres1); [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) [L357] COND FALSE !(M_E == 1) [L362] COND FALSE !(T1_E == 1) [L367] COND FALSE !(T2_E == 1) [L372] COND FALSE !(E_1 == 1) [L377] COND FALSE !(E_2 == 1) [L518] COND TRUE 1 [L521] kernel_st = 1 [L257] int tmp ; Loop: [L261] COND TRUE 1 [L231] int __retres1 ; [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 [L252] return (__retres1); [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND FALSE !(\read(tmp_ndt_1)) [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND FALSE !(\read(tmp_ndt_2)) [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...