./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.06.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.06.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7b5159bbdd5292a1bc0941c897062f30a665bf67 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-10-22 08:54:45,836 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-22 08:54:45,837 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-22 08:54:45,846 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-22 08:54:45,846 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-22 08:54:45,847 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-22 08:54:45,848 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-22 08:54:45,850 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-22 08:54:45,851 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-22 08:54:45,852 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-22 08:54:45,853 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-22 08:54:45,854 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-22 08:54:45,854 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-22 08:54:45,855 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-22 08:54:45,855 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-22 08:54:45,856 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-22 08:54:45,857 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-22 08:54:45,857 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-22 08:54:45,859 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-22 08:54:45,860 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-22 08:54:45,861 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-22 08:54:45,862 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-22 08:54:45,863 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-22 08:54:45,863 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-22 08:54:45,866 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-22 08:54:45,866 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-22 08:54:45,866 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-22 08:54:45,867 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-22 08:54:45,867 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-22 08:54:45,868 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-22 08:54:45,868 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-22 08:54:45,869 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-22 08:54:45,869 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-22 08:54:45,870 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-22 08:54:45,871 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-22 08:54:45,871 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-22 08:54:45,871 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-22 08:54:45,871 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-22 08:54:45,871 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-22 08:54:45,872 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-22 08:54:45,873 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-22 08:54:45,873 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-10-22 08:54:45,885 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-22 08:54:45,885 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-22 08:54:45,886 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-22 08:54:45,887 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-22 08:54:45,887 INFO L138 SettingsManager]: * Use SBE=true [2019-10-22 08:54:45,887 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-10-22 08:54:45,887 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-10-22 08:54:45,887 INFO L138 SettingsManager]: * Use old map elimination=false [2019-10-22 08:54:45,887 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-10-22 08:54:45,887 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-10-22 08:54:45,888 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-10-22 08:54:45,888 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-22 08:54:45,888 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-22 08:54:45,888 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-10-22 08:54:45,888 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-22 08:54:45,888 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-22 08:54:45,889 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-22 08:54:45,889 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-10-22 08:54:45,889 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-10-22 08:54:45,889 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-10-22 08:54:45,889 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-22 08:54:45,889 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-22 08:54:45,889 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-10-22 08:54:45,889 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-22 08:54:45,890 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-10-22 08:54:45,890 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-22 08:54:45,890 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-22 08:54:45,890 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-10-22 08:54:45,890 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-22 08:54:45,890 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-22 08:54:45,890 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-10-22 08:54:45,891 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-10-22 08:54:45,891 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7b5159bbdd5292a1bc0941c897062f30a665bf67 [2019-10-22 08:54:45,924 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-22 08:54:45,934 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-22 08:54:45,937 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-22 08:54:45,938 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-22 08:54:45,938 INFO L275 PluginConnector]: CDTParser initialized [2019-10-22 08:54:45,939 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.06.cil.c [2019-10-22 08:54:45,985 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/data/934628ac0/728520eae7a2418c907093037c915e5a/FLAGb690d4a2f [2019-10-22 08:54:46,411 INFO L306 CDTParser]: Found 1 translation units. [2019-10-22 08:54:46,411 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/sv-benchmarks/c/systemc/transmitter.06.cil.c [2019-10-22 08:54:46,426 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/data/934628ac0/728520eae7a2418c907093037c915e5a/FLAGb690d4a2f [2019-10-22 08:54:46,790 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/data/934628ac0/728520eae7a2418c907093037c915e5a [2019-10-22 08:54:46,792 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-22 08:54:46,793 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-10-22 08:54:46,795 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-22 08:54:46,795 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-22 08:54:46,798 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-22 08:54:46,799 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 08:54:46" (1/1) ... [2019-10-22 08:54:46,801 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5b43a16a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:46, skipping insertion in model container [2019-10-22 08:54:46,801 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.10 08:54:46" (1/1) ... [2019-10-22 08:54:46,808 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-22 08:54:46,850 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-22 08:54:47,117 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 08:54:47,124 INFO L188 MainTranslator]: Completed pre-run [2019-10-22 08:54:47,182 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-22 08:54:47,199 INFO L192 MainTranslator]: Completed translation [2019-10-22 08:54:47,199 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47 WrapperNode [2019-10-22 08:54:47,199 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-22 08:54:47,200 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-10-22 08:54:47,200 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-10-22 08:54:47,200 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-10-22 08:54:47,207 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47" (1/1) ... [2019-10-22 08:54:47,214 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47" (1/1) ... [2019-10-22 08:54:47,263 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-10-22 08:54:47,263 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-22 08:54:47,263 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-22 08:54:47,263 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-22 08:54:47,272 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47" (1/1) ... [2019-10-22 08:54:47,273 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47" (1/1) ... [2019-10-22 08:54:47,278 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47" (1/1) ... [2019-10-22 08:54:47,278 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47" (1/1) ... [2019-10-22 08:54:47,292 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47" (1/1) ... [2019-10-22 08:54:47,309 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47" (1/1) ... [2019-10-22 08:54:47,314 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47" (1/1) ... [2019-10-22 08:54:47,321 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-22 08:54:47,321 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-22 08:54:47,322 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-22 08:54:47,322 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-22 08:54:47,322 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-10-22 08:54:47,382 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-22 08:54:47,382 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-22 08:54:48,748 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-22 08:54:48,749 INFO L284 CfgBuilder]: Removed 218 assume(true) statements. [2019-10-22 08:54:48,750 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:54:48 BoogieIcfgContainer [2019-10-22 08:54:48,750 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-22 08:54:48,751 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-10-22 08:54:48,751 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-10-22 08:54:48,754 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-10-22 08:54:48,755 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-10-22 08:54:48,755 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.10 08:54:46" (1/3) ... [2019-10-22 08:54:48,756 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4ac5da47 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.10 08:54:48, skipping insertion in model container [2019-10-22 08:54:48,756 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-10-22 08:54:48,757 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.10 08:54:47" (2/3) ... [2019-10-22 08:54:48,757 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4ac5da47 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.10 08:54:48, skipping insertion in model container [2019-10-22 08:54:48,757 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-10-22 08:54:48,757 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:54:48" (3/3) ... [2019-10-22 08:54:48,759 INFO L371 chiAutomizerObserver]: Analyzing ICFG transmitter.06.cil.c [2019-10-22 08:54:48,793 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-10-22 08:54:48,793 INFO L357 BuchiCegarLoop]: Hoare is false [2019-10-22 08:54:48,794 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-10-22 08:54:48,794 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-22 08:54:48,794 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-22 08:54:48,794 INFO L361 BuchiCegarLoop]: Difference is false [2019-10-22 08:54:48,794 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-22 08:54:48,794 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-10-22 08:54:48,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 611 states. [2019-10-22 08:54:48,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 522 [2019-10-22 08:54:48,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:48,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:48,880 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:48,881 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:48,881 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-10-22 08:54:48,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 611 states. [2019-10-22 08:54:48,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 522 [2019-10-22 08:54:48,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:48,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:48,898 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:48,898 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:48,906 INFO L791 eck$LassoCheckResult]: Stem: 411#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 309#L-1true havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 563#L977true havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 54#L444true assume !(1 == ~m_i~0);~m_st~0 := 2; 429#L451-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 131#L456-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 333#L461-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 56#L466-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 542#L471-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 252#L476-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 599#L481-1true assume !(0 == ~M_E~0); 438#L660-1true assume !(0 == ~T1_E~0); 5#L665-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 342#L670-1true assume !(0 == ~T3_E~0); 61#L675-1true assume !(0 == ~T4_E~0); 550#L680-1true assume !(0 == ~T5_E~0); 261#L685-1true assume !(0 == ~T6_E~0); 607#L690-1true assume !(0 == ~E_1~0); 161#L695-1true assume !(0 == ~E_2~0); 524#L700-1true assume !(0 == ~E_3~0); 390#L705-1true assume 0 == ~E_4~0;~E_4~0 := 1; 101#L710-1true assume !(0 == ~E_5~0); 454#L715-1true assume !(0 == ~E_6~0); 23#L720-1true havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 146#L310true assume 1 == ~m_pc~0; 232#L311true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 144#L321true is_master_triggered_#res := is_master_triggered_~__retres1~0; 231#L322true activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 395#L815true assume !(0 != activate_threads_~tmp~1); 386#L815-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 312#L329true assume !(1 == ~t1_pc~0); 320#L329-2true is_transmit1_triggered_~__retres1~1 := 0; 310#L340true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 432#L341true activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 558#L823true assume !(0 != activate_threads_~tmp___0~0); 559#L823-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 501#L348true assume 1 == ~t2_pc~0; 581#L349true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 498#L359true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 579#L360true activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 107#L831true assume !(0 != activate_threads_~tmp___1~0); 98#L831-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 59#L367true assume 1 == ~t3_pc~0; 135#L368true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 58#L378true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 133#L379true activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 269#L839true assume !(0 != activate_threads_~tmp___2~0); 271#L839-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 196#L386true assume !(1 == ~t4_pc~0); 200#L386-2true is_transmit4_triggered_~__retres1~4 := 0; 195#L397true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 139#L398true activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 461#L847true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 449#L847-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 545#L405true assume 1 == ~t5_pc~0; 336#L406true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 544#L416true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 335#L417true activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 465#L855true assume !(0 != activate_threads_~tmp___4~0); 467#L855-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 83#L424true assume !(1 == ~t6_pc~0); 87#L424-2true is_transmit6_triggered_~__retres1~6 := 0; 81#L435true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 490#L436true activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 32#L863true assume !(0 != activate_threads_~tmp___5~0); 16#L863-2true assume !(1 == ~M_E~0); 521#L733-1true assume !(1 == ~T1_E~0); 388#L738-1true assume !(1 == ~T2_E~0); 100#L743-1true assume !(1 == ~T3_E~0); 452#L748-1true assume !(1 == ~T4_E~0); 20#L753-1true assume !(1 == ~T5_E~0); 353#L758-1true assume !(1 == ~T6_E~0); 66#L763-1true assume 1 == ~E_1~0;~E_1~0 := 2; 560#L768-1true assume !(1 == ~E_2~0); 255#L773-1true assume !(1 == ~E_3~0); 602#L778-1true assume !(1 == ~E_4~0); 157#L783-1true assume !(1 == ~E_5~0); 519#L788-1true assume !(1 == ~E_6~0); 176#L1014-1true [2019-10-22 08:54:48,908 INFO L793 eck$LassoCheckResult]: Loop: 176#L1014-1true assume !false; 276#L1015true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 609#L635true assume false; 391#L650true start_simulation_~kernel_st~0 := 2; 57#L444-1true start_simulation_~kernel_st~0 := 3; 440#L660-2true assume !(0 == ~M_E~0); 445#L660-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 12#L665-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 346#L670-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 62#L675-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 554#L680-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 264#L685-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 612#L690-3true assume 0 == ~E_1~0;~E_1~0 := 1; 154#L695-3true assume !(0 == ~E_2~0); 510#L700-3true assume 0 == ~E_3~0;~E_3~0 := 1; 205#L705-3true assume 0 == ~E_4~0;~E_4~0 := 1; 95#L710-3true assume 0 == ~E_5~0;~E_5~0 := 1; 439#L715-3true assume 0 == ~E_6~0;~E_6~0 := 1; 8#L720-3true havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 262#L310-21true assume 1 == ~m_pc~0; 224#L311-7true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 296#L321-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 223#L322-7true activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 190#L815-21true assume !(0 != activate_threads_~tmp~1); 171#L815-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 434#L329-21true assume !(1 == ~t1_pc~0); 441#L329-23true is_transmit1_triggered_~__retres1~1 := 0; 304#L340-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 397#L341-7true activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 365#L823-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 367#L823-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 605#L348-21true assume !(1 == ~t2_pc~0); 611#L348-23true is_transmit2_triggered_~__retres1~2 := 0; 488#L359-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 572#L360-7true activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 77#L831-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 533#L831-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21#L367-21true assume !(1 == ~t3_pc~0); 6#L367-23true is_transmit3_triggered_~__retres1~3 := 0; 36#L378-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 108#L379-7true activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 220#L839-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 225#L839-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 159#L386-21true assume !(1 == ~t4_pc~0); 162#L386-23true is_transmit4_triggered_~__retres1~4 := 0; 187#L397-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 288#L398-7true activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 423#L847-21true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 400#L847-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 352#L405-21true assume !(1 == ~t5_pc~0); 340#L405-23true is_transmit5_triggered_~__retres1~5 := 0; 361#L416-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 328#L417-7true activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 570#L855-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 574#L855-23true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 520#L424-21true assume 1 == ~t6_pc~0; 482#L425-7true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 73#L435-7true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 480#L436-7true activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 128#L863-21true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 111#L863-23true assume 1 == ~M_E~0;~M_E~0 := 2; 526#L733-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 393#L738-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 93#L743-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 436#L748-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 4#L753-3true assume !(1 == ~T5_E~0); 341#L758-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 60#L763-3true assume 1 == ~E_1~0;~E_1~0 := 2; 548#L768-3true assume 1 == ~E_2~0;~E_2~0 := 2; 260#L773-3true assume 1 == ~E_3~0;~E_3~0 := 2; 606#L778-3true assume 1 == ~E_4~0;~E_4~0 := 2; 160#L783-3true assume 1 == ~E_5~0;~E_5~0 := 2; 523#L788-3true assume 1 == ~E_6~0;~E_6~0 := 2; 389#L793-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 332#L494-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 247#L531-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 50#L532-1true start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 354#L1033true assume !(0 == start_simulation_~tmp~3); 356#L1033-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 334#L494-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 251#L531-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 53#L532-2true stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 562#L988true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 26#L995true stop_simulation_#res := stop_simulation_~__retres2~0; 103#L996true start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 406#L1046true assume !(0 != start_simulation_~tmp___0~1); 176#L1014-1true [2019-10-22 08:54:48,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:48,917 INFO L82 PathProgramCache]: Analyzing trace with hash 1207060675, now seen corresponding path program 1 times [2019-10-22 08:54:48,924 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:48,924 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48508722] [2019-10-22 08:54:48,925 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:48,925 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:48,925 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:49,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:49,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:49,078 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [48508722] [2019-10-22 08:54:49,079 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:49,079 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:49,079 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1860861822] [2019-10-22 08:54:49,084 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:49,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:49,085 INFO L82 PathProgramCache]: Analyzing trace with hash 1842470833, now seen corresponding path program 1 times [2019-10-22 08:54:49,085 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:49,085 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1909756921] [2019-10-22 08:54:49,086 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,087 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,087 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:49,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:49,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:49,120 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1909756921] [2019-10-22 08:54:49,120 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:49,121 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:54:49,121 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265007853] [2019-10-22 08:54:49,123 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:49,124 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:49,139 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:49,140 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:49,142 INFO L87 Difference]: Start difference. First operand 611 states. Second operand 3 states. [2019-10-22 08:54:49,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:49,198 INFO L93 Difference]: Finished difference Result 611 states and 922 transitions. [2019-10-22 08:54:49,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:49,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 611 states and 922 transitions. [2019-10-22 08:54:49,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:49,222 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 611 states to 606 states and 917 transitions. [2019-10-22 08:54:49,223 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2019-10-22 08:54:49,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2019-10-22 08:54:49,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 917 transitions. [2019-10-22 08:54:49,235 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:49,235 INFO L688 BuchiCegarLoop]: Abstraction has 606 states and 917 transitions. [2019-10-22 08:54:49,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 917 transitions. [2019-10-22 08:54:49,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2019-10-22 08:54:49,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 606 states. [2019-10-22 08:54:49,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 917 transitions. [2019-10-22 08:54:49,283 INFO L711 BuchiCegarLoop]: Abstraction has 606 states and 917 transitions. [2019-10-22 08:54:49,283 INFO L591 BuchiCegarLoop]: Abstraction has 606 states and 917 transitions. [2019-10-22 08:54:49,284 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-10-22 08:54:49,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 917 transitions. [2019-10-22 08:54:49,287 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:49,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:49,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:49,290 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:49,290 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:49,291 INFO L791 eck$LassoCheckResult]: Stem: 1742#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1641#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1642#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1329#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 1330#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1432#L456-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1433#L461-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1331#L466-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1332#L471-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1591#L476-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1592#L481-1 assume !(0 == ~M_E~0); 1758#L660-1 assume !(0 == ~T1_E~0); 1235#L665-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1236#L670-1 assume !(0 == ~T3_E~0); 1340#L675-1 assume !(0 == ~T4_E~0); 1341#L680-1 assume !(0 == ~T5_E~0); 1600#L685-1 assume !(0 == ~T6_E~0); 1601#L690-1 assume !(0 == ~E_1~0); 1490#L695-1 assume !(0 == ~E_2~0); 1491#L700-1 assume !(0 == ~E_3~0); 1727#L705-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1404#L710-1 assume !(0 == ~E_5~0); 1405#L715-1 assume !(0 == ~E_6~0); 1271#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1272#L310 assume 1 == ~m_pc~0; 1457#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1452#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1453#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1575#L815 assume !(0 != activate_threads_~tmp~1); 1723#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1645#L329 assume !(1 == ~t1_pc~0); 1646#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 1643#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1644#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1756#L823 assume !(0 != activate_threads_~tmp___0~0); 1824#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1806#L348 assume 1 == ~t2_pc~0; 1807#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1804#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1805#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1412#L831 assume !(0 != activate_threads_~tmp___1~0); 1399#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1336#L367 assume 1 == ~t3_pc~0; 1337#L368 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1305#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1335#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1435#L839 assume !(0 != activate_threads_~tmp___2~0); 1607#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1533#L386 assume !(1 == ~t4_pc~0); 1444#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 1443#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1440#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1441#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1761#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1762#L405 assume 1 == ~t5_pc~0; 1687#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1688#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1685#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1686#L855 assume !(0 != activate_threads_~tmp___4~0); 1768#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1380#L424 assume !(1 == ~t6_pc~0); 1381#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 1376#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1377#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1291#L863 assume !(0 != activate_threads_~tmp___5~0); 1258#L863-2 assume !(1 == ~M_E~0); 1259#L733-1 assume !(1 == ~T1_E~0); 1725#L738-1 assume !(1 == ~T2_E~0); 1402#L743-1 assume !(1 == ~T3_E~0); 1403#L748-1 assume !(1 == ~T4_E~0); 1266#L753-1 assume !(1 == ~T5_E~0); 1267#L758-1 assume !(1 == ~T6_E~0); 1350#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1351#L768-1 assume !(1 == ~E_2~0); 1595#L773-1 assume !(1 == ~E_3~0); 1596#L778-1 assume !(1 == ~E_4~0); 1481#L783-1 assume !(1 == ~E_5~0); 1482#L788-1 assume !(1 == ~E_6~0); 1512#L1014-1 [2019-10-22 08:54:49,291 INFO L793 eck$LassoCheckResult]: Loop: 1512#L1014-1 assume !false; 1513#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1240#L635 assume !false; 1583#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1584#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1315#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1312#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1313#L546 assume !(0 != eval_~tmp~0); 1728#L650 start_simulation_~kernel_st~0 := 2; 1333#L444-1 start_simulation_~kernel_st~0 := 3; 1334#L660-2 assume !(0 == ~M_E~0); 1759#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1253#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1254#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1342#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1343#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1603#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1604#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1476#L695-3 assume !(0 == ~E_2~0); 1477#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1539#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1396#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1397#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1242#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1243#L310-21 assume !(1 == ~m_pc~0); 1568#L310-23 is_master_triggered_~__retres1~0 := 0; 1567#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1565#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1527#L815-21 assume !(0 != activate_threads_~tmp~1); 1505#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1506#L329-21 assume 1 == ~t1_pc~0; 1733#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1631#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1632#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1707#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1708#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1710#L348-21 assume 1 == ~t2_pc~0; 1828#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1798#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1799#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1369#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1370#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1269#L367-21 assume !(1 == ~t3_pc~0); 1237#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 1238#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1296#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1413#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1557#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1485#L386-21 assume !(1 == ~t4_pc~0); 1486#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 1492#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1524#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1614#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1735#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1699#L405-21 assume !(1 == ~t5_pc~0); 1680#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 1679#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1676#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1677#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1827#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1814#L424-21 assume 1 == ~t6_pc~0; 1788#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1364#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1365#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1429#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1415#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1416#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1729#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1392#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1393#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1233#L753-3 assume !(1 == ~T5_E~0); 1234#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1338#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1339#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1598#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1599#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1488#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1489#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1726#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1683#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1320#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1317#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1318#L1033 assume !(0 == start_simulation_~tmp~3); 1286#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1684#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1327#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1324#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 1325#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1275#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 1276#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1406#L1046 assume !(0 != start_simulation_~tmp___0~1); 1512#L1014-1 [2019-10-22 08:54:49,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:49,292 INFO L82 PathProgramCache]: Analyzing trace with hash -527043775, now seen corresponding path program 1 times [2019-10-22 08:54:49,292 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:49,292 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144613737] [2019-10-22 08:54:49,293 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,293 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,293 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:49,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:49,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:49,336 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144613737] [2019-10-22 08:54:49,336 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:49,337 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:49,337 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100359966] [2019-10-22 08:54:49,337 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:49,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:49,338 INFO L82 PathProgramCache]: Analyzing trace with hash -498972221, now seen corresponding path program 1 times [2019-10-22 08:54:49,338 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:49,338 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536933106] [2019-10-22 08:54:49,338 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,339 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,339 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:49,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:49,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:49,421 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536933106] [2019-10-22 08:54:49,422 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:49,422 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:49,422 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79063346] [2019-10-22 08:54:49,422 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:49,423 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:49,423 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:49,423 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:49,423 INFO L87 Difference]: Start difference. First operand 606 states and 917 transitions. cyclomatic complexity: 312 Second operand 3 states. [2019-10-22 08:54:49,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:49,442 INFO L93 Difference]: Finished difference Result 606 states and 916 transitions. [2019-10-22 08:54:49,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:49,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 916 transitions. [2019-10-22 08:54:49,453 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:49,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 916 transitions. [2019-10-22 08:54:49,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2019-10-22 08:54:49,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2019-10-22 08:54:49,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 916 transitions. [2019-10-22 08:54:49,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:49,463 INFO L688 BuchiCegarLoop]: Abstraction has 606 states and 916 transitions. [2019-10-22 08:54:49,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 916 transitions. [2019-10-22 08:54:49,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2019-10-22 08:54:49,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 606 states. [2019-10-22 08:54:49,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 916 transitions. [2019-10-22 08:54:49,484 INFO L711 BuchiCegarLoop]: Abstraction has 606 states and 916 transitions. [2019-10-22 08:54:49,484 INFO L591 BuchiCegarLoop]: Abstraction has 606 states and 916 transitions. [2019-10-22 08:54:49,484 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-10-22 08:54:49,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 916 transitions. [2019-10-22 08:54:49,488 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:49,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:49,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:49,490 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:49,490 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:49,490 INFO L791 eck$LassoCheckResult]: Stem: 2962#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 2860#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2861#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2548#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 2549#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2651#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2652#L461-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2550#L466-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2551#L471-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2810#L476-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2811#L481-1 assume !(0 == ~M_E~0); 2977#L660-1 assume !(0 == ~T1_E~0); 2456#L665-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2457#L670-1 assume !(0 == ~T3_E~0); 2559#L675-1 assume !(0 == ~T4_E~0); 2560#L680-1 assume !(0 == ~T5_E~0); 2819#L685-1 assume !(0 == ~T6_E~0); 2820#L690-1 assume !(0 == ~E_1~0); 2709#L695-1 assume !(0 == ~E_2~0); 2710#L700-1 assume !(0 == ~E_3~0); 2946#L705-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2623#L710-1 assume !(0 == ~E_5~0); 2624#L715-1 assume !(0 == ~E_6~0); 2490#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2491#L310 assume 1 == ~m_pc~0; 2676#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2674#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2675#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2794#L815 assume !(0 != activate_threads_~tmp~1); 2942#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2864#L329 assume !(1 == ~t1_pc~0); 2865#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 2862#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2863#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2975#L823 assume !(0 != activate_threads_~tmp___0~0); 3043#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3025#L348 assume 1 == ~t2_pc~0; 3026#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3023#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3024#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2631#L831 assume !(0 != activate_threads_~tmp___1~0); 2618#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2555#L367 assume 1 == ~t3_pc~0; 2556#L368 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2524#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2554#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2654#L839 assume !(0 != activate_threads_~tmp___2~0); 2826#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2752#L386 assume !(1 == ~t4_pc~0); 2663#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 2662#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2659#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2660#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2980#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2981#L405 assume 1 == ~t5_pc~0; 2906#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2907#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2904#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2905#L855 assume !(0 != activate_threads_~tmp___4~0); 2987#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2599#L424 assume !(1 == ~t6_pc~0); 2600#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 2597#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2598#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2510#L863 assume !(0 != activate_threads_~tmp___5~0); 2480#L863-2 assume !(1 == ~M_E~0); 2481#L733-1 assume !(1 == ~T1_E~0); 2944#L738-1 assume !(1 == ~T2_E~0); 2621#L743-1 assume !(1 == ~T3_E~0); 2622#L748-1 assume !(1 == ~T4_E~0); 2485#L753-1 assume !(1 == ~T5_E~0); 2486#L758-1 assume !(1 == ~T6_E~0); 2569#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2570#L768-1 assume !(1 == ~E_2~0); 2815#L773-1 assume !(1 == ~E_3~0); 2816#L778-1 assume !(1 == ~E_4~0); 2702#L783-1 assume !(1 == ~E_5~0); 2703#L788-1 assume !(1 == ~E_6~0); 2731#L1014-1 [2019-10-22 08:54:49,491 INFO L793 eck$LassoCheckResult]: Loop: 2731#L1014-1 assume !false; 2732#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 2461#L635 assume !false; 2803#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2804#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2534#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2531#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2532#L546 assume !(0 != eval_~tmp~0); 2947#L650 start_simulation_~kernel_st~0 := 2; 2552#L444-1 start_simulation_~kernel_st~0 := 3; 2553#L660-2 assume !(0 == ~M_E~0); 2978#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2472#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2473#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2561#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2562#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2822#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2823#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2695#L695-3 assume !(0 == ~E_2~0); 2696#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2758#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2615#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2616#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2458#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2459#L310-21 assume 1 == ~m_pc~0; 2785#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2786#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2784#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2746#L815-21 assume !(0 != activate_threads_~tmp~1); 2724#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2725#L329-21 assume 1 == ~t1_pc~0; 2952#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2850#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2851#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2926#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2927#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2929#L348-21 assume 1 == ~t2_pc~0; 3047#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3017#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3018#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2588#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2589#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2487#L367-21 assume !(1 == ~t3_pc~0); 2454#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 2455#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2515#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2632#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2776#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2704#L386-21 assume !(1 == ~t4_pc~0); 2705#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 2711#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2743#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2833#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2954#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2918#L405-21 assume 1 == ~t5_pc~0; 2899#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2900#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2895#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2896#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3046#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3033#L424-21 assume 1 == ~t6_pc~0; 3008#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2583#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2584#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2648#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2634#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2635#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2948#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2611#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2612#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2452#L753-3 assume !(1 == ~T5_E~0); 2453#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2557#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2558#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2817#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2818#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2707#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2708#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2945#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2902#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2539#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2536#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2537#L1033 assume !(0 == start_simulation_~tmp~3); 2505#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2903#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2546#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2543#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 2544#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2497#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 2498#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2625#L1046 assume !(0 != start_simulation_~tmp___0~1); 2731#L1014-1 [2019-10-22 08:54:49,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:49,491 INFO L82 PathProgramCache]: Analyzing trace with hash 1383998783, now seen corresponding path program 1 times [2019-10-22 08:54:49,491 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:49,491 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228489279] [2019-10-22 08:54:49,492 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,492 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,492 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:49,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:49,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:49,521 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228489279] [2019-10-22 08:54:49,521 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:49,521 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:49,521 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425343180] [2019-10-22 08:54:49,522 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:49,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:49,522 INFO L82 PathProgramCache]: Analyzing trace with hash 533240833, now seen corresponding path program 1 times [2019-10-22 08:54:49,522 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:49,522 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135746341] [2019-10-22 08:54:49,522 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,523 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,523 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:49,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:49,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:49,600 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135746341] [2019-10-22 08:54:49,600 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:49,600 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:49,600 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370947706] [2019-10-22 08:54:49,601 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:49,601 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:49,601 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:49,601 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:49,602 INFO L87 Difference]: Start difference. First operand 606 states and 916 transitions. cyclomatic complexity: 311 Second operand 3 states. [2019-10-22 08:54:49,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:49,615 INFO L93 Difference]: Finished difference Result 606 states and 915 transitions. [2019-10-22 08:54:49,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:49,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 915 transitions. [2019-10-22 08:54:49,619 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:49,622 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 915 transitions. [2019-10-22 08:54:49,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2019-10-22 08:54:49,623 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2019-10-22 08:54:49,623 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 915 transitions. [2019-10-22 08:54:49,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:49,625 INFO L688 BuchiCegarLoop]: Abstraction has 606 states and 915 transitions. [2019-10-22 08:54:49,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 915 transitions. [2019-10-22 08:54:49,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2019-10-22 08:54:49,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 606 states. [2019-10-22 08:54:49,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 915 transitions. [2019-10-22 08:54:49,636 INFO L711 BuchiCegarLoop]: Abstraction has 606 states and 915 transitions. [2019-10-22 08:54:49,636 INFO L591 BuchiCegarLoop]: Abstraction has 606 states and 915 transitions. [2019-10-22 08:54:49,636 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-10-22 08:54:49,636 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 915 transitions. [2019-10-22 08:54:49,640 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:49,640 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:49,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:49,642 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:49,642 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:49,643 INFO L791 eck$LassoCheckResult]: Stem: 4181#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 4081#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4082#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3767#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 3768#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3870#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3871#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3769#L466-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3770#L471-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4029#L476-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4030#L481-1 assume !(0 == ~M_E~0); 4196#L660-1 assume !(0 == ~T1_E~0); 3673#L665-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3674#L670-1 assume !(0 == ~T3_E~0); 3778#L675-1 assume !(0 == ~T4_E~0); 3779#L680-1 assume !(0 == ~T5_E~0); 4038#L685-1 assume !(0 == ~T6_E~0); 4039#L690-1 assume !(0 == ~E_1~0); 3928#L695-1 assume !(0 == ~E_2~0); 3929#L700-1 assume !(0 == ~E_3~0); 4165#L705-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3842#L710-1 assume !(0 == ~E_5~0); 3843#L715-1 assume !(0 == ~E_6~0); 3709#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3710#L310 assume 1 == ~m_pc~0; 3895#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3890#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3891#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4013#L815 assume !(0 != activate_threads_~tmp~1); 4161#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4083#L329 assume !(1 == ~t1_pc~0); 4084#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 4076#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4077#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4194#L823 assume !(0 != activate_threads_~tmp___0~0); 4262#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4244#L348 assume 1 == ~t2_pc~0; 4245#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4242#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4243#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3850#L831 assume !(0 != activate_threads_~tmp___1~0); 3837#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3774#L367 assume 1 == ~t3_pc~0; 3775#L368 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3743#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3773#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3873#L839 assume !(0 != activate_threads_~tmp___2~0); 4045#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3971#L386 assume !(1 == ~t4_pc~0); 3882#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 3881#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3878#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3879#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4199#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4200#L405 assume 1 == ~t5_pc~0; 4125#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4126#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4123#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4124#L855 assume !(0 != activate_threads_~tmp___4~0); 4206#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3818#L424 assume !(1 == ~t6_pc~0); 3819#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 3814#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3815#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3727#L863 assume !(0 != activate_threads_~tmp___5~0); 3696#L863-2 assume !(1 == ~M_E~0); 3697#L733-1 assume !(1 == ~T1_E~0); 4163#L738-1 assume !(1 == ~T2_E~0); 3840#L743-1 assume !(1 == ~T3_E~0); 3841#L748-1 assume !(1 == ~T4_E~0); 3704#L753-1 assume !(1 == ~T5_E~0); 3705#L758-1 assume !(1 == ~T6_E~0); 3788#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3789#L768-1 assume !(1 == ~E_2~0); 4033#L773-1 assume !(1 == ~E_3~0); 4034#L778-1 assume !(1 == ~E_4~0); 3919#L783-1 assume !(1 == ~E_5~0); 3920#L788-1 assume !(1 == ~E_6~0); 3950#L1014-1 [2019-10-22 08:54:49,643 INFO L793 eck$LassoCheckResult]: Loop: 3950#L1014-1 assume !false; 3951#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 3678#L635 assume !false; 4020#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4021#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 3753#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3750#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3751#L546 assume !(0 != eval_~tmp~0); 4166#L650 start_simulation_~kernel_st~0 := 2; 3771#L444-1 start_simulation_~kernel_st~0 := 3; 3772#L660-2 assume !(0 == ~M_E~0); 4197#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3689#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3690#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3780#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3781#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4041#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4042#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3914#L695-3 assume !(0 == ~E_2~0); 3915#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3977#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3834#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3835#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3680#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3681#L310-21 assume 1 == ~m_pc~0; 4004#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4005#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4003#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3965#L815-21 assume !(0 != activate_threads_~tmp~1); 3943#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3944#L329-21 assume 1 == ~t1_pc~0; 4171#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4069#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4070#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4145#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4146#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4148#L348-21 assume 1 == ~t2_pc~0; 4266#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4236#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4237#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3807#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3808#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3706#L367-21 assume 1 == ~t3_pc~0; 3707#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3676#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3734#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3851#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3998#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3923#L386-21 assume !(1 == ~t4_pc~0); 3924#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 3930#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3962#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4052#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4173#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4137#L405-21 assume 1 == ~t5_pc~0; 4118#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4119#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4114#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4115#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4265#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4252#L424-21 assume 1 == ~t6_pc~0; 4227#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3802#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3803#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3867#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 3853#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3854#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4167#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3830#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3831#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3671#L753-3 assume !(1 == ~T5_E~0); 3672#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3776#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3777#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4036#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4037#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3926#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3927#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4164#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4121#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 3760#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3755#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3756#L1033 assume !(0 == start_simulation_~tmp~3); 3724#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4122#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 3765#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3762#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 3763#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3716#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 3717#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 3844#L1046 assume !(0 != start_simulation_~tmp___0~1); 3950#L1014-1 [2019-10-22 08:54:49,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:49,644 INFO L82 PathProgramCache]: Analyzing trace with hash 1307097985, now seen corresponding path program 1 times [2019-10-22 08:54:49,644 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:49,644 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453668521] [2019-10-22 08:54:49,644 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,645 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,645 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:49,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:49,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:49,698 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1453668521] [2019-10-22 08:54:49,698 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:49,698 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:49,698 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095766917] [2019-10-22 08:54:49,699 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:49,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:49,699 INFO L82 PathProgramCache]: Analyzing trace with hash -934962496, now seen corresponding path program 1 times [2019-10-22 08:54:49,699 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:49,700 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291829188] [2019-10-22 08:54:49,700 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,700 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,700 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:49,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:49,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:49,793 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291829188] [2019-10-22 08:54:49,796 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:49,796 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:49,796 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327369907] [2019-10-22 08:54:49,797 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:49,797 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:49,797 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:49,797 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:49,797 INFO L87 Difference]: Start difference. First operand 606 states and 915 transitions. cyclomatic complexity: 310 Second operand 3 states. [2019-10-22 08:54:49,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:49,811 INFO L93 Difference]: Finished difference Result 606 states and 914 transitions. [2019-10-22 08:54:49,811 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:49,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 914 transitions. [2019-10-22 08:54:49,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:49,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 914 transitions. [2019-10-22 08:54:49,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2019-10-22 08:54:49,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2019-10-22 08:54:49,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 914 transitions. [2019-10-22 08:54:49,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:49,822 INFO L688 BuchiCegarLoop]: Abstraction has 606 states and 914 transitions. [2019-10-22 08:54:49,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 914 transitions. [2019-10-22 08:54:49,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2019-10-22 08:54:49,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 606 states. [2019-10-22 08:54:49,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 914 transitions. [2019-10-22 08:54:49,833 INFO L711 BuchiCegarLoop]: Abstraction has 606 states and 914 transitions. [2019-10-22 08:54:49,833 INFO L591 BuchiCegarLoop]: Abstraction has 606 states and 914 transitions. [2019-10-22 08:54:49,833 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-10-22 08:54:49,840 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 914 transitions. [2019-10-22 08:54:49,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:49,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:49,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:49,844 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:49,844 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:49,845 INFO L791 eck$LassoCheckResult]: Stem: 5399#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 5295#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5296#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4983#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 4984#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5089#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5090#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4988#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4989#L471-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5248#L476-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5249#L481-1 assume !(0 == ~M_E~0); 5415#L660-1 assume !(0 == ~T1_E~0); 4892#L665-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4893#L670-1 assume !(0 == ~T3_E~0); 4997#L675-1 assume !(0 == ~T4_E~0); 4998#L680-1 assume !(0 == ~T5_E~0); 5257#L685-1 assume !(0 == ~T6_E~0); 5258#L690-1 assume !(0 == ~E_1~0); 5147#L695-1 assume !(0 == ~E_2~0); 5148#L700-1 assume !(0 == ~E_3~0); 5384#L705-1 assume 0 == ~E_4~0;~E_4~0 := 1; 5061#L710-1 assume !(0 == ~E_5~0); 5062#L715-1 assume !(0 == ~E_6~0); 4928#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4929#L310 assume 1 == ~m_pc~0; 5114#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5109#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5110#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5232#L815 assume !(0 != activate_threads_~tmp~1); 5380#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5302#L329 assume !(1 == ~t1_pc~0); 5303#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 5297#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5298#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5413#L823 assume !(0 != activate_threads_~tmp___0~0); 5481#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5463#L348 assume 1 == ~t2_pc~0; 5464#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5461#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5462#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5069#L831 assume !(0 != activate_threads_~tmp___1~0); 5056#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4993#L367 assume 1 == ~t3_pc~0; 4994#L368 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4962#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4992#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5092#L839 assume !(0 != activate_threads_~tmp___2~0); 5264#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5190#L386 assume !(1 == ~t4_pc~0); 5101#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 5100#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5097#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5098#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5418#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5419#L405 assume 1 == ~t5_pc~0; 5344#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5345#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5342#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5343#L855 assume !(0 != activate_threads_~tmp___4~0); 5425#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5037#L424 assume !(1 == ~t6_pc~0); 5038#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 5033#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5034#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4946#L863 assume !(0 != activate_threads_~tmp___5~0); 4915#L863-2 assume !(1 == ~M_E~0); 4916#L733-1 assume !(1 == ~T1_E~0); 5382#L738-1 assume !(1 == ~T2_E~0); 5059#L743-1 assume !(1 == ~T3_E~0); 5060#L748-1 assume !(1 == ~T4_E~0); 4923#L753-1 assume !(1 == ~T5_E~0); 4924#L758-1 assume !(1 == ~T6_E~0); 5007#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5008#L768-1 assume !(1 == ~E_2~0); 5252#L773-1 assume !(1 == ~E_3~0); 5253#L778-1 assume !(1 == ~E_4~0); 5138#L783-1 assume !(1 == ~E_5~0); 5139#L788-1 assume !(1 == ~E_6~0); 5169#L1014-1 [2019-10-22 08:54:49,845 INFO L793 eck$LassoCheckResult]: Loop: 5169#L1014-1 assume !false; 5170#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 4897#L635 assume !false; 5239#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5240#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4972#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4969#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4970#L546 assume !(0 != eval_~tmp~0); 5385#L650 start_simulation_~kernel_st~0 := 2; 4990#L444-1 start_simulation_~kernel_st~0 := 3; 4991#L660-2 assume !(0 == ~M_E~0); 5416#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4908#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4909#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4999#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5000#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5260#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5261#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5133#L695-3 assume !(0 == ~E_2~0); 5134#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5196#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5053#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5054#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4899#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4900#L310-21 assume 1 == ~m_pc~0; 5223#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5224#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5222#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5184#L815-21 assume !(0 != activate_threads_~tmp~1); 5162#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5163#L329-21 assume 1 == ~t1_pc~0; 5390#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5288#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5289#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5364#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5365#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5367#L348-21 assume 1 == ~t2_pc~0; 5485#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5455#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5456#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5026#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5027#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4925#L367-21 assume 1 == ~t3_pc~0; 4926#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4895#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4953#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5070#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5217#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5142#L386-21 assume !(1 == ~t4_pc~0); 5143#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 5149#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5181#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5271#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5392#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5356#L405-21 assume 1 == ~t5_pc~0; 5337#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5338#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5333#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5334#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5484#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5471#L424-21 assume 1 == ~t6_pc~0; 5446#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5021#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5022#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5086#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5072#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5073#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5386#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5049#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5050#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4890#L753-3 assume !(1 == ~T5_E~0); 4891#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4995#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4996#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5255#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5256#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5145#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5146#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5383#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5340#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4979#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4974#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4975#L1033 assume !(0 == start_simulation_~tmp~3); 4943#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5341#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4986#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4981#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 4982#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4935#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 4936#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 5063#L1046 assume !(0 != start_simulation_~tmp___0~1); 5169#L1014-1 [2019-10-22 08:54:49,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:49,847 INFO L82 PathProgramCache]: Analyzing trace with hash -2020518657, now seen corresponding path program 1 times [2019-10-22 08:54:49,847 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:49,847 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915081976] [2019-10-22 08:54:49,847 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,847 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,847 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:49,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:49,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:49,905 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915081976] [2019-10-22 08:54:49,905 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:49,905 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:49,905 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180714341] [2019-10-22 08:54:49,905 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:49,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:49,908 INFO L82 PathProgramCache]: Analyzing trace with hash -934962496, now seen corresponding path program 2 times [2019-10-22 08:54:49,909 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:49,909 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539368677] [2019-10-22 08:54:49,909 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,909 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,909 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:49,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:49,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:49,963 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [539368677] [2019-10-22 08:54:49,963 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:49,964 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:49,964 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1086312770] [2019-10-22 08:54:49,964 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:49,964 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:49,964 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:49,965 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:49,965 INFO L87 Difference]: Start difference. First operand 606 states and 914 transitions. cyclomatic complexity: 309 Second operand 3 states. [2019-10-22 08:54:49,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:49,975 INFO L93 Difference]: Finished difference Result 606 states and 913 transitions. [2019-10-22 08:54:49,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:49,976 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 913 transitions. [2019-10-22 08:54:49,979 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:49,981 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 913 transitions. [2019-10-22 08:54:49,981 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2019-10-22 08:54:49,982 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2019-10-22 08:54:49,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 913 transitions. [2019-10-22 08:54:49,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:49,983 INFO L688 BuchiCegarLoop]: Abstraction has 606 states and 913 transitions. [2019-10-22 08:54:49,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 913 transitions. [2019-10-22 08:54:49,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2019-10-22 08:54:49,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 606 states. [2019-10-22 08:54:49,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 913 transitions. [2019-10-22 08:54:49,992 INFO L711 BuchiCegarLoop]: Abstraction has 606 states and 913 transitions. [2019-10-22 08:54:49,992 INFO L591 BuchiCegarLoop]: Abstraction has 606 states and 913 transitions. [2019-10-22 08:54:49,992 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-10-22 08:54:49,992 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 913 transitions. [2019-10-22 08:54:49,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:49,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:49,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:49,996 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:49,996 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:49,996 INFO L791 eck$LassoCheckResult]: Stem: 6618#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 6514#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6515#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6202#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 6203#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6308#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6309#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6207#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6208#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6467#L476-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6468#L481-1 assume !(0 == ~M_E~0); 6634#L660-1 assume !(0 == ~T1_E~0); 6111#L665-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6112#L670-1 assume !(0 == ~T3_E~0); 6216#L675-1 assume !(0 == ~T4_E~0); 6217#L680-1 assume !(0 == ~T5_E~0); 6476#L685-1 assume !(0 == ~T6_E~0); 6477#L690-1 assume !(0 == ~E_1~0); 6366#L695-1 assume !(0 == ~E_2~0); 6367#L700-1 assume !(0 == ~E_3~0); 6603#L705-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6280#L710-1 assume !(0 == ~E_5~0); 6281#L715-1 assume !(0 == ~E_6~0); 6147#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6148#L310 assume 1 == ~m_pc~0; 6333#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6328#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6329#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6451#L815 assume !(0 != activate_threads_~tmp~1); 6599#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6521#L329 assume !(1 == ~t1_pc~0); 6522#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 6516#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6517#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6632#L823 assume !(0 != activate_threads_~tmp___0~0); 6700#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6682#L348 assume 1 == ~t2_pc~0; 6683#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6680#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6681#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6288#L831 assume !(0 != activate_threads_~tmp___1~0); 6275#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6212#L367 assume 1 == ~t3_pc~0; 6213#L368 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6181#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6211#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6311#L839 assume !(0 != activate_threads_~tmp___2~0); 6483#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6409#L386 assume !(1 == ~t4_pc~0); 6320#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 6319#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6316#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6317#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6637#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6638#L405 assume 1 == ~t5_pc~0; 6563#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6564#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6561#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6562#L855 assume !(0 != activate_threads_~tmp___4~0); 6644#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6256#L424 assume !(1 == ~t6_pc~0); 6257#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 6252#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6253#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6165#L863 assume !(0 != activate_threads_~tmp___5~0); 6134#L863-2 assume !(1 == ~M_E~0); 6135#L733-1 assume !(1 == ~T1_E~0); 6601#L738-1 assume !(1 == ~T2_E~0); 6278#L743-1 assume !(1 == ~T3_E~0); 6279#L748-1 assume !(1 == ~T4_E~0); 6142#L753-1 assume !(1 == ~T5_E~0); 6143#L758-1 assume !(1 == ~T6_E~0); 6226#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6227#L768-1 assume !(1 == ~E_2~0); 6471#L773-1 assume !(1 == ~E_3~0); 6472#L778-1 assume !(1 == ~E_4~0); 6357#L783-1 assume !(1 == ~E_5~0); 6358#L788-1 assume !(1 == ~E_6~0); 6388#L1014-1 [2019-10-22 08:54:49,996 INFO L793 eck$LassoCheckResult]: Loop: 6388#L1014-1 assume !false; 6389#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 6116#L635 assume !false; 6458#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6459#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6191#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6188#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6189#L546 assume !(0 != eval_~tmp~0); 6604#L650 start_simulation_~kernel_st~0 := 2; 6209#L444-1 start_simulation_~kernel_st~0 := 3; 6210#L660-2 assume !(0 == ~M_E~0); 6635#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6127#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6128#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6218#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6219#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6479#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6480#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6352#L695-3 assume !(0 == ~E_2~0); 6353#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6415#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6272#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6273#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6118#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6119#L310-21 assume 1 == ~m_pc~0; 6442#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6443#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6441#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6403#L815-21 assume !(0 != activate_threads_~tmp~1); 6381#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6382#L329-21 assume 1 == ~t1_pc~0; 6609#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6507#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6508#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6583#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6584#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6586#L348-21 assume 1 == ~t2_pc~0; 6704#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6674#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6675#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6245#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6246#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6144#L367-21 assume 1 == ~t3_pc~0; 6145#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6114#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6172#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6289#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6436#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6361#L386-21 assume !(1 == ~t4_pc~0); 6362#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 6368#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6400#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6490#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6611#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6575#L405-21 assume 1 == ~t5_pc~0; 6556#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6557#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6552#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6553#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6703#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6690#L424-21 assume 1 == ~t6_pc~0; 6665#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6240#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6241#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6305#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6291#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 6292#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6605#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6268#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6269#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6109#L753-3 assume !(1 == ~T5_E~0); 6110#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6214#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6215#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6474#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6475#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6364#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6365#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6602#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6559#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6198#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6193#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 6194#L1033 assume !(0 == start_simulation_~tmp~3); 6162#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6560#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6205#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6200#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 6201#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6154#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 6155#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 6282#L1046 assume !(0 != start_simulation_~tmp___0~1); 6388#L1014-1 [2019-10-22 08:54:49,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:49,997 INFO L82 PathProgramCache]: Analyzing trace with hash 365990849, now seen corresponding path program 1 times [2019-10-22 08:54:49,997 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:49,997 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690062501] [2019-10-22 08:54:49,997 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,997 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:49,997 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,025 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690062501] [2019-10-22 08:54:50,025 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,025 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:50,026 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [813208128] [2019-10-22 08:54:50,026 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:50,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,026 INFO L82 PathProgramCache]: Analyzing trace with hash -934962496, now seen corresponding path program 3 times [2019-10-22 08:54:50,026 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,026 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521073453] [2019-10-22 08:54:50,027 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,027 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,027 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,062 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1521073453] [2019-10-22 08:54:50,062 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,062 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:50,062 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547631177] [2019-10-22 08:54:50,063 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:50,063 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:50,063 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:50,063 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:50,063 INFO L87 Difference]: Start difference. First operand 606 states and 913 transitions. cyclomatic complexity: 308 Second operand 3 states. [2019-10-22 08:54:50,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:50,074 INFO L93 Difference]: Finished difference Result 606 states and 912 transitions. [2019-10-22 08:54:50,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:50,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 912 transitions. [2019-10-22 08:54:50,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:50,079 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 912 transitions. [2019-10-22 08:54:50,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2019-10-22 08:54:50,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2019-10-22 08:54:50,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 912 transitions. [2019-10-22 08:54:50,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:50,081 INFO L688 BuchiCegarLoop]: Abstraction has 606 states and 912 transitions. [2019-10-22 08:54:50,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 912 transitions. [2019-10-22 08:54:50,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2019-10-22 08:54:50,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 606 states. [2019-10-22 08:54:50,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 912 transitions. [2019-10-22 08:54:50,089 INFO L711 BuchiCegarLoop]: Abstraction has 606 states and 912 transitions. [2019-10-22 08:54:50,089 INFO L591 BuchiCegarLoop]: Abstraction has 606 states and 912 transitions. [2019-10-22 08:54:50,090 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-10-22 08:54:50,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 912 transitions. [2019-10-22 08:54:50,092 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:50,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:50,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:50,093 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,093 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,093 INFO L791 eck$LassoCheckResult]: Stem: 7837#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 7733#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7734#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7424#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 7425#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7527#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7528#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7426#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7427#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7686#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7687#L481-1 assume !(0 == ~M_E~0); 7853#L660-1 assume !(0 == ~T1_E~0); 7330#L665-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7331#L670-1 assume !(0 == ~T3_E~0); 7435#L675-1 assume !(0 == ~T4_E~0); 7436#L680-1 assume !(0 == ~T5_E~0); 7695#L685-1 assume !(0 == ~T6_E~0); 7696#L690-1 assume !(0 == ~E_1~0); 7585#L695-1 assume !(0 == ~E_2~0); 7586#L700-1 assume !(0 == ~E_3~0); 7822#L705-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7499#L710-1 assume !(0 == ~E_5~0); 7500#L715-1 assume !(0 == ~E_6~0); 7366#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7367#L310 assume 1 == ~m_pc~0; 7552#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 7547#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7548#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7670#L815 assume !(0 != activate_threads_~tmp~1); 7818#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7740#L329 assume !(1 == ~t1_pc~0); 7741#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 7735#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7736#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7851#L823 assume !(0 != activate_threads_~tmp___0~0); 7919#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7901#L348 assume 1 == ~t2_pc~0; 7902#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7899#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7900#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7507#L831 assume !(0 != activate_threads_~tmp___1~0); 7494#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7431#L367 assume 1 == ~t3_pc~0; 7432#L368 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7400#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7430#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7530#L839 assume !(0 != activate_threads_~tmp___2~0); 7702#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7628#L386 assume !(1 == ~t4_pc~0); 7539#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 7538#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7535#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7536#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7856#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7857#L405 assume 1 == ~t5_pc~0; 7782#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7783#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7780#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7781#L855 assume !(0 != activate_threads_~tmp___4~0); 7863#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7475#L424 assume !(1 == ~t6_pc~0); 7476#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 7471#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7472#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7386#L863 assume !(0 != activate_threads_~tmp___5~0); 7353#L863-2 assume !(1 == ~M_E~0); 7354#L733-1 assume !(1 == ~T1_E~0); 7820#L738-1 assume !(1 == ~T2_E~0); 7497#L743-1 assume !(1 == ~T3_E~0); 7498#L748-1 assume !(1 == ~T4_E~0); 7361#L753-1 assume !(1 == ~T5_E~0); 7362#L758-1 assume !(1 == ~T6_E~0); 7445#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7446#L768-1 assume !(1 == ~E_2~0); 7690#L773-1 assume !(1 == ~E_3~0); 7691#L778-1 assume !(1 == ~E_4~0); 7576#L783-1 assume !(1 == ~E_5~0); 7577#L788-1 assume !(1 == ~E_6~0); 7607#L1014-1 [2019-10-22 08:54:50,095 INFO L793 eck$LassoCheckResult]: Loop: 7607#L1014-1 assume !false; 7608#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 7335#L635 assume !false; 7678#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7679#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7410#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7407#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 7408#L546 assume !(0 != eval_~tmp~0); 7823#L650 start_simulation_~kernel_st~0 := 2; 7428#L444-1 start_simulation_~kernel_st~0 := 3; 7429#L660-2 assume !(0 == ~M_E~0); 7854#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7348#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7349#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7437#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7438#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7698#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7699#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7571#L695-3 assume !(0 == ~E_2~0); 7572#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7634#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7491#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7492#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7337#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7338#L310-21 assume 1 == ~m_pc~0; 7661#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 7662#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7660#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7622#L815-21 assume !(0 != activate_threads_~tmp~1); 7600#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7601#L329-21 assume 1 == ~t1_pc~0; 7828#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7726#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7727#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7802#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7803#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7805#L348-21 assume 1 == ~t2_pc~0; 7923#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7893#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7894#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7464#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7465#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7364#L367-21 assume !(1 == ~t3_pc~0); 7332#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 7333#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7391#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7508#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7655#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7580#L386-21 assume !(1 == ~t4_pc~0); 7581#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 7587#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7619#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7709#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7830#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7794#L405-21 assume 1 == ~t5_pc~0; 7773#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7774#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7771#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7772#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7922#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7909#L424-21 assume 1 == ~t6_pc~0; 7883#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7459#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7460#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7524#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 7510#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7511#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7824#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7487#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7488#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7328#L753-3 assume !(1 == ~T5_E~0); 7329#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7433#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7434#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7693#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7694#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7583#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7584#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7821#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7778#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7415#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7412#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7413#L1033 assume !(0 == start_simulation_~tmp~3); 7381#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7779#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7422#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7419#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 7420#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7370#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 7371#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 7501#L1046 assume !(0 != start_simulation_~tmp___0~1); 7607#L1014-1 [2019-10-22 08:54:50,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,096 INFO L82 PathProgramCache]: Analyzing trace with hash 858617023, now seen corresponding path program 1 times [2019-10-22 08:54:50,096 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,096 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078238567] [2019-10-22 08:54:50,096 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,096 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,096 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,132 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078238567] [2019-10-22 08:54:50,132 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,133 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:54:50,133 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046188905] [2019-10-22 08:54:50,133 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:50,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,133 INFO L82 PathProgramCache]: Analyzing trace with hash 533240833, now seen corresponding path program 2 times [2019-10-22 08:54:50,134 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,134 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856993206] [2019-10-22 08:54:50,134 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,134 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,134 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,168 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856993206] [2019-10-22 08:54:50,168 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,168 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:50,168 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635168437] [2019-10-22 08:54:50,169 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:50,169 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:50,169 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:50,169 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:50,169 INFO L87 Difference]: Start difference. First operand 606 states and 912 transitions. cyclomatic complexity: 307 Second operand 3 states. [2019-10-22 08:54:50,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:50,186 INFO L93 Difference]: Finished difference Result 606 states and 907 transitions. [2019-10-22 08:54:50,186 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:50,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 907 transitions. [2019-10-22 08:54:50,189 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:50,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 907 transitions. [2019-10-22 08:54:50,192 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2019-10-22 08:54:50,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2019-10-22 08:54:50,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 907 transitions. [2019-10-22 08:54:50,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:50,193 INFO L688 BuchiCegarLoop]: Abstraction has 606 states and 907 transitions. [2019-10-22 08:54:50,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 907 transitions. [2019-10-22 08:54:50,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2019-10-22 08:54:50,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 606 states. [2019-10-22 08:54:50,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 907 transitions. [2019-10-22 08:54:50,202 INFO L711 BuchiCegarLoop]: Abstraction has 606 states and 907 transitions. [2019-10-22 08:54:50,203 INFO L591 BuchiCegarLoop]: Abstraction has 606 states and 907 transitions. [2019-10-22 08:54:50,203 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-10-22 08:54:50,203 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 907 transitions. [2019-10-22 08:54:50,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:50,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:50,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:50,206 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,206 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,206 INFO L791 eck$LassoCheckResult]: Stem: 9056#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 8955#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8956#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8643#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 8644#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8746#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8747#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8645#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8646#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8905#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8906#L481-1 assume !(0 == ~M_E~0); 9072#L660-1 assume !(0 == ~T1_E~0); 8551#L665-1 assume !(0 == ~T2_E~0); 8552#L670-1 assume !(0 == ~T3_E~0); 8654#L675-1 assume !(0 == ~T4_E~0); 8655#L680-1 assume !(0 == ~T5_E~0); 8914#L685-1 assume !(0 == ~T6_E~0); 8915#L690-1 assume !(0 == ~E_1~0); 8804#L695-1 assume !(0 == ~E_2~0); 8805#L700-1 assume !(0 == ~E_3~0); 9041#L705-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8718#L710-1 assume !(0 == ~E_5~0); 8719#L715-1 assume !(0 == ~E_6~0); 8585#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8586#L310 assume 1 == ~m_pc~0; 8771#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8769#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8770#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8889#L815 assume !(0 != activate_threads_~tmp~1); 9037#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8959#L329 assume !(1 == ~t1_pc~0); 8960#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 8957#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8958#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9070#L823 assume !(0 != activate_threads_~tmp___0~0); 9138#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9120#L348 assume 1 == ~t2_pc~0; 9121#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9118#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9119#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8726#L831 assume !(0 != activate_threads_~tmp___1~0); 8713#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8650#L367 assume 1 == ~t3_pc~0; 8651#L368 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8619#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8649#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8749#L839 assume !(0 != activate_threads_~tmp___2~0); 8921#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8847#L386 assume !(1 == ~t4_pc~0); 8758#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 8757#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8754#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8755#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9075#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9076#L405 assume 1 == ~t5_pc~0; 9001#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9002#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8999#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9000#L855 assume !(0 != activate_threads_~tmp___4~0); 9082#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8694#L424 assume !(1 == ~t6_pc~0); 8695#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 8692#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8693#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8605#L863 assume !(0 != activate_threads_~tmp___5~0); 8575#L863-2 assume !(1 == ~M_E~0); 8576#L733-1 assume !(1 == ~T1_E~0); 9039#L738-1 assume !(1 == ~T2_E~0); 8716#L743-1 assume !(1 == ~T3_E~0); 8717#L748-1 assume !(1 == ~T4_E~0); 8580#L753-1 assume !(1 == ~T5_E~0); 8581#L758-1 assume !(1 == ~T6_E~0); 8664#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8665#L768-1 assume !(1 == ~E_2~0); 8910#L773-1 assume !(1 == ~E_3~0); 8911#L778-1 assume !(1 == ~E_4~0); 8797#L783-1 assume !(1 == ~E_5~0); 8798#L788-1 assume !(1 == ~E_6~0); 8826#L1014-1 [2019-10-22 08:54:50,207 INFO L793 eck$LassoCheckResult]: Loop: 8826#L1014-1 assume !false; 8827#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 8554#L635 assume !false; 8898#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8899#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8629#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8626#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 8627#L546 assume !(0 != eval_~tmp~0); 9042#L650 start_simulation_~kernel_st~0 := 2; 8647#L444-1 start_simulation_~kernel_st~0 := 3; 8648#L660-2 assume !(0 == ~M_E~0); 9073#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8567#L665-3 assume !(0 == ~T2_E~0); 8568#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8656#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8657#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8917#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8918#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8790#L695-3 assume !(0 == ~E_2~0); 8791#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8853#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8710#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8711#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8556#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8557#L310-21 assume 1 == ~m_pc~0; 8880#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8881#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8879#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8841#L815-21 assume !(0 != activate_threads_~tmp~1); 8819#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8820#L329-21 assume 1 == ~t1_pc~0; 9047#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8945#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8946#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9021#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9022#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9024#L348-21 assume 1 == ~t2_pc~0; 9142#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9112#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9113#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8683#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8684#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8582#L367-21 assume !(1 == ~t3_pc~0); 8549#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 8550#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8610#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8727#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8871#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8799#L386-21 assume !(1 == ~t4_pc~0); 8800#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 8806#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8838#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8928#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9049#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9013#L405-21 assume 1 == ~t5_pc~0; 8992#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8993#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8990#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8991#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9141#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9128#L424-21 assume !(1 == ~t6_pc~0); 9104#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 8678#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8679#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8743#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8729#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 8730#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9043#L738-3 assume !(1 == ~T2_E~0); 8706#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8707#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8547#L753-3 assume !(1 == ~T5_E~0); 8548#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8652#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8653#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8912#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8913#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8802#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8803#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9040#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8997#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8634#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8631#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 8632#L1033 assume !(0 == start_simulation_~tmp~3); 8600#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8998#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8641#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8638#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 8639#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8592#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 8593#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 8720#L1046 assume !(0 != start_simulation_~tmp___0~1); 8826#L1014-1 [2019-10-22 08:54:50,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,207 INFO L82 PathProgramCache]: Analyzing trace with hash 126649597, now seen corresponding path program 1 times [2019-10-22 08:54:50,207 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,207 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1606636681] [2019-10-22 08:54:50,207 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,208 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,208 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,228 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1606636681] [2019-10-22 08:54:50,228 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,228 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:54:50,228 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928405925] [2019-10-22 08:54:50,228 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:50,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,229 INFO L82 PathProgramCache]: Analyzing trace with hash -1132003902, now seen corresponding path program 1 times [2019-10-22 08:54:50,229 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,229 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974867492] [2019-10-22 08:54:50,229 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,229 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,229 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,267 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974867492] [2019-10-22 08:54:50,267 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,267 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:50,267 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [915308007] [2019-10-22 08:54:50,267 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:50,268 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:50,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:50,268 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:50,268 INFO L87 Difference]: Start difference. First operand 606 states and 907 transitions. cyclomatic complexity: 302 Second operand 3 states. [2019-10-22 08:54:50,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:50,312 INFO L93 Difference]: Finished difference Result 606 states and 894 transitions. [2019-10-22 08:54:50,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:50,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606 states and 894 transitions. [2019-10-22 08:54:50,315 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:50,318 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606 states to 606 states and 894 transitions. [2019-10-22 08:54:50,318 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606 [2019-10-22 08:54:50,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606 [2019-10-22 08:54:50,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606 states and 894 transitions. [2019-10-22 08:54:50,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:50,319 INFO L688 BuchiCegarLoop]: Abstraction has 606 states and 894 transitions. [2019-10-22 08:54:50,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states and 894 transitions. [2019-10-22 08:54:50,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 606. [2019-10-22 08:54:50,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 606 states. [2019-10-22 08:54:50,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 894 transitions. [2019-10-22 08:54:50,328 INFO L711 BuchiCegarLoop]: Abstraction has 606 states and 894 transitions. [2019-10-22 08:54:50,328 INFO L591 BuchiCegarLoop]: Abstraction has 606 states and 894 transitions. [2019-10-22 08:54:50,328 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-10-22 08:54:50,328 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606 states and 894 transitions. [2019-10-22 08:54:50,330 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 521 [2019-10-22 08:54:50,330 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:50,330 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:50,331 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,331 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,332 INFO L791 eck$LassoCheckResult]: Stem: 10276#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 10174#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10175#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9862#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 9863#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9965#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9966#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9864#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9865#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10124#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10125#L481-1 assume !(0 == ~M_E~0); 10291#L660-1 assume !(0 == ~T1_E~0); 9770#L665-1 assume !(0 == ~T2_E~0); 9771#L670-1 assume !(0 == ~T3_E~0); 9873#L675-1 assume !(0 == ~T4_E~0); 9874#L680-1 assume !(0 == ~T5_E~0); 10133#L685-1 assume !(0 == ~T6_E~0); 10134#L690-1 assume !(0 == ~E_1~0); 10019#L695-1 assume !(0 == ~E_2~0); 10020#L700-1 assume !(0 == ~E_3~0); 10260#L705-1 assume !(0 == ~E_4~0); 9937#L710-1 assume !(0 == ~E_5~0); 9938#L715-1 assume !(0 == ~E_6~0); 9804#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9805#L310 assume 1 == ~m_pc~0; 9987#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9985#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9986#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 10108#L815 assume !(0 != activate_threads_~tmp~1); 10256#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10178#L329 assume !(1 == ~t1_pc~0); 10179#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 10176#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10177#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10289#L823 assume !(0 != activate_threads_~tmp___0~0); 10357#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10339#L348 assume 1 == ~t2_pc~0; 10340#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10337#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10338#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9945#L831 assume !(0 != activate_threads_~tmp___1~0); 9932#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9869#L367 assume 1 == ~t3_pc~0; 9870#L368 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9838#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9868#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9970#L839 assume !(0 != activate_threads_~tmp___2~0); 10141#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10066#L386 assume !(1 == ~t4_pc~0); 9976#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 10065#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9973#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9974#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10294#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10295#L405 assume 1 == ~t5_pc~0; 10220#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10221#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10218#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10219#L855 assume !(0 != activate_threads_~tmp___4~0); 10301#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9913#L424 assume !(1 == ~t6_pc~0); 9914#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 9909#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9910#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9822#L863 assume !(0 != activate_threads_~tmp___5~0); 9791#L863-2 assume !(1 == ~M_E~0); 9792#L733-1 assume !(1 == ~T1_E~0); 10258#L738-1 assume !(1 == ~T2_E~0); 9935#L743-1 assume !(1 == ~T3_E~0); 9936#L748-1 assume !(1 == ~T4_E~0); 9799#L753-1 assume !(1 == ~T5_E~0); 9800#L758-1 assume !(1 == ~T6_E~0); 9883#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9884#L768-1 assume !(1 == ~E_2~0); 10128#L773-1 assume !(1 == ~E_3~0); 10129#L778-1 assume !(1 == ~E_4~0); 10010#L783-1 assume !(1 == ~E_5~0); 10011#L788-1 assume !(1 == ~E_6~0); 10042#L1014-1 [2019-10-22 08:54:50,332 INFO L793 eck$LassoCheckResult]: Loop: 10042#L1014-1 assume !false; 10043#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 9773#L635 assume !false; 10115#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10116#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9848#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9845#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9846#L546 assume !(0 != eval_~tmp~0); 10261#L650 start_simulation_~kernel_st~0 := 2; 9866#L444-1 start_simulation_~kernel_st~0 := 3; 9867#L660-2 assume !(0 == ~M_E~0); 10292#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9784#L665-3 assume !(0 == ~T2_E~0); 9785#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9875#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9876#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10136#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10137#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10005#L695-3 assume !(0 == ~E_2~0); 10006#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10072#L705-3 assume !(0 == ~E_4~0); 9929#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9930#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9775#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9776#L310-21 assume 1 == ~m_pc~0; 10099#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 10100#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10098#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 10058#L815-21 assume !(0 != activate_threads_~tmp~1); 10034#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10035#L329-21 assume 1 == ~t1_pc~0; 10266#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10164#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10165#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10240#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10241#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10243#L348-21 assume 1 == ~t2_pc~0; 10361#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10331#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10332#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9902#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9903#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9801#L367-21 assume !(1 == ~t3_pc~0); 9768#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 9769#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9829#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9946#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10093#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10014#L386-21 assume !(1 == ~t4_pc~0); 10015#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 10021#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10055#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10147#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10268#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10232#L405-21 assume 1 == ~t5_pc~0; 10213#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10214#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10209#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10210#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10360#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10347#L424-21 assume 1 == ~t6_pc~0; 10322#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9897#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9898#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9962#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9948#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 9949#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10262#L738-3 assume !(1 == ~T2_E~0); 9925#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9926#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9766#L753-3 assume !(1 == ~T5_E~0); 9767#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9871#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9872#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10131#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10132#L778-3 assume !(1 == ~E_4~0); 10017#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10018#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10259#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10216#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9855#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9850#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 9851#L1033 assume !(0 == start_simulation_~tmp~3); 9819#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10217#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9860#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9857#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 9858#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9811#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 9812#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9939#L1046 assume !(0 != start_simulation_~tmp___0~1); 10042#L1014-1 [2019-10-22 08:54:50,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,332 INFO L82 PathProgramCache]: Analyzing trace with hash 560378683, now seen corresponding path program 1 times [2019-10-22 08:54:50,332 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,332 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971586037] [2019-10-22 08:54:50,333 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,333 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,333 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,354 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971586037] [2019-10-22 08:54:50,354 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,355 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:54:50,355 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436673836] [2019-10-22 08:54:50,355 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:50,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,355 INFO L82 PathProgramCache]: Analyzing trace with hash -1348951935, now seen corresponding path program 1 times [2019-10-22 08:54:50,355 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,356 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426482731] [2019-10-22 08:54:50,356 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,356 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,356 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,384 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [426482731] [2019-10-22 08:54:50,384 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,385 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:50,385 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915959946] [2019-10-22 08:54:50,385 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:50,385 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:50,385 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:50,385 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:50,386 INFO L87 Difference]: Start difference. First operand 606 states and 894 transitions. cyclomatic complexity: 289 Second operand 3 states. [2019-10-22 08:54:50,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:50,449 INFO L93 Difference]: Finished difference Result 1118 states and 1632 transitions. [2019-10-22 08:54:50,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:50,450 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1118 states and 1632 transitions. [2019-10-22 08:54:50,454 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1032 [2019-10-22 08:54:50,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1118 states to 1118 states and 1632 transitions. [2019-10-22 08:54:50,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1118 [2019-10-22 08:54:50,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1118 [2019-10-22 08:54:50,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1118 states and 1632 transitions. [2019-10-22 08:54:50,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:50,461 INFO L688 BuchiCegarLoop]: Abstraction has 1118 states and 1632 transitions. [2019-10-22 08:54:50,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1118 states and 1632 transitions. [2019-10-22 08:54:50,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1118 to 1069. [2019-10-22 08:54:50,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1069 states. [2019-10-22 08:54:50,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1069 states to 1069 states and 1565 transitions. [2019-10-22 08:54:50,479 INFO L711 BuchiCegarLoop]: Abstraction has 1069 states and 1565 transitions. [2019-10-22 08:54:50,479 INFO L591 BuchiCegarLoop]: Abstraction has 1069 states and 1565 transitions. [2019-10-22 08:54:50,479 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-10-22 08:54:50,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1069 states and 1565 transitions. [2019-10-22 08:54:50,483 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 983 [2019-10-22 08:54:50,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:50,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:50,484 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,484 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,485 INFO L791 eck$LassoCheckResult]: Stem: 12019#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 11915#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 11916#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11590#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 11591#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11697#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11698#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11595#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11596#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11858#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11859#L481-1 assume !(0 == ~M_E~0); 12035#L660-1 assume !(0 == ~T1_E~0); 11499#L665-1 assume !(0 == ~T2_E~0); 11500#L670-1 assume !(0 == ~T3_E~0); 11604#L675-1 assume !(0 == ~T4_E~0); 11605#L680-1 assume !(0 == ~T5_E~0); 11869#L685-1 assume !(0 == ~T6_E~0); 11870#L690-1 assume !(0 == ~E_1~0); 11750#L695-1 assume !(0 == ~E_2~0); 11751#L700-1 assume !(0 == ~E_3~0); 12004#L705-1 assume !(0 == ~E_4~0); 11669#L710-1 assume !(0 == ~E_5~0); 11670#L715-1 assume !(0 == ~E_6~0); 11535#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11536#L310 assume !(1 == ~m_pc~0); 11719#L310-2 is_master_triggered_~__retres1~0 := 0; 11715#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11716#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11839#L815 assume !(0 != activate_threads_~tmp~1); 12000#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11922#L329 assume !(1 == ~t1_pc~0); 11923#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 11917#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11918#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12033#L823 assume !(0 != activate_threads_~tmp___0~0); 12102#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12084#L348 assume 1 == ~t2_pc~0; 12085#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12082#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12083#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11677#L831 assume !(0 != activate_threads_~tmp___1~0); 11664#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11600#L367 assume 1 == ~t3_pc~0; 11601#L368 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11569#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11599#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11700#L839 assume !(0 != activate_threads_~tmp___2~0); 11880#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11797#L386 assume !(1 == ~t4_pc~0); 11708#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 11796#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11705#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11706#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12039#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12040#L405 assume 1 == ~t5_pc~0; 11964#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11965#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11962#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11963#L855 assume !(0 != activate_threads_~tmp___4~0); 12046#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11645#L424 assume !(1 == ~t6_pc~0); 11646#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 11641#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11642#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11553#L863 assume !(0 != activate_threads_~tmp___5~0); 11522#L863-2 assume !(1 == ~M_E~0); 11523#L733-1 assume !(1 == ~T1_E~0); 12002#L738-1 assume !(1 == ~T2_E~0); 11667#L743-1 assume !(1 == ~T3_E~0); 11668#L748-1 assume !(1 == ~T4_E~0); 11530#L753-1 assume !(1 == ~T5_E~0); 11531#L758-1 assume !(1 == ~T6_E~0); 11615#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11616#L768-1 assume !(1 == ~E_2~0); 11862#L773-1 assume !(1 == ~E_3~0); 11863#L778-1 assume !(1 == ~E_4~0); 11741#L783-1 assume !(1 == ~E_5~0); 11742#L788-1 assume !(1 == ~E_6~0); 11773#L1014-1 [2019-10-22 08:54:50,485 INFO L793 eck$LassoCheckResult]: Loop: 11773#L1014-1 assume !false; 11774#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 11504#L635 assume !false; 11847#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11848#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 11579#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 11576#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 11577#L546 assume !(0 != eval_~tmp~0); 12005#L650 start_simulation_~kernel_st~0 := 2; 11597#L444-1 start_simulation_~kernel_st~0 := 3; 11598#L660-2 assume !(0 == ~M_E~0); 12036#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11515#L665-3 assume !(0 == ~T2_E~0); 11516#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11606#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11607#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11873#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11874#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11736#L695-3 assume !(0 == ~E_2~0); 11737#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11803#L705-3 assume !(0 == ~E_4~0); 11661#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11662#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11506#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11507#L310-21 assume !(1 == ~m_pc~0); 11871#L310-23 is_master_triggered_~__retres1~0 := 0; 11875#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11829#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11789#L815-21 assume !(0 != activate_threads_~tmp~1); 11765#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11766#L329-21 assume 1 == ~t1_pc~0; 12010#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11908#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11909#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11984#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11985#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11987#L348-21 assume 1 == ~t2_pc~0; 12106#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12076#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12077#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11634#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11635#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11532#L367-21 assume 1 == ~t3_pc~0; 11533#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11502#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11560#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11678#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11821#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11745#L386-21 assume !(1 == ~t4_pc~0); 11746#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 11752#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11786#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11891#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12012#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11976#L405-21 assume 1 == ~t5_pc~0; 11957#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11958#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11953#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11954#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12105#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12092#L424-21 assume 1 == ~t6_pc~0; 12067#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11629#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11630#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11694#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 11680#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 11681#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12006#L738-3 assume !(1 == ~T2_E~0); 11657#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11658#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11497#L753-3 assume !(1 == ~T5_E~0); 11498#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11602#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11603#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11867#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11868#L778-3 assume !(1 == ~E_4~0); 11748#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11749#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12003#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11960#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 11586#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 11581#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 11582#L1033 assume !(0 == start_simulation_~tmp~3); 11550#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11961#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 11593#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 11588#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 11589#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11542#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 11543#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 11671#L1046 assume !(0 != start_simulation_~tmp___0~1); 11773#L1014-1 [2019-10-22 08:54:50,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,485 INFO L82 PathProgramCache]: Analyzing trace with hash 663179930, now seen corresponding path program 1 times [2019-10-22 08:54:50,485 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,485 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797843345] [2019-10-22 08:54:50,485 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,486 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,486 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,508 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797843345] [2019-10-22 08:54:50,508 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,508 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:54:50,508 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1519137033] [2019-10-22 08:54:50,508 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:50,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,509 INFO L82 PathProgramCache]: Analyzing trace with hash -679660991, now seen corresponding path program 1 times [2019-10-22 08:54:50,509 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,509 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1929820976] [2019-10-22 08:54:50,509 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,509 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,509 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,538 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1929820976] [2019-10-22 08:54:50,539 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,539 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:50,539 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283748428] [2019-10-22 08:54:50,539 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:50,539 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:50,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:50,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:50,540 INFO L87 Difference]: Start difference. First operand 1069 states and 1565 transitions. cyclomatic complexity: 498 Second operand 3 states. [2019-10-22 08:54:50,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:50,603 INFO L93 Difference]: Finished difference Result 1941 states and 2824 transitions. [2019-10-22 08:54:50,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:50,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1941 states and 2824 transitions. [2019-10-22 08:54:50,612 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1850 [2019-10-22 08:54:50,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1941 states to 1941 states and 2824 transitions. [2019-10-22 08:54:50,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1941 [2019-10-22 08:54:50,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1941 [2019-10-22 08:54:50,622 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1941 states and 2824 transitions. [2019-10-22 08:54:50,624 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:50,624 INFO L688 BuchiCegarLoop]: Abstraction has 1941 states and 2824 transitions. [2019-10-22 08:54:50,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1941 states and 2824 transitions. [2019-10-22 08:54:50,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1941 to 1937. [2019-10-22 08:54:50,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1937 states. [2019-10-22 08:54:50,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1937 states to 1937 states and 2820 transitions. [2019-10-22 08:54:50,652 INFO L711 BuchiCegarLoop]: Abstraction has 1937 states and 2820 transitions. [2019-10-22 08:54:50,652 INFO L591 BuchiCegarLoop]: Abstraction has 1937 states and 2820 transitions. [2019-10-22 08:54:50,652 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-10-22 08:54:50,652 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1937 states and 2820 transitions. [2019-10-22 08:54:50,659 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1846 [2019-10-22 08:54:50,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:50,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:50,661 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,661 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,661 INFO L791 eck$LassoCheckResult]: Stem: 15050#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 14940#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14941#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14608#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 14609#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14717#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14718#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14613#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14614#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14882#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14883#L481-1 assume !(0 == ~M_E~0); 15068#L660-1 assume !(0 == ~T1_E~0); 14516#L665-1 assume !(0 == ~T2_E~0); 14517#L670-1 assume !(0 == ~T3_E~0); 14622#L675-1 assume !(0 == ~T4_E~0); 14623#L680-1 assume !(0 == ~T5_E~0); 14891#L685-1 assume !(0 == ~T6_E~0); 14892#L690-1 assume !(0 == ~E_1~0); 14770#L695-1 assume !(0 == ~E_2~0); 14771#L700-1 assume !(0 == ~E_3~0); 15033#L705-1 assume !(0 == ~E_4~0); 14687#L710-1 assume !(0 == ~E_5~0); 14688#L715-1 assume !(0 == ~E_6~0); 14553#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14554#L310 assume !(1 == ~m_pc~0); 14739#L310-2 is_master_triggered_~__retres1~0 := 0; 14735#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14736#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 14860#L815 assume !(0 != activate_threads_~tmp~1); 15029#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14947#L329 assume !(1 == ~t1_pc~0); 14948#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 14942#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14943#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15065#L823 assume !(0 != activate_threads_~tmp___0~0); 15142#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15118#L348 assume !(1 == ~t2_pc~0); 15119#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 15116#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15117#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14696#L831 assume !(0 != activate_threads_~tmp___1~0); 14682#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14618#L367 assume 1 == ~t3_pc~0; 14619#L368 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14587#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14617#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14720#L839 assume !(0 != activate_threads_~tmp___2~0); 14903#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14817#L386 assume !(1 == ~t4_pc~0); 14728#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 14816#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14725#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14726#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15071#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15072#L405 assume 1 == ~t5_pc~0; 14989#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14990#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14987#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14988#L855 assume !(0 != activate_threads_~tmp___4~0); 15079#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14662#L424 assume !(1 == ~t6_pc~0); 14663#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 14658#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14659#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14571#L863 assume !(0 != activate_threads_~tmp___5~0); 14540#L863-2 assume !(1 == ~M_E~0); 14541#L733-1 assume !(1 == ~T1_E~0); 15031#L738-1 assume !(1 == ~T2_E~0); 14685#L743-1 assume !(1 == ~T3_E~0); 14686#L748-1 assume !(1 == ~T4_E~0); 14548#L753-1 assume !(1 == ~T5_E~0); 14549#L758-1 assume !(1 == ~T6_E~0); 14632#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14633#L768-1 assume !(1 == ~E_2~0); 14886#L773-1 assume !(1 == ~E_3~0); 14887#L778-1 assume !(1 == ~E_4~0); 14761#L783-1 assume !(1 == ~E_5~0); 14762#L788-1 assume !(1 == ~E_6~0); 15127#L1014-1 [2019-10-22 08:54:50,661 INFO L793 eck$LassoCheckResult]: Loop: 15127#L1014-1 assume !false; 15315#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 15309#L635 assume !false; 15307#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 15241#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 15234#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 15224#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 15219#L546 assume !(0 != eval_~tmp~0); 15034#L650 start_simulation_~kernel_st~0 := 2; 14615#L444-1 start_simulation_~kernel_st~0 := 3; 14616#L660-2 assume !(0 == ~M_E~0); 15069#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14532#L665-3 assume !(0 == ~T2_E~0); 14533#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14624#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14625#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14895#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14896#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14756#L695-3 assume !(0 == ~E_2~0); 14757#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14823#L705-3 assume !(0 == ~E_4~0); 14679#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14680#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14523#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14524#L310-21 assume !(1 == ~m_pc~0); 14893#L310-23 is_master_triggered_~__retres1~0 := 0; 14897#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14849#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 14809#L815-21 assume !(0 != activate_threads_~tmp~1); 14785#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14786#L329-21 assume 1 == ~t1_pc~0; 15041#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14933#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14934#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15012#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15013#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15015#L348-21 assume !(1 == ~t2_pc~0); 15165#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 15110#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15111#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14651#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14652#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14550#L367-21 assume !(1 == ~t3_pc~0); 14518#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 14519#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14578#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14697#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14841#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14765#L386-21 assume !(1 == ~t4_pc~0); 14766#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 14772#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14806#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14916#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15043#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15002#L405-21 assume 1 == ~t5_pc~0; 14982#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14983#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16265#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16264#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 16263#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16262#L424-21 assume !(1 == ~t6_pc~0); 16260#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 16259#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16258#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16257#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 16256#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 16255#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16254#L738-3 assume !(1 == ~T2_E~0); 14675#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14676#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16237#L753-3 assume !(1 == ~T5_E~0); 16236#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16235#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16234#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16233#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16232#L778-3 assume !(1 == ~E_4~0); 16231#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16230#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16229#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 16214#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 14879#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 14599#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 14600#L1033 assume !(0 == start_simulation_~tmp~3); 15004#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 16222#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 16213#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 16178#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 15772#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15727#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 15726#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 15725#L1046 assume !(0 != start_simulation_~tmp___0~1); 15127#L1014-1 [2019-10-22 08:54:50,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,661 INFO L82 PathProgramCache]: Analyzing trace with hash -1492334471, now seen corresponding path program 1 times [2019-10-22 08:54:50,662 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,662 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242526685] [2019-10-22 08:54:50,662 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,662 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,662 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,689 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242526685] [2019-10-22 08:54:50,689 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,690 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:54:50,690 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [570435147] [2019-10-22 08:54:50,690 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:50,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,690 INFO L82 PathProgramCache]: Analyzing trace with hash -2091057276, now seen corresponding path program 1 times [2019-10-22 08:54:50,690 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,691 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775617581] [2019-10-22 08:54:50,691 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,691 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,691 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,717 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1775617581] [2019-10-22 08:54:50,717 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,717 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:50,717 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717329034] [2019-10-22 08:54:50,717 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:50,717 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:50,717 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:50,718 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:50,718 INFO L87 Difference]: Start difference. First operand 1937 states and 2820 transitions. cyclomatic complexity: 887 Second operand 3 states. [2019-10-22 08:54:50,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:50,783 INFO L93 Difference]: Finished difference Result 3570 states and 5167 transitions. [2019-10-22 08:54:50,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:50,784 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3570 states and 5167 transitions. [2019-10-22 08:54:50,799 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3464 [2019-10-22 08:54:50,813 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3570 states to 3570 states and 5167 transitions. [2019-10-22 08:54:50,813 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3570 [2019-10-22 08:54:50,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3570 [2019-10-22 08:54:50,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3570 states and 5167 transitions. [2019-10-22 08:54:50,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:50,821 INFO L688 BuchiCegarLoop]: Abstraction has 3570 states and 5167 transitions. [2019-10-22 08:54:50,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3570 states and 5167 transitions. [2019-10-22 08:54:50,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3570 to 3562. [2019-10-22 08:54:50,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3562 states. [2019-10-22 08:54:50,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3562 states to 3562 states and 5159 transitions. [2019-10-22 08:54:50,870 INFO L711 BuchiCegarLoop]: Abstraction has 3562 states and 5159 transitions. [2019-10-22 08:54:50,870 INFO L591 BuchiCegarLoop]: Abstraction has 3562 states and 5159 transitions. [2019-10-22 08:54:50,870 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-10-22 08:54:50,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3562 states and 5159 transitions. [2019-10-22 08:54:50,883 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3456 [2019-10-22 08:54:50,883 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:50,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:50,885 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,885 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:50,885 INFO L791 eck$LassoCheckResult]: Stem: 20577#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 20465#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 20466#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20120#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 20121#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20235#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20236#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20125#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20126#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20405#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20406#L481-1 assume !(0 == ~M_E~0); 20598#L660-1 assume !(0 == ~T1_E~0); 20030#L665-1 assume !(0 == ~T2_E~0); 20031#L670-1 assume !(0 == ~T3_E~0); 20133#L675-1 assume !(0 == ~T4_E~0); 20134#L680-1 assume !(0 == ~T5_E~0); 20417#L685-1 assume !(0 == ~T6_E~0); 20418#L690-1 assume !(0 == ~E_1~0); 20293#L695-1 assume !(0 == ~E_2~0); 20294#L700-1 assume !(0 == ~E_3~0); 20561#L705-1 assume !(0 == ~E_4~0); 20200#L710-1 assume !(0 == ~E_5~0); 20201#L715-1 assume !(0 == ~E_6~0); 20067#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20068#L310 assume !(1 == ~m_pc~0); 20262#L310-2 is_master_triggered_~__retres1~0 := 0; 20258#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20259#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 20387#L815 assume !(0 != activate_threads_~tmp~1); 20557#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20472#L329 assume !(1 == ~t1_pc~0); 20473#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 20467#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20468#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20596#L823 assume !(0 != activate_threads_~tmp___0~0); 20679#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20652#L348 assume !(1 == ~t2_pc~0); 20653#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 20648#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20649#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 20208#L831 assume !(0 != activate_threads_~tmp___1~0); 20195#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20130#L367 assume !(1 == ~t3_pc~0); 20099#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 20100#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20129#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 20239#L839 assume !(0 != activate_threads_~tmp___2~0); 20429#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20342#L386 assume !(1 == ~t4_pc~0); 20251#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 20341#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20248#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 20249#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 20602#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20603#L405 assume 1 == ~t5_pc~0; 20515#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 20516#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20513#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20514#L855 assume !(0 != activate_threads_~tmp___4~0); 20612#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20176#L424 assume !(1 == ~t6_pc~0); 20177#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 20172#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 20173#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20085#L863 assume !(0 != activate_threads_~tmp___5~0); 20054#L863-2 assume !(1 == ~M_E~0); 20055#L733-1 assume !(1 == ~T1_E~0); 20559#L738-1 assume !(1 == ~T2_E~0); 20198#L743-1 assume !(1 == ~T3_E~0); 20199#L748-1 assume !(1 == ~T4_E~0); 20062#L753-1 assume !(1 == ~T5_E~0); 20063#L758-1 assume !(1 == ~T6_E~0); 20144#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20145#L768-1 assume !(1 == ~E_2~0); 20409#L773-1 assume !(1 == ~E_3~0); 20410#L778-1 assume !(1 == ~E_4~0); 20284#L783-1 assume !(1 == ~E_5~0); 20285#L788-1 assume !(1 == ~E_6~0); 20663#L1014-1 [2019-10-22 08:54:50,885 INFO L793 eck$LassoCheckResult]: Loop: 20663#L1014-1 assume !false; 22881#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 22876#L635 assume !false; 22875#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 22747#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 22736#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22729#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 22721#L546 assume !(0 != eval_~tmp~0); 22722#L650 start_simulation_~kernel_st~0 := 2; 23472#L444-1 start_simulation_~kernel_st~0 := 3; 23471#L660-2 assume !(0 == ~M_E~0); 20600#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20046#L665-3 assume !(0 == ~T2_E~0); 20047#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20526#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23467#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23346#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23345#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23344#L695-3 assume !(0 == ~E_2~0); 23343#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23342#L705-3 assume !(0 == ~E_4~0); 23341#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23340#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23339#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23337#L310-21 assume !(1 == ~m_pc~0); 23335#L310-23 is_master_triggered_~__retres1~0 := 0; 23333#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23331#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 23329#L815-21 assume !(0 != activate_threads_~tmp~1); 23326#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23324#L329-21 assume 1 == ~t1_pc~0; 23321#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 23319#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23317#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 23314#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 23312#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23310#L348-21 assume !(1 == ~t2_pc~0); 23308#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 23306#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23305#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 23304#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23303#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23302#L367-21 assume !(1 == ~t3_pc~0); 23301#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 23300#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20209#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 20210#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20369#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20288#L386-21 assume !(1 == ~t4_pc~0); 20289#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 20295#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20330#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 20442#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 20570#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20528#L405-21 assume 1 == ~t5_pc~0; 20508#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 20509#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20504#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20505#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 20686#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20664#L424-21 assume 1 == ~t6_pc~0; 20633#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 20158#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 20159#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20232#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 20212#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 20213#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20563#L738-3 assume !(1 == ~T2_E~0); 20188#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20189#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20028#L753-3 assume !(1 == ~T5_E~0); 20029#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20131#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20132#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20415#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20416#L778-3 assume !(1 == ~E_4~0); 20291#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20292#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20560#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 20511#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 20116#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 20111#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 20112#L1033 assume !(0 == start_simulation_~tmp~3); 20530#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 22898#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 22894#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22892#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 22887#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22886#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 22885#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 22883#L1046 assume !(0 != start_simulation_~tmp___0~1); 20663#L1014-1 [2019-10-22 08:54:50,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,886 INFO L82 PathProgramCache]: Analyzing trace with hash 1037816216, now seen corresponding path program 1 times [2019-10-22 08:54:50,886 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,886 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212526552] [2019-10-22 08:54:50,886 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,886 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,887 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,914 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212526552] [2019-10-22 08:54:50,914 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,914 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:54:50,914 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [421466694] [2019-10-22 08:54:50,915 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:50,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:50,915 INFO L82 PathProgramCache]: Analyzing trace with hash -319586301, now seen corresponding path program 1 times [2019-10-22 08:54:50,915 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:50,915 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307364313] [2019-10-22 08:54:50,916 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,916 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:50,916 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:50,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:50,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:50,945 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307364313] [2019-10-22 08:54:50,946 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:50,946 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:50,946 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1077955335] [2019-10-22 08:54:50,946 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:50,946 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:50,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:50,947 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:50,947 INFO L87 Difference]: Start difference. First operand 3562 states and 5159 transitions. cyclomatic complexity: 1605 Second operand 3 states. [2019-10-22 08:54:51,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:51,026 INFO L93 Difference]: Finished difference Result 6609 states and 9532 transitions. [2019-10-22 08:54:51,026 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:51,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6609 states and 9532 transitions. [2019-10-22 08:54:51,056 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6464 [2019-10-22 08:54:51,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6609 states to 6609 states and 9532 transitions. [2019-10-22 08:54:51,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6609 [2019-10-22 08:54:51,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6609 [2019-10-22 08:54:51,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6609 states and 9532 transitions. [2019-10-22 08:54:51,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:51,100 INFO L688 BuchiCegarLoop]: Abstraction has 6609 states and 9532 transitions. [2019-10-22 08:54:51,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6609 states and 9532 transitions. [2019-10-22 08:54:51,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6609 to 6593. [2019-10-22 08:54:51,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6593 states. [2019-10-22 08:54:51,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6593 states to 6593 states and 9516 transitions. [2019-10-22 08:54:51,247 INFO L711 BuchiCegarLoop]: Abstraction has 6593 states and 9516 transitions. [2019-10-22 08:54:51,247 INFO L591 BuchiCegarLoop]: Abstraction has 6593 states and 9516 transitions. [2019-10-22 08:54:51,247 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-10-22 08:54:51,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6593 states and 9516 transitions. [2019-10-22 08:54:51,265 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6448 [2019-10-22 08:54:51,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:51,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:51,267 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:51,267 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:51,267 INFO L791 eck$LassoCheckResult]: Stem: 30740#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 30618#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 30619#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 30299#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 30300#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30406#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30407#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30304#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30305#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30567#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30568#L481-1 assume !(0 == ~M_E~0); 30758#L660-1 assume !(0 == ~T1_E~0); 30208#L665-1 assume !(0 == ~T2_E~0); 30209#L670-1 assume !(0 == ~T3_E~0); 30312#L675-1 assume !(0 == ~T4_E~0); 30313#L680-1 assume !(0 == ~T5_E~0); 30578#L685-1 assume !(0 == ~T6_E~0); 30579#L690-1 assume !(0 == ~E_1~0); 30460#L695-1 assume !(0 == ~E_2~0); 30461#L700-1 assume !(0 == ~E_3~0); 30722#L705-1 assume !(0 == ~E_4~0); 30377#L710-1 assume !(0 == ~E_5~0); 30378#L715-1 assume !(0 == ~E_6~0); 30244#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30245#L310 assume !(1 == ~m_pc~0); 30429#L310-2 is_master_triggered_~__retres1~0 := 0; 30425#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30426#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30550#L815 assume !(0 != activate_threads_~tmp~1); 30718#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30625#L329 assume !(1 == ~t1_pc~0); 30626#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 30620#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30621#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 30756#L823 assume !(0 != activate_threads_~tmp___0~0); 30828#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30806#L348 assume !(1 == ~t2_pc~0); 30807#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 30803#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30804#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 30385#L831 assume !(0 != activate_threads_~tmp___1~0); 30372#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30309#L367 assume !(1 == ~t3_pc~0); 30277#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 30278#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30308#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 30409#L839 assume !(0 != activate_threads_~tmp___2~0); 30585#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30507#L386 assume !(1 == ~t4_pc~0); 30418#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 30506#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30415#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 30416#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 30761#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30762#L405 assume !(1 == ~t5_pc~0); 30703#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 30704#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30666#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 30667#L855 assume !(0 != activate_threads_~tmp___4~0); 30769#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30353#L424 assume !(1 == ~t6_pc~0); 30354#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 30349#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 30350#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30262#L863 assume !(0 != activate_threads_~tmp___5~0); 30231#L863-2 assume !(1 == ~M_E~0); 30232#L733-1 assume !(1 == ~T1_E~0); 30720#L738-1 assume !(1 == ~T2_E~0); 30375#L743-1 assume !(1 == ~T3_E~0); 30376#L748-1 assume !(1 == ~T4_E~0); 30239#L753-1 assume !(1 == ~T5_E~0); 30240#L758-1 assume !(1 == ~T6_E~0); 30322#L763-1 assume 1 == ~E_1~0;~E_1~0 := 2; 30323#L768-1 assume !(1 == ~E_2~0); 30571#L773-1 assume !(1 == ~E_3~0); 30572#L778-1 assume !(1 == ~E_4~0); 30451#L783-1 assume !(1 == ~E_5~0); 30452#L788-1 assume !(1 == ~E_6~0); 30814#L1014-1 [2019-10-22 08:54:51,267 INFO L793 eck$LassoCheckResult]: Loop: 30814#L1014-1 assume !false; 32607#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 32601#L635 assume !false; 32599#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 32592#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 32583#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 32579#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 32571#L546 assume !(0 != eval_~tmp~0); 32572#L650 start_simulation_~kernel_st~0 := 2; 32796#L444-1 start_simulation_~kernel_st~0 := 3; 32795#L660-2 assume !(0 == ~M_E~0); 32794#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32793#L665-3 assume !(0 == ~T2_E~0); 32792#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32791#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32790#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32789#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32788#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32787#L695-3 assume !(0 == ~E_2~0); 32785#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32783#L705-3 assume !(0 == ~E_4~0); 32781#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32779#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32777#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32775#L310-21 assume !(1 == ~m_pc~0); 32773#L310-23 is_master_triggered_~__retres1~0 := 0; 32770#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32768#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 32766#L815-21 assume !(0 != activate_threads_~tmp~1); 32764#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32762#L329-21 assume 1 == ~t1_pc~0; 32759#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 32757#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32755#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 32753#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 32751#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32749#L348-21 assume !(1 == ~t2_pc~0); 32747#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 32745#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32743#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 32741#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 32739#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32737#L367-21 assume !(1 == ~t3_pc~0); 32734#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 32732#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32730#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 32728#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 32726#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32724#L386-21 assume !(1 == ~t4_pc~0); 32721#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 32719#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32717#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 32715#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 32713#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32711#L405-21 assume !(1 == ~t5_pc~0); 32709#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 32706#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32704#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 32702#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 32700#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32698#L424-21 assume !(1 == ~t6_pc~0); 32695#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 32693#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32691#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 32689#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 32687#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 32685#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32683#L738-3 assume !(1 == ~T2_E~0); 32681#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32679#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32677#L753-3 assume !(1 == ~T5_E~0); 32675#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32674#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32673#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32671#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32669#L778-3 assume !(1 == ~E_4~0); 32667#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32665#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32663#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 32647#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 32645#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 32643#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 32640#L1033 assume !(0 == start_simulation_~tmp~3); 32637#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 32623#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 32620#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 32618#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 32616#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 32614#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 32612#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 32610#L1046 assume !(0 != start_simulation_~tmp___0~1); 30814#L1014-1 [2019-10-22 08:54:51,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:51,268 INFO L82 PathProgramCache]: Analyzing trace with hash -552578761, now seen corresponding path program 1 times [2019-10-22 08:54:51,268 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:51,268 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350469908] [2019-10-22 08:54:51,268 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:51,268 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:51,268 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:51,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:51,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:51,297 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1350469908] [2019-10-22 08:54:51,297 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:51,297 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:54:51,297 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [385300413] [2019-10-22 08:54:51,298 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:51,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:51,298 INFO L82 PathProgramCache]: Analyzing trace with hash -965797307, now seen corresponding path program 1 times [2019-10-22 08:54:51,298 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:51,298 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998185700] [2019-10-22 08:54:51,298 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:51,298 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:51,299 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:51,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:51,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:51,324 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [998185700] [2019-10-22 08:54:51,324 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:51,324 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:51,324 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673157245] [2019-10-22 08:54:51,325 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:51,325 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:51,325 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:51,325 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:51,325 INFO L87 Difference]: Start difference. First operand 6593 states and 9516 transitions. cyclomatic complexity: 2939 Second operand 3 states. [2019-10-22 08:54:51,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:51,383 INFO L93 Difference]: Finished difference Result 6593 states and 9377 transitions. [2019-10-22 08:54:51,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:51,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6593 states and 9377 transitions. [2019-10-22 08:54:51,407 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6448 [2019-10-22 08:54:51,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6593 states to 6593 states and 9377 transitions. [2019-10-22 08:54:51,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6593 [2019-10-22 08:54:51,448 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6593 [2019-10-22 08:54:51,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6593 states and 9377 transitions. [2019-10-22 08:54:51,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:51,456 INFO L688 BuchiCegarLoop]: Abstraction has 6593 states and 9377 transitions. [2019-10-22 08:54:51,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6593 states and 9377 transitions. [2019-10-22 08:54:51,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6593 to 6593. [2019-10-22 08:54:51,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6593 states. [2019-10-22 08:54:51,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6593 states to 6593 states and 9377 transitions. [2019-10-22 08:54:51,541 INFO L711 BuchiCegarLoop]: Abstraction has 6593 states and 9377 transitions. [2019-10-22 08:54:51,541 INFO L591 BuchiCegarLoop]: Abstraction has 6593 states and 9377 transitions. [2019-10-22 08:54:51,541 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-10-22 08:54:51,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6593 states and 9377 transitions. [2019-10-22 08:54:51,560 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6448 [2019-10-22 08:54:51,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:51,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:51,561 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:51,561 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:51,561 INFO L791 eck$LassoCheckResult]: Stem: 43924#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 43818#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 43819#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 43485#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 43486#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43609#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43610#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43490#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43491#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43771#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43772#L481-1 assume !(0 == ~M_E~0); 43940#L660-1 assume !(0 == ~T1_E~0); 43401#L665-1 assume !(0 == ~T2_E~0); 43402#L670-1 assume !(0 == ~T3_E~0); 43498#L675-1 assume !(0 == ~T4_E~0); 43499#L680-1 assume !(0 == ~T5_E~0); 43780#L685-1 assume !(0 == ~T6_E~0); 43781#L690-1 assume !(0 == ~E_1~0); 43665#L695-1 assume !(0 == ~E_2~0); 43666#L700-1 assume !(0 == ~E_3~0); 43908#L705-1 assume !(0 == ~E_4~0); 43563#L710-1 assume !(0 == ~E_5~0); 43564#L715-1 assume !(0 == ~E_6~0); 43434#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43435#L310 assume !(1 == ~m_pc~0); 43634#L310-2 is_master_triggered_~__retres1~0 := 0; 43630#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43631#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 43755#L815 assume !(0 != activate_threads_~tmp~1); 43904#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43825#L329 assume !(1 == ~t1_pc~0); 43826#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 43820#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43821#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 43938#L823 assume !(0 != activate_threads_~tmp___0~0); 44009#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43987#L348 assume !(1 == ~t2_pc~0); 43988#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 43984#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43985#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 43571#L831 assume !(0 != activate_threads_~tmp___1~0); 43558#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43495#L367 assume !(1 == ~t3_pc~0); 43464#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 43465#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43494#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 43612#L839 assume !(0 != activate_threads_~tmp___2~0); 43787#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43713#L386 assume !(1 == ~t4_pc~0); 43623#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 43712#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 43620#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 43621#L847 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 43944#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 43945#L405 assume !(1 == ~t5_pc~0); 43893#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 43894#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 43865#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 43866#L855 assume !(0 != activate_threads_~tmp___4~0); 43950#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 43539#L424 assume !(1 == ~t6_pc~0); 43540#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 43535#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 43536#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 43451#L863 assume !(0 != activate_threads_~tmp___5~0); 43423#L863-2 assume !(1 == ~M_E~0); 43424#L733-1 assume !(1 == ~T1_E~0); 43906#L738-1 assume !(1 == ~T2_E~0); 43561#L743-1 assume !(1 == ~T3_E~0); 43562#L748-1 assume !(1 == ~T4_E~0); 43430#L753-1 assume !(1 == ~T5_E~0); 43431#L758-1 assume !(1 == ~T6_E~0); 43508#L763-1 assume !(1 == ~E_1~0); 43509#L768-1 assume !(1 == ~E_2~0); 43775#L773-1 assume !(1 == ~E_3~0); 43776#L778-1 assume !(1 == ~E_4~0); 43656#L783-1 assume !(1 == ~E_5~0); 43657#L788-1 assume !(1 == ~E_6~0); 43995#L1014-1 [2019-10-22 08:54:51,561 INFO L793 eck$LassoCheckResult]: Loop: 43995#L1014-1 assume !false; 46098#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 46092#L635 assume !false; 46090#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 46085#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 46078#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 46075#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 46072#L546 assume !(0 != eval_~tmp~0); 46073#L650 start_simulation_~kernel_st~0 := 2; 46699#L444-1 start_simulation_~kernel_st~0 := 3; 46697#L660-2 assume !(0 == ~M_E~0); 46693#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46691#L665-3 assume !(0 == ~T2_E~0); 46688#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46686#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46684#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46682#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46680#L690-3 assume !(0 == ~E_1~0); 46678#L695-3 assume !(0 == ~E_2~0); 46676#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46673#L705-3 assume !(0 == ~E_4~0); 46671#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46669#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46668#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 46667#L310-21 assume !(1 == ~m_pc~0); 46665#L310-23 is_master_triggered_~__retres1~0 := 0; 46663#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 46652#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 46647#L815-21 assume !(0 != activate_threads_~tmp~1); 46642#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 46255#L329-21 assume !(1 == ~t1_pc~0); 46252#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 46250#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 46248#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 46246#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 46244#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 46242#L348-21 assume !(1 == ~t2_pc~0); 46240#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 46238#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46236#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 46234#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 46232#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 46230#L367-21 assume !(1 == ~t3_pc~0); 46228#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 46226#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 46224#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 46222#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 46220#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 46217#L386-21 assume !(1 == ~t4_pc~0); 46214#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 46212#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46210#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 46208#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 46206#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 46204#L405-21 assume !(1 == ~t5_pc~0); 46202#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 46200#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 46198#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 46196#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 46194#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 46192#L424-21 assume !(1 == ~t6_pc~0); 46188#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 46186#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 46184#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 46182#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 46180#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 46177#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46175#L738-3 assume !(1 == ~T2_E~0); 46173#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46171#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46169#L753-3 assume !(1 == ~T5_E~0); 46167#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46165#L763-3 assume !(1 == ~E_1~0); 46163#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46161#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46159#L778-3 assume !(1 == ~E_4~0); 46157#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46155#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46153#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 46138#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 46136#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 46134#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 46131#L1033 assume !(0 == start_simulation_~tmp~3); 46128#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 46113#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 46111#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 46109#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 46107#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 46105#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 46103#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 46101#L1046 assume !(0 != start_simulation_~tmp___0~1); 43995#L1014-1 [2019-10-22 08:54:51,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:51,562 INFO L82 PathProgramCache]: Analyzing trace with hash -495320459, now seen corresponding path program 1 times [2019-10-22 08:54:51,562 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:51,562 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186891729] [2019-10-22 08:54:51,562 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:51,562 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:51,562 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:51,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:51,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:51,620 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [186891729] [2019-10-22 08:54:51,620 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:51,620 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:54:51,620 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768894681] [2019-10-22 08:54:51,621 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:51,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:51,621 INFO L82 PathProgramCache]: Analyzing trace with hash -738986042, now seen corresponding path program 1 times [2019-10-22 08:54:51,621 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:51,621 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905699335] [2019-10-22 08:54:51,621 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:51,621 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:51,624 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:51,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:51,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:51,655 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905699335] [2019-10-22 08:54:51,655 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:51,655 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:51,655 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1055622049] [2019-10-22 08:54:51,655 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:51,656 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:51,656 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:54:51,656 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:54:51,656 INFO L87 Difference]: Start difference. First operand 6593 states and 9377 transitions. cyclomatic complexity: 2800 Second operand 5 states. [2019-10-22 08:54:51,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:51,829 INFO L93 Difference]: Finished difference Result 9213 states and 13092 transitions. [2019-10-22 08:54:51,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 08:54:51,829 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9213 states and 13092 transitions. [2019-10-22 08:54:51,865 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9020 [2019-10-22 08:54:51,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9213 states to 9213 states and 13092 transitions. [2019-10-22 08:54:51,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9213 [2019-10-22 08:54:51,903 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9213 [2019-10-22 08:54:51,903 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9213 states and 13092 transitions. [2019-10-22 08:54:51,915 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:51,916 INFO L688 BuchiCegarLoop]: Abstraction has 9213 states and 13092 transitions. [2019-10-22 08:54:51,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9213 states and 13092 transitions. [2019-10-22 08:54:52,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9213 to 6617. [2019-10-22 08:54:52,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6617 states. [2019-10-22 08:54:52,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6617 states to 6617 states and 9312 transitions. [2019-10-22 08:54:52,022 INFO L711 BuchiCegarLoop]: Abstraction has 6617 states and 9312 transitions. [2019-10-22 08:54:52,022 INFO L591 BuchiCegarLoop]: Abstraction has 6617 states and 9312 transitions. [2019-10-22 08:54:52,022 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-10-22 08:54:52,022 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6617 states and 9312 transitions. [2019-10-22 08:54:52,042 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6472 [2019-10-22 08:54:52,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:52,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:52,043 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:52,043 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:52,043 INFO L791 eck$LassoCheckResult]: Stem: 59774#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 59647#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 59648#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 59312#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 59313#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59422#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59423#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59317#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59318#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59592#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59593#L481-1 assume !(0 == ~M_E~0); 59792#L660-1 assume !(0 == ~T1_E~0); 59220#L665-1 assume !(0 == ~T2_E~0); 59221#L670-1 assume !(0 == ~T3_E~0); 59325#L675-1 assume !(0 == ~T4_E~0); 59326#L680-1 assume !(0 == ~T5_E~0); 59603#L685-1 assume !(0 == ~T6_E~0); 59604#L690-1 assume !(0 == ~E_1~0); 59476#L695-1 assume !(0 == ~E_2~0); 59477#L700-1 assume !(0 == ~E_3~0); 59754#L705-1 assume !(0 == ~E_4~0); 59393#L710-1 assume !(0 == ~E_5~0); 59394#L715-1 assume !(0 == ~E_6~0); 59257#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 59258#L310 assume !(1 == ~m_pc~0); 59445#L310-2 is_master_triggered_~__retres1~0 := 0; 59441#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 59442#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 59572#L815 assume !(0 != activate_threads_~tmp~1); 59750#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 59654#L329 assume !(1 == ~t1_pc~0); 59655#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 59649#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59650#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 59790#L823 assume !(0 != activate_threads_~tmp___0~0); 59863#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 59842#L348 assume !(1 == ~t2_pc~0); 59843#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 59839#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 59840#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 59401#L831 assume !(0 != activate_threads_~tmp___1~0); 59388#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 59322#L367 assume !(1 == ~t3_pc~0); 59290#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 59291#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 59321#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 59426#L839 assume !(0 != activate_threads_~tmp___2~0); 59612#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 59528#L386 assume !(1 == ~t4_pc~0); 59434#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 59527#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 59431#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 59432#L847 assume !(0 != activate_threads_~tmp___3~0); 59795#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 59796#L405 assume !(1 == ~t5_pc~0); 59737#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 59738#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 59694#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 59695#L855 assume !(0 != activate_threads_~tmp___4~0); 59802#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 59367#L424 assume !(1 == ~t6_pc~0); 59368#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 59363#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 59364#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 59275#L863 assume !(0 != activate_threads_~tmp___5~0); 59244#L863-2 assume !(1 == ~M_E~0); 59245#L733-1 assume !(1 == ~T1_E~0); 59752#L738-1 assume !(1 == ~T2_E~0); 59391#L743-1 assume !(1 == ~T3_E~0); 59392#L748-1 assume !(1 == ~T4_E~0); 59252#L753-1 assume !(1 == ~T5_E~0); 59253#L758-1 assume !(1 == ~T6_E~0); 59336#L763-1 assume !(1 == ~E_1~0); 59337#L768-1 assume !(1 == ~E_2~0); 59596#L773-1 assume !(1 == ~E_3~0); 59597#L778-1 assume !(1 == ~E_4~0); 59467#L783-1 assume !(1 == ~E_5~0); 59468#L788-1 assume !(1 == ~E_6~0); 59849#L1014-1 [2019-10-22 08:54:52,044 INFO L793 eck$LassoCheckResult]: Loop: 59849#L1014-1 assume !false; 62745#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 62730#L635 assume !false; 62725#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 62638#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 62626#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 62619#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 62609#L546 assume !(0 != eval_~tmp~0); 62610#L650 start_simulation_~kernel_st~0 := 2; 62974#L444-1 start_simulation_~kernel_st~0 := 3; 62972#L660-2 assume !(0 == ~M_E~0); 62970#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62968#L665-3 assume !(0 == ~T2_E~0); 62966#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62964#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62962#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62960#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62958#L690-3 assume !(0 == ~E_1~0); 62956#L695-3 assume !(0 == ~E_2~0); 62954#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62952#L705-3 assume !(0 == ~E_4~0); 62950#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62948#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62946#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 62944#L310-21 assume !(1 == ~m_pc~0); 62941#L310-23 is_master_triggered_~__retres1~0 := 0; 62939#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 62937#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 62935#L815-21 assume !(0 != activate_threads_~tmp~1); 62933#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 62931#L329-21 assume !(1 == ~t1_pc~0); 62928#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 62926#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 62924#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 62922#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 62920#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 62918#L348-21 assume !(1 == ~t2_pc~0); 62916#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 62913#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 62911#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 62909#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 62907#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 62905#L367-21 assume !(1 == ~t3_pc~0); 62903#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 62901#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62899#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 62897#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 62895#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 62893#L386-21 assume !(1 == ~t4_pc~0); 62890#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 62888#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 62886#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 62884#L847-21 assume !(0 != activate_threads_~tmp___3~0); 62882#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 62881#L405-21 assume !(1 == ~t5_pc~0); 62880#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 62878#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 62876#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 62875#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 62874#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 62873#L424-21 assume !(1 == ~t6_pc~0); 62871#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 62870#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 62868#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 62865#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 62863#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 62861#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62859#L738-3 assume !(1 == ~T2_E~0); 62857#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62854#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62852#L753-3 assume !(1 == ~T5_E~0); 62850#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62848#L763-3 assume !(1 == ~E_1~0); 62846#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62844#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62842#L778-3 assume !(1 == ~E_4~0); 62840#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62837#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62835#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 62819#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 62817#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 62815#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 62812#L1033 assume !(0 == start_simulation_~tmp~3); 62809#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 62764#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 62762#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 62760#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 62758#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 62757#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 62755#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 62751#L1046 assume !(0 != start_simulation_~tmp___0~1); 59849#L1014-1 [2019-10-22 08:54:52,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:52,044 INFO L82 PathProgramCache]: Analyzing trace with hash -433280845, now seen corresponding path program 1 times [2019-10-22 08:54:52,044 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:52,044 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085858994] [2019-10-22 08:54:52,044 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,044 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,044 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:52,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:52,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:52,099 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:52,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:52,100 INFO L82 PathProgramCache]: Analyzing trace with hash 1710614088, now seen corresponding path program 1 times [2019-10-22 08:54:52,100 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:52,100 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667000419] [2019-10-22 08:54:52,100 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,100 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,100 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:52,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:52,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:52,126 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667000419] [2019-10-22 08:54:52,126 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:52,126 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:52,127 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2021898723] [2019-10-22 08:54:52,127 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:52,127 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:52,127 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:52,127 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:52,127 INFO L87 Difference]: Start difference. First operand 6617 states and 9312 transitions. cyclomatic complexity: 2711 Second operand 3 states. [2019-10-22 08:54:52,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:52,172 INFO L93 Difference]: Finished difference Result 7635 states and 10717 transitions. [2019-10-22 08:54:52,172 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:52,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7635 states and 10717 transitions. [2019-10-22 08:54:52,202 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7432 [2019-10-22 08:54:52,224 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7635 states to 7635 states and 10717 transitions. [2019-10-22 08:54:52,225 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7635 [2019-10-22 08:54:52,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7635 [2019-10-22 08:54:52,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7635 states and 10717 transitions. [2019-10-22 08:54:52,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:52,240 INFO L688 BuchiCegarLoop]: Abstraction has 7635 states and 10717 transitions. [2019-10-22 08:54:52,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7635 states and 10717 transitions. [2019-10-22 08:54:52,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7635 to 7635. [2019-10-22 08:54:52,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7635 states. [2019-10-22 08:54:52,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7635 states to 7635 states and 10717 transitions. [2019-10-22 08:54:52,329 INFO L711 BuchiCegarLoop]: Abstraction has 7635 states and 10717 transitions. [2019-10-22 08:54:52,329 INFO L591 BuchiCegarLoop]: Abstraction has 7635 states and 10717 transitions. [2019-10-22 08:54:52,329 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-10-22 08:54:52,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7635 states and 10717 transitions. [2019-10-22 08:54:52,349 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7432 [2019-10-22 08:54:52,349 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:52,349 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:52,351 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:52,351 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:52,351 INFO L791 eck$LassoCheckResult]: Stem: 74019#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 73902#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 73903#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 73568#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 73569#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 73678#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73679#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73573#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73574#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 73846#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 73847#L481-1 assume !(0 == ~M_E~0); 74035#L660-1 assume !(0 == ~T1_E~0); 73478#L665-1 assume !(0 == ~T2_E~0); 73479#L670-1 assume !(0 == ~T3_E~0); 73581#L675-1 assume !(0 == ~T4_E~0); 73582#L680-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 74114#L685-1 assume !(0 == ~T6_E~0); 74152#L690-1 assume !(0 == ~E_1~0); 74153#L695-1 assume !(0 == ~E_2~0); 74095#L700-1 assume !(0 == ~E_3~0); 74096#L705-1 assume !(0 == ~E_4~0); 74191#L710-1 assume !(0 == ~E_5~0); 74190#L715-1 assume !(0 == ~E_6~0); 73514#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 73515#L310 assume !(1 == ~m_pc~0); 73870#L310-2 is_master_triggered_~__retres1~0 := 0; 73871#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 74189#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 74188#L815 assume !(0 != activate_threads_~tmp~1); 74187#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 73909#L329 assume !(1 == ~t1_pc~0); 73910#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 73924#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 74184#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 74117#L823 assume !(0 != activate_threads_~tmp___0~0); 74118#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 74183#L348 assume !(1 == ~t2_pc~0); 74182#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 74181#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 74138#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 73657#L831 assume !(0 != activate_threads_~tmp___1~0); 73644#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 73578#L367 assume !(1 == ~t3_pc~0); 73547#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 73548#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 73577#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 73863#L839 assume !(0 != activate_threads_~tmp___2~0); 73864#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 74175#L386 assume !(1 == ~t4_pc~0); 74173#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 74172#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 73690#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 73691#L847 assume !(0 != activate_threads_~tmp___3~0); 74039#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 74040#L405 assume !(1 == ~t5_pc~0); 74169#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 74109#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 73950#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 73951#L855 assume !(0 != activate_threads_~tmp___4~0); 74047#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 73624#L424 assume !(1 == ~t6_pc~0); 73625#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 73629#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 74162#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 74161#L863 assume !(0 != activate_threads_~tmp___5~0); 74160#L863-2 assume !(1 == ~M_E~0); 74094#L733-1 assume !(1 == ~T1_E~0); 74000#L738-1 assume !(1 == ~T2_E~0); 73647#L743-1 assume !(1 == ~T3_E~0); 73648#L748-1 assume !(1 == ~T4_E~0); 73509#L753-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 73510#L758-1 assume !(1 == ~T6_E~0); 73593#L763-1 assume !(1 == ~E_1~0); 73594#L768-1 assume !(1 == ~E_2~0); 73850#L773-1 assume !(1 == ~E_3~0); 73851#L778-1 assume !(1 == ~E_4~0); 73727#L783-1 assume !(1 == ~E_5~0); 73728#L788-1 assume !(1 == ~E_6~0); 74092#L1014-1 [2019-10-22 08:54:52,351 INFO L793 eck$LassoCheckResult]: Loop: 74092#L1014-1 assume !false; 76352#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 76346#L635 assume !false; 76344#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 76338#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 76331#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 76329#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 76326#L546 assume !(0 != eval_~tmp~0); 76327#L650 start_simulation_~kernel_st~0 := 2; 76544#L444-1 start_simulation_~kernel_st~0 := 3; 76542#L660-2 assume !(0 == ~M_E~0); 76540#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76538#L665-3 assume !(0 == ~T2_E~0); 76536#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 76534#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76531#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76529#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76527#L690-3 assume !(0 == ~E_1~0); 76524#L695-3 assume !(0 == ~E_2~0); 76522#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76520#L705-3 assume !(0 == ~E_4~0); 76518#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76516#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76514#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 76512#L310-21 assume !(1 == ~m_pc~0); 76510#L310-23 is_master_triggered_~__retres1~0 := 0; 76508#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 76506#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 76504#L815-21 assume !(0 != activate_threads_~tmp~1); 76502#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 76500#L329-21 assume !(1 == ~t1_pc~0); 76496#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 76494#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 76492#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 76490#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 76488#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 76486#L348-21 assume !(1 == ~t2_pc~0); 76484#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 76482#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76480#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 76479#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 76478#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76477#L367-21 assume !(1 == ~t3_pc~0); 76476#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 76475#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 76474#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 76472#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 76470#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 76468#L386-21 assume !(1 == ~t4_pc~0); 76465#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 76463#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 76461#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 76458#L847-21 assume !(0 != activate_threads_~tmp___3~0); 76456#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 76454#L405-21 assume !(1 == ~t5_pc~0); 76452#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 76450#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 76448#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 76446#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 76444#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 76442#L424-21 assume !(1 == ~t6_pc~0); 76439#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 76437#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 76435#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 76433#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 76431#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 76429#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76427#L738-3 assume !(1 == ~T2_E~0); 76425#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76423#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76420#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76417#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76415#L763-3 assume !(1 == ~E_1~0); 76413#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 76411#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76409#L778-3 assume !(1 == ~E_4~0); 76407#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 76405#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 76403#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 76383#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 76382#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 76378#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 76374#L1033 assume !(0 == start_simulation_~tmp~3); 76372#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 76365#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 76363#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 76361#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 76360#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 76359#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 76357#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 76355#L1046 assume !(0 != start_simulation_~tmp___0~1); 74092#L1014-1 [2019-10-22 08:54:52,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:52,351 INFO L82 PathProgramCache]: Analyzing trace with hash 793462387, now seen corresponding path program 1 times [2019-10-22 08:54:52,352 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:52,352 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014298258] [2019-10-22 08:54:52,352 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,352 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,352 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:52,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:52,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:52,376 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1014298258] [2019-10-22 08:54:52,376 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:52,376 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:54:52,376 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1632992733] [2019-10-22 08:54:52,376 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:52,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:52,377 INFO L82 PathProgramCache]: Analyzing trace with hash 1287912262, now seen corresponding path program 1 times [2019-10-22 08:54:52,377 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:52,377 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636524810] [2019-10-22 08:54:52,377 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,377 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,377 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:52,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:52,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:52,410 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636524810] [2019-10-22 08:54:52,410 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:52,410 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:54:52,410 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852408735] [2019-10-22 08:54:52,410 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:52,411 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:52,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:52,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:52,411 INFO L87 Difference]: Start difference. First operand 7635 states and 10717 transitions. cyclomatic complexity: 3098 Second operand 3 states. [2019-10-22 08:54:52,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:52,449 INFO L93 Difference]: Finished difference Result 6617 states and 9262 transitions. [2019-10-22 08:54:52,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:52,450 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6617 states and 9262 transitions. [2019-10-22 08:54:52,475 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6472 [2019-10-22 08:54:52,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6617 states to 6617 states and 9262 transitions. [2019-10-22 08:54:52,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6617 [2019-10-22 08:54:52,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6617 [2019-10-22 08:54:52,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6617 states and 9262 transitions. [2019-10-22 08:54:52,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:52,510 INFO L688 BuchiCegarLoop]: Abstraction has 6617 states and 9262 transitions. [2019-10-22 08:54:52,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6617 states and 9262 transitions. [2019-10-22 08:54:52,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6617 to 6617. [2019-10-22 08:54:52,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6617 states. [2019-10-22 08:54:52,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6617 states to 6617 states and 9262 transitions. [2019-10-22 08:54:52,608 INFO L711 BuchiCegarLoop]: Abstraction has 6617 states and 9262 transitions. [2019-10-22 08:54:52,608 INFO L591 BuchiCegarLoop]: Abstraction has 6617 states and 9262 transitions. [2019-10-22 08:54:52,608 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-10-22 08:54:52,608 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6617 states and 9262 transitions. [2019-10-22 08:54:52,629 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6472 [2019-10-22 08:54:52,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:52,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:52,630 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:52,630 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:52,631 INFO L791 eck$LassoCheckResult]: Stem: 88275#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 88161#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 88162#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 87829#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 87830#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87945#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87946#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87831#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87832#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 88108#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 88109#L481-1 assume !(0 == ~M_E~0); 88291#L660-1 assume !(0 == ~T1_E~0); 87741#L665-1 assume !(0 == ~T2_E~0); 87742#L670-1 assume !(0 == ~T3_E~0); 87839#L675-1 assume !(0 == ~T4_E~0); 87840#L680-1 assume !(0 == ~T5_E~0); 88119#L685-1 assume !(0 == ~T6_E~0); 88120#L690-1 assume !(0 == ~E_1~0); 88001#L695-1 assume !(0 == ~E_2~0); 88002#L700-1 assume !(0 == ~E_3~0); 88257#L705-1 assume !(0 == ~E_4~0); 87905#L710-1 assume !(0 == ~E_5~0); 87906#L715-1 assume !(0 == ~E_6~0); 87773#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87774#L310 assume !(1 == ~m_pc~0); 87970#L310-2 is_master_triggered_~__retres1~0 := 0; 87968#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 87969#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 88092#L815 assume !(0 != activate_threads_~tmp~1); 88253#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 88165#L329 assume !(1 == ~t1_pc~0); 88166#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 88163#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 88164#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 88289#L823 assume !(0 != activate_threads_~tmp___0~0); 88365#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 88340#L348 assume !(1 == ~t2_pc~0); 88341#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 88338#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 88339#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 87913#L831 assume !(0 != activate_threads_~tmp___1~0); 87900#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87836#L367 assume !(1 == ~t3_pc~0); 87805#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 87806#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 87835#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 87950#L839 assume !(0 != activate_threads_~tmp___2~0); 88127#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 88049#L386 assume !(1 == ~t4_pc~0); 87959#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 88048#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 87956#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 87957#L847 assume !(0 != activate_threads_~tmp___3~0); 88294#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 88295#L405 assume !(1 == ~t5_pc~0); 88242#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 88243#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 88207#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 88208#L855 assume !(0 != activate_threads_~tmp___4~0); 88300#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 87880#L424 assume !(1 == ~t6_pc~0); 87881#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 87878#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 87879#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 87793#L863 assume !(0 != activate_threads_~tmp___5~0); 87763#L863-2 assume !(1 == ~M_E~0); 87764#L733-1 assume !(1 == ~T1_E~0); 88255#L738-1 assume !(1 == ~T2_E~0); 87903#L743-1 assume !(1 == ~T3_E~0); 87904#L748-1 assume !(1 == ~T4_E~0); 87768#L753-1 assume !(1 == ~T5_E~0); 87769#L758-1 assume !(1 == ~T6_E~0); 87850#L763-1 assume !(1 == ~E_1~0); 87851#L768-1 assume !(1 == ~E_2~0); 88114#L773-1 assume !(1 == ~E_3~0); 88115#L778-1 assume !(1 == ~E_4~0); 87994#L783-1 assume !(1 == ~E_5~0); 87995#L788-1 assume !(1 == ~E_6~0); 88352#L1014-1 [2019-10-22 08:54:52,631 INFO L793 eck$LassoCheckResult]: Loop: 88352#L1014-1 assume !false; 90990#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 90983#L635 assume !false; 90980#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 90896#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 90887#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 90462#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 90460#L546 assume !(0 != eval_~tmp~0); 90461#L650 start_simulation_~kernel_st~0 := 2; 91215#L444-1 start_simulation_~kernel_st~0 := 3; 91214#L660-2 assume !(0 == ~M_E~0); 91213#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 91212#L665-3 assume !(0 == ~T2_E~0); 91211#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 91210#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 91209#L680-3 assume !(0 == ~T5_E~0); 91208#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 91207#L690-3 assume !(0 == ~E_1~0); 91206#L695-3 assume !(0 == ~E_2~0); 91205#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 91204#L705-3 assume !(0 == ~E_4~0); 91203#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 91202#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 91201#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 91200#L310-21 assume !(1 == ~m_pc~0); 91199#L310-23 is_master_triggered_~__retres1~0 := 0; 91198#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 91197#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 91196#L815-21 assume !(0 != activate_threads_~tmp~1); 91195#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 91193#L329-21 assume !(1 == ~t1_pc~0); 91190#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 91188#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 91186#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 91184#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 91182#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 91179#L348-21 assume !(1 == ~t2_pc~0); 91177#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 91175#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 91173#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 91171#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 91169#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 91167#L367-21 assume !(1 == ~t3_pc~0); 91165#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 91163#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 91161#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 91159#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 91157#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 91155#L386-21 assume !(1 == ~t4_pc~0); 91152#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 91150#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 91148#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 91145#L847-21 assume !(0 != activate_threads_~tmp___3~0); 91142#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 91138#L405-21 assume !(1 == ~t5_pc~0); 91135#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 91132#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 91129#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 91125#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 91122#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 91119#L424-21 assume !(1 == ~t6_pc~0); 91115#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 91112#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 91109#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 91106#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 91102#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 91099#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 91095#L738-3 assume !(1 == ~T2_E~0); 91092#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 91089#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 91086#L753-3 assume !(1 == ~T5_E~0); 91083#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 91080#L763-3 assume !(1 == ~E_1~0); 91077#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 91074#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 91071#L778-3 assume !(1 == ~E_4~0); 91067#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 91064#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 91061#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 91048#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 91044#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 91040#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 91035#L1033 assume !(0 == start_simulation_~tmp~3); 91031#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 91021#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 91017#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 91014#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 91010#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 91007#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 91002#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 90999#L1046 assume !(0 != start_simulation_~tmp___0~1); 88352#L1014-1 [2019-10-22 08:54:52,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:52,631 INFO L82 PathProgramCache]: Analyzing trace with hash -433280845, now seen corresponding path program 2 times [2019-10-22 08:54:52,632 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:52,632 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276409631] [2019-10-22 08:54:52,632 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,632 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,632 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:52,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:52,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:52,699 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:52,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:52,700 INFO L82 PathProgramCache]: Analyzing trace with hash -366722810, now seen corresponding path program 1 times [2019-10-22 08:54:52,700 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:52,700 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050333026] [2019-10-22 08:54:52,700 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,700 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:52,700 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:52,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:52,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:52,735 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050333026] [2019-10-22 08:54:52,735 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:52,736 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:54:52,736 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83262737] [2019-10-22 08:54:52,736 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:52,736 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:52,736 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:54:52,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:54:52,737 INFO L87 Difference]: Start difference. First operand 6617 states and 9262 transitions. cyclomatic complexity: 2661 Second operand 5 states. [2019-10-22 08:54:52,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:52,881 INFO L93 Difference]: Finished difference Result 11809 states and 16318 transitions. [2019-10-22 08:54:52,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-10-22 08:54:52,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11809 states and 16318 transitions. [2019-10-22 08:54:52,923 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11600 [2019-10-22 08:54:52,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11809 states to 11809 states and 16318 transitions. [2019-10-22 08:54:52,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11809 [2019-10-22 08:54:52,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11809 [2019-10-22 08:54:52,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11809 states and 16318 transitions. [2019-10-22 08:54:52,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:52,980 INFO L688 BuchiCegarLoop]: Abstraction has 11809 states and 16318 transitions. [2019-10-22 08:54:52,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11809 states and 16318 transitions. [2019-10-22 08:54:53,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11809 to 6665. [2019-10-22 08:54:53,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6665 states. [2019-10-22 08:54:53,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6665 states to 6665 states and 9310 transitions. [2019-10-22 08:54:53,093 INFO L711 BuchiCegarLoop]: Abstraction has 6665 states and 9310 transitions. [2019-10-22 08:54:53,093 INFO L591 BuchiCegarLoop]: Abstraction has 6665 states and 9310 transitions. [2019-10-22 08:54:53,093 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-10-22 08:54:53,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6665 states and 9310 transitions. [2019-10-22 08:54:53,111 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6520 [2019-10-22 08:54:53,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:53,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:53,112 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:53,112 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:53,112 INFO L791 eck$LassoCheckResult]: Stem: 106761#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 106630#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 106631#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 106272#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 106273#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106391#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 106392#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 106274#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 106275#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 106569#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 106570#L481-1 assume !(0 == ~M_E~0); 106779#L660-1 assume !(0 == ~T1_E~0); 106183#L665-1 assume !(0 == ~T2_E~0); 106184#L670-1 assume !(0 == ~T3_E~0); 106282#L675-1 assume !(0 == ~T4_E~0); 106283#L680-1 assume !(0 == ~T5_E~0); 106578#L685-1 assume !(0 == ~T6_E~0); 106579#L690-1 assume !(0 == ~E_1~0); 106447#L695-1 assume !(0 == ~E_2~0); 106448#L700-1 assume !(0 == ~E_3~0); 106741#L705-1 assume !(0 == ~E_4~0); 106347#L710-1 assume !(0 == ~E_5~0); 106348#L715-1 assume !(0 == ~E_6~0); 106216#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 106217#L310 assume !(1 == ~m_pc~0); 106416#L310-2 is_master_triggered_~__retres1~0 := 0; 106414#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 106415#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 106549#L815 assume !(0 != activate_threads_~tmp~1); 106737#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 106634#L329 assume !(1 == ~t1_pc~0); 106635#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 106632#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 106633#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 106775#L823 assume !(0 != activate_threads_~tmp___0~0); 106866#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 106834#L348 assume !(1 == ~t2_pc~0); 106835#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 106832#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 106833#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 106355#L831 assume !(0 != activate_threads_~tmp___1~0); 106342#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 106279#L367 assume !(1 == ~t3_pc~0); 106247#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 106248#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 106278#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 106396#L839 assume !(0 != activate_threads_~tmp___2~0); 106589#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 106501#L386 assume !(1 == ~t4_pc~0); 106405#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 106500#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 106402#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 106403#L847 assume !(0 != activate_threads_~tmp___3~0); 106788#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 106789#L405 assume !(1 == ~t5_pc~0); 106726#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 106727#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 106675#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 106676#L855 assume !(0 != activate_threads_~tmp___4~0); 106795#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 106323#L424 assume !(1 == ~t6_pc~0); 106324#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 106321#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 106322#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 106235#L863 assume !(0 != activate_threads_~tmp___5~0); 106206#L863-2 assume !(1 == ~M_E~0); 106207#L733-1 assume !(1 == ~T1_E~0); 106739#L738-1 assume !(1 == ~T2_E~0); 106345#L743-1 assume !(1 == ~T3_E~0); 106346#L748-1 assume !(1 == ~T4_E~0); 106211#L753-1 assume !(1 == ~T5_E~0); 106212#L758-1 assume !(1 == ~T6_E~0); 106292#L763-1 assume !(1 == ~E_1~0); 106293#L768-1 assume !(1 == ~E_2~0); 106573#L773-1 assume !(1 == ~E_3~0); 106574#L778-1 assume !(1 == ~E_4~0); 106440#L783-1 assume !(1 == ~E_5~0); 106441#L788-1 assume !(1 == ~E_6~0); 106847#L1014-1 [2019-10-22 08:54:53,113 INFO L793 eck$LassoCheckResult]: Loop: 106847#L1014-1 assume !false; 108355#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 108351#L635 assume !false; 108350#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 108348#L494 assume !(0 == ~m_st~0); 108349#L498 assume !(0 == ~t1_st~0); 108344#L502 assume !(0 == ~t2_st~0); 108345#L506 assume !(0 == ~t3_st~0); 108347#L510 assume !(0 == ~t4_st~0); 108342#L514 assume !(0 == ~t5_st~0); 108343#L518 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 108346#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 107967#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 107968#L546 assume !(0 != eval_~tmp~0); 108460#L650 start_simulation_~kernel_st~0 := 2; 108459#L444-1 start_simulation_~kernel_st~0 := 3; 108458#L660-2 assume !(0 == ~M_E~0); 108457#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 108456#L665-3 assume !(0 == ~T2_E~0); 108455#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 108454#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 108453#L680-3 assume !(0 == ~T5_E~0); 108452#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 108451#L690-3 assume !(0 == ~E_1~0); 108450#L695-3 assume !(0 == ~E_2~0); 108449#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 108448#L705-3 assume !(0 == ~E_4~0); 108447#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 108446#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 108445#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 108444#L310-21 assume !(1 == ~m_pc~0); 108443#L310-23 is_master_triggered_~__retres1~0 := 0; 108442#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 108441#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 108440#L815-21 assume !(0 != activate_threads_~tmp~1); 108439#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 108438#L329-21 assume !(1 == ~t1_pc~0); 108436#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 108435#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 108434#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 108433#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 108432#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 108431#L348-21 assume !(1 == ~t2_pc~0); 108430#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 108429#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 108428#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 108427#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 108426#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 108425#L367-21 assume !(1 == ~t3_pc~0); 108424#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 108423#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 108422#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 108421#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 108420#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 108419#L386-21 assume !(1 == ~t4_pc~0); 108417#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 108416#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 108415#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 108414#L847-21 assume !(0 != activate_threads_~tmp___3~0); 108413#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 108412#L405-21 assume !(1 == ~t5_pc~0); 108411#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 108410#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 108409#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 108408#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 108407#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 108406#L424-21 assume 1 == ~t6_pc~0; 108405#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 108403#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 108402#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 108401#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 108400#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 108399#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 108398#L738-3 assume !(1 == ~T2_E~0); 108397#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 108396#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 108395#L753-3 assume !(1 == ~T5_E~0); 108394#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 108393#L763-3 assume !(1 == ~E_1~0); 108392#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 108391#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 108390#L778-3 assume !(1 == ~E_4~0); 108389#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 108388#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 108387#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 108380#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 108378#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 108376#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 108373#L1033 assume !(0 == start_simulation_~tmp~3); 108371#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 108365#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 108363#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 108362#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 108361#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 108360#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 108359#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 108358#L1046 assume !(0 != start_simulation_~tmp___0~1); 106847#L1014-1 [2019-10-22 08:54:53,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:53,113 INFO L82 PathProgramCache]: Analyzing trace with hash -433280845, now seen corresponding path program 3 times [2019-10-22 08:54:53,113 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:53,114 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1491356330] [2019-10-22 08:54:53,114 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:53,114 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:53,114 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:53,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:53,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:53,151 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:53,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:53,153 INFO L82 PathProgramCache]: Analyzing trace with hash -1277961130, now seen corresponding path program 1 times [2019-10-22 08:54:53,153 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:53,153 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068106450] [2019-10-22 08:54:53,153 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:53,153 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:53,153 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:53,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:53,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:53,185 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2068106450] [2019-10-22 08:54:53,185 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:53,185 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:53,186 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334883299] [2019-10-22 08:54:53,186 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:53,187 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:53,187 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:53,187 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:53,187 INFO L87 Difference]: Start difference. First operand 6665 states and 9310 transitions. cyclomatic complexity: 2661 Second operand 3 states. [2019-10-22 08:54:53,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:53,270 INFO L93 Difference]: Finished difference Result 12433 states and 17086 transitions. [2019-10-22 08:54:53,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:53,271 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12433 states and 17086 transitions. [2019-10-22 08:54:53,315 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12240 [2019-10-22 08:54:53,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12433 states to 12433 states and 17086 transitions. [2019-10-22 08:54:53,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12433 [2019-10-22 08:54:53,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12433 [2019-10-22 08:54:53,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12433 states and 17086 transitions. [2019-10-22 08:54:53,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:53,369 INFO L688 BuchiCegarLoop]: Abstraction has 12433 states and 17086 transitions. [2019-10-22 08:54:53,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12433 states and 17086 transitions. [2019-10-22 08:54:53,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12433 to 12085. [2019-10-22 08:54:53,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12085 states. [2019-10-22 08:54:53,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12085 states to 12085 states and 16634 transitions. [2019-10-22 08:54:53,502 INFO L711 BuchiCegarLoop]: Abstraction has 12085 states and 16634 transitions. [2019-10-22 08:54:53,502 INFO L591 BuchiCegarLoop]: Abstraction has 12085 states and 16634 transitions. [2019-10-22 08:54:53,502 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-10-22 08:54:53,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12085 states and 16634 transitions. [2019-10-22 08:54:53,535 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11892 [2019-10-22 08:54:53,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:53,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:53,536 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:53,537 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:53,537 INFO L791 eck$LassoCheckResult]: Stem: 125910#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 125772#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 125773#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 125381#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 125382#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 125512#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125513#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125386#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 125387#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 125706#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 125707#L481-1 assume !(0 == ~M_E~0); 125932#L660-1 assume !(0 == ~T1_E~0); 125285#L665-1 assume !(0 == ~T2_E~0); 125286#L670-1 assume !(0 == ~T3_E~0); 125394#L675-1 assume !(0 == ~T4_E~0); 125395#L680-1 assume !(0 == ~T5_E~0); 125716#L685-1 assume !(0 == ~T6_E~0); 125717#L690-1 assume !(0 == ~E_1~0); 125566#L695-1 assume !(0 == ~E_2~0); 125567#L700-1 assume !(0 == ~E_3~0); 125887#L705-1 assume !(0 == ~E_4~0); 125465#L710-1 assume !(0 == ~E_5~0); 125466#L715-1 assume !(0 == ~E_6~0); 125322#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 125323#L310 assume !(1 == ~m_pc~0); 125535#L310-2 is_master_triggered_~__retres1~0 := 0; 125531#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 125532#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 125681#L815 assume !(0 != activate_threads_~tmp~1); 125883#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 125779#L329 assume !(1 == ~t1_pc~0); 125780#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 125774#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 125775#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 125928#L823 assume !(0 != activate_threads_~tmp___0~0); 126032#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 125993#L348 assume !(1 == ~t2_pc~0); 125994#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 125989#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 125990#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 125473#L831 assume !(0 != activate_threads_~tmp___1~0); 125460#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 125391#L367 assume !(1 == ~t3_pc~0); 125358#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 125359#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 125390#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 125515#L839 assume !(0 != activate_threads_~tmp___2~0); 125728#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 125623#L386 assume !(1 == ~t4_pc~0); 125524#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 125622#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 125521#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 125522#L847 assume !(0 != activate_threads_~tmp___3~0); 125941#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 125942#L405 assume !(1 == ~t5_pc~0); 125864#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 125865#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 125821#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 125822#L855 assume !(0 != activate_threads_~tmp___4~0); 125950#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 125438#L424 assume !(1 == ~t6_pc~0); 125439#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 125434#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 125435#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 125341#L863 assume !(0 != activate_threads_~tmp___5~0); 125309#L863-2 assume !(1 == ~M_E~0); 125310#L733-1 assume !(1 == ~T1_E~0); 125885#L738-1 assume !(1 == ~T2_E~0); 125463#L743-1 assume !(1 == ~T3_E~0); 125464#L748-1 assume !(1 == ~T4_E~0); 125316#L753-1 assume !(1 == ~T5_E~0); 125317#L758-1 assume !(1 == ~T6_E~0); 125406#L763-1 assume !(1 == ~E_1~0); 125407#L768-1 assume !(1 == ~E_2~0); 125710#L773-1 assume !(1 == ~E_3~0); 125711#L778-1 assume !(1 == ~E_4~0); 125557#L783-1 assume !(1 == ~E_5~0); 125558#L788-1 assume !(1 == ~E_6~0); 126008#L1014-1 [2019-10-22 08:54:53,537 INFO L793 eck$LassoCheckResult]: Loop: 126008#L1014-1 assume !false; 132831#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 132823#L635 assume !false; 132821#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 132819#L494 assume !(0 == ~m_st~0); 132820#L498 assume !(0 == ~t1_st~0); 133023#L502 assume !(0 == ~t2_st~0); 133021#L506 assume !(0 == ~t3_st~0); 133019#L510 assume !(0 == ~t4_st~0); 133017#L514 assume !(0 == ~t5_st~0); 133014#L518 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 133012#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 133010#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 133008#L546 assume !(0 != eval_~tmp~0); 133006#L650 start_simulation_~kernel_st~0 := 2; 133004#L444-1 start_simulation_~kernel_st~0 := 3; 133002#L660-2 assume !(0 == ~M_E~0); 133000#L660-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 132998#L665-3 assume !(0 == ~T2_E~0); 132996#L670-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 132994#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 132992#L680-3 assume !(0 == ~T5_E~0); 132990#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 132987#L690-3 assume !(0 == ~E_1~0); 132985#L695-3 assume !(0 == ~E_2~0); 132983#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 132981#L705-3 assume !(0 == ~E_4~0); 132979#L710-3 assume 0 == ~E_5~0;~E_5~0 := 1; 132977#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 132975#L720-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 132973#L310-21 assume !(1 == ~m_pc~0); 132971#L310-23 is_master_triggered_~__retres1~0 := 0; 132969#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 132967#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 132964#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 132962#L815-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 132959#L329-21 assume !(1 == ~t1_pc~0); 132956#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 132954#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 132952#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 132950#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 132948#L823-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 132946#L348-21 assume !(1 == ~t2_pc~0); 132944#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 132942#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 132940#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 132938#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 132936#L831-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 132934#L367-21 assume !(1 == ~t3_pc~0); 132932#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 132930#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 132928#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 132927#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 132926#L839-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 132925#L386-21 assume !(1 == ~t4_pc~0); 132923#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 132922#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 132921#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 132919#L847-21 assume !(0 != activate_threads_~tmp___3~0); 132917#L847-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 132915#L405-21 assume !(1 == ~t5_pc~0); 132913#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 132910#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 132908#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 132905#L855-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 132903#L855-23 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 132901#L424-21 assume !(1 == ~t6_pc~0); 132898#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 132896#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 132894#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 132892#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 132890#L863-23 assume 1 == ~M_E~0;~M_E~0 := 2; 132888#L733-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 132886#L738-3 assume !(1 == ~T2_E~0); 132884#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 132882#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 132880#L753-3 assume !(1 == ~T5_E~0); 132878#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 132876#L763-3 assume !(1 == ~E_1~0); 132874#L768-3 assume 1 == ~E_2~0;~E_2~0 := 2; 132872#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 132870#L778-3 assume !(1 == ~E_4~0); 132867#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 132865#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 132863#L793-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 132860#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 132858#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 132856#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 132853#L1033 assume !(0 == start_simulation_~tmp~3); 132850#L1033-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 132847#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 132845#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 132843#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 132841#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 132839#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 132836#L996 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 132834#L1046 assume !(0 != start_simulation_~tmp___0~1); 126008#L1014-1 [2019-10-22 08:54:53,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:53,538 INFO L82 PathProgramCache]: Analyzing trace with hash -433280845, now seen corresponding path program 4 times [2019-10-22 08:54:53,538 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:53,538 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266967455] [2019-10-22 08:54:53,538 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:53,538 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:53,538 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:53,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:53,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:53,570 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:53,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:53,571 INFO L82 PathProgramCache]: Analyzing trace with hash 1662931797, now seen corresponding path program 1 times [2019-10-22 08:54:53,571 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:53,571 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668912384] [2019-10-22 08:54:53,572 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:53,572 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:53,572 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:53,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:53,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:53,620 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668912384] [2019-10-22 08:54:53,620 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:53,620 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-22 08:54:53,621 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [592027184] [2019-10-22 08:54:53,621 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-10-22 08:54:53,621 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:53,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-22 08:54:53,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-22 08:54:53,621 INFO L87 Difference]: Start difference. First operand 12085 states and 16634 transitions. cyclomatic complexity: 4565 Second operand 5 states. [2019-10-22 08:54:53,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:53,863 INFO L93 Difference]: Finished difference Result 19771 states and 27099 transitions. [2019-10-22 08:54:53,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-22 08:54:53,864 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19771 states and 27099 transitions. [2019-10-22 08:54:53,931 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19480 [2019-10-22 08:54:53,991 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19771 states to 19771 states and 27099 transitions. [2019-10-22 08:54:53,991 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19771 [2019-10-22 08:54:54,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19771 [2019-10-22 08:54:54,003 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19771 states and 27099 transitions. [2019-10-22 08:54:54,017 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:54,017 INFO L688 BuchiCegarLoop]: Abstraction has 19771 states and 27099 transitions. [2019-10-22 08:54:54,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19771 states and 27099 transitions. [2019-10-22 08:54:54,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19771 to 11327. [2019-10-22 08:54:54,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11327 states. [2019-10-22 08:54:54,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11327 states to 11327 states and 15427 transitions. [2019-10-22 08:54:54,368 INFO L711 BuchiCegarLoop]: Abstraction has 11327 states and 15427 transitions. [2019-10-22 08:54:54,368 INFO L591 BuchiCegarLoop]: Abstraction has 11327 states and 15427 transitions. [2019-10-22 08:54:54,368 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-10-22 08:54:54,368 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11327 states and 15427 transitions. [2019-10-22 08:54:54,392 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 11132 [2019-10-22 08:54:54,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:54,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:54,393 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:54,393 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:54,393 INFO L791 eck$LassoCheckResult]: Stem: 157730#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 157610#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 157611#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 157245#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 157246#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 157360#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 157361#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 157250#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157251#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 157540#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 157541#L481-1 assume !(0 == ~M_E~0); 157747#L660-1 assume !(0 == ~T1_E~0); 157154#L665-1 assume !(0 == ~T2_E~0); 157155#L670-1 assume !(0 == ~T3_E~0); 157258#L675-1 assume !(0 == ~T4_E~0); 157259#L680-1 assume !(0 == ~T5_E~0); 157551#L685-1 assume !(0 == ~T6_E~0); 157552#L690-1 assume !(0 == ~E_1~0); 157416#L695-1 assume !(0 == ~E_2~0); 157417#L700-1 assume !(0 == ~E_3~0); 157713#L705-1 assume !(0 == ~E_4~0); 157325#L710-1 assume !(0 == ~E_5~0); 157326#L715-1 assume !(0 == ~E_6~0); 157188#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 157189#L310 assume !(1 == ~m_pc~0); 157385#L310-2 is_master_triggered_~__retres1~0 := 0; 157381#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 157382#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 157517#L815 assume !(0 != activate_threads_~tmp~1); 157708#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 157617#L329 assume !(1 == ~t1_pc~0); 157618#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 157612#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 157613#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 157745#L823 assume !(0 != activate_threads_~tmp___0~0); 157827#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 157799#L348 assume !(1 == ~t2_pc~0); 157800#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 157796#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 157797#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 157333#L831 assume !(0 != activate_threads_~tmp___1~0); 157320#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 157255#L367 assume !(1 == ~t3_pc~0); 157222#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 157223#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 157254#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 157364#L839 assume !(0 != activate_threads_~tmp___2~0); 157563#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 157467#L386 assume !(1 == ~t4_pc~0); 157374#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 157466#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 157371#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 157372#L847 assume !(0 != activate_threads_~tmp___3~0); 157751#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 157752#L405 assume !(1 == ~t5_pc~0); 157696#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 157697#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 157657#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 157658#L855 assume !(0 != activate_threads_~tmp___4~0); 157759#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 157300#L424 assume !(1 == ~t6_pc~0); 157301#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 157296#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 157297#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 157206#L863 assume !(0 != activate_threads_~tmp___5~0); 157176#L863-2 assume !(1 == ~M_E~0); 157177#L733-1 assume !(1 == ~T1_E~0); 157711#L738-1 assume !(1 == ~T2_E~0); 157323#L743-1 assume !(1 == ~T3_E~0); 157324#L748-1 assume !(1 == ~T4_E~0); 157184#L753-1 assume !(1 == ~T5_E~0); 157185#L758-1 assume !(1 == ~T6_E~0); 157269#L763-1 assume !(1 == ~E_1~0); 157270#L768-1 assume !(1 == ~E_2~0); 157544#L773-1 assume !(1 == ~E_3~0); 157545#L778-1 assume !(1 == ~E_4~0); 157407#L783-1 assume !(1 == ~E_5~0); 157408#L788-1 assume !(1 == ~E_6~0); 157810#L1014-1 assume !false; 158419#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 158410#L635 [2019-10-22 08:54:54,393 INFO L793 eck$LassoCheckResult]: Loop: 158410#L635 assume !false; 158403#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 158395#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 158390#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 158385#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 158381#L546 assume 0 != eval_~tmp~0; 158368#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 158360#L554 assume !(0 != eval_~tmp_ndt_1~0); 158351#L551 assume !(0 == ~t1_st~0); 158344#L565 assume !(0 == ~t2_st~0); 158338#L579 assume !(0 == ~t3_st~0); 158440#L593 assume !(0 == ~t4_st~0); 158429#L607 assume !(0 == ~t5_st~0); 158417#L621 assume !(0 == ~t6_st~0); 158410#L635 [2019-10-22 08:54:54,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:54,394 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 1 times [2019-10-22 08:54:54,394 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:54,394 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790323215] [2019-10-22 08:54:54,394 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:54,394 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:54,394 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:54,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:54,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:54,422 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:54,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:54,422 INFO L82 PathProgramCache]: Analyzing trace with hash -435712619, now seen corresponding path program 1 times [2019-10-22 08:54:54,422 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:54,422 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561442008] [2019-10-22 08:54:54,422 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:54,422 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:54,423 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:54,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:54,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:54,429 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:54,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:54,429 INFO L82 PathProgramCache]: Analyzing trace with hash -1300950615, now seen corresponding path program 1 times [2019-10-22 08:54:54,430 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:54,430 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589865400] [2019-10-22 08:54:54,430 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:54,430 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:54,430 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:54,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:54,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:54,461 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [589865400] [2019-10-22 08:54:54,461 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:54,461 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:54,461 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775595501] [2019-10-22 08:54:54,539 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:54,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:54,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:54,540 INFO L87 Difference]: Start difference. First operand 11327 states and 15427 transitions. cyclomatic complexity: 4124 Second operand 3 states. [2019-10-22 08:54:54,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:54,658 INFO L93 Difference]: Finished difference Result 21249 states and 28688 transitions. [2019-10-22 08:54:54,658 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:54,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21249 states and 28688 transitions. [2019-10-22 08:54:54,729 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 20864 [2019-10-22 08:54:54,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21249 states to 21249 states and 28688 transitions. [2019-10-22 08:54:54,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21249 [2019-10-22 08:54:54,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21249 [2019-10-22 08:54:54,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21249 states and 28688 transitions. [2019-10-22 08:54:54,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:54,813 INFO L688 BuchiCegarLoop]: Abstraction has 21249 states and 28688 transitions. [2019-10-22 08:54:54,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21249 states and 28688 transitions. [2019-10-22 08:54:54,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21249 to 20081. [2019-10-22 08:54:54,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20081 states. [2019-10-22 08:54:55,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20081 states to 20081 states and 27200 transitions. [2019-10-22 08:54:55,026 INFO L711 BuchiCegarLoop]: Abstraction has 20081 states and 27200 transitions. [2019-10-22 08:54:55,026 INFO L591 BuchiCegarLoop]: Abstraction has 20081 states and 27200 transitions. [2019-10-22 08:54:55,026 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-10-22 08:54:55,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20081 states and 27200 transitions. [2019-10-22 08:54:55,081 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19696 [2019-10-22 08:54:55,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:55,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:55,082 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:55,082 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:55,083 INFO L791 eck$LassoCheckResult]: Stem: 190305#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 190188#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 190189#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 189830#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 189831#L451-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 190321#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 192187#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 192186#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 192185#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 192184#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 192183#L481-1 assume !(0 == ~M_E~0); 192182#L660-1 assume !(0 == ~T1_E~0); 192181#L665-1 assume !(0 == ~T2_E~0); 192180#L670-1 assume !(0 == ~T3_E~0); 192179#L675-1 assume !(0 == ~T4_E~0); 192178#L680-1 assume !(0 == ~T5_E~0); 192177#L685-1 assume !(0 == ~T6_E~0); 192176#L690-1 assume !(0 == ~E_1~0); 192175#L695-1 assume !(0 == ~E_2~0); 192174#L700-1 assume !(0 == ~E_3~0); 192173#L705-1 assume !(0 == ~E_4~0); 192172#L710-1 assume !(0 == ~E_5~0); 192171#L715-1 assume !(0 == ~E_6~0); 192170#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 192169#L310 assume !(1 == ~m_pc~0); 192168#L310-2 is_master_triggered_~__retres1~0 := 0; 192167#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 192166#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 192165#L815 assume !(0 != activate_threads_~tmp~1); 192164#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 192162#L329 assume !(1 == ~t1_pc~0); 192161#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 192160#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 192159#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 192158#L823 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 190413#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 190379#L348 assume !(1 == ~t2_pc~0); 190380#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 190376#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 190377#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 189918#L831 assume !(0 != activate_threads_~tmp___1~0); 189904#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 189840#L367 assume !(1 == ~t3_pc~0); 189808#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 189809#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 189839#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 189942#L839 assume !(0 != activate_threads_~tmp___2~0); 192137#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 192136#L386 assume !(1 == ~t4_pc~0); 192134#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 192133#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 192132#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 192131#L847 assume !(0 != activate_threads_~tmp___3~0); 192130#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 192129#L405 assume !(1 == ~t5_pc~0); 192128#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 192127#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 192126#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 192125#L855 assume !(0 != activate_threads_~tmp___4~0); 192124#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 192123#L424 assume !(1 == ~t6_pc~0); 192122#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 192120#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 192119#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 192118#L863 assume !(0 != activate_threads_~tmp___5~0); 192117#L863-2 assume !(1 == ~M_E~0); 192116#L733-1 assume !(1 == ~T1_E~0); 192115#L738-1 assume !(1 == ~T2_E~0); 192114#L743-1 assume !(1 == ~T3_E~0); 192113#L748-1 assume !(1 == ~T4_E~0); 192112#L753-1 assume !(1 == ~T5_E~0); 192111#L758-1 assume !(1 == ~T6_E~0); 192110#L763-1 assume !(1 == ~E_1~0); 190414#L768-1 assume !(1 == ~E_2~0); 190126#L773-1 assume !(1 == ~E_3~0); 190127#L778-1 assume !(1 == ~E_4~0); 189986#L783-1 assume !(1 == ~E_5~0); 189987#L788-1 assume !(1 == ~E_6~0); 190394#L1014-1 assume !false; 192280#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 192274#L635 [2019-10-22 08:54:55,083 INFO L793 eck$LassoCheckResult]: Loop: 192274#L635 assume !false; 192272#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 192269#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 192267#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 192264#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 192239#L546 assume 0 != eval_~tmp~0; 192230#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 192215#L554 assume !(0 != eval_~tmp_ndt_1~0); 192191#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 191978#L568 assume !(0 != eval_~tmp_ndt_2~0); 191944#L565 assume !(0 == ~t2_st~0); 191940#L579 assume !(0 == ~t3_st~0); 191937#L593 assume !(0 == ~t4_st~0); 192333#L607 assume !(0 == ~t5_st~0); 192278#L621 assume !(0 == ~t6_st~0); 192274#L635 [2019-10-22 08:54:55,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:55,083 INFO L82 PathProgramCache]: Analyzing trace with hash 518305429, now seen corresponding path program 1 times [2019-10-22 08:54:55,083 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:55,083 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022485175] [2019-10-22 08:54:55,083 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:55,084 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:55,084 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:55,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:55,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:55,102 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022485175] [2019-10-22 08:54:55,103 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:55,103 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:55,103 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1251828482] [2019-10-22 08:54:55,103 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-10-22 08:54:55,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:55,103 INFO L82 PathProgramCache]: Analyzing trace with hash -2021030379, now seen corresponding path program 1 times [2019-10-22 08:54:55,104 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:55,104 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119657104] [2019-10-22 08:54:55,104 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:55,104 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:55,104 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:55,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:55,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:55,115 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:55,205 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:55,205 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:55,206 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:55,206 INFO L87 Difference]: Start difference. First operand 20081 states and 27200 transitions. cyclomatic complexity: 7143 Second operand 3 states. [2019-10-22 08:54:55,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:55,270 INFO L93 Difference]: Finished difference Result 20003 states and 27094 transitions. [2019-10-22 08:54:55,270 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:55,270 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20003 states and 27094 transitions. [2019-10-22 08:54:55,343 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19696 [2019-10-22 08:54:55,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20003 states to 20003 states and 27094 transitions. [2019-10-22 08:54:55,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20003 [2019-10-22 08:54:55,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20003 [2019-10-22 08:54:55,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20003 states and 27094 transitions. [2019-10-22 08:54:55,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:55,423 INFO L688 BuchiCegarLoop]: Abstraction has 20003 states and 27094 transitions. [2019-10-22 08:54:55,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20003 states and 27094 transitions. [2019-10-22 08:54:55,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20003 to 20003. [2019-10-22 08:54:55,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20003 states. [2019-10-22 08:54:55,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20003 states to 20003 states and 27094 transitions. [2019-10-22 08:54:55,619 INFO L711 BuchiCegarLoop]: Abstraction has 20003 states and 27094 transitions. [2019-10-22 08:54:55,619 INFO L591 BuchiCegarLoop]: Abstraction has 20003 states and 27094 transitions. [2019-10-22 08:54:55,619 INFO L424 BuchiCegarLoop]: ======== Iteration 22============ [2019-10-22 08:54:55,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20003 states and 27094 transitions. [2019-10-22 08:54:55,674 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19696 [2019-10-22 08:54:55,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:55,675 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:55,675 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:55,675 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:55,676 INFO L791 eck$LassoCheckResult]: Stem: 230399#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 230276#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 230277#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 229917#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 229918#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 230044#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 230045#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 229922#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 229923#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 230218#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 230219#L481-1 assume !(0 == ~M_E~0); 230416#L660-1 assume !(0 == ~T1_E~0); 229828#L665-1 assume !(0 == ~T2_E~0); 229829#L670-1 assume !(0 == ~T3_E~0); 229930#L675-1 assume !(0 == ~T4_E~0); 229931#L680-1 assume !(0 == ~T5_E~0); 230229#L685-1 assume !(0 == ~T6_E~0); 230230#L690-1 assume !(0 == ~E_1~0); 230101#L695-1 assume !(0 == ~E_2~0); 230102#L700-1 assume !(0 == ~E_3~0); 230383#L705-1 assume !(0 == ~E_4~0); 230001#L710-1 assume !(0 == ~E_5~0); 230002#L715-1 assume !(0 == ~E_6~0); 229862#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 229863#L310 assume !(1 == ~m_pc~0); 230070#L310-2 is_master_triggered_~__retres1~0 := 0; 230066#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 230067#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 230197#L815 assume !(0 != activate_threads_~tmp~1); 230379#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 230283#L329 assume !(1 == ~t1_pc~0); 230284#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 230278#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 230279#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 230414#L823 assume !(0 != activate_threads_~tmp___0~0); 230497#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 230468#L348 assume !(1 == ~t2_pc~0); 230469#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 230465#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 230466#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 230009#L831 assume !(0 != activate_threads_~tmp___1~0); 229996#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 229927#L367 assume !(1 == ~t3_pc~0); 229895#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 229896#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 229926#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 230047#L839 assume !(0 != activate_threads_~tmp___2~0); 230240#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 230152#L386 assume !(1 == ~t4_pc~0); 230059#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 230151#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 230056#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 230057#L847 assume !(0 != activate_threads_~tmp___3~0); 230420#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 230421#L405 assume !(1 == ~t5_pc~0); 230365#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 230366#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 230325#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 230326#L855 assume !(0 != activate_threads_~tmp___4~0); 230428#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 229975#L424 assume !(1 == ~t6_pc~0); 229976#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 229971#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 229972#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 229882#L863 assume !(0 != activate_threads_~tmp___5~0); 229850#L863-2 assume !(1 == ~M_E~0); 229851#L733-1 assume !(1 == ~T1_E~0); 230381#L738-1 assume !(1 == ~T2_E~0); 229999#L743-1 assume !(1 == ~T3_E~0); 230000#L748-1 assume !(1 == ~T4_E~0); 229858#L753-1 assume !(1 == ~T5_E~0); 229859#L758-1 assume !(1 == ~T6_E~0); 229942#L763-1 assume !(1 == ~E_1~0); 229943#L768-1 assume !(1 == ~E_2~0); 230222#L773-1 assume !(1 == ~E_3~0); 230223#L778-1 assume !(1 == ~E_4~0); 230092#L783-1 assume !(1 == ~E_5~0); 230093#L788-1 assume !(1 == ~E_6~0); 230480#L1014-1 assume !false; 232484#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 232478#L635 [2019-10-22 08:54:55,676 INFO L793 eck$LassoCheckResult]: Loop: 232478#L635 assume !false; 232476#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 232473#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 232470#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 232468#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 232467#L546 assume 0 != eval_~tmp~0; 232466#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 232464#L554 assume !(0 != eval_~tmp_ndt_1~0); 232462#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 232339#L568 assume !(0 != eval_~tmp_ndt_2~0); 232460#L565 assume !(0 == ~t2_st~0); 232508#L579 assume !(0 == ~t3_st~0); 232501#L593 assume !(0 == ~t4_st~0); 232498#L607 assume !(0 == ~t5_st~0); 232482#L621 assume !(0 == ~t6_st~0); 232478#L635 [2019-10-22 08:54:55,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:55,676 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 2 times [2019-10-22 08:54:55,676 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:55,676 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563745914] [2019-10-22 08:54:55,676 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:55,676 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:55,677 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:55,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:55,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:55,702 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:55,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:55,704 INFO L82 PathProgramCache]: Analyzing trace with hash -2021030379, now seen corresponding path program 2 times [2019-10-22 08:54:55,704 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:55,704 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565974587] [2019-10-22 08:54:55,707 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:55,707 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:55,707 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:55,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:55,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:55,713 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:55,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:55,713 INFO L82 PathProgramCache]: Analyzing trace with hash 1221362817, now seen corresponding path program 1 times [2019-10-22 08:54:55,713 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:55,716 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152266944] [2019-10-22 08:54:55,717 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:55,717 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:55,717 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:55,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:55,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:55,751 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152266944] [2019-10-22 08:54:55,751 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:55,752 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:55,752 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288755938] [2019-10-22 08:54:55,826 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:55,826 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:55,827 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:55,827 INFO L87 Difference]: Start difference. First operand 20003 states and 27094 transitions. cyclomatic complexity: 7115 Second operand 3 states. [2019-10-22 08:54:55,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:55,939 INFO L93 Difference]: Finished difference Result 26127 states and 35182 transitions. [2019-10-22 08:54:55,939 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:55,940 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26127 states and 35182 transitions. [2019-10-22 08:54:56,047 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 25740 [2019-10-22 08:54:56,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26127 states to 26127 states and 35182 transitions. [2019-10-22 08:54:56,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26127 [2019-10-22 08:54:56,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26127 [2019-10-22 08:54:56,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26127 states and 35182 transitions. [2019-10-22 08:54:56,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:56,350 INFO L688 BuchiCegarLoop]: Abstraction has 26127 states and 35182 transitions. [2019-10-22 08:54:56,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26127 states and 35182 transitions. [2019-10-22 08:54:56,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26127 to 25167. [2019-10-22 08:54:56,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25167 states. [2019-10-22 08:54:56,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25167 states to 25167 states and 33966 transitions. [2019-10-22 08:54:56,608 INFO L711 BuchiCegarLoop]: Abstraction has 25167 states and 33966 transitions. [2019-10-22 08:54:56,608 INFO L591 BuchiCegarLoop]: Abstraction has 25167 states and 33966 transitions. [2019-10-22 08:54:56,608 INFO L424 BuchiCegarLoop]: ======== Iteration 23============ [2019-10-22 08:54:56,608 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25167 states and 33966 transitions. [2019-10-22 08:54:56,683 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 24780 [2019-10-22 08:54:56,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:56,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:56,684 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:56,684 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:56,685 INFO L791 eck$LassoCheckResult]: Stem: 276549#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 276430#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 276431#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 276057#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 276058#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 276181#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 276182#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 276059#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 276060#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 276363#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 276364#L481-1 assume !(0 == ~M_E~0); 276566#L660-1 assume !(0 == ~T1_E~0); 275968#L665-1 assume !(0 == ~T2_E~0); 275969#L670-1 assume !(0 == ~T3_E~0); 276067#L675-1 assume !(0 == ~T4_E~0); 276068#L680-1 assume !(0 == ~T5_E~0); 276374#L685-1 assume !(0 == ~T6_E~0); 276375#L690-1 assume !(0 == ~E_1~0); 276235#L695-1 assume !(0 == ~E_2~0); 276236#L700-1 assume !(0 == ~E_3~0); 276531#L705-1 assume !(0 == ~E_4~0); 276138#L710-1 assume !(0 == ~E_5~0); 276139#L715-1 assume !(0 == ~E_6~0); 276001#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 276002#L310 assume !(1 == ~m_pc~0); 276204#L310-2 is_master_triggered_~__retres1~0 := 0; 276202#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 276203#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 276339#L815 assume !(0 != activate_threads_~tmp~1); 276525#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 276434#L329 assume !(1 == ~t1_pc~0); 276435#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 276432#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 276433#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 276563#L823 assume !(0 != activate_threads_~tmp___0~0); 276651#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 276620#L348 assume !(1 == ~t2_pc~0); 276621#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 276618#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 276619#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 276146#L831 assume !(0 != activate_threads_~tmp___1~0); 276133#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 276064#L367 assume !(1 == ~t3_pc~0); 276032#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 276033#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 276063#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 276186#L839 assume !(0 != activate_threads_~tmp___2~0); 276386#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 276289#L386 assume !(1 == ~t4_pc~0); 276193#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 276288#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 276190#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 276191#L847 assume !(0 != activate_threads_~tmp___3~0); 276574#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 276575#L405 assume !(1 == ~t5_pc~0); 276513#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 276514#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 276475#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 276476#L855 assume !(0 != activate_threads_~tmp___4~0); 276582#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 276112#L424 assume !(1 == ~t6_pc~0); 276113#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 276110#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 276111#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 276021#L863 assume !(0 != activate_threads_~tmp___5~0); 275991#L863-2 assume !(1 == ~M_E~0); 275992#L733-1 assume !(1 == ~T1_E~0); 276528#L738-1 assume !(1 == ~T2_E~0); 276136#L743-1 assume !(1 == ~T3_E~0); 276137#L748-1 assume !(1 == ~T4_E~0); 275997#L753-1 assume !(1 == ~T5_E~0); 275998#L758-1 assume !(1 == ~T6_E~0); 276078#L763-1 assume !(1 == ~E_1~0); 276079#L768-1 assume !(1 == ~E_2~0); 276367#L773-1 assume !(1 == ~E_3~0); 276368#L778-1 assume !(1 == ~E_4~0); 276228#L783-1 assume !(1 == ~E_5~0); 276229#L788-1 assume !(1 == ~E_6~0); 276634#L1014-1 assume !false; 280387#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 280388#L635 [2019-10-22 08:54:56,685 INFO L793 eck$LassoCheckResult]: Loop: 280388#L635 assume !false; 281241#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 281240#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 281239#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 281238#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 281237#L546 assume 0 != eval_~tmp~0; 281235#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 281231#L554 assume !(0 != eval_~tmp_ndt_1~0); 280358#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 280284#L568 assume !(0 != eval_~tmp_ndt_2~0); 280352#L565 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 280349#L582 assume !(0 != eval_~tmp_ndt_3~0); 280350#L579 assume !(0 == ~t3_st~0); 281224#L593 assume !(0 == ~t4_st~0); 282877#L607 assume !(0 == ~t5_st~0); 281243#L621 assume !(0 == ~t6_st~0); 280388#L635 [2019-10-22 08:54:56,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:56,685 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 3 times [2019-10-22 08:54:56,686 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:56,686 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887507306] [2019-10-22 08:54:56,686 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:56,686 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:56,686 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:56,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:56,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:56,712 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:56,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:56,713 INFO L82 PathProgramCache]: Analyzing trace with hash 203429809, now seen corresponding path program 1 times [2019-10-22 08:54:56,713 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:56,713 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619977918] [2019-10-22 08:54:56,713 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:56,713 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:56,714 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:56,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:56,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:56,723 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:56,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:56,723 INFO L82 PathProgramCache]: Analyzing trace with hash 1933371077, now seen corresponding path program 1 times [2019-10-22 08:54:56,724 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:56,724 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779982719] [2019-10-22 08:54:56,724 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:56,724 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:56,724 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:56,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:56,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:56,758 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779982719] [2019-10-22 08:54:56,758 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:56,758 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:56,758 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704036093] [2019-10-22 08:54:56,863 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:56,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:56,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:56,863 INFO L87 Difference]: Start difference. First operand 25167 states and 33966 transitions. cyclomatic complexity: 8823 Second operand 3 states. [2019-10-22 08:54:56,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:56,998 INFO L93 Difference]: Finished difference Result 34043 states and 45784 transitions. [2019-10-22 08:54:56,999 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:56,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34043 states and 45784 transitions. [2019-10-22 08:54:57,142 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 33552 [2019-10-22 08:54:57,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34043 states to 34043 states and 45784 transitions. [2019-10-22 08:54:57,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34043 [2019-10-22 08:54:57,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34043 [2019-10-22 08:54:57,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34043 states and 45784 transitions. [2019-10-22 08:54:57,299 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:57,299 INFO L688 BuchiCegarLoop]: Abstraction has 34043 states and 45784 transitions. [2019-10-22 08:54:57,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34043 states and 45784 transitions. [2019-10-22 08:54:57,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34043 to 32771. [2019-10-22 08:54:57,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32771 states. [2019-10-22 08:54:57,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32771 states to 32771 states and 44128 transitions. [2019-10-22 08:54:57,616 INFO L711 BuchiCegarLoop]: Abstraction has 32771 states and 44128 transitions. [2019-10-22 08:54:57,617 INFO L591 BuchiCegarLoop]: Abstraction has 32771 states and 44128 transitions. [2019-10-22 08:54:57,617 INFO L424 BuchiCegarLoop]: ======== Iteration 24============ [2019-10-22 08:54:57,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32771 states and 44128 transitions. [2019-10-22 08:54:57,706 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 32280 [2019-10-22 08:54:57,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:57,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:57,708 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:57,708 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:57,708 INFO L791 eck$LassoCheckResult]: Stem: 335764#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 335641#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 335642#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 335276#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 335277#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 335387#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 335388#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 335278#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 335279#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 335576#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 335577#L481-1 assume !(0 == ~M_E~0); 335784#L660-1 assume !(0 == ~T1_E~0); 335184#L665-1 assume !(0 == ~T2_E~0); 335185#L670-1 assume !(0 == ~T3_E~0); 335286#L675-1 assume !(0 == ~T4_E~0); 335287#L680-1 assume !(0 == ~T5_E~0); 335587#L685-1 assume !(0 == ~T6_E~0); 335588#L690-1 assume !(0 == ~E_1~0); 335444#L695-1 assume !(0 == ~E_2~0); 335445#L700-1 assume !(0 == ~E_3~0); 335746#L705-1 assume !(0 == ~E_4~0); 335354#L710-1 assume !(0 == ~E_5~0); 335355#L715-1 assume !(0 == ~E_6~0); 335220#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 335221#L310 assume !(1 == ~m_pc~0); 335413#L310-2 is_master_triggered_~__retres1~0 := 0; 335409#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 335410#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 335549#L815 assume !(0 != activate_threads_~tmp~1); 335740#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 335648#L329 assume !(1 == ~t1_pc~0); 335649#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 335643#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 335644#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 335782#L823 assume !(0 != activate_threads_~tmp___0~0); 335879#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 335842#L348 assume !(1 == ~t2_pc~0); 335843#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 335840#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 335841#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 335362#L831 assume !(0 != activate_threads_~tmp___1~0); 335349#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 335283#L367 assume !(1 == ~t3_pc~0); 335252#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 335253#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 335282#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 335392#L839 assume !(0 != activate_threads_~tmp___2~0); 335601#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 335499#L386 assume !(1 == ~t4_pc~0); 335402#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 335498#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 335399#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 335400#L847 assume !(0 != activate_threads_~tmp___3~0); 335794#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 335795#L405 assume !(1 == ~t5_pc~0); 335728#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 335729#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 335691#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 335692#L855 assume !(0 != activate_threads_~tmp___4~0); 335801#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 335329#L424 assume !(1 == ~t6_pc~0); 335330#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 335325#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 335326#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 335240#L863 assume !(0 != activate_threads_~tmp___5~0); 335207#L863-2 assume !(1 == ~M_E~0); 335208#L733-1 assume !(1 == ~T1_E~0); 335743#L738-1 assume !(1 == ~T2_E~0); 335352#L743-1 assume !(1 == ~T3_E~0); 335353#L748-1 assume !(1 == ~T4_E~0); 335215#L753-1 assume !(1 == ~T5_E~0); 335216#L758-1 assume !(1 == ~T6_E~0); 335297#L763-1 assume !(1 == ~E_1~0); 335298#L768-1 assume !(1 == ~E_2~0); 335581#L773-1 assume !(1 == ~E_3~0); 335582#L778-1 assume !(1 == ~E_4~0); 335435#L783-1 assume !(1 == ~E_5~0); 335436#L788-1 assume !(1 == ~E_6~0); 335860#L1014-1 assume !false; 341993#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 341994#L635 [2019-10-22 08:54:57,708 INFO L793 eck$LassoCheckResult]: Loop: 341994#L635 assume !false; 346790#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 341977#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 341978#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 341971#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 341972#L546 assume 0 != eval_~tmp~0; 341962#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 341963#L554 assume !(0 != eval_~tmp_ndt_1~0); 341925#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 341277#L568 assume !(0 != eval_~tmp_ndt_2~0); 341279#L565 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 341221#L582 assume !(0 != eval_~tmp_ndt_3~0); 341209#L579 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 341198#L596 assume !(0 != eval_~tmp_ndt_4~0); 341200#L593 assume !(0 == ~t4_st~0); 346898#L607 assume !(0 == ~t5_st~0); 346794#L621 assume !(0 == ~t6_st~0); 341994#L635 [2019-10-22 08:54:57,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:57,709 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 4 times [2019-10-22 08:54:57,709 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:57,709 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372842402] [2019-10-22 08:54:57,709 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:57,710 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:57,710 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:57,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:57,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:57,739 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:57,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:57,739 INFO L82 PathProgramCache]: Analyzing trace with hash 1822198777, now seen corresponding path program 1 times [2019-10-22 08:54:57,740 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:57,740 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021786207] [2019-10-22 08:54:57,740 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:57,740 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:57,740 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:57,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:57,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:57,749 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:57,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:57,749 INFO L82 PathProgramCache]: Analyzing trace with hash -384196763, now seen corresponding path program 1 times [2019-10-22 08:54:57,749 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:57,750 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144376162] [2019-10-22 08:54:57,750 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:57,750 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:57,750 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:57,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:57,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:57,788 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144376162] [2019-10-22 08:54:57,788 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:57,789 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:57,789 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797433969] [2019-10-22 08:54:57,906 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:57,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:57,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:57,906 INFO L87 Difference]: Start difference. First operand 32771 states and 44128 transitions. cyclomatic complexity: 11381 Second operand 3 states. [2019-10-22 08:54:58,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:58,448 INFO L93 Difference]: Finished difference Result 54147 states and 72854 transitions. [2019-10-22 08:54:58,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:58,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54147 states and 72854 transitions. [2019-10-22 08:54:58,644 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 53248 [2019-10-22 08:54:58,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54147 states to 54147 states and 72854 transitions. [2019-10-22 08:54:58,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54147 [2019-10-22 08:54:58,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54147 [2019-10-22 08:54:58,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54147 states and 72854 transitions. [2019-10-22 08:54:58,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:54:58,855 INFO L688 BuchiCegarLoop]: Abstraction has 54147 states and 72854 transitions. [2019-10-22 08:54:58,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54147 states and 72854 transitions. [2019-10-22 08:54:59,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54147 to 54147. [2019-10-22 08:54:59,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54147 states. [2019-10-22 08:54:59,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54147 states to 54147 states and 72854 transitions. [2019-10-22 08:54:59,401 INFO L711 BuchiCegarLoop]: Abstraction has 54147 states and 72854 transitions. [2019-10-22 08:54:59,401 INFO L591 BuchiCegarLoop]: Abstraction has 54147 states and 72854 transitions. [2019-10-22 08:54:59,401 INFO L424 BuchiCegarLoop]: ======== Iteration 25============ [2019-10-22 08:54:59,401 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54147 states and 72854 transitions. [2019-10-22 08:54:59,549 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 53248 [2019-10-22 08:54:59,549 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:54:59,549 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:54:59,550 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:59,550 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:54:59,551 INFO L791 eck$LassoCheckResult]: Stem: 422698#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 422570#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 422571#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 422201#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 422202#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 422312#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 422313#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 422203#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 422204#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 422501#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 422502#L481-1 assume !(0 == ~M_E~0); 422716#L660-1 assume !(0 == ~T1_E~0); 422112#L665-1 assume !(0 == ~T2_E~0); 422113#L670-1 assume !(0 == ~T3_E~0); 422211#L675-1 assume !(0 == ~T4_E~0); 422212#L680-1 assume !(0 == ~T5_E~0); 422511#L685-1 assume !(0 == ~T6_E~0); 422512#L690-1 assume !(0 == ~E_1~0); 422367#L695-1 assume !(0 == ~E_2~0); 422368#L700-1 assume !(0 == ~E_3~0); 422673#L705-1 assume !(0 == ~E_4~0); 422280#L710-1 assume !(0 == ~E_5~0); 422281#L715-1 assume !(0 == ~E_6~0); 422145#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 422146#L310 assume !(1 == ~m_pc~0); 422336#L310-2 is_master_triggered_~__retres1~0 := 0; 422334#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 422335#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 422476#L815 assume !(0 != activate_threads_~tmp~1); 422668#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 422574#L329 assume !(1 == ~t1_pc~0); 422575#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 422572#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 422573#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 422713#L823 assume !(0 != activate_threads_~tmp___0~0); 422815#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 422774#L348 assume !(1 == ~t2_pc~0); 422775#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 422772#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 422773#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 422288#L831 assume !(0 != activate_threads_~tmp___1~0); 422275#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 422208#L367 assume !(1 == ~t3_pc~0); 422178#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 422179#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 422207#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 422318#L839 assume !(0 != activate_threads_~tmp___2~0); 422525#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 422421#L386 assume !(1 == ~t4_pc~0); 422325#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 422420#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 422322#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 422323#L847 assume !(0 != activate_threads_~tmp___3~0); 422726#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 422727#L405 assume !(1 == ~t5_pc~0); 422658#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 422659#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 422616#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 422617#L855 assume !(0 != activate_threads_~tmp___4~0); 422733#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 422255#L424 assume !(1 == ~t6_pc~0); 422256#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 422253#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 422254#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 422165#L863 assume !(0 != activate_threads_~tmp___5~0); 422135#L863-2 assume !(1 == ~M_E~0); 422136#L733-1 assume !(1 == ~T1_E~0); 422670#L738-1 assume !(1 == ~T2_E~0); 422278#L743-1 assume !(1 == ~T3_E~0); 422279#L748-1 assume !(1 == ~T4_E~0); 422140#L753-1 assume !(1 == ~T5_E~0); 422141#L758-1 assume !(1 == ~T6_E~0); 422222#L763-1 assume !(1 == ~E_1~0); 422223#L768-1 assume !(1 == ~E_2~0); 422504#L773-1 assume !(1 == ~E_3~0); 422505#L778-1 assume !(1 == ~E_4~0); 422360#L783-1 assume !(1 == ~E_5~0); 422361#L788-1 assume !(1 == ~E_6~0); 422794#L1014-1 assume !false; 442716#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 442710#L635 [2019-10-22 08:54:59,551 INFO L793 eck$LassoCheckResult]: Loop: 442710#L635 assume !false; 442707#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 442704#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 442702#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 442700#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 442697#L546 assume 0 != eval_~tmp~0; 442694#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 442695#L554 assume !(0 != eval_~tmp_ndt_1~0); 436175#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 436172#L568 assume !(0 != eval_~tmp_ndt_2~0); 436160#L565 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 435825#L582 assume !(0 != eval_~tmp_ndt_3~0); 435826#L579 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 437637#L596 assume !(0 != eval_~tmp_ndt_4~0); 437635#L593 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 437620#L610 assume !(0 != eval_~tmp_ndt_5~0); 437632#L607 assume !(0 == ~t5_st~0); 442714#L621 assume !(0 == ~t6_st~0); 442710#L635 [2019-10-22 08:54:59,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:59,551 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 5 times [2019-10-22 08:54:59,551 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:59,551 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309609935] [2019-10-22 08:54:59,551 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:59,551 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:59,552 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:59,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:59,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:59,578 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:59,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:59,579 INFO L82 PathProgramCache]: Analyzing trace with hash 647492045, now seen corresponding path program 1 times [2019-10-22 08:54:59,579 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:59,579 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458568870] [2019-10-22 08:54:59,579 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:59,579 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:59,579 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:59,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:59,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:54:59,586 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:54:59,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:54:59,587 INFO L82 PathProgramCache]: Analyzing trace with hash 968707041, now seen corresponding path program 1 times [2019-10-22 08:54:59,587 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:54:59,587 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421238153] [2019-10-22 08:54:59,587 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:59,587 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:54:59,587 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:54:59,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:54:59,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:54:59,618 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421238153] [2019-10-22 08:54:59,618 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:54:59,619 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-22 08:54:59,619 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312191860] [2019-10-22 08:54:59,737 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:54:59,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:54:59,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:54:59,737 INFO L87 Difference]: Start difference. First operand 54147 states and 72854 transitions. cyclomatic complexity: 18731 Second operand 3 states. [2019-10-22 08:54:59,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:54:59,958 INFO L93 Difference]: Finished difference Result 73896 states and 99242 transitions. [2019-10-22 08:54:59,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:54:59,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73896 states and 99242 transitions. [2019-10-22 08:55:00,228 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 72733 [2019-10-22 08:55:00,456 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73896 states to 73896 states and 99242 transitions. [2019-10-22 08:55:00,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73896 [2019-10-22 08:55:00,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73896 [2019-10-22 08:55:00,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73896 states and 99242 transitions. [2019-10-22 08:55:00,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:55:00,549 INFO L688 BuchiCegarLoop]: Abstraction has 73896 states and 99242 transitions. [2019-10-22 08:55:00,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73896 states and 99242 transitions. [2019-10-22 08:55:01,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73896 to 72456. [2019-10-22 08:55:01,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72456 states. [2019-10-22 08:55:01,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72456 states to 72456 states and 97370 transitions. [2019-10-22 08:55:01,863 INFO L711 BuchiCegarLoop]: Abstraction has 72456 states and 97370 transitions. [2019-10-22 08:55:01,863 INFO L591 BuchiCegarLoop]: Abstraction has 72456 states and 97370 transitions. [2019-10-22 08:55:01,863 INFO L424 BuchiCegarLoop]: ======== Iteration 26============ [2019-10-22 08:55:01,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72456 states and 97370 transitions. [2019-10-22 08:55:02,062 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 71293 [2019-10-22 08:55:02,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:55:02,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:55:02,063 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:55:02,063 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:55:02,063 INFO L791 eck$LassoCheckResult]: Stem: 550770#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 550638#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 550639#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 550256#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 550257#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 550377#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 550378#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 550258#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 550259#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 550565#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 550566#L481-1 assume !(0 == ~M_E~0); 550791#L660-1 assume !(0 == ~T1_E~0); 550163#L665-1 assume !(0 == ~T2_E~0); 550164#L670-1 assume !(0 == ~T3_E~0); 550266#L675-1 assume !(0 == ~T4_E~0); 550267#L680-1 assume !(0 == ~T5_E~0); 550579#L685-1 assume !(0 == ~T6_E~0); 550580#L690-1 assume !(0 == ~E_1~0); 550431#L695-1 assume !(0 == ~E_2~0); 550432#L700-1 assume !(0 == ~E_3~0); 550748#L705-1 assume !(0 == ~E_4~0); 550339#L710-1 assume !(0 == ~E_5~0); 550340#L715-1 assume !(0 == ~E_6~0); 550197#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 550198#L310 assume !(1 == ~m_pc~0); 550400#L310-2 is_master_triggered_~__retres1~0 := 0; 550398#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 550399#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 550540#L815 assume !(0 != activate_threads_~tmp~1); 550744#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 550642#L329 assume !(1 == ~t1_pc~0); 550643#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 550640#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 550641#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 550788#L823 assume !(0 != activate_threads_~tmp___0~0); 550896#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 550857#L348 assume !(1 == ~t2_pc~0); 550858#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 550855#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 550856#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 550349#L831 assume !(0 != activate_threads_~tmp___1~0); 550334#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 550263#L367 assume !(1 == ~t3_pc~0); 550230#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 550231#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 550262#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 550382#L839 assume !(0 != activate_threads_~tmp___2~0); 550594#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 550486#L386 assume !(1 == ~t4_pc~0); 550389#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 550485#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 550386#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 550387#L847 assume !(0 != activate_threads_~tmp___3~0); 550795#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 550796#L405 assume !(1 == ~t5_pc~0); 550732#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 550733#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 550685#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 550686#L855 assume !(0 != activate_threads_~tmp___4~0); 550809#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 550312#L424 assume !(1 == ~t6_pc~0); 550313#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 550310#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 550311#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 550218#L863 assume !(0 != activate_threads_~tmp___5~0); 550186#L863-2 assume !(1 == ~M_E~0); 550187#L733-1 assume !(1 == ~T1_E~0); 550746#L738-1 assume !(1 == ~T2_E~0); 550337#L743-1 assume !(1 == ~T3_E~0); 550338#L748-1 assume !(1 == ~T4_E~0); 550192#L753-1 assume !(1 == ~T5_E~0); 550193#L758-1 assume !(1 == ~T6_E~0); 550277#L763-1 assume !(1 == ~E_1~0); 550278#L768-1 assume !(1 == ~E_2~0); 550570#L773-1 assume !(1 == ~E_3~0); 550571#L778-1 assume !(1 == ~E_4~0); 550424#L783-1 assume !(1 == ~E_5~0); 550425#L788-1 assume !(1 == ~E_6~0); 550875#L1014-1 assume !false; 577364#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 577357#L635 [2019-10-22 08:55:02,064 INFO L793 eck$LassoCheckResult]: Loop: 577357#L635 assume !false; 577355#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 577352#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 577350#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 577346#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 577344#L546 assume 0 != eval_~tmp~0; 577341#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 577337#L554 assume !(0 != eval_~tmp_ndt_1~0); 577335#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 577174#L568 assume !(0 != eval_~tmp_ndt_2~0); 577333#L565 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 590158#L582 assume !(0 != eval_~tmp_ndt_3~0); 590157#L579 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 590156#L596 assume !(0 != eval_~tmp_ndt_4~0); 577400#L593 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 577398#L610 assume !(0 != eval_~tmp_ndt_5~0); 577396#L607 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 577393#L624 assume !(0 != eval_~tmp_ndt_6~0); 577362#L621 assume !(0 == ~t6_st~0); 577357#L635 [2019-10-22 08:55:02,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:55:02,064 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 6 times [2019-10-22 08:55:02,064 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:55:02,064 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305209226] [2019-10-22 08:55:02,064 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:02,064 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:02,064 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:55:02,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:55:02,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:55:02,096 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:55:02,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:55:02,096 INFO L82 PathProgramCache]: Analyzing trace with hash -1402773027, now seen corresponding path program 1 times [2019-10-22 08:55:02,097 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:55:02,097 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977866335] [2019-10-22 08:55:02,097 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:02,097 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:02,097 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:55:02,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:55:02,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:55:02,105 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:55:02,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:55:02,106 INFO L82 PathProgramCache]: Analyzing trace with hash -35042743, now seen corresponding path program 1 times [2019-10-22 08:55:02,106 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:55:02,107 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850085705] [2019-10-22 08:55:02,107 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:02,107 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:02,107 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:55:02,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-22 08:55:02,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-22 08:55:02,141 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850085705] [2019-10-22 08:55:02,141 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-22 08:55:02,141 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-22 08:55:02,141 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1223183837] [2019-10-22 08:55:02,281 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-10-22 08:55:02,282 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-22 08:55:02,282 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-22 08:55:02,282 INFO L87 Difference]: Start difference. First operand 72456 states and 97370 transitions. cyclomatic complexity: 24938 Second operand 3 states. [2019-10-22 08:55:02,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-22 08:55:02,695 INFO L93 Difference]: Finished difference Result 141792 states and 189968 transitions. [2019-10-22 08:55:02,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-22 08:55:02,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141792 states and 189968 transitions. [2019-10-22 08:55:03,226 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 139549 [2019-10-22 08:55:03,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141792 states to 141792 states and 189968 transitions. [2019-10-22 08:55:03,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 141792 [2019-10-22 08:55:03,582 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 141792 [2019-10-22 08:55:03,582 INFO L73 IsDeterministic]: Start isDeterministic. Operand 141792 states and 189968 transitions. [2019-10-22 08:55:03,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-10-22 08:55:03,666 INFO L688 BuchiCegarLoop]: Abstraction has 141792 states and 189968 transitions. [2019-10-22 08:55:03,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141792 states and 189968 transitions. [2019-10-22 08:55:08,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141792 to 141792. [2019-10-22 08:55:08,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141792 states. [2019-10-22 08:55:08,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141792 states to 141792 states and 189968 transitions. [2019-10-22 08:55:08,551 INFO L711 BuchiCegarLoop]: Abstraction has 141792 states and 189968 transitions. [2019-10-22 08:55:08,551 INFO L591 BuchiCegarLoop]: Abstraction has 141792 states and 189968 transitions. [2019-10-22 08:55:08,551 INFO L424 BuchiCegarLoop]: ======== Iteration 27============ [2019-10-22 08:55:08,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 141792 states and 189968 transitions. [2019-10-22 08:55:08,845 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 139549 [2019-10-22 08:55:08,845 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-10-22 08:55:08,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-10-22 08:55:08,845 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:55:08,845 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-22 08:55:08,846 INFO L791 eck$LassoCheckResult]: Stem: 765014#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 764886#L-1 havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 764887#L977 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 764509#L444 assume 1 == ~m_i~0;~m_st~0 := 0; 764510#L451-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 764628#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 764629#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 764513#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 764514#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 764818#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 764819#L481-1 assume !(0 == ~M_E~0); 765039#L660-1 assume !(0 == ~T1_E~0); 764417#L665-1 assume !(0 == ~T2_E~0); 764418#L670-1 assume !(0 == ~T3_E~0); 764521#L675-1 assume !(0 == ~T4_E~0); 764522#L680-1 assume !(0 == ~T5_E~0); 764830#L685-1 assume !(0 == ~T6_E~0); 764831#L690-1 assume !(0 == ~E_1~0); 764683#L695-1 assume !(0 == ~E_2~0); 764684#L700-1 assume !(0 == ~E_3~0); 764996#L705-1 assume !(0 == ~E_4~0); 764592#L710-1 assume !(0 == ~E_5~0); 764593#L715-1 assume !(0 == ~E_6~0); 764454#L720-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 764455#L310 assume !(1 == ~m_pc~0); 764652#L310-2 is_master_triggered_~__retres1~0 := 0; 764648#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 764649#L322 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 764792#L815 assume !(0 != activate_threads_~tmp~1); 764991#L815-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 764893#L329 assume !(1 == ~t1_pc~0); 764894#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 764888#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 764889#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 765036#L823 assume !(0 != activate_threads_~tmp___0~0); 765146#L823-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 765107#L348 assume !(1 == ~t2_pc~0); 765108#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 765104#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 765105#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 764600#L831 assume !(0 != activate_threads_~tmp___1~0); 764586#L831-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 764518#L367 assume !(1 == ~t3_pc~0); 764488#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 764489#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 764517#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 764632#L839 assume !(0 != activate_threads_~tmp___2~0); 764842#L839-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 764738#L386 assume !(1 == ~t4_pc~0); 764641#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 764737#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 764638#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 764639#L847 assume !(0 != activate_threads_~tmp___3~0); 765049#L847-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 765050#L405 assume !(1 == ~t5_pc~0); 764979#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 764980#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 764935#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 764936#L855 assume !(0 != activate_threads_~tmp___4~0); 765059#L855-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 764563#L424 assume !(1 == ~t6_pc~0); 764564#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 764559#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 764560#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 764473#L863 assume !(0 != activate_threads_~tmp___5~0); 764440#L863-2 assume !(1 == ~M_E~0); 764441#L733-1 assume !(1 == ~T1_E~0); 764993#L738-1 assume !(1 == ~T2_E~0); 764590#L743-1 assume !(1 == ~T3_E~0); 764591#L748-1 assume !(1 == ~T4_E~0); 764448#L753-1 assume !(1 == ~T5_E~0); 764449#L758-1 assume !(1 == ~T6_E~0); 764531#L763-1 assume !(1 == ~E_1~0); 764532#L768-1 assume !(1 == ~E_2~0); 764823#L773-1 assume !(1 == ~E_3~0); 764824#L778-1 assume !(1 == ~E_4~0); 764674#L783-1 assume !(1 == ~E_5~0); 764675#L788-1 assume !(1 == ~E_6~0); 765125#L1014-1 assume !false; 793313#L1015 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 777751#L635 [2019-10-22 08:55:08,846 INFO L793 eck$LassoCheckResult]: Loop: 777751#L635 assume !false; 793302#L542 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 793293#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 793287#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 793281#L532 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 793277#L546 assume 0 != eval_~tmp~0; 793272#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 793263#L554 assume !(0 != eval_~tmp_ndt_1~0); 793256#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 793246#L568 assume !(0 != eval_~tmp_ndt_2~0); 793241#L565 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 793236#L582 assume !(0 != eval_~tmp_ndt_3~0); 793228#L579 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 793205#L596 assume !(0 != eval_~tmp_ndt_4~0); 791110#L593 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 791108#L610 assume !(0 != eval_~tmp_ndt_5~0); 777760#L607 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 777757#L624 assume !(0 != eval_~tmp_ndt_6~0); 777755#L621 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 777741#L638 assume !(0 != eval_~tmp_ndt_7~0); 777751#L635 [2019-10-22 08:55:08,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:55:08,846 INFO L82 PathProgramCache]: Analyzing trace with hash 228947733, now seen corresponding path program 7 times [2019-10-22 08:55:08,846 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:55:08,847 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014903113] [2019-10-22 08:55:08,847 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:08,847 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:08,847 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:55:08,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:55:08,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:55:08,873 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:55:08,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:55:08,873 INFO L82 PathProgramCache]: Analyzing trace with hash -536290327, now seen corresponding path program 1 times [2019-10-22 08:55:08,873 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:55:08,874 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1654268390] [2019-10-22 08:55:08,874 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:08,874 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:08,874 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:55:08,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:55:08,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:55:08,880 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:55:08,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-22 08:55:08,881 INFO L82 PathProgramCache]: Analyzing trace with hash -1086324483, now seen corresponding path program 1 times [2019-10-22 08:55:08,881 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-10-22 08:55:08,881 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845026128] [2019-10-22 08:55:08,881 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:08,881 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-10-22 08:55:08,881 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-22 08:55:08,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:55:08,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-22 08:55:08,913 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-10-22 08:55:09,021 WARN L191 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 51 [2019-10-22 08:55:09,778 WARN L191 SmtUtils]: Spent 701.00 ms on a formula simplification. DAG size of input: 219 DAG size of output: 146 [2019-10-22 08:55:09,969 WARN L191 SmtUtils]: Spent 180.00 ms on a formula simplification that was a NOOP. DAG size: 116 [2019-10-22 08:55:10,005 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 22.10 08:55:10 BoogieIcfgContainer [2019-10-22 08:55:10,005 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-10-22 08:55:10,006 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-10-22 08:55:10,006 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-10-22 08:55:10,006 INFO L275 PluginConnector]: Witness Printer initialized [2019-10-22 08:55:10,007 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.10 08:54:48" (3/4) ... [2019-10-22 08:55:10,009 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-10-22 08:55:10,063 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_6729a43f-f630-4d5c-81c6-25e30ff31678/bin/uautomizer/witness.graphml [2019-10-22 08:55:10,063 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-10-22 08:55:10,064 INFO L168 Benchmark]: Toolchain (without parser) took 23271.32 ms. Allocated memory was 1.0 GB in the beginning and 3.2 GB in the end (delta: 2.1 GB). Free memory was 945.0 MB in the beginning and 1.8 GB in the end (delta: -823.1 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2019-10-22 08:55:10,064 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 963.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-10-22 08:55:10,065 INFO L168 Benchmark]: CACSL2BoogieTranslator took 404.41 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 945.0 MB in the beginning and 1.1 GB in the end (delta: -138.4 MB). Peak memory consumption was 23.3 MB. Max. memory is 11.5 GB. [2019-10-22 08:55:10,065 INFO L168 Benchmark]: Boogie Procedure Inliner took 62.88 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.0 MB). Peak memory consumption was 7.0 MB. Max. memory is 11.5 GB. [2019-10-22 08:55:10,065 INFO L168 Benchmark]: Boogie Preprocessor took 58.24 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-10-22 08:55:10,065 INFO L168 Benchmark]: RCFGBuilder took 1428.78 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 933.0 MB in the end (delta: 143.4 MB). Peak memory consumption was 143.4 MB. Max. memory is 11.5 GB. [2019-10-22 08:55:10,065 INFO L168 Benchmark]: BuchiAutomizer took 21254.81 ms. Allocated memory was 1.1 GB in the beginning and 3.2 GB in the end (delta: 2.0 GB). Free memory was 933.0 MB in the beginning and 1.8 GB in the end (delta: -844.3 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2019-10-22 08:55:10,066 INFO L168 Benchmark]: Witness Printer took 57.31 ms. Allocated memory is still 3.2 GB. Free memory was 1.8 GB in the beginning and 1.8 GB in the end (delta: 9.2 MB). Peak memory consumption was 9.2 MB. Max. memory is 11.5 GB. [2019-10-22 08:55:10,067 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 963.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 404.41 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 945.0 MB in the beginning and 1.1 GB in the end (delta: -138.4 MB). Peak memory consumption was 23.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 62.88 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.0 MB). Peak memory consumption was 7.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 58.24 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 1428.78 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 933.0 MB in the end (delta: 143.4 MB). Peak memory consumption was 143.4 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 21254.81 ms. Allocated memory was 1.1 GB in the beginning and 3.2 GB in the end (delta: 2.0 GB). Free memory was 933.0 MB in the beginning and 1.8 GB in the end (delta: -844.3 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. * Witness Printer took 57.31 ms. Allocated memory is still 3.2 GB. Free memory was 1.8 GB in the beginning and 1.8 GB in the end (delta: 9.2 MB). Peak memory consumption was 9.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 26 terminating modules (26 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.26 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 141792 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 21.1s and 27 iterations. TraceHistogramMax:1. Analysis of lassos took 4.0s. Construction of modules took 0.6s. Büchi inclusion checks took 2.2s. Highest rank in rank-based complementation 0. Minimization of det autom 26. Minimization of nondet autom 0. Automata minimization 9.0s AutomataMinimizationTime, 26 MinimizatonAttempts, 21449 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 3.2s Buchi closure took 0.2s. Biggest automaton had 141792 states and ocurred in iteration 26. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 23461 SDtfs, 23793 SDslu, 16852 SDs, 0 SdLazy, 500 SolverSat, 297 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc6 concLT0 SILN1 SILU0 SILI15 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 541]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7e9b9b5f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@22caddf4=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, \result=0, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, T6_E=2, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@70a39c96=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@24684da4=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, t6_pc=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, \result=0, t6_i=1, m_pc=0, tmp___4=0, \result=0, __retres1=0, t6_st=0, E_6=2, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b9b9600=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, __retres1=1, t5_st=0, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4b29cb64=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@53ee2af2=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5699b9ae=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@99c745=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7c613e4d=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@68e5bdef=0, t2_pc=0, tmp_ndt_7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2688e594=0, tmp___3=0, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@60e452c9=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@21f8bfa9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5e07115b=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@66eea97f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5be446f2=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 541]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int t2_i ; [L32] int t3_i ; [L33] int t4_i ; [L34] int t5_i ; [L35] int t6_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int T4_E = 2; [L41] int T5_E = 2; [L42] int T6_E = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L1059] int __retres1 ; [L969] m_i = 1 [L970] t1_i = 1 [L971] t2_i = 1 [L972] t3_i = 1 [L973] t4_i = 1 [L974] t5_i = 1 [L975] t6_i = 1 [L1000] int kernel_st ; [L1001] int tmp ; [L1002] int tmp___0 ; [L1006] kernel_st = 0 [L451] COND TRUE m_i == 1 [L452] m_st = 0 [L456] COND TRUE t1_i == 1 [L457] t1_st = 0 [L461] COND TRUE t2_i == 1 [L462] t2_st = 0 [L466] COND TRUE t3_i == 1 [L467] t3_st = 0 [L471] COND TRUE t4_i == 1 [L472] t4_st = 0 [L476] COND TRUE t5_i == 1 [L477] t5_st = 0 [L481] COND TRUE t6_i == 1 [L482] t6_st = 0 [L660] COND FALSE !(M_E == 0) [L665] COND FALSE !(T1_E == 0) [L670] COND FALSE !(T2_E == 0) [L675] COND FALSE !(T3_E == 0) [L680] COND FALSE !(T4_E == 0) [L685] COND FALSE !(T5_E == 0) [L690] COND FALSE !(T6_E == 0) [L695] COND FALSE !(E_1 == 0) [L700] COND FALSE !(E_2 == 0) [L705] COND FALSE !(E_3 == 0) [L710] COND FALSE !(E_4 == 0) [L715] COND FALSE !(E_5 == 0) [L720] COND FALSE !(E_6 == 0) [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; [L307] int __retres1 ; [L310] COND FALSE !(m_pc == 1) [L320] __retres1 = 0 [L322] return (__retres1); [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) [L326] int __retres1 ; [L329] COND FALSE !(t1_pc == 1) [L339] __retres1 = 0 [L341] return (__retres1); [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) [L345] int __retres1 ; [L348] COND FALSE !(t2_pc == 1) [L358] __retres1 = 0 [L360] return (__retres1); [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) [L364] int __retres1 ; [L367] COND FALSE !(t3_pc == 1) [L377] __retres1 = 0 [L379] return (__retres1); [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) [L383] int __retres1 ; [L386] COND FALSE !(t4_pc == 1) [L396] __retres1 = 0 [L398] return (__retres1); [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) [L402] int __retres1 ; [L405] COND FALSE !(t5_pc == 1) [L415] __retres1 = 0 [L417] return (__retres1); [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) [L421] int __retres1 ; [L424] COND FALSE !(t6_pc == 1) [L434] __retres1 = 0 [L436] return (__retres1); [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) [L733] COND FALSE !(M_E == 1) [L738] COND FALSE !(T1_E == 1) [L743] COND FALSE !(T2_E == 1) [L748] COND FALSE !(T3_E == 1) [L753] COND FALSE !(T4_E == 1) [L758] COND FALSE !(T5_E == 1) [L763] COND FALSE !(T6_E == 1) [L768] COND FALSE !(E_1 == 1) [L773] COND FALSE !(E_2 == 1) [L778] COND FALSE !(E_3 == 1) [L783] COND FALSE !(E_4 == 1) [L788] COND FALSE !(E_5 == 1) [L793] COND FALSE !(E_6 == 1) [L1014] COND TRUE 1 [L1017] kernel_st = 1 [L537] int tmp ; Loop: [L541] COND TRUE 1 [L491] int __retres1 ; [L494] COND TRUE m_st == 0 [L495] __retres1 = 1 [L532] return (__retres1); [L544] tmp = exists_runnable_thread() [L546] COND TRUE \read(tmp) [L551] COND TRUE m_st == 0 [L552] int tmp_ndt_1; [L553] tmp_ndt_1 = __VERIFIER_nondet_int() [L554] COND FALSE !(\read(tmp_ndt_1)) [L565] COND TRUE t1_st == 0 [L566] int tmp_ndt_2; [L567] tmp_ndt_2 = __VERIFIER_nondet_int() [L568] COND FALSE !(\read(tmp_ndt_2)) [L579] COND TRUE t2_st == 0 [L580] int tmp_ndt_3; [L581] tmp_ndt_3 = __VERIFIER_nondet_int() [L582] COND FALSE !(\read(tmp_ndt_3)) [L593] COND TRUE t3_st == 0 [L594] int tmp_ndt_4; [L595] tmp_ndt_4 = __VERIFIER_nondet_int() [L596] COND FALSE !(\read(tmp_ndt_4)) [L607] COND TRUE t4_st == 0 [L608] int tmp_ndt_5; [L609] tmp_ndt_5 = __VERIFIER_nondet_int() [L610] COND FALSE !(\read(tmp_ndt_5)) [L621] COND TRUE t5_st == 0 [L622] int tmp_ndt_6; [L623] tmp_ndt_6 = __VERIFIER_nondet_int() [L624] COND FALSE !(\read(tmp_ndt_6)) [L635] COND TRUE t6_st == 0 [L636] int tmp_ndt_7; [L637] tmp_ndt_7 = __VERIFIER_nondet_int() [L638] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...