./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_-write.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_-write.c -s /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-11-15 23:09:49,669 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-15 23:09:49,671 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-15 23:09:49,681 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-15 23:09:49,681 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-15 23:09:49,682 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-15 23:09:49,683 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-15 23:09:49,685 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-15 23:09:49,687 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-15 23:09:49,688 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-15 23:09:49,689 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-15 23:09:49,690 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-15 23:09:49,691 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-15 23:09:49,692 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-15 23:09:49,693 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-15 23:09:49,694 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-15 23:09:49,694 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-15 23:09:49,695 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-15 23:09:49,697 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-15 23:09:49,700 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-15 23:09:49,701 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-15 23:09:49,703 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-15 23:09:49,704 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-15 23:09:49,704 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-15 23:09:49,707 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-15 23:09:49,707 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-15 23:09:49,708 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-15 23:09:49,709 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-15 23:09:49,709 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-15 23:09:49,710 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-15 23:09:49,710 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-15 23:09:49,711 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-15 23:09:49,712 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-15 23:09:49,712 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-15 23:09:49,714 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-15 23:09:49,714 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-15 23:09:49,715 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-15 23:09:49,715 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-15 23:09:49,715 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-15 23:09:49,716 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-15 23:09:49,717 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-15 23:09:49,717 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2019-11-15 23:09:49,731 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-15 23:09:49,731 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-15 23:09:49,732 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-15 23:09:49,732 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-15 23:09:49,733 INFO L138 SettingsManager]: * Use SBE=true [2019-11-15 23:09:49,733 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-15 23:09:49,733 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-15 23:09:49,733 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-11-15 23:09:49,734 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-15 23:09:49,734 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-15 23:09:49,734 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-15 23:09:49,734 INFO L138 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2019-11-15 23:09:49,734 INFO L138 SettingsManager]: * Bitprecise bitfields=true [2019-11-15 23:09:49,735 INFO L138 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2019-11-15 23:09:49,735 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-15 23:09:49,735 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-15 23:09:49,735 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-15 23:09:49,736 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-15 23:09:49,736 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-15 23:09:49,736 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-15 23:09:49,736 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-15 23:09:49,736 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 23:09:49,737 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-15 23:09:49,737 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-15 23:09:49,737 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-15 23:09:49,737 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-15 23:09:49,738 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 [2019-11-15 23:09:49,762 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-15 23:09:49,772 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-15 23:09:49,775 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-15 23:09:49,777 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-15 23:09:49,777 INFO L275 PluginConnector]: CDTParser initialized [2019-11-15 23:09:49,778 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_-write.c [2019-11-15 23:09:49,827 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/data/652724362/6604ed24feba46d6b10dabbc0e587861/FLAGf3de1a168 [2019-11-15 23:09:50,247 INFO L306 CDTParser]: Found 1 translation units. [2019-11-15 23:09:50,248 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_-write.c [2019-11-15 23:09:50,253 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/data/652724362/6604ed24feba46d6b10dabbc0e587861/FLAGf3de1a168 [2019-11-15 23:09:50,269 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/data/652724362/6604ed24feba46d6b10dabbc0e587861 [2019-11-15 23:09:50,272 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-15 23:09:50,275 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2019-11-15 23:09:50,278 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-15 23:09:50,278 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-15 23:09:50,281 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-15 23:09:50,282 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 11:09:50" (1/1) ... [2019-11-15 23:09:50,285 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6fcd116b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:09:50, skipping insertion in model container [2019-11-15 23:09:50,285 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 11:09:50" (1/1) ... [2019-11-15 23:09:50,291 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-15 23:09:50,307 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-15 23:09:50,534 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 23:09:50,545 INFO L188 MainTranslator]: Completed pre-run [2019-11-15 23:09:50,561 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 23:09:50,572 INFO L192 MainTranslator]: Completed translation [2019-11-15 23:09:50,573 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:09:50 WrapperNode [2019-11-15 23:09:50,573 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-15 23:09:50,573 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-15 23:09:50,573 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-15 23:09:50,573 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-15 23:09:50,585 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:09:50" (1/1) ... [2019-11-15 23:09:50,585 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:09:50" (1/1) ... [2019-11-15 23:09:50,592 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:09:50" (1/1) ... [2019-11-15 23:09:50,593 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:09:50" (1/1) ... [2019-11-15 23:09:50,599 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:09:50" (1/1) ... [2019-11-15 23:09:50,603 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:09:50" (1/1) ... [2019-11-15 23:09:50,604 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:09:50" (1/1) ... [2019-11-15 23:09:50,606 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-15 23:09:50,606 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-15 23:09:50,606 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-15 23:09:50,607 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-15 23:09:50,607 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:09:50" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 23:09:50,663 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-11-15 23:09:50,664 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-15 23:09:50,664 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2019-11-15 23:09:50,665 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-11-15 23:09:50,665 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2019-11-15 23:09:50,665 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-11-15 23:09:50,666 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-11-15 23:09:50,667 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-15 23:09:50,667 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-15 23:09:50,667 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-15 23:09:50,667 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-11-15 23:09:50,667 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-15 23:09:50,930 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-15 23:09:50,930 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-11-15 23:09:50,931 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 11:09:50 BoogieIcfgContainer [2019-11-15 23:09:50,931 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-15 23:09:50,932 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-15 23:09:50,933 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-15 23:09:50,935 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-15 23:09:50,935 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 15.11 11:09:50" (1/3) ... [2019-11-15 23:09:50,936 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@32bf82a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 11:09:50, skipping insertion in model container [2019-11-15 23:09:50,936 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:09:50" (2/3) ... [2019-11-15 23:09:50,937 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@32bf82a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 11:09:50, skipping insertion in model container [2019-11-15 23:09:50,937 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 11:09:50" (3/3) ... [2019-11-15 23:09:50,938 INFO L109 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_-write.c [2019-11-15 23:09:50,946 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-15 23:09:50,952 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2019-11-15 23:09:50,961 INFO L249 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2019-11-15 23:09:50,978 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-15 23:09:50,979 INFO L374 AbstractCegarLoop]: Hoare is false [2019-11-15 23:09:50,979 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-15 23:09:50,979 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-15 23:09:50,979 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-15 23:09:50,979 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-15 23:09:50,979 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-15 23:09:50,979 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-15 23:09:50,991 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states. [2019-11-15 23:09:50,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2019-11-15 23:09:50,999 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:51,000 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:51,001 INFO L410 AbstractCegarLoop]: === Iteration 1 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:51,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:51,004 INFO L82 PathProgramCache]: Analyzing trace with hash 1909189377, now seen corresponding path program 1 times [2019-11-15 23:09:51,010 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:51,010 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217148098] [2019-11-15 23:09:51,011 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:51,011 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:51,011 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:51,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:51,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:51,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:09:51,173 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217148098] [2019-11-15 23:09:51,177 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:09:51,178 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:09:51,178 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662517791] [2019-11-15 23:09:51,181 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:09:51,181 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:51,191 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:09:51,192 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:09:51,193 INFO L87 Difference]: Start difference. First operand 40 states. Second operand 4 states. [2019-11-15 23:09:51,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:51,382 INFO L93 Difference]: Finished difference Result 58 states and 63 transitions. [2019-11-15 23:09:51,383 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:09:51,384 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 10 [2019-11-15 23:09:51,384 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:51,392 INFO L225 Difference]: With dead ends: 58 [2019-11-15 23:09:51,393 INFO L226 Difference]: Without dead ends: 54 [2019-11-15 23:09:51,394 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:09:51,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-11-15 23:09:51,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 39. [2019-11-15 23:09:51,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2019-11-15 23:09:51,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 42 transitions. [2019-11-15 23:09:51,440 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 42 transitions. Word has length 10 [2019-11-15 23:09:51,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:51,441 INFO L462 AbstractCegarLoop]: Abstraction has 39 states and 42 transitions. [2019-11-15 23:09:51,441 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:09:51,442 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 42 transitions. [2019-11-15 23:09:51,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-11-15 23:09:51,442 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:51,442 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:51,444 INFO L410 AbstractCegarLoop]: === Iteration 2 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:51,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:51,444 INFO L82 PathProgramCache]: Analyzing trace with hash -941983064, now seen corresponding path program 1 times [2019-11-15 23:09:51,445 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:51,445 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172717705] [2019-11-15 23:09:51,445 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:51,445 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:51,446 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:51,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:51,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:51,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:09:51,535 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [172717705] [2019-11-15 23:09:51,535 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:09:51,535 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:09:51,536 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336997079] [2019-11-15 23:09:51,537 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:09:51,537 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:51,537 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:09:51,537 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:09:51,538 INFO L87 Difference]: Start difference. First operand 39 states and 42 transitions. Second operand 4 states. [2019-11-15 23:09:51,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:51,642 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2019-11-15 23:09:51,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-15 23:09:51,643 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-11-15 23:09:51,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:51,645 INFO L225 Difference]: With dead ends: 49 [2019-11-15 23:09:51,646 INFO L226 Difference]: Without dead ends: 49 [2019-11-15 23:09:51,646 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:09:51,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2019-11-15 23:09:51,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 41. [2019-11-15 23:09:51,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2019-11-15 23:09:51,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 45 transitions. [2019-11-15 23:09:51,652 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 45 transitions. Word has length 11 [2019-11-15 23:09:51,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:51,652 INFO L462 AbstractCegarLoop]: Abstraction has 41 states and 45 transitions. [2019-11-15 23:09:51,652 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:09:51,653 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 45 transitions. [2019-11-15 23:09:51,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2019-11-15 23:09:51,653 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:51,653 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:51,654 INFO L410 AbstractCegarLoop]: === Iteration 3 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:51,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:51,654 INFO L82 PathProgramCache]: Analyzing trace with hash 863296133, now seen corresponding path program 1 times [2019-11-15 23:09:51,654 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:51,655 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953135538] [2019-11-15 23:09:51,655 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:51,655 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:51,655 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:51,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:51,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:51,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:09:51,750 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [953135538] [2019-11-15 23:09:51,750 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:09:51,750 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 23:09:51,750 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130405356] [2019-11-15 23:09:51,751 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:09:51,751 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:51,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:09:51,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 23:09:51,751 INFO L87 Difference]: Start difference. First operand 41 states and 45 transitions. Second operand 6 states. [2019-11-15 23:09:51,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:51,867 INFO L93 Difference]: Finished difference Result 40 states and 44 transitions. [2019-11-15 23:09:51,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 23:09:51,868 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 12 [2019-11-15 23:09:51,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:51,869 INFO L225 Difference]: With dead ends: 40 [2019-11-15 23:09:51,869 INFO L226 Difference]: Without dead ends: 40 [2019-11-15 23:09:51,870 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2019-11-15 23:09:51,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2019-11-15 23:09:51,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2019-11-15 23:09:51,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2019-11-15 23:09:51,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 44 transitions. [2019-11-15 23:09:51,881 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 44 transitions. Word has length 12 [2019-11-15 23:09:51,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:51,881 INFO L462 AbstractCegarLoop]: Abstraction has 40 states and 44 transitions. [2019-11-15 23:09:51,882 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:09:51,882 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 44 transitions. [2019-11-15 23:09:51,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2019-11-15 23:09:51,882 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:51,882 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:51,883 INFO L410 AbstractCegarLoop]: === Iteration 4 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:51,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:51,883 INFO L82 PathProgramCache]: Analyzing trace with hash 863296134, now seen corresponding path program 1 times [2019-11-15 23:09:51,883 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:51,883 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387721409] [2019-11-15 23:09:51,884 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:51,884 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:51,884 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:51,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:51,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:51,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:09:51,986 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387721409] [2019-11-15 23:09:51,987 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:09:51,987 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 23:09:51,987 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [544149377] [2019-11-15 23:09:51,987 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-15 23:09:51,987 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:51,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-15 23:09:51,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-11-15 23:09:51,988 INFO L87 Difference]: Start difference. First operand 40 states and 44 transitions. Second operand 7 states. [2019-11-15 23:09:52,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:52,144 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2019-11-15 23:09:52,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-15 23:09:52,145 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 12 [2019-11-15 23:09:52,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:52,146 INFO L225 Difference]: With dead ends: 42 [2019-11-15 23:09:52,146 INFO L226 Difference]: Without dead ends: 42 [2019-11-15 23:09:52,146 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2019-11-15 23:09:52,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2019-11-15 23:09:52,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 39. [2019-11-15 23:09:52,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2019-11-15 23:09:52,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 43 transitions. [2019-11-15 23:09:52,152 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 43 transitions. Word has length 12 [2019-11-15 23:09:52,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:52,152 INFO L462 AbstractCegarLoop]: Abstraction has 39 states and 43 transitions. [2019-11-15 23:09:52,152 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-15 23:09:52,152 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 43 transitions. [2019-11-15 23:09:52,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-11-15 23:09:52,153 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:52,153 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:52,154 INFO L410 AbstractCegarLoop]: === Iteration 5 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:52,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:52,154 INFO L82 PathProgramCache]: Analyzing trace with hash 143250926, now seen corresponding path program 1 times [2019-11-15 23:09:52,154 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:52,155 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204209339] [2019-11-15 23:09:52,155 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:52,155 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:52,155 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:52,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:52,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:52,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:52,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:09:52,230 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1204209339] [2019-11-15 23:09:52,231 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:09:52,231 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:09:52,231 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [513713385] [2019-11-15 23:09:52,231 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:09:52,232 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:52,232 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:09:52,232 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:09:52,232 INFO L87 Difference]: Start difference. First operand 39 states and 43 transitions. Second operand 4 states. [2019-11-15 23:09:52,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:52,293 INFO L93 Difference]: Finished difference Result 37 states and 41 transitions. [2019-11-15 23:09:52,293 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-15 23:09:52,293 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-11-15 23:09:52,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:52,294 INFO L225 Difference]: With dead ends: 37 [2019-11-15 23:09:52,294 INFO L226 Difference]: Without dead ends: 37 [2019-11-15 23:09:52,295 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:09:52,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2019-11-15 23:09:52,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2019-11-15 23:09:52,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2019-11-15 23:09:52,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 41 transitions. [2019-11-15 23:09:52,299 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 41 transitions. Word has length 15 [2019-11-15 23:09:52,299 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:52,299 INFO L462 AbstractCegarLoop]: Abstraction has 37 states and 41 transitions. [2019-11-15 23:09:52,300 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:09:52,300 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 41 transitions. [2019-11-15 23:09:52,300 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-11-15 23:09:52,300 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:52,301 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:52,301 INFO L410 AbstractCegarLoop]: === Iteration 6 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:52,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:52,301 INFO L82 PathProgramCache]: Analyzing trace with hash 143250927, now seen corresponding path program 1 times [2019-11-15 23:09:52,301 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:52,302 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66677512] [2019-11-15 23:09:52,302 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:52,302 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:52,302 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:52,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:52,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:52,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:52,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:09:52,399 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [66677512] [2019-11-15 23:09:52,399 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:09:52,399 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 23:09:52,399 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938600859] [2019-11-15 23:09:52,400 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:09:52,400 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:52,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:09:52,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 23:09:52,401 INFO L87 Difference]: Start difference. First operand 37 states and 41 transitions. Second operand 6 states. [2019-11-15 23:09:52,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:52,575 INFO L93 Difference]: Finished difference Result 56 states and 61 transitions. [2019-11-15 23:09:52,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 23:09:52,576 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 15 [2019-11-15 23:09:52,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:52,577 INFO L225 Difference]: With dead ends: 56 [2019-11-15 23:09:52,577 INFO L226 Difference]: Without dead ends: 56 [2019-11-15 23:09:52,577 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2019-11-15 23:09:52,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2019-11-15 23:09:52,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 41. [2019-11-15 23:09:52,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2019-11-15 23:09:52,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 46 transitions. [2019-11-15 23:09:52,583 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 46 transitions. Word has length 15 [2019-11-15 23:09:52,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:52,584 INFO L462 AbstractCegarLoop]: Abstraction has 41 states and 46 transitions. [2019-11-15 23:09:52,584 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:09:52,584 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 46 transitions. [2019-11-15 23:09:52,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-11-15 23:09:52,586 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:52,586 INFO L380 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:52,586 INFO L410 AbstractCegarLoop]: === Iteration 7 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:52,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:52,587 INFO L82 PathProgramCache]: Analyzing trace with hash 1623425863, now seen corresponding path program 1 times [2019-11-15 23:09:52,587 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:52,587 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452951558] [2019-11-15 23:09:52,587 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:52,588 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:52,588 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:52,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:52,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:52,716 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:09:52,716 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1452951558] [2019-11-15 23:09:52,716 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [670402256] [2019-11-15 23:09:52,717 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:52,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:52,775 INFO L256 TraceCheckSpWp]: Trace formula consists of 74 conjuncts, 5 conjunts are in the unsatisfiable core [2019-11-15 23:09:52,782 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:09:52,825 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:09:52,826 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:09:52,826 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 3] total 9 [2019-11-15 23:09:52,826 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [638837377] [2019-11-15 23:09:52,826 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-11-15 23:09:52,827 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:52,827 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-11-15 23:09:52,827 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2019-11-15 23:09:52,827 INFO L87 Difference]: Start difference. First operand 41 states and 46 transitions. Second operand 10 states. [2019-11-15 23:09:53,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:53,213 INFO L93 Difference]: Finished difference Result 85 states and 92 transitions. [2019-11-15 23:09:53,213 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-11-15 23:09:53,213 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 16 [2019-11-15 23:09:53,213 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:53,214 INFO L225 Difference]: With dead ends: 85 [2019-11-15 23:09:53,214 INFO L226 Difference]: Without dead ends: 82 [2019-11-15 23:09:53,215 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 15 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=77, Invalid=229, Unknown=0, NotChecked=0, Total=306 [2019-11-15 23:09:53,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2019-11-15 23:09:53,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 53. [2019-11-15 23:09:53,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2019-11-15 23:09:53,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 59 transitions. [2019-11-15 23:09:53,220 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 59 transitions. Word has length 16 [2019-11-15 23:09:53,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:53,221 INFO L462 AbstractCegarLoop]: Abstraction has 53 states and 59 transitions. [2019-11-15 23:09:53,221 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-11-15 23:09:53,221 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 59 transitions. [2019-11-15 23:09:53,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2019-11-15 23:09:53,222 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:53,222 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:53,423 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:53,423 INFO L410 AbstractCegarLoop]: === Iteration 8 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:53,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:53,423 INFO L82 PathProgramCache]: Analyzing trace with hash 2121234190, now seen corresponding path program 1 times [2019-11-15 23:09:53,423 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:53,424 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945163367] [2019-11-15 23:09:53,424 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:53,424 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:53,424 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:53,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:53,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:53,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:53,518 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:09:53,518 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945163367] [2019-11-15 23:09:53,518 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1972838472] [2019-11-15 23:09:53,519 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:53,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:53,562 INFO L256 TraceCheckSpWp]: Trace formula consists of 81 conjuncts, 6 conjunts are in the unsatisfiable core [2019-11-15 23:09:53,564 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:09:53,626 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:09:53,627 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:09:53,627 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6] total 10 [2019-11-15 23:09:53,627 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194008592] [2019-11-15 23:09:53,628 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-11-15 23:09:53,628 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:53,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-11-15 23:09:53,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-11-15 23:09:53,629 INFO L87 Difference]: Start difference. First operand 53 states and 59 transitions. Second operand 10 states. [2019-11-15 23:09:53,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:53,868 INFO L93 Difference]: Finished difference Result 86 states and 90 transitions. [2019-11-15 23:09:53,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-15 23:09:53,869 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 20 [2019-11-15 23:09:53,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:53,870 INFO L225 Difference]: With dead ends: 86 [2019-11-15 23:09:53,870 INFO L226 Difference]: Without dead ends: 77 [2019-11-15 23:09:53,870 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 19 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=128, Unknown=0, NotChecked=0, Total=182 [2019-11-15 23:09:53,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2019-11-15 23:09:53,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 58. [2019-11-15 23:09:53,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2019-11-15 23:09:53,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 62 transitions. [2019-11-15 23:09:53,877 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 62 transitions. Word has length 20 [2019-11-15 23:09:53,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:53,877 INFO L462 AbstractCegarLoop]: Abstraction has 58 states and 62 transitions. [2019-11-15 23:09:53,877 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-11-15 23:09:53,877 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 62 transitions. [2019-11-15 23:09:53,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-11-15 23:09:53,878 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:53,878 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:54,086 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:54,086 INFO L410 AbstractCegarLoop]: === Iteration 9 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:54,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:54,087 INFO L82 PathProgramCache]: Analyzing trace with hash -523456177, now seen corresponding path program 2 times [2019-11-15 23:09:54,087 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:54,087 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1243995692] [2019-11-15 23:09:54,087 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:54,088 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:54,088 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:54,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:54,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:54,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:54,156 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-15 23:09:54,156 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1243995692] [2019-11-15 23:09:54,156 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:09:54,157 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:09:54,157 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [890095349] [2019-11-15 23:09:54,157 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:09:54,158 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:54,158 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:09:54,158 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:09:54,158 INFO L87 Difference]: Start difference. First operand 58 states and 62 transitions. Second operand 4 states. [2019-11-15 23:09:54,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:54,240 INFO L93 Difference]: Finished difference Result 62 states and 66 transitions. [2019-11-15 23:09:54,241 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-15 23:09:54,241 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2019-11-15 23:09:54,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:54,242 INFO L225 Difference]: With dead ends: 62 [2019-11-15 23:09:54,242 INFO L226 Difference]: Without dead ends: 62 [2019-11-15 23:09:54,243 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:09:54,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2019-11-15 23:09:54,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 60. [2019-11-15 23:09:54,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2019-11-15 23:09:54,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 64 transitions. [2019-11-15 23:09:54,247 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 64 transitions. Word has length 25 [2019-11-15 23:09:54,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:54,248 INFO L462 AbstractCegarLoop]: Abstraction has 60 states and 64 transitions. [2019-11-15 23:09:54,248 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:09:54,248 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 64 transitions. [2019-11-15 23:09:54,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-11-15 23:09:54,249 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:54,249 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:54,249 INFO L410 AbstractCegarLoop]: === Iteration 10 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:54,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:54,250 INFO L82 PathProgramCache]: Analyzing trace with hash 2020089664, now seen corresponding path program 1 times [2019-11-15 23:09:54,250 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:54,250 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557391398] [2019-11-15 23:09:54,250 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:54,251 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:54,251 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:54,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:54,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:54,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:54,377 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:09:54,377 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557391398] [2019-11-15 23:09:54,377 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1915979442] [2019-11-15 23:09:54,378 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:54,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:54,441 INFO L256 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 3 conjunts are in the unsatisfiable core [2019-11-15 23:09:54,444 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:09:54,466 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-15 23:09:54,466 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:09:54,466 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 4] total 11 [2019-11-15 23:09:54,467 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1857453694] [2019-11-15 23:09:54,467 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-11-15 23:09:54,467 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:54,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-11-15 23:09:54,468 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=82, Unknown=0, NotChecked=0, Total=110 [2019-11-15 23:09:54,468 INFO L87 Difference]: Start difference. First operand 60 states and 64 transitions. Second operand 11 states. [2019-11-15 23:09:54,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:54,797 INFO L93 Difference]: Finished difference Result 118 states and 126 transitions. [2019-11-15 23:09:54,797 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-11-15 23:09:54,797 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 31 [2019-11-15 23:09:54,798 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:54,798 INFO L225 Difference]: With dead ends: 118 [2019-11-15 23:09:54,799 INFO L226 Difference]: Without dead ends: 118 [2019-11-15 23:09:54,799 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=80, Invalid=226, Unknown=0, NotChecked=0, Total=306 [2019-11-15 23:09:54,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2019-11-15 23:09:54,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 96. [2019-11-15 23:09:54,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2019-11-15 23:09:54,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 114 transitions. [2019-11-15 23:09:54,807 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 114 transitions. Word has length 31 [2019-11-15 23:09:54,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:54,808 INFO L462 AbstractCegarLoop]: Abstraction has 96 states and 114 transitions. [2019-11-15 23:09:54,808 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-11-15 23:09:54,808 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 114 transitions. [2019-11-15 23:09:54,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-11-15 23:09:54,809 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:54,809 INFO L380 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:55,012 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:55,012 INFO L410 AbstractCegarLoop]: === Iteration 11 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:55,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:55,013 INFO L82 PathProgramCache]: Analyzing trace with hash -1710006518, now seen corresponding path program 1 times [2019-11-15 23:09:55,013 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:55,013 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1712936379] [2019-11-15 23:09:55,013 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:55,013 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:55,013 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:55,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:55,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:55,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:55,129 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 35 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-15 23:09:55,129 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1712936379] [2019-11-15 23:09:55,129 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [418696358] [2019-11-15 23:09:55,129 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:55,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:55,179 INFO L256 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 7 conjunts are in the unsatisfiable core [2019-11-15 23:09:55,181 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:09:55,221 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 27 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-11-15 23:09:55,222 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:09:55,222 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 4] total 12 [2019-11-15 23:09:55,222 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112263911] [2019-11-15 23:09:55,222 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-15 23:09:55,223 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:55,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-15 23:09:55,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2019-11-15 23:09:55,223 INFO L87 Difference]: Start difference. First operand 96 states and 114 transitions. Second operand 13 states. [2019-11-15 23:09:55,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:55,678 INFO L93 Difference]: Finished difference Result 152 states and 170 transitions. [2019-11-15 23:09:55,678 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-11-15 23:09:55,678 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 42 [2019-11-15 23:09:55,679 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:55,681 INFO L225 Difference]: With dead ends: 152 [2019-11-15 23:09:55,681 INFO L226 Difference]: Without dead ends: 152 [2019-11-15 23:09:55,681 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 42 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=96, Invalid=366, Unknown=0, NotChecked=0, Total=462 [2019-11-15 23:09:55,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2019-11-15 23:09:55,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 124. [2019-11-15 23:09:55,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2019-11-15 23:09:55,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 144 transitions. [2019-11-15 23:09:55,690 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 144 transitions. Word has length 42 [2019-11-15 23:09:55,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:55,691 INFO L462 AbstractCegarLoop]: Abstraction has 124 states and 144 transitions. [2019-11-15 23:09:55,691 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-15 23:09:55,691 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 144 transitions. [2019-11-15 23:09:55,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-15 23:09:55,692 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:55,692 INFO L380 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:55,893 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:55,893 INFO L410 AbstractCegarLoop]: === Iteration 12 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:55,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:55,894 INFO L82 PathProgramCache]: Analyzing trace with hash -1860847279, now seen corresponding path program 1 times [2019-11-15 23:09:55,894 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:55,894 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925262198] [2019-11-15 23:09:55,894 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:55,894 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:55,895 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:55,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:55,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:55,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:55,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:56,049 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 5 proven. 41 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-11-15 23:09:56,050 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925262198] [2019-11-15 23:09:56,050 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1257942815] [2019-11-15 23:09:56,050 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:56,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:56,106 INFO L256 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-15 23:09:56,109 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:09:56,184 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 32 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-15 23:09:56,184 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:09:56,184 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 8] total 16 [2019-11-15 23:09:56,185 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090943595] [2019-11-15 23:09:56,185 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-11-15 23:09:56,185 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:56,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-11-15 23:09:56,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=196, Unknown=0, NotChecked=0, Total=240 [2019-11-15 23:09:56,186 INFO L87 Difference]: Start difference. First operand 124 states and 144 transitions. Second operand 16 states. [2019-11-15 23:09:56,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:56,546 INFO L93 Difference]: Finished difference Result 141 states and 154 transitions. [2019-11-15 23:09:56,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-15 23:09:56,546 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 46 [2019-11-15 23:09:56,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:56,547 INFO L225 Difference]: With dead ends: 141 [2019-11-15 23:09:56,547 INFO L226 Difference]: Without dead ends: 135 [2019-11-15 23:09:56,548 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 48 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=107, Invalid=355, Unknown=0, NotChecked=0, Total=462 [2019-11-15 23:09:56,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2019-11-15 23:09:56,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 112. [2019-11-15 23:09:56,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2019-11-15 23:09:56,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 126 transitions. [2019-11-15 23:09:56,554 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 126 transitions. Word has length 46 [2019-11-15 23:09:56,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:56,554 INFO L462 AbstractCegarLoop]: Abstraction has 112 states and 126 transitions. [2019-11-15 23:09:56,554 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-11-15 23:09:56,554 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 126 transitions. [2019-11-15 23:09:56,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-11-15 23:09:56,556 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:56,556 INFO L380 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:56,756 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:56,756 INFO L410 AbstractCegarLoop]: === Iteration 13 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:56,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:56,757 INFO L82 PathProgramCache]: Analyzing trace with hash -1743494932, now seen corresponding path program 2 times [2019-11-15 23:09:56,757 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:56,757 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781163391] [2019-11-15 23:09:56,757 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:56,757 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:56,757 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:56,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:56,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:56,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:56,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:56,845 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-11-15 23:09:56,846 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781163391] [2019-11-15 23:09:56,846 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [49493881] [2019-11-15 23:09:56,846 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:56,914 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-11-15 23:09:56,914 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:09:56,915 INFO L256 TraceCheckSpWp]: Trace formula consists of 162 conjuncts, 10 conjunts are in the unsatisfiable core [2019-11-15 23:09:56,924 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:09:56,966 INFO L392 ElimStorePlain]: Different costs {0=[|v_#length_12|], 1=[|v_#valid_24|]} [2019-11-15 23:09:56,978 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-11-15 23:09:56,989 INFO L375 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 11 [2019-11-15 23:09:56,990 INFO L496 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-11-15 23:09:57,015 INFO L567 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-11-15 23:09:57,021 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-11-15 23:09:57,025 INFO L375 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2019-11-15 23:09:57,026 INFO L496 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2019-11-15 23:09:57,035 INFO L567 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-11-15 23:09:57,036 INFO L496 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-11-15 23:09:57,037 INFO L221 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:24, output treesize:17 [2019-11-15 23:09:57,255 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-11-15 23:09:57,255 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:09:57,256 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 7 [2019-11-15 23:09:57,256 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1119928088] [2019-11-15 23:09:57,257 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-11-15 23:09:57,257 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:57,258 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-15 23:09:57,258 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2019-11-15 23:09:57,258 INFO L87 Difference]: Start difference. First operand 112 states and 126 transitions. Second operand 8 states. [2019-11-15 23:09:57,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:57,474 INFO L93 Difference]: Finished difference Result 112 states and 125 transitions. [2019-11-15 23:09:57,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-15 23:09:57,474 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2019-11-15 23:09:57,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:57,476 INFO L225 Difference]: With dead ends: 112 [2019-11-15 23:09:57,476 INFO L226 Difference]: Without dead ends: 112 [2019-11-15 23:09:57,476 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 52 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-11-15 23:09:57,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2019-11-15 23:09:57,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2019-11-15 23:09:57,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2019-11-15 23:09:57,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 125 transitions. [2019-11-15 23:09:57,487 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 125 transitions. Word has length 51 [2019-11-15 23:09:57,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:57,488 INFO L462 AbstractCegarLoop]: Abstraction has 112 states and 125 transitions. [2019-11-15 23:09:57,488 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-11-15 23:09:57,488 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 125 transitions. [2019-11-15 23:09:57,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 23:09:57,503 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:57,503 INFO L380 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:57,707 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:57,708 INFO L410 AbstractCegarLoop]: === Iteration 14 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:57,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:57,708 INFO L82 PathProgramCache]: Analyzing trace with hash 1240037378, now seen corresponding path program 2 times [2019-11-15 23:09:57,708 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:57,709 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725393743] [2019-11-15 23:09:57,709 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:57,709 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:57,709 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:57,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:57,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:57,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:57,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:57,873 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 113 proven. 13 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-11-15 23:09:57,874 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725393743] [2019-11-15 23:09:57,874 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [36739464] [2019-11-15 23:09:57,874 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:57,944 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-11-15 23:09:57,944 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:09:57,945 INFO L256 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 9 conjunts are in the unsatisfiable core [2019-11-15 23:09:57,948 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:09:58,008 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 93 proven. 21 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2019-11-15 23:09:58,009 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:09:58,009 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 5] total 15 [2019-11-15 23:09:58,009 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188499952] [2019-11-15 23:09:58,009 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-11-15 23:09:58,010 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:58,010 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-11-15 23:09:58,010 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=198, Unknown=0, NotChecked=0, Total=240 [2019-11-15 23:09:58,011 INFO L87 Difference]: Start difference. First operand 112 states and 125 transitions. Second operand 16 states. [2019-11-15 23:09:58,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:58,592 INFO L93 Difference]: Finished difference Result 188 states and 199 transitions. [2019-11-15 23:09:58,593 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-11-15 23:09:58,593 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 73 [2019-11-15 23:09:58,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:58,594 INFO L225 Difference]: With dead ends: 188 [2019-11-15 23:09:58,594 INFO L226 Difference]: Without dead ends: 188 [2019-11-15 23:09:58,595 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 74 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 120 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=126, Invalid=576, Unknown=0, NotChecked=0, Total=702 [2019-11-15 23:09:58,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2019-11-15 23:09:58,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 137. [2019-11-15 23:09:58,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2019-11-15 23:09:58,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 151 transitions. [2019-11-15 23:09:58,600 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 151 transitions. Word has length 73 [2019-11-15 23:09:58,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:58,601 INFO L462 AbstractCegarLoop]: Abstraction has 137 states and 151 transitions. [2019-11-15 23:09:58,601 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-11-15 23:09:58,601 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 151 transitions. [2019-11-15 23:09:58,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2019-11-15 23:09:58,602 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:58,602 INFO L380 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:58,803 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:58,803 INFO L410 AbstractCegarLoop]: === Iteration 15 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:58,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:58,803 INFO L82 PathProgramCache]: Analyzing trace with hash -976841143, now seen corresponding path program 3 times [2019-11-15 23:09:58,804 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:58,804 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946268331] [2019-11-15 23:09:58,804 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:58,804 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:58,804 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:58,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:58,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:58,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:58,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:58,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:59,023 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 70 proven. 102 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-11-15 23:09:59,023 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1946268331] [2019-11-15 23:09:59,023 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1664468780] [2019-11-15 23:09:59,023 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:59,090 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-11-15 23:09:59,091 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:09:59,091 INFO L256 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-15 23:09:59,099 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:09:59,105 INFO L392 ElimStorePlain]: Different costs {0=[|v_#length_13|], 1=[|v_#valid_25|]} [2019-11-15 23:09:59,109 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-11-15 23:09:59,110 INFO L375 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 11 [2019-11-15 23:09:59,111 INFO L496 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-11-15 23:09:59,119 INFO L567 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-11-15 23:09:59,121 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-11-15 23:09:59,123 INFO L375 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2019-11-15 23:09:59,123 INFO L496 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2019-11-15 23:09:59,133 INFO L567 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-11-15 23:09:59,134 INFO L496 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-11-15 23:09:59,134 INFO L221 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:14 [2019-11-15 23:09:59,460 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 183 trivial. 0 not checked. [2019-11-15 23:09:59,461 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 23:09:59,461 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [15] total 20 [2019-11-15 23:09:59,461 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128492899] [2019-11-15 23:09:59,462 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-15 23:09:59,462 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:09:59,462 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-15 23:09:59,463 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=317, Unknown=0, NotChecked=0, Total=380 [2019-11-15 23:09:59,463 INFO L87 Difference]: Start difference. First operand 137 states and 151 transitions. Second operand 7 states. [2019-11-15 23:09:59,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:09:59,531 INFO L93 Difference]: Finished difference Result 137 states and 147 transitions. [2019-11-15 23:09:59,531 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-15 23:09:59,531 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 77 [2019-11-15 23:09:59,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:09:59,532 INFO L225 Difference]: With dead ends: 137 [2019-11-15 23:09:59,532 INFO L226 Difference]: Without dead ends: 137 [2019-11-15 23:09:59,532 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 73 SyntacticMatches, 5 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 114 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=63, Invalid=317, Unknown=0, NotChecked=0, Total=380 [2019-11-15 23:09:59,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2019-11-15 23:09:59,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 136. [2019-11-15 23:09:59,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2019-11-15 23:09:59,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 146 transitions. [2019-11-15 23:09:59,537 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 146 transitions. Word has length 77 [2019-11-15 23:09:59,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:09:59,537 INFO L462 AbstractCegarLoop]: Abstraction has 136 states and 146 transitions. [2019-11-15 23:09:59,538 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-15 23:09:59,538 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 146 transitions. [2019-11-15 23:09:59,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2019-11-15 23:09:59,539 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:09:59,539 INFO L380 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:09:59,742 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:59,743 INFO L410 AbstractCegarLoop]: === Iteration 16 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:09:59,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:09:59,743 INFO L82 PathProgramCache]: Analyzing trace with hash -526178640, now seen corresponding path program 3 times [2019-11-15 23:09:59,743 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:09:59,743 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674589283] [2019-11-15 23:09:59,743 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:59,743 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:09:59,743 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:09:59,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:59,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:59,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:59,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:59,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:09:59,929 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 274 proven. 102 refuted. 0 times theorem prover too weak. 59 trivial. 0 not checked. [2019-11-15 23:09:59,930 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1674589283] [2019-11-15 23:09:59,930 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [299957708] [2019-11-15 23:09:59,930 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:09:59,995 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2019-11-15 23:09:59,996 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:09:59,997 INFO L256 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 10 conjunts are in the unsatisfiable core [2019-11-15 23:09:59,999 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:00,166 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 207 proven. 28 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2019-11-15 23:10:00,166 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:00,167 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 10] total 24 [2019-11-15 23:10:00,167 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962972103] [2019-11-15 23:10:00,168 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-11-15 23:10:00,168 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:00,168 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-11-15 23:10:00,169 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=486, Unknown=0, NotChecked=0, Total=552 [2019-11-15 23:10:00,169 INFO L87 Difference]: Start difference. First operand 136 states and 146 transitions. Second operand 24 states. [2019-11-15 23:10:01,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:01,449 INFO L93 Difference]: Finished difference Result 224 states and 237 transitions. [2019-11-15 23:10:01,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-11-15 23:10:01,449 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 104 [2019-11-15 23:10:01,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:01,451 INFO L225 Difference]: With dead ends: 224 [2019-11-15 23:10:01,451 INFO L226 Difference]: Without dead ends: 218 [2019-11-15 23:10:01,452 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 106 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 442 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=399, Invalid=1763, Unknown=0, NotChecked=0, Total=2162 [2019-11-15 23:10:01,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states. [2019-11-15 23:10:01,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 180. [2019-11-15 23:10:01,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2019-11-15 23:10:01,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 193 transitions. [2019-11-15 23:10:01,458 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 193 transitions. Word has length 104 [2019-11-15 23:10:01,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:01,459 INFO L462 AbstractCegarLoop]: Abstraction has 180 states and 193 transitions. [2019-11-15 23:10:01,459 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-11-15 23:10:01,459 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 193 transitions. [2019-11-15 23:10:01,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2019-11-15 23:10:01,460 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:01,460 INFO L380 BasicCegarLoop]: trace histogram [13, 13, 13, 13, 13, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:01,664 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:01,664 INFO L410 AbstractCegarLoop]: === Iteration 17 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:01,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:01,664 INFO L82 PathProgramCache]: Analyzing trace with hash -118889443, now seen corresponding path program 2 times [2019-11-15 23:10:01,664 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:01,664 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466850592] [2019-11-15 23:10:01,665 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:01,665 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:01,665 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:01,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:01,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:01,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:01,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:01,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:01,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:01,807 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 229 proven. 34 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2019-11-15 23:10:01,807 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466850592] [2019-11-15 23:10:01,808 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1169013917] [2019-11-15 23:10:01,808 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:01,853 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2019-11-15 23:10:01,853 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:01,854 INFO L256 TraceCheckSpWp]: Trace formula consists of 48 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-15 23:10:01,856 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:01,862 INFO L392 ElimStorePlain]: Different costs {0=[|v_#length_14|], 1=[|v_#valid_26|]} [2019-11-15 23:10:01,865 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-11-15 23:10:01,866 INFO L375 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 11 [2019-11-15 23:10:01,866 INFO L496 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-11-15 23:10:01,872 INFO L567 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-11-15 23:10:01,874 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-11-15 23:10:01,875 INFO L375 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2019-11-15 23:10:01,876 INFO L496 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2019-11-15 23:10:01,888 INFO L567 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-11-15 23:10:01,889 INFO L496 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-11-15 23:10:01,889 INFO L221 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:14 [2019-11-15 23:10:02,231 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2019-11-15 23:10:02,232 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 23:10:02,232 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [11] total 15 [2019-11-15 23:10:02,232 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1898022781] [2019-11-15 23:10:02,232 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:10:02,233 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:02,233 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:10:02,233 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=165, Unknown=0, NotChecked=0, Total=210 [2019-11-15 23:10:02,233 INFO L87 Difference]: Start difference. First operand 180 states and 193 transitions. Second operand 6 states. [2019-11-15 23:10:02,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:02,270 INFO L93 Difference]: Finished difference Result 179 states and 192 transitions. [2019-11-15 23:10:02,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:10:02,273 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 119 [2019-11-15 23:10:02,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:02,275 INFO L225 Difference]: With dead ends: 179 [2019-11-15 23:10:02,275 INFO L226 Difference]: Without dead ends: 179 [2019-11-15 23:10:02,275 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 117 SyntacticMatches, 7 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=45, Invalid=165, Unknown=0, NotChecked=0, Total=210 [2019-11-15 23:10:02,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2019-11-15 23:10:02,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2019-11-15 23:10:02,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2019-11-15 23:10:02,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 192 transitions. [2019-11-15 23:10:02,281 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 192 transitions. Word has length 119 [2019-11-15 23:10:02,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:02,281 INFO L462 AbstractCegarLoop]: Abstraction has 179 states and 192 transitions. [2019-11-15 23:10:02,282 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:10:02,282 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 192 transitions. [2019-11-15 23:10:02,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2019-11-15 23:10:02,283 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:02,283 INFO L380 BasicCegarLoop]: trace histogram [13, 13, 13, 13, 13, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:02,486 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:02,486 INFO L410 AbstractCegarLoop]: === Iteration 18 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:02,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:02,487 INFO L82 PathProgramCache]: Analyzing trace with hash 1512623851, now seen corresponding path program 1 times [2019-11-15 23:10:02,487 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:02,487 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568216555] [2019-11-15 23:10:02,487 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:02,487 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:02,487 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:02,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:02,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:02,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:02,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:02,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:02,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:02,637 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 229 proven. 34 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2019-11-15 23:10:02,638 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568216555] [2019-11-15 23:10:02,638 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [560990699] [2019-11-15 23:10:02,638 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:02,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:02,735 INFO L256 TraceCheckSpWp]: Trace formula consists of 346 conjuncts, 12 conjunts are in the unsatisfiable core [2019-11-15 23:10:02,737 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:02,945 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 253 proven. 34 refuted. 0 times theorem prover too weak. 225 trivial. 0 not checked. [2019-11-15 23:10:02,945 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:02,946 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12] total 20 [2019-11-15 23:10:02,946 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304274505] [2019-11-15 23:10:02,946 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-11-15 23:10:02,947 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:02,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-11-15 23:10:02,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=301, Unknown=0, NotChecked=0, Total=380 [2019-11-15 23:10:02,948 INFO L87 Difference]: Start difference. First operand 179 states and 192 transitions. Second operand 20 states. [2019-11-15 23:10:03,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:03,409 INFO L93 Difference]: Finished difference Result 267 states and 280 transitions. [2019-11-15 23:10:03,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-11-15 23:10:03,409 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 122 [2019-11-15 23:10:03,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:03,410 INFO L225 Difference]: With dead ends: 267 [2019-11-15 23:10:03,411 INFO L226 Difference]: Without dead ends: 264 [2019-11-15 23:10:03,411 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 167 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=212, Invalid=910, Unknown=0, NotChecked=0, Total=1122 [2019-11-15 23:10:03,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 264 states. [2019-11-15 23:10:03,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 264 to 176. [2019-11-15 23:10:03,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2019-11-15 23:10:03,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 186 transitions. [2019-11-15 23:10:03,417 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 186 transitions. Word has length 122 [2019-11-15 23:10:03,418 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:03,418 INFO L462 AbstractCegarLoop]: Abstraction has 176 states and 186 transitions. [2019-11-15 23:10:03,418 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-11-15 23:10:03,418 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 186 transitions. [2019-11-15 23:10:03,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-11-15 23:10:03,419 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:03,419 INFO L380 BasicCegarLoop]: trace histogram [14, 14, 14, 14, 14, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:03,619 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:03,620 INFO L410 AbstractCegarLoop]: === Iteration 19 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:03,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:03,620 INFO L82 PathProgramCache]: Analyzing trace with hash -1295783610, now seen corresponding path program 2 times [2019-11-15 23:10:03,620 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:03,620 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806525886] [2019-11-15 23:10:03,620 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:03,621 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:03,621 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:03,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:03,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:03,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:03,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:03,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:03,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:03,804 INFO L134 CoverageAnalysis]: Checked inductivity of 581 backedges. 277 proven. 55 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2019-11-15 23:10:03,805 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806525886] [2019-11-15 23:10:03,805 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1541280196] [2019-11-15 23:10:03,805 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:03,859 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2019-11-15 23:10:03,859 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:03,859 INFO L256 TraceCheckSpWp]: Trace formula consists of 58 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-15 23:10:03,861 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:03,906 INFO L341 Elim1Store]: treesize reduction 14, result has 50.0 percent of original size [2019-11-15 23:10:03,907 INFO L375 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 29 [2019-11-15 23:10:03,907 INFO L496 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-11-15 23:10:03,911 INFO L567 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-11-15 23:10:03,912 INFO L496 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-11-15 23:10:03,912 INFO L221 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:23, output treesize:15 [2019-11-15 23:10:03,986 INFO L341 Elim1Store]: treesize reduction 14, result has 50.0 percent of original size [2019-11-15 23:10:03,986 INFO L375 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 29 [2019-11-15 23:10:03,987 INFO L496 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-11-15 23:10:03,992 INFO L567 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-11-15 23:10:03,993 INFO L496 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-11-15 23:10:03,993 INFO L221 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:23, output treesize:15 [2019-11-15 23:10:04,067 INFO L341 Elim1Store]: treesize reduction 14, result has 50.0 percent of original size [2019-11-15 23:10:04,067 INFO L375 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 29 [2019-11-15 23:10:04,068 INFO L496 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-11-15 23:10:04,073 INFO L567 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-11-15 23:10:04,074 INFO L496 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-11-15 23:10:04,074 INFO L221 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:23, output treesize:15 [2019-11-15 23:10:04,154 INFO L341 Elim1Store]: treesize reduction 14, result has 50.0 percent of original size [2019-11-15 23:10:04,155 INFO L375 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 29 [2019-11-15 23:10:04,155 INFO L496 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-11-15 23:10:04,161 INFO L567 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-11-15 23:10:04,161 INFO L496 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-11-15 23:10:04,162 INFO L221 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:23, output treesize:15 [2019-11-15 23:10:04,332 INFO L134 CoverageAnalysis]: Checked inductivity of 581 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 581 trivial. 0 not checked. [2019-11-15 23:10:04,332 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 23:10:04,333 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [12] total 16 [2019-11-15 23:10:04,333 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083048280] [2019-11-15 23:10:04,333 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:10:04,333 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:04,333 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:10:04,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2019-11-15 23:10:04,334 INFO L87 Difference]: Start difference. First operand 176 states and 186 transitions. Second operand 6 states. [2019-11-15 23:10:04,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:04,413 INFO L93 Difference]: Finished difference Result 175 states and 185 transitions. [2019-11-15 23:10:04,414 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 23:10:04,414 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 127 [2019-11-15 23:10:04,414 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:04,415 INFO L225 Difference]: With dead ends: 175 [2019-11-15 23:10:04,415 INFO L226 Difference]: Without dead ends: 154 [2019-11-15 23:10:04,415 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 125 SyntacticMatches, 7 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=52, Invalid=220, Unknown=0, NotChecked=0, Total=272 [2019-11-15 23:10:04,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2019-11-15 23:10:04,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 154. [2019-11-15 23:10:04,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2019-11-15 23:10:04,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 159 transitions. [2019-11-15 23:10:04,419 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 159 transitions. Word has length 127 [2019-11-15 23:10:04,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:04,420 INFO L462 AbstractCegarLoop]: Abstraction has 154 states and 159 transitions. [2019-11-15 23:10:04,420 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:10:04,420 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 159 transitions. [2019-11-15 23:10:04,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2019-11-15 23:10:04,421 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:04,421 INFO L380 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:04,622 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:04,622 INFO L410 AbstractCegarLoop]: === Iteration 20 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:04,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:04,622 INFO L82 PathProgramCache]: Analyzing trace with hash -1371846361, now seen corresponding path program 4 times [2019-11-15 23:10:04,622 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:04,623 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60215029] [2019-11-15 23:10:04,623 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:04,623 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:04,623 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:04,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:04,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:04,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:04,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:04,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:04,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:04,935 INFO L134 CoverageAnalysis]: Checked inductivity of 1051 backedges. 461 proven. 49 refuted. 0 times theorem prover too weak. 541 trivial. 0 not checked. [2019-11-15 23:10:04,936 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60215029] [2019-11-15 23:10:04,936 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1684258156] [2019-11-15 23:10:04,936 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:05,051 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-11-15 23:10:05,051 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:05,053 INFO L256 TraceCheckSpWp]: Trace formula consists of 422 conjuncts, 13 conjunts are in the unsatisfiable core [2019-11-15 23:10:05,055 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:05,168 INFO L134 CoverageAnalysis]: Checked inductivity of 1051 backedges. 402 proven. 60 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-11-15 23:10:05,168 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:05,168 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 7] total 21 [2019-11-15 23:10:05,169 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568246469] [2019-11-15 23:10:05,169 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-11-15 23:10:05,170 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:05,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-11-15 23:10:05,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=390, Unknown=0, NotChecked=0, Total=462 [2019-11-15 23:10:05,170 INFO L87 Difference]: Start difference. First operand 154 states and 159 transitions. Second operand 22 states. [2019-11-15 23:10:05,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:05,907 INFO L93 Difference]: Finished difference Result 293 states and 311 transitions. [2019-11-15 23:10:05,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-11-15 23:10:05,908 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 150 [2019-11-15 23:10:05,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:05,909 INFO L225 Difference]: With dead ends: 293 [2019-11-15 23:10:05,910 INFO L226 Difference]: Without dead ends: 293 [2019-11-15 23:10:05,910 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 189 GetRequests, 153 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=195, Invalid=1137, Unknown=0, NotChecked=0, Total=1332 [2019-11-15 23:10:05,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293 states. [2019-11-15 23:10:05,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293 to 195. [2019-11-15 23:10:05,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2019-11-15 23:10:05,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 202 transitions. [2019-11-15 23:10:05,931 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 202 transitions. Word has length 150 [2019-11-15 23:10:05,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:05,931 INFO L462 AbstractCegarLoop]: Abstraction has 195 states and 202 transitions. [2019-11-15 23:10:05,931 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-11-15 23:10:05,932 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 202 transitions. [2019-11-15 23:10:05,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 192 [2019-11-15 23:10:05,934 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:05,934 INFO L380 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:06,141 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:06,141 INFO L410 AbstractCegarLoop]: === Iteration 21 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:06,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:06,142 INFO L82 PathProgramCache]: Analyzing trace with hash 1382499467, now seen corresponding path program 5 times [2019-11-15 23:10:06,142 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:06,142 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027291902] [2019-11-15 23:10:06,142 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:06,142 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:06,142 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:06,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:06,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:06,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:06,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:06,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:06,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:06,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:06,446 INFO L134 CoverageAnalysis]: Checked inductivity of 1805 backedges. 1058 proven. 272 refuted. 0 times theorem prover too weak. 475 trivial. 0 not checked. [2019-11-15 23:10:06,447 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027291902] [2019-11-15 23:10:06,447 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1214108761] [2019-11-15 23:10:06,447 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:06,591 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2019-11-15 23:10:06,591 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:06,593 INFO L256 TraceCheckSpWp]: Trace formula consists of 467 conjuncts, 18 conjunts are in the unsatisfiable core [2019-11-15 23:10:06,596 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:06,884 INFO L134 CoverageAnalysis]: Checked inductivity of 1805 backedges. 1075 proven. 311 refuted. 0 times theorem prover too weak. 419 trivial. 0 not checked. [2019-11-15 23:10:06,884 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:06,885 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 17] total 29 [2019-11-15 23:10:06,885 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553818162] [2019-11-15 23:10:06,886 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2019-11-15 23:10:06,886 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:06,887 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2019-11-15 23:10:06,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=125, Invalid=687, Unknown=0, NotChecked=0, Total=812 [2019-11-15 23:10:06,887 INFO L87 Difference]: Start difference. First operand 195 states and 202 transitions. Second operand 29 states. [2019-11-15 23:10:07,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:07,666 INFO L93 Difference]: Finished difference Result 331 states and 355 transitions. [2019-11-15 23:10:07,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-11-15 23:10:07,667 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 191 [2019-11-15 23:10:07,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:07,668 INFO L225 Difference]: With dead ends: 331 [2019-11-15 23:10:07,669 INFO L226 Difference]: Without dead ends: 325 [2019-11-15 23:10:07,669 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 235 GetRequests, 192 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 367 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=423, Invalid=1557, Unknown=0, NotChecked=0, Total=1980 [2019-11-15 23:10:07,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2019-11-15 23:10:07,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 234. [2019-11-15 23:10:07,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2019-11-15 23:10:07,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 245 transitions. [2019-11-15 23:10:07,680 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 245 transitions. Word has length 191 [2019-11-15 23:10:07,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:07,681 INFO L462 AbstractCegarLoop]: Abstraction has 234 states and 245 transitions. [2019-11-15 23:10:07,681 INFO L463 AbstractCegarLoop]: Interpolant automaton has 29 states. [2019-11-15 23:10:07,681 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 245 transitions. [2019-11-15 23:10:07,683 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2019-11-15 23:10:07,684 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:07,684 INFO L380 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:07,888 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:07,888 INFO L410 AbstractCegarLoop]: === Iteration 22 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:07,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:07,888 INFO L82 PathProgramCache]: Analyzing trace with hash 1146107562, now seen corresponding path program 6 times [2019-11-15 23:10:07,888 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:07,888 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [559842820] [2019-11-15 23:10:07,888 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:07,888 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:07,889 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:07,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:08,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:08,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:08,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:08,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:08,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:08,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:08,211 INFO L134 CoverageAnalysis]: Checked inductivity of 1937 backedges. 761 proven. 76 refuted. 0 times theorem prover too weak. 1100 trivial. 0 not checked. [2019-11-15 23:10:08,211 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [559842820] [2019-11-15 23:10:08,212 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1063249790] [2019-11-15 23:10:08,212 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:08,330 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2019-11-15 23:10:08,330 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:08,331 INFO L256 TraceCheckSpWp]: Trace formula consists of 395 conjuncts, 12 conjunts are in the unsatisfiable core [2019-11-15 23:10:08,335 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:08,419 INFO L134 CoverageAnalysis]: Checked inductivity of 1937 backedges. 701 proven. 76 refuted. 0 times theorem prover too weak. 1160 trivial. 0 not checked. [2019-11-15 23:10:08,419 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:08,419 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 12] total 20 [2019-11-15 23:10:08,420 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852595970] [2019-11-15 23:10:08,420 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-15 23:10:08,420 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:08,421 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-15 23:10:08,421 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=331, Unknown=0, NotChecked=0, Total=420 [2019-11-15 23:10:08,421 INFO L87 Difference]: Start difference. First operand 234 states and 245 transitions. Second operand 21 states. [2019-11-15 23:10:09,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:09,035 INFO L93 Difference]: Finished difference Result 367 states and 392 transitions. [2019-11-15 23:10:09,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-11-15 23:10:09,038 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 196 [2019-11-15 23:10:09,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:09,040 INFO L225 Difference]: With dead ends: 367 [2019-11-15 23:10:09,041 INFO L226 Difference]: Without dead ends: 367 [2019-11-15 23:10:09,041 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 239 GetRequests, 206 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 159 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=296, Invalid=894, Unknown=0, NotChecked=0, Total=1190 [2019-11-15 23:10:09,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states. [2019-11-15 23:10:09,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 275. [2019-11-15 23:10:09,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 275 states. [2019-11-15 23:10:09,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 275 states to 275 states and 287 transitions. [2019-11-15 23:10:09,057 INFO L78 Accepts]: Start accepts. Automaton has 275 states and 287 transitions. Word has length 196 [2019-11-15 23:10:09,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:09,058 INFO L462 AbstractCegarLoop]: Abstraction has 275 states and 287 transitions. [2019-11-15 23:10:09,058 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-15 23:10:09,058 INFO L276 IsEmpty]: Start isEmpty. Operand 275 states and 287 transitions. [2019-11-15 23:10:09,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 238 [2019-11-15 23:10:09,060 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:09,060 INFO L380 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 32, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:09,271 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:09,272 INFO L410 AbstractCegarLoop]: === Iteration 23 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:09,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:09,272 INFO L82 PathProgramCache]: Analyzing trace with hash 499852904, now seen corresponding path program 7 times [2019-11-15 23:10:09,272 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:09,272 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4607793] [2019-11-15 23:10:09,272 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:09,272 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:09,272 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:09,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:09,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:09,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:09,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:09,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:09,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:09,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:09,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:09,695 INFO L134 CoverageAnalysis]: Checked inductivity of 2925 backedges. 1581 proven. 381 refuted. 0 times theorem prover too weak. 963 trivial. 0 not checked. [2019-11-15 23:10:09,695 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [4607793] [2019-11-15 23:10:09,695 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1994560762] [2019-11-15 23:10:09,695 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:09,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:09,838 INFO L256 TraceCheckSpWp]: Trace formula consists of 644 conjuncts, 16 conjunts are in the unsatisfiable core [2019-11-15 23:10:09,841 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:10,029 INFO L134 CoverageAnalysis]: Checked inductivity of 2925 backedges. 1652 proven. 81 refuted. 0 times theorem prover too weak. 1192 trivial. 0 not checked. [2019-11-15 23:10:10,029 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:10,029 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 16] total 28 [2019-11-15 23:10:10,029 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710991703] [2019-11-15 23:10:10,030 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-11-15 23:10:10,030 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:10,031 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-11-15 23:10:10,031 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=616, Unknown=0, NotChecked=0, Total=756 [2019-11-15 23:10:10,031 INFO L87 Difference]: Start difference. First operand 275 states and 287 transitions. Second operand 28 states. [2019-11-15 23:10:10,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:10,770 INFO L93 Difference]: Finished difference Result 422 states and 455 transitions. [2019-11-15 23:10:10,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-11-15 23:10:10,771 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 237 [2019-11-15 23:10:10,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:10,773 INFO L225 Difference]: With dead ends: 422 [2019-11-15 23:10:10,774 INFO L226 Difference]: Without dead ends: 416 [2019-11-15 23:10:10,774 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 283 GetRequests, 243 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 312 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=389, Invalid=1333, Unknown=0, NotChecked=0, Total=1722 [2019-11-15 23:10:10,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416 states. [2019-11-15 23:10:10,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416 to 285. [2019-11-15 23:10:10,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 285 states. [2019-11-15 23:10:10,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 285 states to 285 states and 297 transitions. [2019-11-15 23:10:10,794 INFO L78 Accepts]: Start accepts. Automaton has 285 states and 297 transitions. Word has length 237 [2019-11-15 23:10:10,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:10,796 INFO L462 AbstractCegarLoop]: Abstraction has 285 states and 297 transitions. [2019-11-15 23:10:10,796 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-11-15 23:10:10,796 INFO L276 IsEmpty]: Start isEmpty. Operand 285 states and 297 transitions. [2019-11-15 23:10:10,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 248 [2019-11-15 23:10:10,798 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:10,799 INFO L380 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 34, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:11,010 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:11,011 INFO L410 AbstractCegarLoop]: === Iteration 24 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:11,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:11,011 INFO L82 PathProgramCache]: Analyzing trace with hash -300291550, now seen corresponding path program 8 times [2019-11-15 23:10:11,011 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:11,012 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919328534] [2019-11-15 23:10:11,012 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:11,012 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:11,012 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:11,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:11,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:11,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:11,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:11,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:11,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:11,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:11,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:11,424 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1165 proven. 109 refuted. 0 times theorem prover too weak. 1992 trivial. 0 not checked. [2019-11-15 23:10:11,425 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1919328534] [2019-11-15 23:10:11,425 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [924137791] [2019-11-15 23:10:11,425 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:11,574 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-11-15 23:10:11,574 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:11,576 INFO L256 TraceCheckSpWp]: Trace formula consists of 668 conjuncts, 17 conjunts are in the unsatisfiable core [2019-11-15 23:10:11,580 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:11,762 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1047 proven. 119 refuted. 0 times theorem prover too weak. 2100 trivial. 0 not checked. [2019-11-15 23:10:11,762 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:11,763 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 9] total 27 [2019-11-15 23:10:11,763 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726686660] [2019-11-15 23:10:11,763 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-11-15 23:10:11,763 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:11,763 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-11-15 23:10:11,764 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=646, Unknown=0, NotChecked=0, Total=756 [2019-11-15 23:10:11,764 INFO L87 Difference]: Start difference. First operand 285 states and 297 transitions. Second operand 28 states. [2019-11-15 23:10:12,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:12,817 INFO L93 Difference]: Finished difference Result 506 states and 551 transitions. [2019-11-15 23:10:12,822 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-11-15 23:10:12,822 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 247 [2019-11-15 23:10:12,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:12,825 INFO L225 Difference]: With dead ends: 506 [2019-11-15 23:10:12,825 INFO L226 Difference]: Without dead ends: 506 [2019-11-15 23:10:12,826 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 298 GetRequests, 252 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 454 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=276, Invalid=1886, Unknown=0, NotChecked=0, Total=2162 [2019-11-15 23:10:12,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states. [2019-11-15 23:10:12,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 336. [2019-11-15 23:10:12,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 336 states. [2019-11-15 23:10:12,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 336 states to 336 states and 350 transitions. [2019-11-15 23:10:12,839 INFO L78 Accepts]: Start accepts. Automaton has 336 states and 350 transitions. Word has length 247 [2019-11-15 23:10:12,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:12,840 INFO L462 AbstractCegarLoop]: Abstraction has 336 states and 350 transitions. [2019-11-15 23:10:12,840 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-11-15 23:10:12,840 INFO L276 IsEmpty]: Start isEmpty. Operand 336 states and 350 transitions. [2019-11-15 23:10:12,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 299 [2019-11-15 23:10:12,842 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:12,842 INFO L380 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 42, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:13,046 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:13,046 INFO L410 AbstractCegarLoop]: === Iteration 25 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:13,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:13,047 INFO L82 PathProgramCache]: Analyzing trace with hash -1652634800, now seen corresponding path program 9 times [2019-11-15 23:10:13,047 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:13,047 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [762177325] [2019-11-15 23:10:13,047 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:13,047 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:13,047 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:13,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:13,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:13,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:13,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:13,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:13,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:13,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:13,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:13,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:13,533 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 2594 proven. 506 refuted. 0 times theorem prover too weak. 1842 trivial. 0 not checked. [2019-11-15 23:10:13,533 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [762177325] [2019-11-15 23:10:13,533 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1765367550] [2019-11-15 23:10:13,533 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:13,674 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2019-11-15 23:10:13,674 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:13,675 INFO L256 TraceCheckSpWp]: Trace formula consists of 473 conjuncts, 12 conjunts are in the unsatisfiable core [2019-11-15 23:10:13,679 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:13,913 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 1491 proven. 156 refuted. 0 times theorem prover too weak. 3295 trivial. 0 not checked. [2019-11-15 23:10:13,913 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:13,914 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 11] total 33 [2019-11-15 23:10:13,914 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [121603524] [2019-11-15 23:10:13,914 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-11-15 23:10:13,914 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:13,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-11-15 23:10:13,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=179, Invalid=877, Unknown=0, NotChecked=0, Total=1056 [2019-11-15 23:10:13,915 INFO L87 Difference]: Start difference. First operand 336 states and 350 transitions. Second operand 33 states. [2019-11-15 23:10:14,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:14,782 INFO L93 Difference]: Finished difference Result 594 states and 648 transitions. [2019-11-15 23:10:14,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-11-15 23:10:14,782 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 298 [2019-11-15 23:10:14,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:14,786 INFO L225 Difference]: With dead ends: 594 [2019-11-15 23:10:14,786 INFO L226 Difference]: Without dead ends: 588 [2019-11-15 23:10:14,788 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 351 GetRequests, 303 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 490 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=542, Invalid=1908, Unknown=0, NotChecked=0, Total=2450 [2019-11-15 23:10:14,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 588 states. [2019-11-15 23:10:14,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 588 to 346. [2019-11-15 23:10:14,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 346 states. [2019-11-15 23:10:14,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346 states to 346 states and 360 transitions. [2019-11-15 23:10:14,804 INFO L78 Accepts]: Start accepts. Automaton has 346 states and 360 transitions. Word has length 298 [2019-11-15 23:10:14,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:14,804 INFO L462 AbstractCegarLoop]: Abstraction has 346 states and 360 transitions. [2019-11-15 23:10:14,804 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-11-15 23:10:14,804 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 360 transitions. [2019-11-15 23:10:14,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 309 [2019-11-15 23:10:14,806 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:14,807 INFO L380 BasicCegarLoop]: trace histogram [45, 44, 44, 44, 44, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:15,022 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:15,022 INFO L410 AbstractCegarLoop]: === Iteration 26 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:15,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:15,023 INFO L82 PathProgramCache]: Analyzing trace with hash 699884682, now seen corresponding path program 10 times [2019-11-15 23:10:15,023 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:15,023 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101958868] [2019-11-15 23:10:15,023 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:15,023 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:15,023 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:15,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:15,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:15,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:15,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:15,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:15,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:15,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:15,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:15,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:15,500 INFO L134 CoverageAnalysis]: Checked inductivity of 5385 backedges. 1903 proven. 157 refuted. 0 times theorem prover too weak. 3325 trivial. 0 not checked. [2019-11-15 23:10:15,500 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101958868] [2019-11-15 23:10:15,500 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1729832775] [2019-11-15 23:10:15,501 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:15,685 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-11-15 23:10:15,685 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:15,688 INFO L256 TraceCheckSpWp]: Trace formula consists of 694 conjuncts, 26 conjunts are in the unsatisfiable core [2019-11-15 23:10:15,693 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:16,270 INFO L134 CoverageAnalysis]: Checked inductivity of 5385 backedges. 1832 proven. 634 refuted. 0 times theorem prover too weak. 2919 trivial. 0 not checked. [2019-11-15 23:10:16,271 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:16,271 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 25] total 38 [2019-11-15 23:10:16,271 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690459289] [2019-11-15 23:10:16,272 INFO L442 AbstractCegarLoop]: Interpolant automaton has 38 states [2019-11-15 23:10:16,272 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:16,272 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2019-11-15 23:10:16,273 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=268, Invalid=1138, Unknown=0, NotChecked=0, Total=1406 [2019-11-15 23:10:16,273 INFO L87 Difference]: Start difference. First operand 346 states and 360 transitions. Second operand 38 states. [2019-11-15 23:10:17,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:17,505 INFO L93 Difference]: Finished difference Result 543 states and 567 transitions. [2019-11-15 23:10:17,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-11-15 23:10:17,505 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 308 [2019-11-15 23:10:17,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:17,508 INFO L225 Difference]: With dead ends: 543 [2019-11-15 23:10:17,508 INFO L226 Difference]: Without dead ends: 543 [2019-11-15 23:10:17,509 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 370 GetRequests, 309 SyntacticMatches, 0 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 825 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=769, Invalid=3137, Unknown=0, NotChecked=0, Total=3906 [2019-11-15 23:10:17,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2019-11-15 23:10:17,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 473. [2019-11-15 23:10:17,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2019-11-15 23:10:17,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 497 transitions. [2019-11-15 23:10:17,522 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 497 transitions. Word has length 308 [2019-11-15 23:10:17,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:17,523 INFO L462 AbstractCegarLoop]: Abstraction has 473 states and 497 transitions. [2019-11-15 23:10:17,523 INFO L463 AbstractCegarLoop]: Interpolant automaton has 38 states. [2019-11-15 23:10:17,523 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 497 transitions. [2019-11-15 23:10:17,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 360 [2019-11-15 23:10:17,525 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:17,526 INFO L380 BasicCegarLoop]: trace histogram [53, 52, 52, 52, 52, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:17,730 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 20 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:17,730 INFO L410 AbstractCegarLoop]: === Iteration 27 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:17,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:17,731 INFO L82 PathProgramCache]: Analyzing trace with hash -1109948414, now seen corresponding path program 11 times [2019-11-15 23:10:17,731 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:17,731 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098908851] [2019-11-15 23:10:17,731 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:17,731 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:17,731 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:17,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:17,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:17,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:17,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:17,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:17,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:17,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:17,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:17,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:17,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:18,361 INFO L134 CoverageAnalysis]: Checked inductivity of 7490 backedges. 3719 proven. 647 refuted. 0 times theorem prover too weak. 3124 trivial. 0 not checked. [2019-11-15 23:10:18,361 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1098908851] [2019-11-15 23:10:18,361 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1064020738] [2019-11-15 23:10:18,362 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:18,704 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 20 check-sat command(s) [2019-11-15 23:10:18,704 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:18,707 INFO L256 TraceCheckSpWp]: Trace formula consists of 890 conjuncts, 24 conjunts are in the unsatisfiable core [2019-11-15 23:10:18,711 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:19,166 INFO L134 CoverageAnalysis]: Checked inductivity of 7490 backedges. 3721 proven. 809 refuted. 0 times theorem prover too weak. 2960 trivial. 0 not checked. [2019-11-15 23:10:19,166 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:19,166 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24] total 39 [2019-11-15 23:10:19,167 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695958383] [2019-11-15 23:10:19,167 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2019-11-15 23:10:19,167 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:19,168 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-11-15 23:10:19,168 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=1238, Unknown=0, NotChecked=0, Total=1482 [2019-11-15 23:10:19,168 INFO L87 Difference]: Start difference. First operand 473 states and 497 transitions. Second operand 39 states. [2019-11-15 23:10:20,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:20,355 INFO L93 Difference]: Finished difference Result 545 states and 567 transitions. [2019-11-15 23:10:20,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-11-15 23:10:20,356 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 359 [2019-11-15 23:10:20,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:20,359 INFO L225 Difference]: With dead ends: 545 [2019-11-15 23:10:20,359 INFO L226 Difference]: Without dead ends: 539 [2019-11-15 23:10:20,360 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 421 GetRequests, 362 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 766 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=793, Invalid=2867, Unknown=0, NotChecked=0, Total=3660 [2019-11-15 23:10:20,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 539 states. [2019-11-15 23:10:20,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 539 to 473. [2019-11-15 23:10:20,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2019-11-15 23:10:20,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 495 transitions. [2019-11-15 23:10:20,371 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 495 transitions. Word has length 359 [2019-11-15 23:10:20,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:20,371 INFO L462 AbstractCegarLoop]: Abstraction has 473 states and 495 transitions. [2019-11-15 23:10:20,372 INFO L463 AbstractCegarLoop]: Interpolant automaton has 39 states. [2019-11-15 23:10:20,372 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 495 transitions. [2019-11-15 23:10:20,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 365 [2019-11-15 23:10:20,374 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:20,375 INFO L380 BasicCegarLoop]: trace histogram [54, 53, 53, 53, 53, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:20,579 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:20,580 INFO L410 AbstractCegarLoop]: === Iteration 28 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:20,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:20,580 INFO L82 PathProgramCache]: Analyzing trace with hash -1526039033, now seen corresponding path program 12 times [2019-11-15 23:10:20,580 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:20,580 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326123815] [2019-11-15 23:10:20,580 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:20,580 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:20,580 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:20,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:20,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:20,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:21,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:21,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:21,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:21,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:21,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:21,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:21,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:21,177 INFO L134 CoverageAnalysis]: Checked inductivity of 7760 backedges. 2345 proven. 193 refuted. 0 times theorem prover too weak. 5222 trivial. 0 not checked. [2019-11-15 23:10:21,177 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1326123815] [2019-11-15 23:10:21,177 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [519506806] [2019-11-15 23:10:21,177 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:21,438 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2019-11-15 23:10:21,438 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:21,440 INFO L256 TraceCheckSpWp]: Trace formula consists of 806 conjuncts, 15 conjunts are in the unsatisfiable core [2019-11-15 23:10:21,445 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:21,569 INFO L134 CoverageAnalysis]: Checked inductivity of 7760 backedges. 2189 proven. 193 refuted. 0 times theorem prover too weak. 5378 trivial. 0 not checked. [2019-11-15 23:10:21,569 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:21,570 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 15] total 26 [2019-11-15 23:10:21,570 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551532400] [2019-11-15 23:10:21,571 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2019-11-15 23:10:21,571 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:21,571 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-11-15 23:10:21,571 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=152, Invalid=550, Unknown=0, NotChecked=0, Total=702 [2019-11-15 23:10:21,572 INFO L87 Difference]: Start difference. First operand 473 states and 495 transitions. Second operand 27 states. [2019-11-15 23:10:22,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:22,477 INFO L93 Difference]: Finished difference Result 600 states and 623 transitions. [2019-11-15 23:10:22,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-11-15 23:10:22,477 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 364 [2019-11-15 23:10:22,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:22,480 INFO L225 Difference]: With dead ends: 600 [2019-11-15 23:10:22,480 INFO L226 Difference]: Without dead ends: 600 [2019-11-15 23:10:22,481 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 425 GetRequests, 380 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=524, Invalid=1638, Unknown=0, NotChecked=0, Total=2162 [2019-11-15 23:10:22,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 600 states. [2019-11-15 23:10:22,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 600 to 529. [2019-11-15 23:10:22,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 529 states. [2019-11-15 23:10:22,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 529 states to 529 states and 552 transitions. [2019-11-15 23:10:22,493 INFO L78 Accepts]: Start accepts. Automaton has 529 states and 552 transitions. Word has length 364 [2019-11-15 23:10:22,494 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:22,494 INFO L462 AbstractCegarLoop]: Abstraction has 529 states and 552 transitions. [2019-11-15 23:10:22,494 INFO L463 AbstractCegarLoop]: Interpolant automaton has 27 states. [2019-11-15 23:10:22,494 INFO L276 IsEmpty]: Start isEmpty. Operand 529 states and 552 transitions. [2019-11-15 23:10:22,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 421 [2019-11-15 23:10:22,497 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:22,497 INFO L380 BasicCegarLoop]: trace histogram [63, 62, 62, 62, 62, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:22,702 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:22,702 INFO L410 AbstractCegarLoop]: === Iteration 29 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:22,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:22,702 INFO L82 PathProgramCache]: Analyzing trace with hash -645464956, now seen corresponding path program 13 times [2019-11-15 23:10:22,703 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:22,703 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699913847] [2019-11-15 23:10:22,703 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:22,703 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:22,703 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:22,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:22,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:22,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:22,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:22,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:22,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:22,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:22,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:22,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:22,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:22,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:23,395 INFO L134 CoverageAnalysis]: Checked inductivity of 10569 backedges. 4848 proven. 804 refuted. 0 times theorem prover too weak. 4917 trivial. 0 not checked. [2019-11-15 23:10:23,396 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [699913847] [2019-11-15 23:10:23,396 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [309099968] [2019-11-15 23:10:23,396 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:23,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:23,596 INFO L256 TraceCheckSpWp]: Trace formula consists of 1103 conjuncts, 22 conjunts are in the unsatisfiable core [2019-11-15 23:10:23,600 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:23,936 INFO L134 CoverageAnalysis]: Checked inductivity of 10569 backedges. 4952 proven. 189 refuted. 0 times theorem prover too weak. 5428 trivial. 0 not checked. [2019-11-15 23:10:23,936 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:23,937 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 22] total 37 [2019-11-15 23:10:23,937 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906753595] [2019-11-15 23:10:23,938 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2019-11-15 23:10:23,938 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:23,938 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2019-11-15 23:10:23,939 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=254, Invalid=1078, Unknown=0, NotChecked=0, Total=1332 [2019-11-15 23:10:23,939 INFO L87 Difference]: Start difference. First operand 529 states and 552 transitions. Second operand 37 states. [2019-11-15 23:10:24,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:24,964 INFO L93 Difference]: Finished difference Result 615 states and 638 transitions. [2019-11-15 23:10:24,966 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-11-15 23:10:24,966 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 420 [2019-11-15 23:10:24,967 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:24,969 INFO L225 Difference]: With dead ends: 615 [2019-11-15 23:10:24,969 INFO L226 Difference]: Without dead ends: 609 [2019-11-15 23:10:24,970 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 484 GetRequests, 429 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 657 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=716, Invalid=2476, Unknown=0, NotChecked=0, Total=3192 [2019-11-15 23:10:24,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 609 states. [2019-11-15 23:10:24,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 609 to 539. [2019-11-15 23:10:24,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 539 states. [2019-11-15 23:10:24,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 539 states and 562 transitions. [2019-11-15 23:10:24,985 INFO L78 Accepts]: Start accepts. Automaton has 539 states and 562 transitions. Word has length 420 [2019-11-15 23:10:24,985 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:24,985 INFO L462 AbstractCegarLoop]: Abstraction has 539 states and 562 transitions. [2019-11-15 23:10:24,986 INFO L463 AbstractCegarLoop]: Interpolant automaton has 37 states. [2019-11-15 23:10:24,986 INFO L276 IsEmpty]: Start isEmpty. Operand 539 states and 562 transitions. [2019-11-15 23:10:24,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 431 [2019-11-15 23:10:24,990 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:24,990 INFO L380 BasicCegarLoop]: trace histogram [65, 64, 64, 64, 64, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:25,195 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:25,195 INFO L410 AbstractCegarLoop]: === Iteration 30 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:25,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:25,195 INFO L82 PathProgramCache]: Analyzing trace with hash -867500726, now seen corresponding path program 14 times [2019-11-15 23:10:25,196 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:25,196 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431257437] [2019-11-15 23:10:25,196 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:25,196 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:25,196 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:25,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:25,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:25,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:25,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:25,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:25,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:25,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:25,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:25,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:25,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:25,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:25,869 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 3151 proven. 244 refuted. 0 times theorem prover too weak. 7821 trivial. 0 not checked. [2019-11-15 23:10:25,869 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431257437] [2019-11-15 23:10:25,870 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [825433377] [2019-11-15 23:10:25,870 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:26,056 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-11-15 23:10:26,056 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:26,058 INFO L256 TraceCheckSpWp]: Trace formula consists of 1127 conjuncts, 23 conjunts are in the unsatisfiable core [2019-11-15 23:10:26,064 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:26,377 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 2907 proven. 245 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2019-11-15 23:10:26,377 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:26,377 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 12] total 36 [2019-11-15 23:10:26,377 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879928956] [2019-11-15 23:10:26,378 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2019-11-15 23:10:26,379 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:26,379 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2019-11-15 23:10:26,379 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=182, Invalid=1150, Unknown=0, NotChecked=0, Total=1332 [2019-11-15 23:10:26,380 INFO L87 Difference]: Start difference. First operand 539 states and 562 transitions. Second operand 37 states. [2019-11-15 23:10:28,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:28,000 INFO L93 Difference]: Finished difference Result 694 states and 721 transitions. [2019-11-15 23:10:28,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-11-15 23:10:28,001 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 430 [2019-11-15 23:10:28,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:28,003 INFO L225 Difference]: With dead ends: 694 [2019-11-15 23:10:28,003 INFO L226 Difference]: Without dead ends: 694 [2019-11-15 23:10:28,005 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 499 GetRequests, 438 SyntacticMatches, 1 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 841 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=420, Invalid=3362, Unknown=0, NotChecked=0, Total=3782 [2019-11-15 23:10:28,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states. [2019-11-15 23:10:28,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 605. [2019-11-15 23:10:28,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 605 states. [2019-11-15 23:10:28,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 605 states to 605 states and 630 transitions. [2019-11-15 23:10:28,018 INFO L78 Accepts]: Start accepts. Automaton has 605 states and 630 transitions. Word has length 430 [2019-11-15 23:10:28,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:28,019 INFO L462 AbstractCegarLoop]: Abstraction has 605 states and 630 transitions. [2019-11-15 23:10:28,019 INFO L463 AbstractCegarLoop]: Interpolant automaton has 37 states. [2019-11-15 23:10:28,019 INFO L276 IsEmpty]: Start isEmpty. Operand 605 states and 630 transitions. [2019-11-15 23:10:28,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 497 [2019-11-15 23:10:28,023 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:28,023 INFO L380 BasicCegarLoop]: trace histogram [76, 75, 75, 75, 75, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:28,227 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:28,227 INFO L410 AbstractCegarLoop]: === Iteration 31 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:28,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:28,228 INFO L82 PathProgramCache]: Analyzing trace with hash -1675425945, now seen corresponding path program 15 times [2019-11-15 23:10:28,228 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:28,228 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953640656] [2019-11-15 23:10:28,228 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:28,228 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:28,228 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:28,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:28,966 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 6833 proven. 977 refuted. 0 times theorem prover too weak. 7500 trivial. 0 not checked. [2019-11-15 23:10:28,966 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [953640656] [2019-11-15 23:10:28,967 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1046324506] [2019-11-15 23:10:28,967 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:29,172 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2019-11-15 23:10:29,173 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:29,175 INFO L256 TraceCheckSpWp]: Trace formula consists of 617 conjuncts, 21 conjunts are in the unsatisfiable core [2019-11-15 23:10:29,188 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:30,118 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 6173 proven. 828 refuted. 0 times theorem prover too weak. 8309 trivial. 0 not checked. [2019-11-15 23:10:30,119 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:30,119 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 20] total 47 [2019-11-15 23:10:30,120 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1014149512] [2019-11-15 23:10:30,121 INFO L442 AbstractCegarLoop]: Interpolant automaton has 47 states [2019-11-15 23:10:30,121 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:30,122 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2019-11-15 23:10:30,122 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=319, Invalid=1843, Unknown=0, NotChecked=0, Total=2162 [2019-11-15 23:10:30,123 INFO L87 Difference]: Start difference. First operand 605 states and 630 transitions. Second operand 47 states. [2019-11-15 23:10:32,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:32,650 INFO L93 Difference]: Finished difference Result 764 states and 791 transitions. [2019-11-15 23:10:32,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2019-11-15 23:10:32,650 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 496 [2019-11-15 23:10:32,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:32,652 INFO L225 Difference]: With dead ends: 764 [2019-11-15 23:10:32,652 INFO L226 Difference]: Without dead ends: 758 [2019-11-15 23:10:32,655 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 600 GetRequests, 499 SyntacticMatches, 0 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2578 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1799, Invalid=8707, Unknown=0, NotChecked=0, Total=10506 [2019-11-15 23:10:32,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 758 states. [2019-11-15 23:10:32,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 758 to 610. [2019-11-15 23:10:32,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 610 states. [2019-11-15 23:10:32,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 610 states to 610 states and 634 transitions. [2019-11-15 23:10:32,667 INFO L78 Accepts]: Start accepts. Automaton has 610 states and 634 transitions. Word has length 496 [2019-11-15 23:10:32,667 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:32,668 INFO L462 AbstractCegarLoop]: Abstraction has 610 states and 634 transitions. [2019-11-15 23:10:32,668 INFO L463 AbstractCegarLoop]: Interpolant automaton has 47 states. [2019-11-15 23:10:32,668 INFO L276 IsEmpty]: Start isEmpty. Operand 610 states and 634 transitions. [2019-11-15 23:10:32,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 502 [2019-11-15 23:10:32,671 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:32,672 INFO L380 BasicCegarLoop]: trace histogram [77, 76, 76, 76, 76, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:32,875 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 25 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:32,876 INFO L410 AbstractCegarLoop]: === Iteration 32 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:32,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:32,876 INFO L82 PathProgramCache]: Analyzing trace with hash -422752958, now seen corresponding path program 16 times [2019-11-15 23:10:32,876 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:32,876 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347492425] [2019-11-15 23:10:32,877 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:32,877 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:32,877 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:32,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:33,628 INFO L134 CoverageAnalysis]: Checked inductivity of 15697 backedges. 4121 proven. 301 refuted. 0 times theorem prover too weak. 11275 trivial. 0 not checked. [2019-11-15 23:10:33,628 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347492425] [2019-11-15 23:10:33,628 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1910392051] [2019-11-15 23:10:33,628 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:33,908 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-11-15 23:10:33,908 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:33,912 INFO L256 TraceCheckSpWp]: Trace formula consists of 1304 conjuncts, 25 conjunts are in the unsatisfiable core [2019-11-15 23:10:33,917 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:34,264 INFO L134 CoverageAnalysis]: Checked inductivity of 15697 backedges. 3825 proven. 297 refuted. 0 times theorem prover too weak. 11575 trivial. 0 not checked. [2019-11-15 23:10:34,264 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:34,264 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 13] total 39 [2019-11-15 23:10:34,264 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068387140] [2019-11-15 23:10:34,265 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-11-15 23:10:34,265 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:34,265 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-11-15 23:10:34,266 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=1350, Unknown=0, NotChecked=0, Total=1560 [2019-11-15 23:10:34,266 INFO L87 Difference]: Start difference. First operand 610 states and 634 transitions. Second operand 40 states. [2019-11-15 23:10:36,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:36,012 INFO L93 Difference]: Finished difference Result 786 states and 816 transitions. [2019-11-15 23:10:36,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-11-15 23:10:36,012 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 501 [2019-11-15 23:10:36,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:36,014 INFO L225 Difference]: With dead ends: 786 [2019-11-15 23:10:36,014 INFO L226 Difference]: Without dead ends: 786 [2019-11-15 23:10:36,015 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 576 GetRequests, 510 SyntacticMatches, 1 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 996 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=474, Invalid=3948, Unknown=0, NotChecked=0, Total=4422 [2019-11-15 23:10:36,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 786 states. [2019-11-15 23:10:36,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 786 to 681. [2019-11-15 23:10:36,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 681 states. [2019-11-15 23:10:36,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 707 transitions. [2019-11-15 23:10:36,027 INFO L78 Accepts]: Start accepts. Automaton has 681 states and 707 transitions. Word has length 501 [2019-11-15 23:10:36,028 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:36,028 INFO L462 AbstractCegarLoop]: Abstraction has 681 states and 707 transitions. [2019-11-15 23:10:36,028 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-11-15 23:10:36,028 INFO L276 IsEmpty]: Start isEmpty. Operand 681 states and 707 transitions. [2019-11-15 23:10:36,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 573 [2019-11-15 23:10:36,033 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:36,033 INFO L380 BasicCegarLoop]: trace histogram [89, 88, 88, 88, 88, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:36,238 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:36,238 INFO L410 AbstractCegarLoop]: === Iteration 33 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:36,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:36,239 INFO L82 PathProgramCache]: Analyzing trace with hash -347201808, now seen corresponding path program 17 times [2019-11-15 23:10:36,239 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:36,239 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659652494] [2019-11-15 23:10:36,239 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:36,239 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:36,239 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:36,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:36,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:37,046 INFO L134 CoverageAnalysis]: Checked inductivity of 20933 backedges. 8882 proven. 1166 refuted. 0 times theorem prover too weak. 10885 trivial. 0 not checked. [2019-11-15 23:10:37,046 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659652494] [2019-11-15 23:10:37,047 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [18305608] [2019-11-15 23:10:37,047 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:37,553 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2019-11-15 23:10:37,553 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:37,558 INFO L256 TraceCheckSpWp]: Trace formula consists of 1421 conjuncts, 30 conjunts are in the unsatisfiable core [2019-11-15 23:10:37,563 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:38,491 INFO L134 CoverageAnalysis]: Checked inductivity of 20933 backedges. 8869 proven. 1496 refuted. 0 times theorem prover too weak. 10568 trivial. 0 not checked. [2019-11-15 23:10:38,491 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:38,492 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 30] total 48 [2019-11-15 23:10:38,492 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280932291] [2019-11-15 23:10:38,493 INFO L442 AbstractCegarLoop]: Interpolant automaton has 48 states [2019-11-15 23:10:38,493 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:38,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2019-11-15 23:10:38,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=385, Invalid=1871, Unknown=0, NotChecked=0, Total=2256 [2019-11-15 23:10:38,494 INFO L87 Difference]: Start difference. First operand 681 states and 707 transitions. Second operand 48 states. [2019-11-15 23:10:40,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:40,273 INFO L93 Difference]: Finished difference Result 794 states and 822 transitions. [2019-11-15 23:10:40,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-11-15 23:10:40,273 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 572 [2019-11-15 23:10:40,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:40,276 INFO L225 Difference]: With dead ends: 794 [2019-11-15 23:10:40,277 INFO L226 Difference]: Without dead ends: 788 [2019-11-15 23:10:40,278 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 652 GetRequests, 578 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1270 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1234, Invalid=4466, Unknown=0, NotChecked=0, Total=5700 [2019-11-15 23:10:40,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 788 states. [2019-11-15 23:10:40,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 788 to 686. [2019-11-15 23:10:40,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 686 states. [2019-11-15 23:10:40,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 711 transitions. [2019-11-15 23:10:40,296 INFO L78 Accepts]: Start accepts. Automaton has 686 states and 711 transitions. Word has length 572 [2019-11-15 23:10:40,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:40,296 INFO L462 AbstractCegarLoop]: Abstraction has 686 states and 711 transitions. [2019-11-15 23:10:40,297 INFO L463 AbstractCegarLoop]: Interpolant automaton has 48 states. [2019-11-15 23:10:40,297 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 711 transitions. [2019-11-15 23:10:40,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 578 [2019-11-15 23:10:40,301 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:40,301 INFO L380 BasicCegarLoop]: trace histogram [90, 89, 89, 89, 89, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:40,507 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:40,507 INFO L410 AbstractCegarLoop]: === Iteration 34 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:40,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:40,508 INFO L82 PathProgramCache]: Analyzing trace with hash 35953893, now seen corresponding path program 18 times [2019-11-15 23:10:40,508 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:40,508 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213749746] [2019-11-15 23:10:40,508 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:40,508 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:40,508 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:40,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:41,405 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 5270 proven. 364 refuted. 0 times theorem prover too weak. 15752 trivial. 0 not checked. [2019-11-15 23:10:41,406 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213749746] [2019-11-15 23:10:41,406 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2057479326] [2019-11-15 23:10:41,406 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:41,979 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2019-11-15 23:10:41,979 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:41,983 INFO L256 TraceCheckSpWp]: Trace formula consists of 1361 conjuncts, 18 conjunts are in the unsatisfiable core [2019-11-15 23:10:41,988 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:42,268 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 4973 proven. 364 refuted. 0 times theorem prover too weak. 16049 trivial. 0 not checked. [2019-11-15 23:10:42,268 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:42,269 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 18] total 32 [2019-11-15 23:10:42,269 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [972848744] [2019-11-15 23:10:42,270 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-11-15 23:10:42,270 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:42,271 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-11-15 23:10:42,271 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=233, Invalid=823, Unknown=0, NotChecked=0, Total=1056 [2019-11-15 23:10:42,271 INFO L87 Difference]: Start difference. First operand 686 states and 711 transitions. Second operand 33 states. [2019-11-15 23:10:43,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:43,550 INFO L93 Difference]: Finished difference Result 864 states and 893 transitions. [2019-11-15 23:10:43,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-11-15 23:10:43,551 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 577 [2019-11-15 23:10:43,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:43,554 INFO L225 Difference]: With dead ends: 864 [2019-11-15 23:10:43,554 INFO L226 Difference]: Without dead ends: 864 [2019-11-15 23:10:43,555 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 656 GetRequests, 599 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 498 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=815, Invalid=2607, Unknown=0, NotChecked=0, Total=3422 [2019-11-15 23:10:43,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 864 states. [2019-11-15 23:10:43,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 864 to 757. [2019-11-15 23:10:43,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 757 states. [2019-11-15 23:10:43,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 757 states to 757 states and 783 transitions. [2019-11-15 23:10:43,567 INFO L78 Accepts]: Start accepts. Automaton has 757 states and 783 transitions. Word has length 577 [2019-11-15 23:10:43,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:43,568 INFO L462 AbstractCegarLoop]: Abstraction has 757 states and 783 transitions. [2019-11-15 23:10:43,568 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-11-15 23:10:43,568 INFO L276 IsEmpty]: Start isEmpty. Operand 757 states and 783 transitions. [2019-11-15 23:10:43,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 649 [2019-11-15 23:10:43,573 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:43,574 INFO L380 BasicCegarLoop]: trace histogram [102, 101, 101, 101, 101, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:43,779 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 28 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:43,779 INFO L410 AbstractCegarLoop]: === Iteration 35 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:43,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:43,780 INFO L82 PathProgramCache]: Analyzing trace with hash -344385043, now seen corresponding path program 19 times [2019-11-15 23:10:43,780 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:43,780 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977648923] [2019-11-15 23:10:43,780 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:43,781 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:43,781 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:43,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,742 INFO L134 CoverageAnalysis]: Checked inductivity of 27438 backedges. 10842 proven. 1371 refuted. 0 times theorem prover too weak. 15225 trivial. 0 not checked. [2019-11-15 23:10:44,742 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977648923] [2019-11-15 23:10:44,742 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [50290654] [2019-11-15 23:10:44,742 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:44,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:44,990 INFO L256 TraceCheckSpWp]: Trace formula consists of 1670 conjuncts, 28 conjunts are in the unsatisfiable core [2019-11-15 23:10:44,994 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:45,649 INFO L134 CoverageAnalysis]: Checked inductivity of 27438 backedges. 10979 proven. 342 refuted. 0 times theorem prover too weak. 16117 trivial. 0 not checked. [2019-11-15 23:10:45,649 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:45,650 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 28] total 46 [2019-11-15 23:10:45,650 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1360518559] [2019-11-15 23:10:45,651 INFO L442 AbstractCegarLoop]: Interpolant automaton has 46 states [2019-11-15 23:10:45,651 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:45,651 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2019-11-15 23:10:45,651 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=404, Invalid=1666, Unknown=0, NotChecked=0, Total=2070 [2019-11-15 23:10:45,651 INFO L87 Difference]: Start difference. First operand 757 states and 783 transitions. Second operand 46 states. [2019-11-15 23:10:47,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:47,071 INFO L93 Difference]: Finished difference Result 903 states and 935 transitions. [2019-11-15 23:10:47,073 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-11-15 23:10:47,073 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 648 [2019-11-15 23:10:47,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:47,077 INFO L225 Difference]: With dead ends: 903 [2019-11-15 23:10:47,077 INFO L226 Difference]: Without dead ends: 897 [2019-11-15 23:10:47,078 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 730 GetRequests, 660 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1128 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1142, Invalid=3970, Unknown=0, NotChecked=0, Total=5112 [2019-11-15 23:10:47,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 897 states. [2019-11-15 23:10:47,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 897 to 767. [2019-11-15 23:10:47,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 767 states. [2019-11-15 23:10:47,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 767 states to 767 states and 793 transitions. [2019-11-15 23:10:47,091 INFO L78 Accepts]: Start accepts. Automaton has 767 states and 793 transitions. Word has length 648 [2019-11-15 23:10:47,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:47,092 INFO L462 AbstractCegarLoop]: Abstraction has 767 states and 793 transitions. [2019-11-15 23:10:47,092 INFO L463 AbstractCegarLoop]: Interpolant automaton has 46 states. [2019-11-15 23:10:47,092 INFO L276 IsEmpty]: Start isEmpty. Operand 767 states and 793 transitions. [2019-11-15 23:10:47,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 659 [2019-11-15 23:10:47,097 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:47,097 INFO L380 BasicCegarLoop]: trace histogram [104, 103, 103, 103, 103, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:47,302 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 29 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:47,302 INFO L410 AbstractCegarLoop]: === Iteration 36 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:47,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:47,302 INFO L82 PathProgramCache]: Analyzing trace with hash 1104503271, now seen corresponding path program 20 times [2019-11-15 23:10:47,302 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:47,302 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115031308] [2019-11-15 23:10:47,303 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:47,303 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:47,303 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:47,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:47,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:48,176 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6613 proven. 433 refuted. 0 times theorem prover too weak. 21435 trivial. 0 not checked. [2019-11-15 23:10:48,176 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2115031308] [2019-11-15 23:10:48,176 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [144535382] [2019-11-15 23:10:48,177 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:48,435 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-11-15 23:10:48,435 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:48,439 INFO L256 TraceCheckSpWp]: Trace formula consists of 1694 conjuncts, 29 conjunts are in the unsatisfiable core [2019-11-15 23:10:48,445 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:48,976 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6198 proven. 416 refuted. 0 times theorem prover too weak. 21867 trivial. 0 not checked. [2019-11-15 23:10:48,976 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:48,977 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 15] total 45 [2019-11-15 23:10:48,977 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1715646162] [2019-11-15 23:10:48,977 INFO L442 AbstractCegarLoop]: Interpolant automaton has 46 states [2019-11-15 23:10:48,978 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:48,978 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2019-11-15 23:10:48,978 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=272, Invalid=1798, Unknown=0, NotChecked=0, Total=2070 [2019-11-15 23:10:48,978 INFO L87 Difference]: Start difference. First operand 767 states and 793 transitions. Second operand 46 states. [2019-11-15 23:10:51,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:51,310 INFO L93 Difference]: Finished difference Result 1009 states and 1048 transitions. [2019-11-15 23:10:51,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2019-11-15 23:10:51,310 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 658 [2019-11-15 23:10:51,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:51,314 INFO L225 Difference]: With dead ends: 1009 [2019-11-15 23:10:51,314 INFO L226 Difference]: Without dead ends: 1009 [2019-11-15 23:10:51,315 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 745 GetRequests, 669 SyntacticMatches, 1 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1345 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=591, Invalid=5261, Unknown=0, NotChecked=0, Total=5852 [2019-11-15 23:10:51,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1009 states. [2019-11-15 23:10:51,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1009 to 848. [2019-11-15 23:10:51,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 848 states. [2019-11-15 23:10:51,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 848 states to 848 states and 876 transitions. [2019-11-15 23:10:51,329 INFO L78 Accepts]: Start accepts. Automaton has 848 states and 876 transitions. Word has length 658 [2019-11-15 23:10:51,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:51,330 INFO L462 AbstractCegarLoop]: Abstraction has 848 states and 876 transitions. [2019-11-15 23:10:51,330 INFO L463 AbstractCegarLoop]: Interpolant automaton has 46 states. [2019-11-15 23:10:51,330 INFO L276 IsEmpty]: Start isEmpty. Operand 848 states and 876 transitions. [2019-11-15 23:10:51,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 740 [2019-11-15 23:10:51,336 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:51,337 INFO L380 BasicCegarLoop]: trace histogram [118, 117, 117, 117, 117, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:51,541 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 30 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:51,541 INFO L410 AbstractCegarLoop]: === Iteration 37 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:51,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:51,542 INFO L82 PathProgramCache]: Analyzing trace with hash 79086155, now seen corresponding path program 21 times [2019-11-15 23:10:51,542 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:51,542 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085401711] [2019-11-15 23:10:51,542 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:51,542 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:51,542 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:51,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:51,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:52,607 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 14114 proven. 1592 refuted. 0 times theorem prover too weak. 20889 trivial. 0 not checked. [2019-11-15 23:10:52,607 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085401711] [2019-11-15 23:10:52,607 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [462199644] [2019-11-15 23:10:52,607 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:52,891 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2019-11-15 23:10:52,891 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:52,894 INFO L256 TraceCheckSpWp]: Trace formula consists of 794 conjuncts, 24 conjunts are in the unsatisfiable core [2019-11-15 23:10:52,898 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:53,845 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 12944 proven. 1368 refuted. 0 times theorem prover too weak. 22283 trivial. 0 not checked. [2019-11-15 23:10:53,845 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:53,846 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 23] total 56 [2019-11-15 23:10:53,846 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196736823] [2019-11-15 23:10:53,847 INFO L442 AbstractCegarLoop]: Interpolant automaton has 56 states [2019-11-15 23:10:53,847 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:53,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2019-11-15 23:10:53,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=2599, Unknown=0, NotChecked=0, Total=3080 [2019-11-15 23:10:53,847 INFO L87 Difference]: Start difference. First operand 848 states and 876 transitions. Second operand 56 states. [2019-11-15 23:10:57,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:10:57,174 INFO L93 Difference]: Finished difference Result 1361 states and 1415 transitions. [2019-11-15 23:10:57,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2019-11-15 23:10:57,175 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 739 [2019-11-15 23:10:57,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:10:57,178 INFO L225 Difference]: With dead ends: 1361 [2019-11-15 23:10:57,178 INFO L226 Difference]: Without dead ends: 1355 [2019-11-15 23:10:57,180 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 870 GetRequests, 745 SyntacticMatches, 0 SemanticMatches, 125 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4060 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=2714, Invalid=13288, Unknown=0, NotChecked=0, Total=16002 [2019-11-15 23:10:57,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1355 states. [2019-11-15 23:10:57,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1355 to 853. [2019-11-15 23:10:57,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 853 states. [2019-11-15 23:10:57,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 853 states to 853 states and 880 transitions. [2019-11-15 23:10:57,196 INFO L78 Accepts]: Start accepts. Automaton has 853 states and 880 transitions. Word has length 739 [2019-11-15 23:10:57,197 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:10:57,197 INFO L462 AbstractCegarLoop]: Abstraction has 853 states and 880 transitions. [2019-11-15 23:10:57,197 INFO L463 AbstractCegarLoop]: Interpolant automaton has 56 states. [2019-11-15 23:10:57,197 INFO L276 IsEmpty]: Start isEmpty. Operand 853 states and 880 transitions. [2019-11-15 23:10:57,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 745 [2019-11-15 23:10:57,204 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:10:57,204 INFO L380 BasicCegarLoop]: trace histogram [119, 118, 118, 118, 118, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:10:57,409 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 31 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:57,409 INFO L410 AbstractCegarLoop]: === Iteration 38 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:10:57,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:10:57,409 INFO L82 PathProgramCache]: Analyzing trace with hash 1460105962, now seen corresponding path program 22 times [2019-11-15 23:10:57,410 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:10:57,410 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806621341] [2019-11-15 23:10:57,410 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:57,410 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:10:57,410 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:10:57,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:10:58,537 INFO L134 CoverageAnalysis]: Checked inductivity of 37195 backedges. 8165 proven. 508 refuted. 0 times theorem prover too weak. 28522 trivial. 0 not checked. [2019-11-15 23:10:58,537 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [806621341] [2019-11-15 23:10:58,537 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [992260756] [2019-11-15 23:10:58,537 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:10:58,891 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-11-15 23:10:58,891 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:10:58,897 INFO L256 TraceCheckSpWp]: Trace formula consists of 1907 conjuncts, 31 conjunts are in the unsatisfiable core [2019-11-15 23:10:58,901 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:10:59,456 INFO L134 CoverageAnalysis]: Checked inductivity of 37195 backedges. 7683 proven. 483 refuted. 0 times theorem prover too weak. 29029 trivial. 0 not checked. [2019-11-15 23:10:59,456 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:10:59,457 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 16] total 48 [2019-11-15 23:10:59,457 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371818777] [2019-11-15 23:10:59,458 INFO L442 AbstractCegarLoop]: Interpolant automaton has 49 states [2019-11-15 23:10:59,458 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:10:59,458 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2019-11-15 23:10:59,459 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=306, Invalid=2046, Unknown=0, NotChecked=0, Total=2352 [2019-11-15 23:10:59,459 INFO L87 Difference]: Start difference. First operand 853 states and 880 transitions. Second operand 49 states. [2019-11-15 23:11:01,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:11:01,919 INFO L93 Difference]: Finished difference Result 1140 states and 1185 transitions. [2019-11-15 23:11:01,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-11-15 23:11:01,920 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 744 [2019-11-15 23:11:01,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:11:01,923 INFO L225 Difference]: With dead ends: 1140 [2019-11-15 23:11:01,923 INFO L226 Difference]: Without dead ends: 1140 [2019-11-15 23:11:01,924 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 837 GetRequests, 756 SyntacticMatches, 1 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1539 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=654, Invalid=5988, Unknown=0, NotChecked=0, Total=6642 [2019-11-15 23:11:01,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1140 states. [2019-11-15 23:11:01,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1140 to 939. [2019-11-15 23:11:01,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 939 states. [2019-11-15 23:11:01,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 939 states to 939 states and 968 transitions. [2019-11-15 23:11:01,940 INFO L78 Accepts]: Start accepts. Automaton has 939 states and 968 transitions. Word has length 744 [2019-11-15 23:11:01,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:11:01,941 INFO L462 AbstractCegarLoop]: Abstraction has 939 states and 968 transitions. [2019-11-15 23:11:01,941 INFO L463 AbstractCegarLoop]: Interpolant automaton has 49 states. [2019-11-15 23:11:01,941 INFO L276 IsEmpty]: Start isEmpty. Operand 939 states and 968 transitions. [2019-11-15 23:11:01,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 831 [2019-11-15 23:11:01,948 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:11:01,949 INFO L380 BasicCegarLoop]: trace histogram [134, 133, 133, 133, 133, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:11:02,156 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 32 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:02,156 INFO L410 AbstractCegarLoop]: === Iteration 39 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:11:02,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:11:02,157 INFO L82 PathProgramCache]: Analyzing trace with hash 51252807, now seen corresponding path program 23 times [2019-11-15 23:11:02,157 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:11:02,157 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955015505] [2019-11-15 23:11:02,157 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:02,158 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:02,158 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:11:02,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:02,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:03,488 INFO L134 CoverageAnalysis]: Checked inductivity of 47075 backedges. 17357 proven. 1829 refuted. 0 times theorem prover too weak. 27889 trivial. 0 not checked. [2019-11-15 23:11:03,488 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955015505] [2019-11-15 23:11:03,489 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [132249521] [2019-11-15 23:11:03,489 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:04,488 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 27 check-sat command(s) [2019-11-15 23:11:04,488 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:11:04,497 INFO L256 TraceCheckSpWp]: Trace formula consists of 2060 conjuncts, 36 conjunts are in the unsatisfiable core [2019-11-15 23:11:04,502 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:11:05,494 INFO L134 CoverageAnalysis]: Checked inductivity of 47075 backedges. 17329 proven. 2372 refuted. 0 times theorem prover too weak. 27374 trivial. 0 not checked. [2019-11-15 23:11:05,494 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:11:05,494 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 36] total 57 [2019-11-15 23:11:05,494 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134320510] [2019-11-15 23:11:05,495 INFO L442 AbstractCegarLoop]: Interpolant automaton has 57 states [2019-11-15 23:11:05,495 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:11:05,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2019-11-15 23:11:05,496 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=562, Invalid=2630, Unknown=0, NotChecked=0, Total=3192 [2019-11-15 23:11:05,496 INFO L87 Difference]: Start difference. First operand 939 states and 968 transitions. Second operand 57 states. [2019-11-15 23:11:07,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:11:07,499 INFO L93 Difference]: Finished difference Result 1160 states and 1203 transitions. [2019-11-15 23:11:07,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-11-15 23:11:07,499 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 830 [2019-11-15 23:11:07,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:11:07,502 INFO L225 Difference]: With dead ends: 1160 [2019-11-15 23:11:07,502 INFO L226 Difference]: Without dead ends: 1154 [2019-11-15 23:11:07,503 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 928 GetRequests, 838 SyntacticMatches, 1 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1956 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1774, Invalid=6416, Unknown=0, NotChecked=0, Total=8190 [2019-11-15 23:11:07,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1154 states. [2019-11-15 23:11:07,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1154 to 944. [2019-11-15 23:11:07,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 944 states. [2019-11-15 23:11:07,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 944 states to 944 states and 972 transitions. [2019-11-15 23:11:07,515 INFO L78 Accepts]: Start accepts. Automaton has 944 states and 972 transitions. Word has length 830 [2019-11-15 23:11:07,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:11:07,516 INFO L462 AbstractCegarLoop]: Abstraction has 944 states and 972 transitions. [2019-11-15 23:11:07,516 INFO L463 AbstractCegarLoop]: Interpolant automaton has 57 states. [2019-11-15 23:11:07,516 INFO L276 IsEmpty]: Start isEmpty. Operand 944 states and 972 transitions. [2019-11-15 23:11:07,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 836 [2019-11-15 23:11:07,523 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:11:07,524 INFO L380 BasicCegarLoop]: trace histogram [135, 134, 134, 134, 134, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:11:07,731 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 33 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:07,732 INFO L410 AbstractCegarLoop]: === Iteration 40 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:11:07,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:11:07,732 INFO L82 PathProgramCache]: Analyzing trace with hash 1746428258, now seen corresponding path program 24 times [2019-11-15 23:11:07,732 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:11:07,732 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324389020] [2019-11-15 23:11:07,732 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:07,732 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:07,732 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:11:07,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:08,876 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9941 proven. 589 refuted. 0 times theorem prover too weak. 37226 trivial. 0 not checked. [2019-11-15 23:11:08,877 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324389020] [2019-11-15 23:11:08,877 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [868417915] [2019-11-15 23:11:08,877 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:10,205 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2019-11-15 23:11:10,205 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:11:10,213 INFO L256 TraceCheckSpWp]: Trace formula consists of 2132 conjuncts, 19 conjunts are in the unsatisfiable core [2019-11-15 23:11:10,218 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:11:10,955 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9387 proven. 555 refuted. 0 times theorem prover too weak. 37814 trivial. 0 not checked. [2019-11-15 23:11:10,955 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:11:10,956 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 18] total 53 [2019-11-15 23:11:10,956 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312981078] [2019-11-15 23:11:10,956 INFO L442 AbstractCegarLoop]: Interpolant automaton has 54 states [2019-11-15 23:11:10,956 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:11:10,957 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2019-11-15 23:11:10,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=453, Invalid=2409, Unknown=0, NotChecked=0, Total=2862 [2019-11-15 23:11:10,957 INFO L87 Difference]: Start difference. First operand 944 states and 972 transitions. Second operand 54 states. [2019-11-15 23:11:13,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:11:13,195 INFO L93 Difference]: Finished difference Result 1284 states and 1336 transitions. [2019-11-15 23:11:13,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-11-15 23:11:13,196 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 835 [2019-11-15 23:11:13,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:11:13,200 INFO L225 Difference]: With dead ends: 1284 [2019-11-15 23:11:13,200 INFO L226 Difference]: Without dead ends: 1284 [2019-11-15 23:11:13,200 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 934 GetRequests, 847 SyntacticMatches, 0 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1823 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1310, Invalid=6522, Unknown=0, NotChecked=0, Total=7832 [2019-11-15 23:11:13,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1284 states. [2019-11-15 23:11:13,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1284 to 1035. [2019-11-15 23:11:13,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1035 states. [2019-11-15 23:11:13,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1035 states to 1035 states and 1065 transitions. [2019-11-15 23:11:13,211 INFO L78 Accepts]: Start accepts. Automaton has 1035 states and 1065 transitions. Word has length 835 [2019-11-15 23:11:13,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:11:13,212 INFO L462 AbstractCegarLoop]: Abstraction has 1035 states and 1065 transitions. [2019-11-15 23:11:13,212 INFO L463 AbstractCegarLoop]: Interpolant automaton has 54 states. [2019-11-15 23:11:13,213 INFO L276 IsEmpty]: Start isEmpty. Operand 1035 states and 1065 transitions. [2019-11-15 23:11:13,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 927 [2019-11-15 23:11:13,221 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:11:13,222 INFO L380 BasicCegarLoop]: trace histogram [151, 150, 150, 150, 150, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:11:13,430 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 34 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:13,430 INFO L410 AbstractCegarLoop]: === Iteration 41 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:11:13,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:11:13,430 INFO L82 PathProgramCache]: Analyzing trace with hash -848043632, now seen corresponding path program 25 times [2019-11-15 23:11:13,430 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:11:13,430 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663935950] [2019-11-15 23:11:13,431 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:13,431 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:13,431 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:11:13,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:13,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:14,918 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 21058 proven. 2082 refuted. 0 times theorem prover too weak. 36500 trivial. 0 not checked. [2019-11-15 23:11:14,918 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1663935950] [2019-11-15 23:11:14,918 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [455108853] [2019-11-15 23:11:14,918 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:15,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:15,271 INFO L256 TraceCheckSpWp]: Trace formula consists of 2357 conjuncts, 34 conjunts are in the unsatisfiable core [2019-11-15 23:11:15,277 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:11:16,395 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 21228 proven. 540 refuted. 0 times theorem prover too weak. 37872 trivial. 0 not checked. [2019-11-15 23:11:16,396 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:11:16,396 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 34] total 55 [2019-11-15 23:11:16,396 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1232686172] [2019-11-15 23:11:16,397 INFO L442 AbstractCegarLoop]: Interpolant automaton has 55 states [2019-11-15 23:11:16,397 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:11:16,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2019-11-15 23:11:16,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=590, Invalid=2380, Unknown=0, NotChecked=0, Total=2970 [2019-11-15 23:11:16,398 INFO L87 Difference]: Start difference. First operand 1035 states and 1065 transitions. Second operand 55 states. [2019-11-15 23:11:18,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:11:18,103 INFO L93 Difference]: Finished difference Result 1308 states and 1358 transitions. [2019-11-15 23:11:18,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-11-15 23:11:18,103 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 926 [2019-11-15 23:11:18,104 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:11:18,106 INFO L225 Difference]: With dead ends: 1308 [2019-11-15 23:11:18,107 INFO L226 Difference]: Without dead ends: 1302 [2019-11-15 23:11:18,107 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1026 GetRequests, 941 SyntacticMatches, 0 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1725 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1667, Invalid=5815, Unknown=0, NotChecked=0, Total=7482 [2019-11-15 23:11:18,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1302 states. [2019-11-15 23:11:18,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1302 to 1040. [2019-11-15 23:11:18,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1040 states. [2019-11-15 23:11:18,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1040 states to 1040 states and 1069 transitions. [2019-11-15 23:11:18,121 INFO L78 Accepts]: Start accepts. Automaton has 1040 states and 1069 transitions. Word has length 926 [2019-11-15 23:11:18,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:11:18,122 INFO L462 AbstractCegarLoop]: Abstraction has 1040 states and 1069 transitions. [2019-11-15 23:11:18,122 INFO L463 AbstractCegarLoop]: Interpolant automaton has 55 states. [2019-11-15 23:11:18,122 INFO L276 IsEmpty]: Start isEmpty. Operand 1040 states and 1069 transitions. [2019-11-15 23:11:18,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 932 [2019-11-15 23:11:18,131 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:11:18,131 INFO L380 BasicCegarLoop]: trace histogram [152, 151, 151, 151, 151, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:11:18,336 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 35 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:18,336 INFO L410 AbstractCegarLoop]: === Iteration 42 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:11:18,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:11:18,337 INFO L82 PathProgramCache]: Analyzing trace with hash 401870661, now seen corresponding path program 26 times [2019-11-15 23:11:18,337 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:11:18,337 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648610832] [2019-11-15 23:11:18,337 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:18,337 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:18,337 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:11:18,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:19,789 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11956 proven. 676 refuted. 0 times theorem prover too weak. 47775 trivial. 0 not checked. [2019-11-15 23:11:19,789 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1648610832] [2019-11-15 23:11:19,789 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [470850405] [2019-11-15 23:11:19,789 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:20,145 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-11-15 23:11:20,145 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:11:20,151 INFO L256 TraceCheckSpWp]: Trace formula consists of 2369 conjuncts, 35 conjunts are in the unsatisfiable core [2019-11-15 23:11:20,157 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:11:20,993 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11325 proven. 632 refuted. 0 times theorem prover too weak. 48450 trivial. 0 not checked. [2019-11-15 23:11:20,993 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:11:20,994 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 18] total 54 [2019-11-15 23:11:20,994 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655373304] [2019-11-15 23:11:20,995 INFO L442 AbstractCegarLoop]: Interpolant automaton has 55 states [2019-11-15 23:11:20,995 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:11:20,995 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2019-11-15 23:11:20,995 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=380, Invalid=2590, Unknown=0, NotChecked=0, Total=2970 [2019-11-15 23:11:20,995 INFO L87 Difference]: Start difference. First operand 1040 states and 1069 transitions. Second operand 55 states. [2019-11-15 23:11:24,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:11:24,136 INFO L93 Difference]: Finished difference Result 1441 states and 1501 transitions. [2019-11-15 23:11:24,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2019-11-15 23:11:24,137 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 931 [2019-11-15 23:11:24,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:11:24,140 INFO L225 Difference]: With dead ends: 1441 [2019-11-15 23:11:24,141 INFO L226 Difference]: Without dead ends: 1441 [2019-11-15 23:11:24,141 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1036 GetRequests, 945 SyntacticMatches, 1 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1966 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=789, Invalid=7583, Unknown=0, NotChecked=0, Total=8372 [2019-11-15 23:11:24,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1441 states. [2019-11-15 23:11:24,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1441 to 1136. [2019-11-15 23:11:24,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1136 states. [2019-11-15 23:11:24,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1136 states to 1136 states and 1167 transitions. [2019-11-15 23:11:24,157 INFO L78 Accepts]: Start accepts. Automaton has 1136 states and 1167 transitions. Word has length 931 [2019-11-15 23:11:24,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:11:24,158 INFO L462 AbstractCegarLoop]: Abstraction has 1136 states and 1167 transitions. [2019-11-15 23:11:24,158 INFO L463 AbstractCegarLoop]: Interpolant automaton has 55 states. [2019-11-15 23:11:24,158 INFO L276 IsEmpty]: Start isEmpty. Operand 1136 states and 1167 transitions. [2019-11-15 23:11:24,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1028 [2019-11-15 23:11:24,168 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:11:24,169 INFO L380 BasicCegarLoop]: trace histogram [169, 168, 168, 168, 168, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:11:24,374 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 36 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:24,374 INFO L410 AbstractCegarLoop]: === Iteration 43 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:11:24,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:11:24,374 INFO L82 PathProgramCache]: Analyzing trace with hash -697239742, now seen corresponding path program 27 times [2019-11-15 23:11:24,374 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:11:24,375 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [835066856] [2019-11-15 23:11:24,375 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:24,375 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:24,375 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:11:24,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:24,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:25,961 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 25247 proven. 2351 refuted. 0 times theorem prover too weak. 46950 trivial. 0 not checked. [2019-11-15 23:11:25,961 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [835066856] [2019-11-15 23:11:25,962 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [623218232] [2019-11-15 23:11:25,962 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:26,345 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2019-11-15 23:11:26,345 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:11:26,348 INFO L256 TraceCheckSpWp]: Trace formula consists of 1073 conjuncts, 27 conjunts are in the unsatisfiable core [2019-11-15 23:11:26,354 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:11:27,728 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 23423 proven. 2043 refuted. 0 times theorem prover too weak. 49082 trivial. 0 not checked. [2019-11-15 23:11:27,728 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:11:27,729 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 26] total 65 [2019-11-15 23:11:27,729 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2113235161] [2019-11-15 23:11:27,730 INFO L442 AbstractCegarLoop]: Interpolant automaton has 65 states [2019-11-15 23:11:27,730 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:11:27,731 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2019-11-15 23:11:27,732 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=679, Invalid=3481, Unknown=0, NotChecked=0, Total=4160 [2019-11-15 23:11:27,732 INFO L87 Difference]: Start difference. First operand 1136 states and 1167 transitions. Second operand 65 states. [2019-11-15 23:11:32,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:11:32,046 INFO L93 Difference]: Finished difference Result 2165 states and 2273 transitions. [2019-11-15 23:11:32,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2019-11-15 23:11:32,047 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 1027 [2019-11-15 23:11:32,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:11:32,053 INFO L225 Difference]: With dead ends: 2165 [2019-11-15 23:11:32,053 INFO L226 Difference]: Without dead ends: 2159 [2019-11-15 23:11:32,054 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1185 GetRequests, 1036 SyntacticMatches, 0 SemanticMatches, 149 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5875 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=3818, Invalid=18832, Unknown=0, NotChecked=0, Total=22650 [2019-11-15 23:11:32,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2159 states. [2019-11-15 23:11:32,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2159 to 1141. [2019-11-15 23:11:32,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1141 states. [2019-11-15 23:11:32,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1141 states to 1141 states and 1171 transitions. [2019-11-15 23:11:32,073 INFO L78 Accepts]: Start accepts. Automaton has 1141 states and 1171 transitions. Word has length 1027 [2019-11-15 23:11:32,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:11:32,074 INFO L462 AbstractCegarLoop]: Abstraction has 1141 states and 1171 transitions. [2019-11-15 23:11:32,074 INFO L463 AbstractCegarLoop]: Interpolant automaton has 65 states. [2019-11-15 23:11:32,075 INFO L276 IsEmpty]: Start isEmpty. Operand 1141 states and 1171 transitions. [2019-11-15 23:11:32,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1033 [2019-11-15 23:11:32,085 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:11:32,085 INFO L380 BasicCegarLoop]: trace histogram [170, 169, 169, 169, 169, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:11:32,290 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 37 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:32,290 INFO L410 AbstractCegarLoop]: === Iteration 44 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:11:32,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:11:32,291 INFO L82 PathProgramCache]: Analyzing trace with hash 548287687, now seen corresponding path program 28 times [2019-11-15 23:11:32,291 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:11:32,291 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336994782] [2019-11-15 23:11:32,291 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:32,291 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:32,291 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:11:32,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:33,801 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 14225 proven. 769 refuted. 0 times theorem prover too weak. 60412 trivial. 0 not checked. [2019-11-15 23:11:33,801 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336994782] [2019-11-15 23:11:33,801 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1112806179] [2019-11-15 23:11:33,801 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:34,507 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-11-15 23:11:34,508 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:11:34,517 INFO L256 TraceCheckSpWp]: Trace formula consists of 2618 conjuncts, 37 conjunts are in the unsatisfiable core [2019-11-15 23:11:34,522 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:11:35,474 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 13512 proven. 714 refuted. 0 times theorem prover too weak. 61180 trivial. 0 not checked. [2019-11-15 23:11:35,475 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:11:35,475 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 19] total 57 [2019-11-15 23:11:35,475 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [183575178] [2019-11-15 23:11:35,476 INFO L442 AbstractCegarLoop]: Interpolant automaton has 58 states [2019-11-15 23:11:35,476 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:11:35,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2019-11-15 23:11:35,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=420, Invalid=2886, Unknown=0, NotChecked=0, Total=3306 [2019-11-15 23:11:35,477 INFO L87 Difference]: Start difference. First operand 1141 states and 1171 transitions. Second operand 58 states. [2019-11-15 23:11:39,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:11:39,027 INFO L93 Difference]: Finished difference Result 1611 states and 1680 transitions. [2019-11-15 23:11:39,027 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2019-11-15 23:11:39,027 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 1032 [2019-11-15 23:11:39,028 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:11:39,032 INFO L225 Difference]: With dead ends: 1611 [2019-11-15 23:11:39,032 INFO L226 Difference]: Without dead ends: 1611 [2019-11-15 23:11:39,033 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1143 GetRequests, 1047 SyntacticMatches, 1 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2199 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=861, Invalid=8451, Unknown=0, NotChecked=0, Total=9312 [2019-11-15 23:11:39,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1611 states. [2019-11-15 23:11:39,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1611 to 1242. [2019-11-15 23:11:39,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1242 states. [2019-11-15 23:11:39,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1242 states to 1242 states and 1274 transitions. [2019-11-15 23:11:39,046 INFO L78 Accepts]: Start accepts. Automaton has 1242 states and 1274 transitions. Word has length 1032 [2019-11-15 23:11:39,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:11:39,047 INFO L462 AbstractCegarLoop]: Abstraction has 1242 states and 1274 transitions. [2019-11-15 23:11:39,047 INFO L463 AbstractCegarLoop]: Interpolant automaton has 58 states. [2019-11-15 23:11:39,047 INFO L276 IsEmpty]: Start isEmpty. Operand 1242 states and 1274 transitions. [2019-11-15 23:11:39,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1134 [2019-11-15 23:11:39,055 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:11:39,055 INFO L380 BasicCegarLoop]: trace histogram [188, 187, 187, 187, 187, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:11:39,256 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 38 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:39,256 INFO L410 AbstractCegarLoop]: === Iteration 45 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:11:39,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:11:39,256 INFO L82 PathProgramCache]: Analyzing trace with hash -1908118869, now seen corresponding path program 29 times [2019-11-15 23:11:39,257 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:11:39,257 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481485877] [2019-11-15 23:11:39,257 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:39,257 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:39,257 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:11:39,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:39,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:40,958 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 29954 proven. 2636 refuted. 0 times theorem prover too weak. 59482 trivial. 0 not checked. [2019-11-15 23:11:40,958 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481485877] [2019-11-15 23:11:40,958 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1393280608] [2019-11-15 23:11:40,958 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:42,897 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2019-11-15 23:11:42,897 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:11:42,912 INFO L256 TraceCheckSpWp]: Trace formula consists of 2807 conjuncts, 42 conjunts are in the unsatisfiable core [2019-11-15 23:11:42,919 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:11:44,537 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 29910 proven. 4185 refuted. 0 times theorem prover too weak. 57977 trivial. 0 not checked. [2019-11-15 23:11:44,537 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:11:44,538 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 42] total 67 [2019-11-15 23:11:44,538 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [590903630] [2019-11-15 23:11:44,539 INFO L442 AbstractCegarLoop]: Interpolant automaton has 67 states [2019-11-15 23:11:44,539 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:11:44,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2019-11-15 23:11:44,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=3641, Unknown=0, NotChecked=0, Total=4422 [2019-11-15 23:11:44,540 INFO L87 Difference]: Start difference. First operand 1242 states and 1274 transitions. Second operand 67 states. [2019-11-15 23:11:47,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:11:47,638 INFO L93 Difference]: Finished difference Result 1731 states and 1862 transitions. [2019-11-15 23:11:47,639 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2019-11-15 23:11:47,639 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1133 [2019-11-15 23:11:47,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:11:47,644 INFO L225 Difference]: With dead ends: 1731 [2019-11-15 23:11:47,645 INFO L226 Difference]: Without dead ends: 1725 [2019-11-15 23:11:47,645 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1250 GetRequests, 1144 SyntacticMatches, 0 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2763 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=2447, Invalid=9109, Unknown=0, NotChecked=0, Total=11556 [2019-11-15 23:11:47,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1725 states. [2019-11-15 23:11:47,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1725 to 1342. [2019-11-15 23:11:47,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1342 states. [2019-11-15 23:11:47,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1342 states to 1342 states and 1388 transitions. [2019-11-15 23:11:47,671 INFO L78 Accepts]: Start accepts. Automaton has 1342 states and 1388 transitions. Word has length 1133 [2019-11-15 23:11:47,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:11:47,672 INFO L462 AbstractCegarLoop]: Abstraction has 1342 states and 1388 transitions. [2019-11-15 23:11:47,672 INFO L463 AbstractCegarLoop]: Interpolant automaton has 67 states. [2019-11-15 23:11:47,672 INFO L276 IsEmpty]: Start isEmpty. Operand 1342 states and 1388 transitions. [2019-11-15 23:11:47,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1139 [2019-11-15 23:11:47,685 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:11:47,685 INFO L380 BasicCegarLoop]: trace histogram [189, 188, 188, 188, 188, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:11:47,896 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 39 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:47,896 INFO L410 AbstractCegarLoop]: === Iteration 46 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:11:47,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:11:47,896 INFO L82 PathProgramCache]: Analyzing trace with hash -1485351030, now seen corresponding path program 30 times [2019-11-15 23:11:47,897 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:11:47,897 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708652302] [2019-11-15 23:11:47,897 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:47,897 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:47,897 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:11:48,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:48,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:49,595 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 16763 proven. 868 refuted. 0 times theorem prover too weak. 75395 trivial. 0 not checked. [2019-11-15 23:11:49,596 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [708652302] [2019-11-15 23:11:49,596 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2034226179] [2019-11-15 23:11:49,596 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:50,762 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2019-11-15 23:11:50,762 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:11:50,771 INFO L256 TraceCheckSpWp]: Trace formula consists of 2153 conjuncts, 22 conjunts are in the unsatisfiable core [2019-11-15 23:11:50,779 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:11:51,988 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 15963 proven. 801 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2019-11-15 23:11:51,988 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:11:51,989 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 21] total 62 [2019-11-15 23:11:51,989 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [528503129] [2019-11-15 23:11:51,990 INFO L442 AbstractCegarLoop]: Interpolant automaton has 63 states [2019-11-15 23:11:51,990 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:11:51,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2019-11-15 23:11:51,990 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=621, Invalid=3285, Unknown=0, NotChecked=0, Total=3906 [2019-11-15 23:11:51,990 INFO L87 Difference]: Start difference. First operand 1342 states and 1388 transitions. Second operand 63 states. [2019-11-15 23:11:55,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:11:55,111 INFO L93 Difference]: Finished difference Result 1878 states and 2029 transitions. [2019-11-15 23:11:55,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2019-11-15 23:11:55,113 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 1138 [2019-11-15 23:11:55,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:11:55,122 INFO L225 Difference]: With dead ends: 1878 [2019-11-15 23:11:55,122 INFO L226 Difference]: Without dead ends: 1878 [2019-11-15 23:11:55,123 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1255 GetRequests, 1153 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2537 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1778, Invalid=8934, Unknown=0, NotChecked=0, Total=10712 [2019-11-15 23:11:55,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1878 states. [2019-11-15 23:11:55,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1878 to 1448. [2019-11-15 23:11:55,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1448 states. [2019-11-15 23:11:55,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 1496 transitions. [2019-11-15 23:11:55,151 INFO L78 Accepts]: Start accepts. Automaton has 1448 states and 1496 transitions. Word has length 1138 [2019-11-15 23:11:55,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:11:55,152 INFO L462 AbstractCegarLoop]: Abstraction has 1448 states and 1496 transitions. [2019-11-15 23:11:55,152 INFO L463 AbstractCegarLoop]: Interpolant automaton has 63 states. [2019-11-15 23:11:55,153 INFO L276 IsEmpty]: Start isEmpty. Operand 1448 states and 1496 transitions. [2019-11-15 23:11:55,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1245 [2019-11-15 23:11:55,168 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:11:55,169 INFO L380 BasicCegarLoop]: trace histogram [208, 207, 207, 207, 207, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:11:55,377 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 40 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:55,377 INFO L410 AbstractCegarLoop]: === Iteration 47 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:11:55,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:11:55,378 INFO L82 PathProgramCache]: Analyzing trace with hash -1962245081, now seen corresponding path program 31 times [2019-11-15 23:11:55,378 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:11:55,378 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676701363] [2019-11-15 23:11:55,378 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:55,378 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:11:55,378 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:11:55,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:55,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:56,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:56,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:56,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:57,411 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 35209 proven. 2937 refuted. 0 times theorem prover too weak. 74354 trivial. 0 not checked. [2019-11-15 23:11:57,412 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [676701363] [2019-11-15 23:11:57,412 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [851884930] [2019-11-15 23:11:57,412 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:11:57,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:11:57,876 INFO L256 TraceCheckSpWp]: Trace formula consists of 3140 conjuncts, 40 conjunts are in the unsatisfiable core [2019-11-15 23:11:57,883 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:11:59,444 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 35412 proven. 783 refuted. 0 times theorem prover too weak. 76305 trivial. 0 not checked. [2019-11-15 23:11:59,444 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:11:59,444 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 40] total 64 [2019-11-15 23:11:59,445 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1350429877] [2019-11-15 23:11:59,446 INFO L442 AbstractCegarLoop]: Interpolant automaton has 64 states [2019-11-15 23:11:59,446 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:11:59,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2019-11-15 23:11:59,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=812, Invalid=3220, Unknown=0, NotChecked=0, Total=4032 [2019-11-15 23:11:59,446 INFO L87 Difference]: Start difference. First operand 1448 states and 1496 transitions. Second operand 64 states. [2019-11-15 23:12:01,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:12:01,263 INFO L93 Difference]: Finished difference Result 1914 states and 2063 transitions. [2019-11-15 23:12:01,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2019-11-15 23:12:01,263 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 1244 [2019-11-15 23:12:01,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:12:01,269 INFO L225 Difference]: With dead ends: 1914 [2019-11-15 23:12:01,269 INFO L226 Difference]: Without dead ends: 1908 [2019-11-15 23:12:01,270 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1362 GetRequests, 1262 SyntacticMatches, 0 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2448 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=2291, Invalid=8011, Unknown=0, NotChecked=0, Total=10302 [2019-11-15 23:12:01,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1908 states. [2019-11-15 23:12:01,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1908 to 1453. [2019-11-15 23:12:01,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1453 states. [2019-11-15 23:12:01,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1453 states to 1453 states and 1500 transitions. [2019-11-15 23:12:01,298 INFO L78 Accepts]: Start accepts. Automaton has 1453 states and 1500 transitions. Word has length 1244 [2019-11-15 23:12:01,299 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:12:01,299 INFO L462 AbstractCegarLoop]: Abstraction has 1453 states and 1500 transitions. [2019-11-15 23:12:01,299 INFO L463 AbstractCegarLoop]: Interpolant automaton has 64 states. [2019-11-15 23:12:01,299 INFO L276 IsEmpty]: Start isEmpty. Operand 1453 states and 1500 transitions. [2019-11-15 23:12:01,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1250 [2019-11-15 23:12:01,313 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:12:01,314 INFO L380 BasicCegarLoop]: trace histogram [209, 208, 208, 208, 208, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:12:01,519 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 41 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:01,519 INFO L410 AbstractCegarLoop]: === Iteration 48 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:12:01,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:12:01,520 INFO L82 PathProgramCache]: Analyzing trace with hash -1184766334, now seen corresponding path program 32 times [2019-11-15 23:12:01,520 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:12:01,520 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671961526] [2019-11-15 23:12:01,520 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:01,520 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:01,520 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:12:01,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:02,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:03,291 INFO L134 CoverageAnalysis]: Checked inductivity of 113555 backedges. 19585 proven. 973 refuted. 0 times theorem prover too weak. 92997 trivial. 0 not checked. [2019-11-15 23:12:03,291 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [671961526] [2019-11-15 23:12:03,291 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [41079935] [2019-11-15 23:12:03,292 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:03,761 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-11-15 23:12:03,761 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:12:03,768 INFO L256 TraceCheckSpWp]: Trace formula consists of 3152 conjuncts, 41 conjunts are in the unsatisfiable core [2019-11-15 23:12:03,775 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:12:05,037 INFO L134 CoverageAnalysis]: Checked inductivity of 113555 backedges. 18693 proven. 893 refuted. 0 times theorem prover too weak. 93969 trivial. 0 not checked. [2019-11-15 23:12:05,037 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:12:05,038 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 21] total 63 [2019-11-15 23:12:05,038 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [201983810] [2019-11-15 23:12:05,039 INFO L442 AbstractCegarLoop]: Interpolant automaton has 64 states [2019-11-15 23:12:05,039 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:12:05,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2019-11-15 23:12:05,040 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=506, Invalid=3526, Unknown=0, NotChecked=0, Total=4032 [2019-11-15 23:12:05,040 INFO L87 Difference]: Start difference. First operand 1453 states and 1500 transitions. Second operand 64 states. [2019-11-15 23:12:09,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:12:09,327 INFO L93 Difference]: Finished difference Result 2074 states and 2244 transitions. [2019-11-15 23:12:09,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2019-11-15 23:12:09,329 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 1249 [2019-11-15 23:12:09,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:12:09,342 INFO L225 Difference]: With dead ends: 2074 [2019-11-15 23:12:09,349 INFO L226 Difference]: Without dead ends: 2074 [2019-11-15 23:12:09,350 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1372 GetRequests, 1266 SyntacticMatches, 1 SemanticMatches, 105 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2704 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1014, Invalid=10328, Unknown=0, NotChecked=0, Total=11342 [2019-11-15 23:12:09,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2074 states. [2019-11-15 23:12:09,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2074 to 1564. [2019-11-15 23:12:09,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1564 states. [2019-11-15 23:12:09,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1564 states to 1564 states and 1613 transitions. [2019-11-15 23:12:09,385 INFO L78 Accepts]: Start accepts. Automaton has 1564 states and 1613 transitions. Word has length 1249 [2019-11-15 23:12:09,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:12:09,386 INFO L462 AbstractCegarLoop]: Abstraction has 1564 states and 1613 transitions. [2019-11-15 23:12:09,386 INFO L463 AbstractCegarLoop]: Interpolant automaton has 64 states. [2019-11-15 23:12:09,386 INFO L276 IsEmpty]: Start isEmpty. Operand 1564 states and 1613 transitions. [2019-11-15 23:12:09,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1361 [2019-11-15 23:12:09,403 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:12:09,403 INFO L380 BasicCegarLoop]: trace histogram [229, 228, 228, 228, 228, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:12:09,608 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 42 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:09,608 INFO L410 AbstractCegarLoop]: === Iteration 49 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:12:09,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:12:09,609 INFO L82 PathProgramCache]: Analyzing trace with hash -1077882064, now seen corresponding path program 33 times [2019-11-15 23:12:09,609 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:12:09,609 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859707589] [2019-11-15 23:12:09,609 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:09,609 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:09,609 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:12:09,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:10,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:11,632 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 41042 proven. 3254 refuted. 0 times theorem prover too weak. 91839 trivial. 0 not checked. [2019-11-15 23:12:11,632 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859707589] [2019-11-15 23:12:11,632 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [790241150] [2019-11-15 23:12:11,632 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:12,325 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2019-11-15 23:12:12,325 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:12:12,330 INFO L256 TraceCheckSpWp]: Trace formula consists of 1460 conjuncts, 30 conjunts are in the unsatisfiable core [2019-11-15 23:12:12,338 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:12:14,232 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 38420 proven. 2853 refuted. 0 times theorem prover too weak. 94862 trivial. 0 not checked. [2019-11-15 23:12:14,232 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:12:14,233 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 29] total 74 [2019-11-15 23:12:14,233 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [538686487] [2019-11-15 23:12:14,234 INFO L442 AbstractCegarLoop]: Interpolant automaton has 74 states [2019-11-15 23:12:14,234 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:12:14,234 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2019-11-15 23:12:14,235 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=913, Invalid=4489, Unknown=0, NotChecked=0, Total=5402 [2019-11-15 23:12:14,235 INFO L87 Difference]: Start difference. First operand 1564 states and 1613 transitions. Second operand 74 states. [2019-11-15 23:12:19,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:12:19,372 INFO L93 Difference]: Finished difference Result 3326 states and 3643 transitions. [2019-11-15 23:12:19,373 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 114 states. [2019-11-15 23:12:19,373 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 1360 [2019-11-15 23:12:19,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:12:19,383 INFO L225 Difference]: With dead ends: 3326 [2019-11-15 23:12:19,383 INFO L226 Difference]: Without dead ends: 3320 [2019-11-15 23:12:19,386 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1545 GetRequests, 1372 SyntacticMatches, 0 SemanticMatches, 173 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8023 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=5111, Invalid=25339, Unknown=0, NotChecked=0, Total=30450 [2019-11-15 23:12:19,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3320 states. [2019-11-15 23:12:19,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3320 to 1569. [2019-11-15 23:12:19,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1569 states. [2019-11-15 23:12:19,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1569 states to 1569 states and 1617 transitions. [2019-11-15 23:12:19,428 INFO L78 Accepts]: Start accepts. Automaton has 1569 states and 1617 transitions. Word has length 1360 [2019-11-15 23:12:19,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:12:19,429 INFO L462 AbstractCegarLoop]: Abstraction has 1569 states and 1617 transitions. [2019-11-15 23:12:19,429 INFO L463 AbstractCegarLoop]: Interpolant automaton has 74 states. [2019-11-15 23:12:19,429 INFO L276 IsEmpty]: Start isEmpty. Operand 1569 states and 1617 transitions. [2019-11-15 23:12:19,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1366 [2019-11-15 23:12:19,446 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:12:19,446 INFO L380 BasicCegarLoop]: trace histogram [230, 229, 229, 229, 229, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:12:19,653 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 43 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:19,653 INFO L410 AbstractCegarLoop]: === Iteration 50 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:12:19,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:12:19,653 INFO L82 PathProgramCache]: Analyzing trace with hash -1160826203, now seen corresponding path program 34 times [2019-11-15 23:12:19,654 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:12:19,654 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1979384556] [2019-11-15 23:12:19,654 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:19,654 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:19,654 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:12:19,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:20,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:21,758 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 22706 proven. 1084 refuted. 0 times theorem prover too weak. 113506 trivial. 0 not checked. [2019-11-15 23:12:21,758 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1979384556] [2019-11-15 23:12:21,758 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [84209434] [2019-11-15 23:12:21,758 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:23,944 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-11-15 23:12:23,944 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:12:23,958 INFO L256 TraceCheckSpWp]: Trace formula consists of 3437 conjuncts, 43 conjunts are in the unsatisfiable core [2019-11-15 23:12:23,965 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:12:25,346 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 21717 proven. 990 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2019-11-15 23:12:25,346 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:12:25,347 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 22] total 66 [2019-11-15 23:12:25,347 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497610923] [2019-11-15 23:12:25,348 INFO L442 AbstractCegarLoop]: Interpolant automaton has 67 states [2019-11-15 23:12:25,348 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:12:25,348 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2019-11-15 23:12:25,348 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=552, Invalid=3870, Unknown=0, NotChecked=0, Total=4422 [2019-11-15 23:12:25,349 INFO L87 Difference]: Start difference. First operand 1569 states and 1617 transitions. Second operand 67 states. [2019-11-15 23:12:30,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:12:30,202 INFO L93 Difference]: Finished difference Result 2283 states and 2473 transitions. [2019-11-15 23:12:30,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-11-15 23:12:30,202 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1365 [2019-11-15 23:12:30,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:12:30,208 INFO L225 Difference]: With dead ends: 2283 [2019-11-15 23:12:30,208 INFO L226 Difference]: Without dead ends: 2283 [2019-11-15 23:12:30,209 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1494 GetRequests, 1383 SyntacticMatches, 1 SemanticMatches, 110 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2976 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1095, Invalid=11337, Unknown=0, NotChecked=0, Total=12432 [2019-11-15 23:12:30,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2283 states. [2019-11-15 23:12:30,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2283 to 1685. [2019-11-15 23:12:30,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1685 states. [2019-11-15 23:12:30,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1685 states to 1685 states and 1735 transitions. [2019-11-15 23:12:30,233 INFO L78 Accepts]: Start accepts. Automaton has 1685 states and 1735 transitions. Word has length 1365 [2019-11-15 23:12:30,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:12:30,234 INFO L462 AbstractCegarLoop]: Abstraction has 1685 states and 1735 transitions. [2019-11-15 23:12:30,234 INFO L463 AbstractCegarLoop]: Interpolant automaton has 67 states. [2019-11-15 23:12:30,234 INFO L276 IsEmpty]: Start isEmpty. Operand 1685 states and 1735 transitions. [2019-11-15 23:12:30,254 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1482 [2019-11-15 23:12:30,254 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:12:30,255 INFO L380 BasicCegarLoop]: trace histogram [251, 250, 250, 250, 250, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:12:30,466 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 44 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:30,467 INFO L410 AbstractCegarLoop]: === Iteration 51 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:12:30,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:12:30,467 INFO L82 PathProgramCache]: Analyzing trace with hash -667535262, now seen corresponding path program 35 times [2019-11-15 23:12:30,467 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:12:30,467 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286928483] [2019-11-15 23:12:30,468 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:30,468 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:30,468 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:12:30,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:30,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:30,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:31,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:32,856 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 47483 proven. 3587 refuted. 0 times theorem prover too weak. 112225 trivial. 0 not checked. [2019-11-15 23:12:32,857 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1286928483] [2019-11-15 23:12:32,857 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [806161024] [2019-11-15 23:12:32,857 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:35,627 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2019-11-15 23:12:35,627 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:12:35,644 INFO L256 TraceCheckSpWp]: Trace formula consists of 3662 conjuncts, 48 conjunts are in the unsatisfiable core [2019-11-15 23:12:35,653 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:12:37,865 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 47409 proven. 5742 refuted. 0 times theorem prover too weak. 110144 trivial. 0 not checked. [2019-11-15 23:12:37,865 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:12:37,866 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 48] total 76 [2019-11-15 23:12:37,866 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1944556618] [2019-11-15 23:12:37,867 INFO L442 AbstractCegarLoop]: Interpolant automaton has 76 states [2019-11-15 23:12:37,867 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:12:37,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2019-11-15 23:12:37,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1030, Invalid=4670, Unknown=0, NotChecked=0, Total=5700 [2019-11-15 23:12:37,867 INFO L87 Difference]: Start difference. First operand 1685 states and 1735 transitions. Second operand 76 states. [2019-11-15 23:12:40,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:12:40,776 INFO L93 Difference]: Finished difference Result 2349 states and 2545 transitions. [2019-11-15 23:12:40,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2019-11-15 23:12:40,777 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 1481 [2019-11-15 23:12:40,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:12:40,783 INFO L225 Difference]: With dead ends: 2349 [2019-11-15 23:12:40,783 INFO L226 Difference]: Without dead ends: 2343 [2019-11-15 23:12:40,785 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1616 GetRequests, 1495 SyntacticMatches, 0 SemanticMatches, 121 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3660 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=3188, Invalid=11818, Unknown=0, NotChecked=0, Total=15006 [2019-11-15 23:12:40,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2343 states. [2019-11-15 23:12:40,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2343 to 1716. [2019-11-15 23:12:40,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1716 states. [2019-11-15 23:12:40,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1716 states to 1716 states and 1769 transitions. [2019-11-15 23:12:40,812 INFO L78 Accepts]: Start accepts. Automaton has 1716 states and 1769 transitions. Word has length 1481 [2019-11-15 23:12:40,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:12:40,813 INFO L462 AbstractCegarLoop]: Abstraction has 1716 states and 1769 transitions. [2019-11-15 23:12:40,813 INFO L463 AbstractCegarLoop]: Interpolant automaton has 76 states. [2019-11-15 23:12:40,814 INFO L276 IsEmpty]: Start isEmpty. Operand 1716 states and 1769 transitions. [2019-11-15 23:12:40,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1487 [2019-11-15 23:12:40,833 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:12:40,834 INFO L380 BasicCegarLoop]: trace histogram [252, 251, 251, 251, 251, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:12:41,049 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 45 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:41,049 INFO L410 AbstractCegarLoop]: === Iteration 52 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:12:41,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:12:41,050 INFO L82 PathProgramCache]: Analyzing trace with hash 9778855, now seen corresponding path program 36 times [2019-11-15 23:12:41,050 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:12:41,050 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036905670] [2019-11-15 23:12:41,050 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:41,051 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:41,051 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:12:41,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:42,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:43,333 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 26141 proven. 1201 refuted. 0 times theorem prover too weak. 137225 trivial. 0 not checked. [2019-11-15 23:12:43,333 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036905670] [2019-11-15 23:12:43,333 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [661389330] [2019-11-15 23:12:43,333 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:45,851 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2019-11-15 23:12:45,851 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:12:45,861 INFO L256 TraceCheckSpWp]: Trace formula consists of 2927 conjuncts, 25 conjunts are in the unsatisfiable core [2019-11-15 23:12:45,869 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:12:47,477 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 25050 proven. 1092 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2019-11-15 23:12:47,477 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:12:47,478 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 24] total 71 [2019-11-15 23:12:47,478 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007452019] [2019-11-15 23:12:47,479 INFO L442 AbstractCegarLoop]: Interpolant automaton has 72 states [2019-11-15 23:12:47,479 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:12:47,479 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2019-11-15 23:12:47,479 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=816, Invalid=4296, Unknown=0, NotChecked=0, Total=5112 [2019-11-15 23:12:47,479 INFO L87 Difference]: Start difference. First operand 1716 states and 1769 transitions. Second operand 72 states. [2019-11-15 23:12:51,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:12:51,121 INFO L93 Difference]: Finished difference Result 2523 states and 2745 transitions. [2019-11-15 23:12:51,121 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2019-11-15 23:12:51,121 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 1486 [2019-11-15 23:12:51,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:12:51,127 INFO L225 Difference]: With dead ends: 2523 [2019-11-15 23:12:51,127 INFO L226 Difference]: Without dead ends: 2523 [2019-11-15 23:12:51,128 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1621 GetRequests, 1504 SyntacticMatches, 0 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3368 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=2318, Invalid=11724, Unknown=0, NotChecked=0, Total=14042 [2019-11-15 23:12:51,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2523 states. [2019-11-15 23:12:51,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2523 to 1837. [2019-11-15 23:12:51,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1837 states. [2019-11-15 23:12:51,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1837 states to 1837 states and 1892 transitions. [2019-11-15 23:12:51,157 INFO L78 Accepts]: Start accepts. Automaton has 1837 states and 1892 transitions. Word has length 1486 [2019-11-15 23:12:51,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:12:51,158 INFO L462 AbstractCegarLoop]: Abstraction has 1837 states and 1892 transitions. [2019-11-15 23:12:51,158 INFO L463 AbstractCegarLoop]: Interpolant automaton has 72 states. [2019-11-15 23:12:51,158 INFO L276 IsEmpty]: Start isEmpty. Operand 1837 states and 1892 transitions. [2019-11-15 23:12:51,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1608 [2019-11-15 23:12:51,180 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:12:51,181 INFO L380 BasicCegarLoop]: trace histogram [274, 273, 273, 273, 273, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:12:51,391 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 46 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:51,391 INFO L410 AbstractCegarLoop]: === Iteration 53 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:12:51,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:12:51,392 INFO L82 PathProgramCache]: Analyzing trace with hash -1747254261, now seen corresponding path program 37 times [2019-11-15 23:12:51,392 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:12:51,392 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538331853] [2019-11-15 23:12:51,392 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:51,392 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:51,392 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:12:51,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:51,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:52,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:52,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:52,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:52,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:52,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:52,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:54,036 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 54562 proven. 3936 refuted. 0 times theorem prover too weak. 135815 trivial. 0 not checked. [2019-11-15 23:12:54,036 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538331853] [2019-11-15 23:12:54,036 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1925151798] [2019-11-15 23:12:54,037 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:54,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:12:54,625 INFO L256 TraceCheckSpWp]: Trace formula consists of 4031 conjuncts, 46 conjunts are in the unsatisfiable core [2019-11-15 23:12:54,634 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:12:56,837 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 54798 proven. 1071 refuted. 0 times theorem prover too weak. 138444 trivial. 0 not checked. [2019-11-15 23:12:56,838 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:12:56,838 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 46] total 73 [2019-11-15 23:12:56,838 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266290324] [2019-11-15 23:12:56,840 INFO L442 AbstractCegarLoop]: Interpolant automaton has 73 states [2019-11-15 23:12:56,840 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:12:56,840 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2019-11-15 23:12:56,840 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1070, Invalid=4186, Unknown=0, NotChecked=0, Total=5256 [2019-11-15 23:12:56,840 INFO L87 Difference]: Start difference. First operand 1837 states and 1892 transitions. Second operand 73 states. [2019-11-15 23:12:59,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:12:59,192 INFO L93 Difference]: Finished difference Result 2571 states and 2791 transitions. [2019-11-15 23:12:59,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-11-15 23:12:59,192 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1607 [2019-11-15 23:12:59,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:12:59,197 INFO L225 Difference]: With dead ends: 2571 [2019-11-15 23:12:59,197 INFO L226 Difference]: Without dead ends: 2565 [2019-11-15 23:12:59,198 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1743 GetRequests, 1628 SyntacticMatches, 0 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3297 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=3014, Invalid=10558, Unknown=0, NotChecked=0, Total=13572 [2019-11-15 23:12:59,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2565 states. [2019-11-15 23:12:59,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2565 to 1842. [2019-11-15 23:12:59,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1842 states. [2019-11-15 23:12:59,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1842 states to 1842 states and 1896 transitions. [2019-11-15 23:12:59,226 INFO L78 Accepts]: Start accepts. Automaton has 1842 states and 1896 transitions. Word has length 1607 [2019-11-15 23:12:59,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:12:59,228 INFO L462 AbstractCegarLoop]: Abstraction has 1842 states and 1896 transitions. [2019-11-15 23:12:59,228 INFO L463 AbstractCegarLoop]: Interpolant automaton has 73 states. [2019-11-15 23:12:59,228 INFO L276 IsEmpty]: Start isEmpty. Operand 1842 states and 1896 transitions. [2019-11-15 23:12:59,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1613 [2019-11-15 23:12:59,250 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:12:59,251 INFO L380 BasicCegarLoop]: trace histogram [275, 274, 274, 274, 274, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:12:59,461 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 47 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:12:59,462 INFO L410 AbstractCegarLoop]: === Iteration 54 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:12:59,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:12:59,462 INFO L82 PathProgramCache]: Analyzing trace with hash 318401322, now seen corresponding path program 38 times [2019-11-15 23:12:59,462 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:12:59,462 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596130377] [2019-11-15 23:12:59,462 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:59,462 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:12:59,462 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:12:59,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:00,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:02,051 INFO L134 CoverageAnalysis]: Checked inductivity of 195701 backedges. 29905 proven. 1324 refuted. 0 times theorem prover too weak. 164472 trivial. 0 not checked. [2019-11-15 23:13:02,051 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596130377] [2019-11-15 23:13:02,051 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [403721015] [2019-11-15 23:13:02,051 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:13:02,644 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-11-15 23:13:02,644 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:13:02,653 INFO L256 TraceCheckSpWp]: Trace formula consists of 4043 conjuncts, 47 conjunts are in the unsatisfiable core [2019-11-15 23:13:02,662 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:13:04,489 INFO L134 CoverageAnalysis]: Checked inductivity of 195701 backedges. 28707 proven. 1199 refuted. 0 times theorem prover too weak. 165795 trivial. 0 not checked. [2019-11-15 23:13:04,489 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:13:04,490 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 24] total 72 [2019-11-15 23:13:04,490 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627946082] [2019-11-15 23:13:04,491 INFO L442 AbstractCegarLoop]: Interpolant automaton has 73 states [2019-11-15 23:13:04,491 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:13:04,492 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2019-11-15 23:13:04,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=650, Invalid=4606, Unknown=0, NotChecked=0, Total=5256 [2019-11-15 23:13:04,492 INFO L87 Difference]: Start difference. First operand 1842 states and 1896 transitions. Second operand 73 states. [2019-11-15 23:13:10,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:13:10,445 INFO L93 Difference]: Finished difference Result 2758 states and 3005 transitions. [2019-11-15 23:13:10,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2019-11-15 23:13:10,446 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1612 [2019-11-15 23:13:10,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:13:10,452 INFO L225 Difference]: With dead ends: 2758 [2019-11-15 23:13:10,452 INFO L226 Difference]: Without dead ends: 2758 [2019-11-15 23:13:10,453 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1753 GetRequests, 1632 SyntacticMatches, 1 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3559 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=1266, Invalid=13496, Unknown=0, NotChecked=0, Total=14762 [2019-11-15 23:13:10,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2758 states. [2019-11-15 23:13:10,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2758 to 1968. [2019-11-15 23:13:10,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1968 states. [2019-11-15 23:13:10,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1968 states to 1968 states and 2024 transitions. [2019-11-15 23:13:10,485 INFO L78 Accepts]: Start accepts. Automaton has 1968 states and 2024 transitions. Word has length 1612 [2019-11-15 23:13:10,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:13:10,486 INFO L462 AbstractCegarLoop]: Abstraction has 1968 states and 2024 transitions. [2019-11-15 23:13:10,486 INFO L463 AbstractCegarLoop]: Interpolant automaton has 73 states. [2019-11-15 23:13:10,487 INFO L276 IsEmpty]: Start isEmpty. Operand 1968 states and 2024 transitions. [2019-11-15 23:13:10,511 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1739 [2019-11-15 23:13:10,512 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:13:10,513 INFO L380 BasicCegarLoop]: trace histogram [298, 297, 297, 297, 297, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:13:10,719 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 48 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:13:10,720 INFO L410 AbstractCegarLoop]: === Iteration 55 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:13:10,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:13:10,720 INFO L82 PathProgramCache]: Analyzing trace with hash -1675122425, now seen corresponding path program 39 times [2019-11-15 23:13:10,721 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:13:10,722 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428993097] [2019-11-15 23:13:10,722 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:13:10,722 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:13:10,722 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:13:10,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:11,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:13,805 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 62309 proven. 4301 refuted. 0 times theorem prover too weak. 162927 trivial. 0 not checked. [2019-11-15 23:13:13,806 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428993097] [2019-11-15 23:13:13,806 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1536014942] [2019-11-15 23:13:13,806 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:13:14,903 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2019-11-15 23:13:14,903 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:13:14,910 INFO L256 TraceCheckSpWp]: Trace formula consists of 1955 conjuncts, 27 conjunts are in the unsatisfiable core [2019-11-15 23:13:14,965 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:13:17,114 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 32586 proven. 1311 refuted. 0 times theorem prover too weak. 195640 trivial. 0 not checked. [2019-11-15 23:13:17,115 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:13:17,115 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 26] total 78 [2019-11-15 23:13:17,115 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [814351212] [2019-11-15 23:13:17,117 INFO L442 AbstractCegarLoop]: Interpolant automaton has 78 states [2019-11-15 23:13:17,117 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:13:17,117 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2019-11-15 23:13:17,118 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1169, Invalid=4837, Unknown=0, NotChecked=0, Total=6006 [2019-11-15 23:13:17,118 INFO L87 Difference]: Start difference. First operand 1968 states and 2024 transitions. Second operand 78 states. [2019-11-15 23:13:20,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:13:20,367 INFO L93 Difference]: Finished difference Result 2930 states and 3201 transitions. [2019-11-15 23:13:20,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2019-11-15 23:13:20,367 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 1738 [2019-11-15 23:13:20,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:13:20,373 INFO L225 Difference]: With dead ends: 2930 [2019-11-15 23:13:20,374 INFO L226 Difference]: Without dead ends: 2924 [2019-11-15 23:13:20,374 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1881 GetRequests, 1758 SyntacticMatches, 0 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3835 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=3422, Invalid=12078, Unknown=0, NotChecked=0, Total=15500 [2019-11-15 23:13:20,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2924 states. [2019-11-15 23:13:20,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2924 to 1978. [2019-11-15 23:13:20,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1978 states. [2019-11-15 23:13:20,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1978 states to 1978 states and 2034 transitions. [2019-11-15 23:13:20,405 INFO L78 Accepts]: Start accepts. Automaton has 1978 states and 2034 transitions. Word has length 1738 [2019-11-15 23:13:20,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:13:20,406 INFO L462 AbstractCegarLoop]: Abstraction has 1978 states and 2034 transitions. [2019-11-15 23:13:20,406 INFO L463 AbstractCegarLoop]: Interpolant automaton has 78 states. [2019-11-15 23:13:20,406 INFO L276 IsEmpty]: Start isEmpty. Operand 1978 states and 2034 transitions. [2019-11-15 23:13:20,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1749 [2019-11-15 23:13:20,431 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:13:20,432 INFO L380 BasicCegarLoop]: trace histogram [300, 299, 299, 299, 299, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:13:20,633 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 49 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:13:20,633 INFO L410 AbstractCegarLoop]: === Iteration 56 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:13:20,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:13:20,633 INFO L82 PathProgramCache]: Analyzing trace with hash 1749257613, now seen corresponding path program 40 times [2019-11-15 23:13:20,634 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:13:20,634 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435931954] [2019-11-15 23:13:20,634 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:13:20,634 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:13:20,634 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:13:20,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:21,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:22,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:22,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:22,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:23,504 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35503 proven. 1477 refuted. 0 times theorem prover too weak. 195580 trivial. 0 not checked. [2019-11-15 23:13:23,504 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435931954] [2019-11-15 23:13:23,504 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [124718523] [2019-11-15 23:13:23,504 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:13:24,175 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-11-15 23:13:24,176 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:13:24,190 INFO L256 TraceCheckSpWp]: Trace formula consists of 3694 conjuncts, 56 conjunts are in the unsatisfiable core [2019-11-15 23:13:24,204 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:13:27,046 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35327 proven. 4789 refuted. 0 times theorem prover too weak. 192444 trivial. 0 not checked. [2019-11-15 23:13:27,046 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:13:27,047 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 55] total 83 [2019-11-15 23:13:27,047 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665624611] [2019-11-15 23:13:27,049 INFO L442 AbstractCegarLoop]: Interpolant automaton has 83 states [2019-11-15 23:13:27,049 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:13:27,050 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2019-11-15 23:13:27,050 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1393, Invalid=5413, Unknown=0, NotChecked=0, Total=6806 [2019-11-15 23:13:27,050 INFO L87 Difference]: Start difference. First operand 1978 states and 2034 transitions. Second operand 83 states. [2019-11-15 23:13:31,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:13:31,837 INFO L93 Difference]: Finished difference Result 3000 states and 3258 transitions. [2019-11-15 23:13:31,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2019-11-15 23:13:31,837 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 1748 [2019-11-15 23:13:31,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:13:31,843 INFO L225 Difference]: With dead ends: 3000 [2019-11-15 23:13:31,843 INFO L226 Difference]: Without dead ends: 3000 [2019-11-15 23:13:31,845 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 1900 GetRequests, 1764 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3795 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=4039, Invalid=14867, Unknown=0, NotChecked=0, Total=18906 [2019-11-15 23:13:31,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3000 states. [2019-11-15 23:13:31,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3000 to 2624. [2019-11-15 23:13:31,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2624 states. [2019-11-15 23:13:31,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2624 states to 2624 states and 2770 transitions. [2019-11-15 23:13:31,885 INFO L78 Accepts]: Start accepts. Automaton has 2624 states and 2770 transitions. Word has length 1748 [2019-11-15 23:13:31,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:13:31,886 INFO L462 AbstractCegarLoop]: Abstraction has 2624 states and 2770 transitions. [2019-11-15 23:13:31,886 INFO L463 AbstractCegarLoop]: Interpolant automaton has 83 states. [2019-11-15 23:13:31,886 INFO L276 IsEmpty]: Start isEmpty. Operand 2624 states and 2770 transitions. [2019-11-15 23:13:31,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1875 [2019-11-15 23:13:31,916 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:13:31,917 INFO L380 BasicCegarLoop]: trace histogram [323, 322, 322, 322, 322, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:13:32,123 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 50 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:13:32,123 INFO L410 AbstractCegarLoop]: === Iteration 57 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:13:32,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:13:32,124 INFO L82 PathProgramCache]: Analyzing trace with hash 754168784, now seen corresponding path program 41 times [2019-11-15 23:13:32,124 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:13:32,124 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821147559] [2019-11-15 23:13:32,124 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:13:32,124 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:13:32,124 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:13:32,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:32,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:33,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:33,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:33,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:33,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:33,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:33,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:33,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:33,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:35,489 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 70754 proven. 4682 refuted. 0 times theorem prover too weak. 193894 trivial. 0 not checked. [2019-11-15 23:13:35,489 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821147559] [2019-11-15 23:13:35,489 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [228473557] [2019-11-15 23:13:35,490 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:13:40,776 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 52 check-sat command(s) [2019-11-15 23:13:40,776 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:13:40,799 INFO L256 TraceCheckSpWp]: Trace formula consists of 4625 conjuncts, 54 conjunts are in the unsatisfiable core [2019-11-15 23:13:40,810 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:13:43,808 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 70650 proven. 7533 refuted. 0 times theorem prover too weak. 191147 trivial. 0 not checked. [2019-11-15 23:13:43,809 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:13:43,809 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 54] total 85 [2019-11-15 23:13:43,810 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [444123670] [2019-11-15 23:13:43,811 INFO L442 AbstractCegarLoop]: Interpolant automaton has 85 states [2019-11-15 23:13:43,811 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:13:43,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2019-11-15 23:13:43,812 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1315, Invalid=5825, Unknown=0, NotChecked=0, Total=7140 [2019-11-15 23:13:43,812 INFO L87 Difference]: Start difference. First operand 2624 states and 2770 transitions. Second operand 85 states. [2019-11-15 23:13:47,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:13:47,199 INFO L93 Difference]: Finished difference Result 3024 states and 3288 transitions. [2019-11-15 23:13:47,199 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 79 states. [2019-11-15 23:13:47,199 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 1874 [2019-11-15 23:13:47,200 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:13:47,204 INFO L225 Difference]: With dead ends: 3024 [2019-11-15 23:13:47,204 INFO L226 Difference]: Without dead ends: 3018 [2019-11-15 23:13:47,205 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2027 GetRequests, 1891 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4683 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=4028, Invalid=14878, Unknown=0, NotChecked=0, Total=18906 [2019-11-15 23:13:47,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3018 states. [2019-11-15 23:13:47,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3018 to 2645. [2019-11-15 23:13:47,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2645 states. [2019-11-15 23:13:47,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2645 states to 2645 states and 2792 transitions. [2019-11-15 23:13:47,238 INFO L78 Accepts]: Start accepts. Automaton has 2645 states and 2792 transitions. Word has length 1874 [2019-11-15 23:13:47,239 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:13:47,239 INFO L462 AbstractCegarLoop]: Abstraction has 2645 states and 2792 transitions. [2019-11-15 23:13:47,239 INFO L463 AbstractCegarLoop]: Interpolant automaton has 85 states. [2019-11-15 23:13:47,239 INFO L276 IsEmpty]: Start isEmpty. Operand 2645 states and 2792 transitions. [2019-11-15 23:13:47,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1880 [2019-11-15 23:13:47,264 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:13:47,265 INFO L380 BasicCegarLoop]: trace histogram [324, 323, 323, 323, 323, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:13:47,467 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 51 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:13:47,467 INFO L410 AbstractCegarLoop]: === Iteration 58 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:13:47,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:13:47,467 INFO L82 PathProgramCache]: Analyzing trace with hash -1687206139, now seen corresponding path program 42 times [2019-11-15 23:13:47,467 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:13:47,468 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927948412] [2019-11-15 23:13:47,468 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:13:47,468 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:13:47,468 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:13:47,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:48,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:49,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:13:50,707 INFO L134 CoverageAnalysis]: Checked inductivity of 270965 backedges. 38480 proven. 1588 refuted. 0 times theorem prover too weak. 230897 trivial. 0 not checked. [2019-11-15 23:13:50,708 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [927948412] [2019-11-15 23:13:50,708 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [437068799] [2019-11-15 23:13:50,708 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:14:03,638 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2019-11-15 23:14:03,639 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:14:03,659 INFO L256 TraceCheckSpWp]: Trace formula consists of 4157 conjuncts, 28 conjunts are in the unsatisfiable core [2019-11-15 23:14:03,670 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:14:05,990 INFO L134 CoverageAnalysis]: Checked inductivity of 270965 backedges. 37053 proven. 1428 refuted. 0 times theorem prover too weak. 232484 trivial. 0 not checked. [2019-11-15 23:14:05,990 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:14:05,991 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 27] total 80 [2019-11-15 23:14:05,991 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724670382] [2019-11-15 23:14:05,991 INFO L442 AbstractCegarLoop]: Interpolant automaton has 81 states [2019-11-15 23:14:05,992 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:14:05,992 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2019-11-15 23:14:05,992 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1038, Invalid=5442, Unknown=0, NotChecked=0, Total=6480 [2019-11-15 23:14:05,992 INFO L87 Difference]: Start difference. First operand 2645 states and 2792 transitions. Second operand 81 states. [2019-11-15 23:14:11,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:14:11,015 INFO L93 Difference]: Finished difference Result 3165 states and 3432 transitions. [2019-11-15 23:14:11,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2019-11-15 23:14:11,015 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 1879 [2019-11-15 23:14:11,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:14:11,020 INFO L225 Difference]: With dead ends: 3165 [2019-11-15 23:14:11,020 INFO L226 Difference]: Without dead ends: 3165 [2019-11-15 23:14:11,021 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2032 GetRequests, 1900 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4316 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=2930, Invalid=14892, Unknown=0, NotChecked=0, Total=17822 [2019-11-15 23:14:11,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3165 states. [2019-11-15 23:14:11,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3165 to 2781. [2019-11-15 23:14:11,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2781 states. [2019-11-15 23:14:11,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2781 states to 2781 states and 2930 transitions. [2019-11-15 23:14:11,059 INFO L78 Accepts]: Start accepts. Automaton has 2781 states and 2930 transitions. Word has length 1879 [2019-11-15 23:14:11,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:14:11,061 INFO L462 AbstractCegarLoop]: Abstraction has 2781 states and 2930 transitions. [2019-11-15 23:14:11,061 INFO L463 AbstractCegarLoop]: Interpolant automaton has 81 states. [2019-11-15 23:14:11,061 INFO L276 IsEmpty]: Start isEmpty. Operand 2781 states and 2930 transitions. [2019-11-15 23:14:11,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2016 [2019-11-15 23:14:11,095 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:14:11,096 INFO L380 BasicCegarLoop]: trace histogram [349, 348, 348, 348, 348, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:14:11,301 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 52 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:14:11,301 INFO L410 AbstractCegarLoop]: === Iteration 59 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:14:11,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:14:11,302 INFO L82 PathProgramCache]: Analyzing trace with hash -2048382334, now seen corresponding path program 43 times [2019-11-15 23:14:11,302 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:14:11,302 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094248254] [2019-11-15 23:14:11,302 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:14:11,302 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:14:11,302 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:14:11,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:11,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:11,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:12,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:15,184 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 79927 proven. 5079 refuted. 0 times theorem prover too weak. 229064 trivial. 0 not checked. [2019-11-15 23:14:15,184 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094248254] [2019-11-15 23:14:15,184 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [744364812] [2019-11-15 23:14:15,184 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:14:15,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:15,936 INFO L256 TraceCheckSpWp]: Trace formula consists of 5030 conjuncts, 52 conjunts are in the unsatisfiable core [2019-11-15 23:14:15,947 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:14:19,096 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 80196 proven. 1404 refuted. 0 times theorem prover too weak. 232470 trivial. 0 not checked. [2019-11-15 23:14:19,097 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:14:19,098 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 52] total 82 [2019-11-15 23:14:19,098 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455039079] [2019-11-15 23:14:19,098 INFO L442 AbstractCegarLoop]: Interpolant automaton has 82 states [2019-11-15 23:14:19,099 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:14:19,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2019-11-15 23:14:19,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1364, Invalid=5278, Unknown=0, NotChecked=0, Total=6642 [2019-11-15 23:14:19,099 INFO L87 Difference]: Start difference. First operand 2781 states and 2930 transitions. Second operand 82 states. [2019-11-15 23:14:22,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:14:22,387 INFO L93 Difference]: Finished difference Result 3165 states and 3430 transitions. [2019-11-15 23:14:22,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2019-11-15 23:14:22,393 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 2015 [2019-11-15 23:14:22,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:14:22,401 INFO L225 Difference]: With dead ends: 3165 [2019-11-15 23:14:22,401 INFO L226 Difference]: Without dead ends: 3159 [2019-11-15 23:14:22,402 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2169 GetRequests, 2039 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4272 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=3836, Invalid=13456, Unknown=0, NotChecked=0, Total=17292 [2019-11-15 23:14:22,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3159 states. [2019-11-15 23:14:22,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3159 to 2786. [2019-11-15 23:14:22,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2786 states. [2019-11-15 23:14:22,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2786 states to 2786 states and 2934 transitions. [2019-11-15 23:14:22,447 INFO L78 Accepts]: Start accepts. Automaton has 2786 states and 2934 transitions. Word has length 2015 [2019-11-15 23:14:22,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:14:22,448 INFO L462 AbstractCegarLoop]: Abstraction has 2786 states and 2934 transitions. [2019-11-15 23:14:22,448 INFO L463 AbstractCegarLoop]: Interpolant automaton has 82 states. [2019-11-15 23:14:22,448 INFO L276 IsEmpty]: Start isEmpty. Operand 2786 states and 2934 transitions. [2019-11-15 23:14:22,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2021 [2019-11-15 23:14:22,485 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:14:22,487 INFO L380 BasicCegarLoop]: trace histogram [350, 349, 349, 349, 349, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:14:22,694 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 53 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:14:22,695 INFO L410 AbstractCegarLoop]: === Iteration 60 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:14:22,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:14:22,695 INFO L82 PathProgramCache]: Analyzing trace with hash 1794680711, now seen corresponding path program 44 times [2019-11-15 23:14:22,695 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:14:22,695 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581251712] [2019-11-15 23:14:22,695 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:14:22,695 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:14:22,695 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:14:23,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:24,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:26,484 INFO L134 CoverageAnalysis]: Checked inductivity of 315836 backedges. 43321 proven. 1729 refuted. 0 times theorem prover too weak. 270786 trivial. 0 not checked. [2019-11-15 23:14:26,485 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581251712] [2019-11-15 23:14:26,485 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1466341102] [2019-11-15 23:14:26,485 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:14:27,239 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-11-15 23:14:27,239 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:14:27,251 INFO L256 TraceCheckSpWp]: Trace formula consists of 5042 conjuncts, 53 conjunts are in the unsatisfiable core [2019-11-15 23:14:27,262 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:14:29,825 INFO L134 CoverageAnalysis]: Checked inductivity of 315836 backedges. 41772 proven. 1550 refuted. 0 times theorem prover too weak. 272514 trivial. 0 not checked. [2019-11-15 23:14:29,826 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:14:29,827 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 27] total 81 [2019-11-15 23:14:29,827 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303037561] [2019-11-15 23:14:29,828 INFO L442 AbstractCegarLoop]: Interpolant automaton has 82 states [2019-11-15 23:14:29,828 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:14:29,828 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2019-11-15 23:14:29,828 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=812, Invalid=5830, Unknown=0, NotChecked=0, Total=6642 [2019-11-15 23:14:29,828 INFO L87 Difference]: Start difference. First operand 2786 states and 2934 transitions. Second operand 82 states. [2019-11-15 23:14:38,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:14:38,359 INFO L93 Difference]: Finished difference Result 3319 states and 3588 transitions. [2019-11-15 23:14:38,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2019-11-15 23:14:38,360 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 2020 [2019-11-15 23:14:38,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:14:38,365 INFO L225 Difference]: With dead ends: 3319 [2019-11-15 23:14:38,365 INFO L226 Difference]: Without dead ends: 3319 [2019-11-15 23:14:38,366 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2179 GetRequests, 2043 SyntacticMatches, 1 SemanticMatches, 135 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4531 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=1545, Invalid=17087, Unknown=0, NotChecked=0, Total=18632 [2019-11-15 23:14:38,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3319 states. [2019-11-15 23:14:38,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3319 to 2927. [2019-11-15 23:14:38,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2927 states. [2019-11-15 23:14:38,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2927 states to 2927 states and 3077 transitions. [2019-11-15 23:14:38,393 INFO L78 Accepts]: Start accepts. Automaton has 2927 states and 3077 transitions. Word has length 2020 [2019-11-15 23:14:38,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:14:38,394 INFO L462 AbstractCegarLoop]: Abstraction has 2927 states and 3077 transitions. [2019-11-15 23:14:38,394 INFO L463 AbstractCegarLoop]: Interpolant automaton has 82 states. [2019-11-15 23:14:38,394 INFO L276 IsEmpty]: Start isEmpty. Operand 2927 states and 3077 transitions. [2019-11-15 23:14:38,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2162 [2019-11-15 23:14:38,419 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:14:38,420 INFO L380 BasicCegarLoop]: trace histogram [376, 375, 375, 375, 375, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:14:38,620 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 54 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:14:38,620 INFO L410 AbstractCegarLoop]: === Iteration 61 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:14:38,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:14:38,621 INFO L82 PathProgramCache]: Analyzing trace with hash 567594603, now seen corresponding path program 45 times [2019-11-15 23:14:38,621 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:14:38,621 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [249464035] [2019-11-15 23:14:38,622 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:14:38,622 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:14:38,622 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:14:38,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:39,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:42,878 INFO L134 CoverageAnalysis]: Checked inductivity of 364150 backedges. 89858 proven. 5492 refuted. 0 times theorem prover too weak. 268800 trivial. 0 not checked. [2019-11-15 23:14:42,878 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [249464035] [2019-11-15 23:14:42,878 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1502907415] [2019-11-15 23:14:42,879 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:14:44,978 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2019-11-15 23:14:44,978 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:14:44,988 INFO L256 TraceCheckSpWp]: Trace formula consists of 2480 conjuncts, 30 conjunts are in the unsatisfiable core [2019-11-15 23:14:45,001 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:14:48,071 INFO L134 CoverageAnalysis]: Checked inductivity of 364150 backedges. 46743 proven. 1677 refuted. 0 times theorem prover too weak. 315730 trivial. 0 not checked. [2019-11-15 23:14:48,072 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:14:48,073 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 29] total 87 [2019-11-15 23:14:48,073 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1882150150] [2019-11-15 23:14:48,073 INFO L442 AbstractCegarLoop]: Interpolant automaton has 87 states [2019-11-15 23:14:48,073 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:14:48,074 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2019-11-15 23:14:48,074 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1475, Invalid=6007, Unknown=0, NotChecked=0, Total=7482 [2019-11-15 23:14:48,074 INFO L87 Difference]: Start difference. First operand 2927 states and 3077 transitions. Second operand 87 states. [2019-11-15 23:14:51,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:14:51,650 INFO L93 Difference]: Finished difference Result 3347 states and 3617 transitions. [2019-11-15 23:14:51,651 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2019-11-15 23:14:51,651 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 2161 [2019-11-15 23:14:51,652 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:14:51,656 INFO L225 Difference]: With dead ends: 3347 [2019-11-15 23:14:51,656 INFO L226 Difference]: Without dead ends: 3341 [2019-11-15 23:14:51,658 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2322 GetRequests, 2184 SyntacticMatches, 0 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4882 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=4295, Invalid=15165, Unknown=0, NotChecked=0, Total=19460 [2019-11-15 23:14:51,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3341 states. [2019-11-15 23:14:51,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3341 to 2937. [2019-11-15 23:14:51,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2937 states. [2019-11-15 23:14:51,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2937 states to 2937 states and 3087 transitions. [2019-11-15 23:14:51,684 INFO L78 Accepts]: Start accepts. Automaton has 2937 states and 3087 transitions. Word has length 2161 [2019-11-15 23:14:51,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:14:51,684 INFO L462 AbstractCegarLoop]: Abstraction has 2937 states and 3087 transitions. [2019-11-15 23:14:51,684 INFO L463 AbstractCegarLoop]: Interpolant automaton has 87 states. [2019-11-15 23:14:51,685 INFO L276 IsEmpty]: Start isEmpty. Operand 2937 states and 3087 transitions. [2019-11-15 23:14:51,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2172 [2019-11-15 23:14:51,708 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:14:51,709 INFO L380 BasicCegarLoop]: trace histogram [378, 377, 377, 377, 377, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:14:51,909 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 55 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:14:51,909 INFO L410 AbstractCegarLoop]: === Iteration 62 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:14:51,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:14:51,910 INFO L82 PathProgramCache]: Analyzing trace with hash 1011103077, now seen corresponding path program 46 times [2019-11-15 23:14:51,910 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:14:51,910 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530456914] [2019-11-15 23:14:51,910 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:14:51,910 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:14:51,910 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:14:52,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:53,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:14:55,921 INFO L134 CoverageAnalysis]: Checked inductivity of 367959 backedges. 50431 proven. 1903 refuted. 0 times theorem prover too weak. 315625 trivial. 0 not checked. [2019-11-15 23:14:55,922 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1530456914] [2019-11-15 23:14:55,922 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1921904769] [2019-11-15 23:14:55,922 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:14:56,653 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-11-15 23:14:56,653 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:14:56,666 INFO L256 TraceCheckSpWp]: Trace formula consists of 4564 conjuncts, 62 conjunts are in the unsatisfiable core [2019-11-15 23:14:56,678 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:15:00,538 INFO L134 CoverageAnalysis]: Checked inductivity of 367959 backedges. 50234 proven. 6079 refuted. 0 times theorem prover too weak. 311646 trivial. 0 not checked. [2019-11-15 23:15:00,538 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:15:00,539 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 61] total 92 [2019-11-15 23:15:00,539 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822551124] [2019-11-15 23:15:00,540 INFO L442 AbstractCegarLoop]: Interpolant automaton has 92 states [2019-11-15 23:15:00,540 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:15:00,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2019-11-15 23:15:00,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1726, Invalid=6646, Unknown=0, NotChecked=0, Total=8372 [2019-11-15 23:15:00,541 INFO L87 Difference]: Start difference. First operand 2937 states and 3087 transitions. Second operand 92 states. [2019-11-15 23:15:05,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:15:05,204 INFO L93 Difference]: Finished difference Result 3480 states and 3749 transitions. [2019-11-15 23:15:05,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2019-11-15 23:15:05,209 INFO L78 Accepts]: Start accepts. Automaton has 92 states. Word has length 2171 [2019-11-15 23:15:05,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:15:05,217 INFO L225 Difference]: With dead ends: 3480 [2019-11-15 23:15:05,217 INFO L226 Difference]: Without dead ends: 3480 [2019-11-15 23:15:05,219 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2341 GetRequests, 2190 SyntacticMatches, 0 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4632 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=5017, Invalid=18239, Unknown=0, NotChecked=0, Total=23256 [2019-11-15 23:15:05,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3480 states. [2019-11-15 23:15:05,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3480 to 3098. [2019-11-15 23:15:05,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3098 states. [2019-11-15 23:15:05,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3098 states to 3098 states and 3250 transitions. [2019-11-15 23:15:05,247 INFO L78 Accepts]: Start accepts. Automaton has 3098 states and 3250 transitions. Word has length 2171 [2019-11-15 23:15:05,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:15:05,248 INFO L462 AbstractCegarLoop]: Abstraction has 3098 states and 3250 transitions. [2019-11-15 23:15:05,248 INFO L463 AbstractCegarLoop]: Interpolant automaton has 92 states. [2019-11-15 23:15:05,248 INFO L276 IsEmpty]: Start isEmpty. Operand 3098 states and 3250 transitions. [2019-11-15 23:15:05,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2313 [2019-11-15 23:15:05,274 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:15:05,275 INFO L380 BasicCegarLoop]: trace histogram [404, 403, 403, 403, 403, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:15:05,476 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 56 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:15:05,476 INFO L410 AbstractCegarLoop]: === Iteration 63 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:15:05,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:15:05,476 INFO L82 PathProgramCache]: Analyzing trace with hash 1323482343, now seen corresponding path program 47 times [2019-11-15 23:15:05,476 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:15:05,476 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516816524] [2019-11-15 23:15:05,477 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:15:05,477 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:15:05,477 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:15:05,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:06,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:15:10,082 INFO L134 CoverageAnalysis]: Checked inductivity of 419978 backedges. 100577 proven. 5921 refuted. 0 times theorem prover too weak. 313480 trivial. 0 not checked. [2019-11-15 23:15:10,083 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [516816524] [2019-11-15 23:15:10,083 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [383162596] [2019-11-15 23:15:10,083 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:17:50,607 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 59 check-sat command(s) [2019-11-15 23:17:50,607 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:17:50,687 INFO L256 TraceCheckSpWp]: Trace formula consists of 5696 conjuncts, 60 conjunts are in the unsatisfiable core [2019-11-15 23:17:50,700 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:17:54,840 INFO L134 CoverageAnalysis]: Checked inductivity of 419978 backedges. 100443 proven. 9558 refuted. 0 times theorem prover too weak. 309977 trivial. 0 not checked. [2019-11-15 23:17:54,841 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:17:54,842 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 60] total 94 [2019-11-15 23:17:54,842 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74534463] [2019-11-15 23:17:54,843 INFO L442 AbstractCegarLoop]: Interpolant automaton has 94 states [2019-11-15 23:17:54,843 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:17:54,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2019-11-15 23:17:54,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1636, Invalid=7106, Unknown=0, NotChecked=0, Total=8742 [2019-11-15 23:17:54,844 INFO L87 Difference]: Start difference. First operand 3098 states and 3250 transitions. Second operand 94 states. [2019-11-15 23:17:59,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:17:59,416 INFO L93 Difference]: Finished difference Result 3504 states and 3776 transitions. [2019-11-15 23:17:59,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2019-11-15 23:17:59,417 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 2312 [2019-11-15 23:17:59,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:17:59,423 INFO L225 Difference]: With dead ends: 3504 [2019-11-15 23:17:59,424 INFO L226 Difference]: Without dead ends: 3498 [2019-11-15 23:17:59,425 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2483 GetRequests, 2332 SyntacticMatches, 0 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5832 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=4967, Invalid=18289, Unknown=0, NotChecked=0, Total=23256 [2019-11-15 23:17:59,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3498 states. [2019-11-15 23:17:59,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3498 to 3119. [2019-11-15 23:17:59,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3119 states. [2019-11-15 23:17:59,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3119 states to 3119 states and 3272 transitions. [2019-11-15 23:17:59,466 INFO L78 Accepts]: Start accepts. Automaton has 3119 states and 3272 transitions. Word has length 2312 [2019-11-15 23:17:59,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:17:59,467 INFO L462 AbstractCegarLoop]: Abstraction has 3119 states and 3272 transitions. [2019-11-15 23:17:59,467 INFO L463 AbstractCegarLoop]: Interpolant automaton has 94 states. [2019-11-15 23:17:59,467 INFO L276 IsEmpty]: Start isEmpty. Operand 3119 states and 3272 transitions. [2019-11-15 23:17:59,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2318 [2019-11-15 23:17:59,506 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:17:59,508 INFO L380 BasicCegarLoop]: trace histogram [405, 404, 404, 404, 404, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:17:59,721 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 57 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:17:59,722 INFO L410 AbstractCegarLoop]: === Iteration 64 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:17:59,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:17:59,723 INFO L82 PathProgramCache]: Analyzing trace with hash 1696940994, now seen corresponding path program 48 times [2019-11-15 23:17:59,723 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:17:59,724 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1500162762] [2019-11-15 23:17:59,724 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:17:59,725 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:17:59,725 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:18:00,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:01,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:04,232 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 54185 proven. 2029 refuted. 0 times theorem prover too weak. 365807 trivial. 0 not checked. [2019-11-15 23:18:04,233 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1500162762] [2019-11-15 23:18:04,233 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1692348095] [2019-11-15 23:18:04,233 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:18:18,368 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2019-11-15 23:18:18,368 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:18:18,397 INFO L256 TraceCheckSpWp]: Trace formula consists of 4244 conjuncts, 69 conjunts are in the unsatisfiable core [2019-11-15 23:18:18,409 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:18:21,262 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 52113 proven. 10491 refuted. 0 times theorem prover too weak. 359417 trivial. 0 not checked. [2019-11-15 23:18:21,262 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:18:21,263 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 40] total 74 [2019-11-15 23:18:21,264 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397616251] [2019-11-15 23:18:21,264 INFO L442 AbstractCegarLoop]: Interpolant automaton has 75 states [2019-11-15 23:18:21,264 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:18:21,265 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2019-11-15 23:18:21,265 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1026, Invalid=4524, Unknown=0, NotChecked=0, Total=5550 [2019-11-15 23:18:21,265 INFO L87 Difference]: Start difference. First operand 3119 states and 3272 transitions. Second operand 75 states. [2019-11-15 23:18:27,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:18:27,662 INFO L93 Difference]: Finished difference Result 3645 states and 3918 transitions. [2019-11-15 23:18:27,663 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2019-11-15 23:18:27,663 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 2317 [2019-11-15 23:18:27,664 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:18:27,669 INFO L225 Difference]: With dead ends: 3645 [2019-11-15 23:18:27,670 INFO L226 Difference]: Without dead ends: 3645 [2019-11-15 23:18:27,672 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2521 GetRequests, 2356 SyntacticMatches, 0 SemanticMatches, 165 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7378 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=3892, Invalid=23830, Unknown=0, NotChecked=0, Total=27722 [2019-11-15 23:18:27,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3645 states. [2019-11-15 23:18:27,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3645 to 3265. [2019-11-15 23:18:27,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3265 states. [2019-11-15 23:18:27,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3265 states to 3265 states and 3419 transitions. [2019-11-15 23:18:27,714 INFO L78 Accepts]: Start accepts. Automaton has 3265 states and 3419 transitions. Word has length 2317 [2019-11-15 23:18:27,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:18:27,715 INFO L462 AbstractCegarLoop]: Abstraction has 3265 states and 3419 transitions. [2019-11-15 23:18:27,716 INFO L463 AbstractCegarLoop]: Interpolant automaton has 75 states. [2019-11-15 23:18:27,716 INFO L276 IsEmpty]: Start isEmpty. Operand 3265 states and 3419 transitions. [2019-11-15 23:18:27,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2464 [2019-11-15 23:18:27,759 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:18:27,761 INFO L380 BasicCegarLoop]: trace histogram [432, 431, 431, 431, 431, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:18:27,976 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 58 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:18:27,976 INFO L410 AbstractCegarLoop]: === Iteration 65 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:18:27,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:18:27,976 INFO L82 PathProgramCache]: Analyzing trace with hash 177571039, now seen corresponding path program 49 times [2019-11-15 23:18:27,977 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:18:27,977 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57215808] [2019-11-15 23:18:27,977 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:18:27,977 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:18:27,977 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:18:28,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:28,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:29,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:29,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:29,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:29,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:29,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:29,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:29,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:29,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:29,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:32,882 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 110067 proven. 6366 refuted. 0 times theorem prover too weak. 363360 trivial. 0 not checked. [2019-11-15 23:18:32,882 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [57215808] [2019-11-15 23:18:32,882 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1859020372] [2019-11-15 23:18:32,882 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:18:33,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:33,782 INFO L256 TraceCheckSpWp]: Trace formula consists of 6125 conjuncts, 58 conjunts are in the unsatisfiable core [2019-11-15 23:18:33,795 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:18:38,062 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 110369 proven. 1782 refuted. 0 times theorem prover too weak. 367642 trivial. 0 not checked. [2019-11-15 23:18:38,062 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:18:38,063 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 58] total 91 [2019-11-15 23:18:38,063 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644324230] [2019-11-15 23:18:38,064 INFO L442 AbstractCegarLoop]: Interpolant automaton has 91 states [2019-11-15 23:18:38,064 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:18:38,065 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2019-11-15 23:18:38,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1694, Invalid=6496, Unknown=0, NotChecked=0, Total=8190 [2019-11-15 23:18:38,065 INFO L87 Difference]: Start difference. First operand 3265 states and 3419 transitions. Second operand 91 states. [2019-11-15 23:18:41,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:18:41,316 INFO L93 Difference]: Finished difference Result 3660 states and 3933 transitions. [2019-11-15 23:18:41,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2019-11-15 23:18:41,321 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2463 [2019-11-15 23:18:41,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:18:41,329 INFO L225 Difference]: With dead ends: 3660 [2019-11-15 23:18:41,329 INFO L226 Difference]: Without dead ends: 3654 [2019-11-15 23:18:41,331 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2635 GetRequests, 2490 SyntacticMatches, 0 SemanticMatches, 145 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5373 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=4757, Invalid=16705, Unknown=0, NotChecked=0, Total=21462 [2019-11-15 23:18:41,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3654 states. [2019-11-15 23:18:41,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3654 to 3275. [2019-11-15 23:18:41,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3275 states. [2019-11-15 23:18:41,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3275 states to 3275 states and 3429 transitions. [2019-11-15 23:18:41,363 INFO L78 Accepts]: Start accepts. Automaton has 3275 states and 3429 transitions. Word has length 2463 [2019-11-15 23:18:41,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:18:41,364 INFO L462 AbstractCegarLoop]: Abstraction has 3275 states and 3429 transitions. [2019-11-15 23:18:41,364 INFO L463 AbstractCegarLoop]: Interpolant automaton has 91 states. [2019-11-15 23:18:41,364 INFO L276 IsEmpty]: Start isEmpty. Operand 3275 states and 3429 transitions. [2019-11-15 23:18:41,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2474 [2019-11-15 23:18:41,394 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:18:41,395 INFO L380 BasicCegarLoop]: trace histogram [434, 433, 433, 433, 433, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:18:41,595 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 59 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:18:41,596 INFO L410 AbstractCegarLoop]: === Iteration 66 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:18:41,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:18:41,596 INFO L82 PathProgramCache]: Analyzing trace with hash -169898907, now seen corresponding path program 50 times [2019-11-15 23:18:41,596 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:18:41,596 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953244142] [2019-11-15 23:18:41,596 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:18:41,596 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:18:41,597 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:18:42,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:43,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:18:46,642 INFO L134 CoverageAnalysis]: Checked inductivity of 484166 backedges. 60238 proven. 2188 refuted. 0 times theorem prover too weak. 421740 trivial. 0 not checked. [2019-11-15 23:18:46,643 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [953244142] [2019-11-15 23:18:46,645 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2121852126] [2019-11-15 23:18:46,645 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:18:47,568 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-11-15 23:18:47,568 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:18:47,584 INFO L256 TraceCheckSpWp]: Trace formula consists of 6149 conjuncts, 59 conjunts are in the unsatisfiable core [2019-11-15 23:18:47,598 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:18:51,213 INFO L134 CoverageAnalysis]: Checked inductivity of 484166 backedges. 58293 proven. 1946 refuted. 0 times theorem prover too weak. 423927 trivial. 0 not checked. [2019-11-15 23:18:51,213 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:18:51,214 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 30] total 90 [2019-11-15 23:18:51,215 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052502712] [2019-11-15 23:18:51,215 INFO L442 AbstractCegarLoop]: Interpolant automaton has 91 states [2019-11-15 23:18:51,216 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:18:51,216 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2019-11-15 23:18:51,216 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=992, Invalid=7198, Unknown=0, NotChecked=0, Total=8190 [2019-11-15 23:18:51,217 INFO L87 Difference]: Start difference. First operand 3275 states and 3429 transitions. Second operand 91 states. [2019-11-15 23:19:00,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:19:00,887 INFO L93 Difference]: Finished difference Result 3829 states and 4106 transitions. [2019-11-15 23:19:00,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2019-11-15 23:19:00,888 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2473 [2019-11-15 23:19:00,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:19:00,893 INFO L225 Difference]: With dead ends: 3829 [2019-11-15 23:19:00,893 INFO L226 Difference]: Without dead ends: 3829 [2019-11-15 23:19:00,894 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2650 GetRequests, 2499 SyntacticMatches, 1 SemanticMatches, 150 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5620 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=1851, Invalid=21101, Unknown=0, NotChecked=0, Total=22952 [2019-11-15 23:19:00,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3829 states. [2019-11-15 23:19:00,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3829 to 3431. [2019-11-15 23:19:00,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3431 states. [2019-11-15 23:19:00,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3431 states to 3431 states and 3587 transitions. [2019-11-15 23:19:00,922 INFO L78 Accepts]: Start accepts. Automaton has 3431 states and 3587 transitions. Word has length 2473 [2019-11-15 23:19:00,924 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:19:00,924 INFO L462 AbstractCegarLoop]: Abstraction has 3431 states and 3587 transitions. [2019-11-15 23:19:00,924 INFO L463 AbstractCegarLoop]: Interpolant automaton has 91 states. [2019-11-15 23:19:00,924 INFO L276 IsEmpty]: Start isEmpty. Operand 3431 states and 3587 transitions. [2019-11-15 23:19:00,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2630 [2019-11-15 23:19:00,964 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:19:00,965 INFO L380 BasicCegarLoop]: trace histogram [463, 462, 462, 462, 462, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:19:01,166 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 60 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:19:01,166 INFO L410 AbstractCegarLoop]: === Iteration 67 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:19:01,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:19:01,166 INFO L82 PathProgramCache]: Analyzing trace with hash 1430424994, now seen corresponding path program 51 times [2019-11-15 23:19:01,166 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:19:01,166 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227964050] [2019-11-15 23:19:01,167 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:19:01,167 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:19:01,167 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:19:01,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:02,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:06,712 INFO L134 CoverageAnalysis]: Checked inductivity of 550585 backedges. 124499 proven. 6827 refuted. 0 times theorem prover too weak. 419259 trivial. 0 not checked. [2019-11-15 23:19:06,712 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227964050] [2019-11-15 23:19:06,712 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1759773854] [2019-11-15 23:19:06,712 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:19:09,911 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2019-11-15 23:19:09,911 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:19:09,923 INFO L256 TraceCheckSpWp]: Trace formula consists of 2984 conjuncts, 39 conjunts are in the unsatisfiable core [2019-11-15 23:19:09,937 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:19:15,029 INFO L134 CoverageAnalysis]: Checked inductivity of 550585 backedges. 118619 proven. 6093 refuted. 0 times theorem prover too weak. 425873 trivial. 0 not checked. [2019-11-15 23:19:15,030 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:19:15,031 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 38] total 101 [2019-11-15 23:19:15,031 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449535108] [2019-11-15 23:19:15,032 INFO L442 AbstractCegarLoop]: Interpolant automaton has 101 states [2019-11-15 23:19:15,032 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:19:15,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2019-11-15 23:19:15,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1831, Invalid=8269, Unknown=0, NotChecked=0, Total=10100 [2019-11-15 23:19:15,034 INFO L87 Difference]: Start difference. First operand 3431 states and 3587 transitions. Second operand 101 states. [2019-11-15 23:19:24,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:19:24,146 INFO L93 Difference]: Finished difference Result 3989 states and 4266 transitions. [2019-11-15 23:19:24,146 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 150 states. [2019-11-15 23:19:24,147 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 2629 [2019-11-15 23:19:24,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:19:24,152 INFO L225 Difference]: With dead ends: 3989 [2019-11-15 23:19:24,152 INFO L226 Difference]: Without dead ends: 3983 [2019-11-15 23:19:24,154 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2895 GetRequests, 2650 SyntacticMatches, 0 SemanticMatches, 245 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16465 ImplicationChecksByTransitivity, 9.8s TimeCoverageRelationStatistics Valid=10124, Invalid=50638, Unknown=0, NotChecked=0, Total=60762 [2019-11-15 23:19:24,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3983 states. [2019-11-15 23:19:24,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3983 to 3436. [2019-11-15 23:19:24,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3436 states. [2019-11-15 23:19:24,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3436 states to 3436 states and 3591 transitions. [2019-11-15 23:19:24,183 INFO L78 Accepts]: Start accepts. Automaton has 3436 states and 3591 transitions. Word has length 2629 [2019-11-15 23:19:24,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:19:24,184 INFO L462 AbstractCegarLoop]: Abstraction has 3436 states and 3591 transitions. [2019-11-15 23:19:24,184 INFO L463 AbstractCegarLoop]: Interpolant automaton has 101 states. [2019-11-15 23:19:24,184 INFO L276 IsEmpty]: Start isEmpty. Operand 3436 states and 3591 transitions. [2019-11-15 23:19:24,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2635 [2019-11-15 23:19:24,231 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:19:24,232 INFO L380 BasicCegarLoop]: trace histogram [464, 463, 463, 463, 463, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:19:24,435 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 61 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:19:24,435 INFO L410 AbstractCegarLoop]: === Iteration 68 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:19:24,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:19:24,435 INFO L82 PathProgramCache]: Analyzing trace with hash 2134165351, now seen corresponding path program 52 times [2019-11-15 23:19:24,435 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:19:24,435 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553937811] [2019-11-15 23:19:24,436 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:19:24,436 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:19:24,436 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:19:24,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:26,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:29,977 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 66725 proven. 2353 refuted. 0 times theorem prover too weak. 483847 trivial. 0 not checked. [2019-11-15 23:19:29,977 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553937811] [2019-11-15 23:19:29,978 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [595435631] [2019-11-15 23:19:29,978 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:19:31,728 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-11-15 23:19:31,728 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:19:31,755 INFO L256 TraceCheckSpWp]: Trace formula consists of 6542 conjuncts, 61 conjunts are in the unsatisfiable core [2019-11-15 23:19:31,770 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:19:35,775 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 64638 proven. 2088 refuted. 0 times theorem prover too weak. 486199 trivial. 0 not checked. [2019-11-15 23:19:35,775 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:19:35,776 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 31] total 93 [2019-11-15 23:19:35,777 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1216058259] [2019-11-15 23:19:35,777 INFO L442 AbstractCegarLoop]: Interpolant automaton has 94 states [2019-11-15 23:19:35,777 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:19:35,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2019-11-15 23:19:35,778 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1056, Invalid=7686, Unknown=0, NotChecked=0, Total=8742 [2019-11-15 23:19:35,778 INFO L87 Difference]: Start difference. First operand 3436 states and 3591 transitions. Second operand 94 states. [2019-11-15 23:19:45,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:19:45,183 INFO L93 Difference]: Finished difference Result 4011 states and 4291 transitions. [2019-11-15 23:19:45,183 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2019-11-15 23:19:45,183 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 2634 [2019-11-15 23:19:45,185 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:19:45,189 INFO L225 Difference]: With dead ends: 4011 [2019-11-15 23:19:45,189 INFO L226 Difference]: Without dead ends: 4011 [2019-11-15 23:19:45,190 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2817 GetRequests, 2661 SyntacticMatches, 1 SemanticMatches, 155 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6009 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=1959, Invalid=22533, Unknown=0, NotChecked=0, Total=24492 [2019-11-15 23:19:45,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4011 states. [2019-11-15 23:19:45,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4011 to 3597. [2019-11-15 23:19:45,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3597 states. [2019-11-15 23:19:45,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3597 states to 3597 states and 3754 transitions. [2019-11-15 23:19:45,219 INFO L78 Accepts]: Start accepts. Automaton has 3597 states and 3754 transitions. Word has length 2634 [2019-11-15 23:19:45,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:19:45,220 INFO L462 AbstractCegarLoop]: Abstraction has 3597 states and 3754 transitions. [2019-11-15 23:19:45,220 INFO L463 AbstractCegarLoop]: Interpolant automaton has 94 states. [2019-11-15 23:19:45,220 INFO L276 IsEmpty]: Start isEmpty. Operand 3597 states and 3754 transitions. [2019-11-15 23:19:45,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2796 [2019-11-15 23:19:45,259 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:19:45,260 INFO L380 BasicCegarLoop]: trace histogram [494, 493, 493, 493, 493, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:19:45,465 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 62 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:19:45,465 INFO L410 AbstractCegarLoop]: === Iteration 69 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:19:45,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:19:45,466 INFO L82 PathProgramCache]: Analyzing trace with hash 945686987, now seen corresponding path program 53 times [2019-11-15 23:19:45,466 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:19:45,466 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330419615] [2019-11-15 23:19:45,466 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:19:45,466 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:19:45,466 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:19:45,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:46,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:19:51,443 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 137762 proven. 7304 refuted. 0 times theorem prover too weak. 481189 trivial. 0 not checked. [2019-11-15 23:19:51,444 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [330419615] [2019-11-15 23:19:51,444 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [752383219] [2019-11-15 23:19:51,444 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:20:26,873 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 77 check-sat command(s) [2019-11-15 23:20:26,873 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:20:26,923 INFO L256 TraceCheckSpWp]: Trace formula consists of 6875 conjuncts, 66 conjunts are in the unsatisfiable core [2019-11-15 23:20:26,942 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:20:32,305 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 137762 proven. 7304 refuted. 0 times theorem prover too weak. 481189 trivial. 0 not checked. [2019-11-15 23:20:32,306 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:20:32,307 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 66] total 100 [2019-11-15 23:20:32,307 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1454064559] [2019-11-15 23:20:32,308 INFO L442 AbstractCegarLoop]: Interpolant automaton has 100 states [2019-11-15 23:20:32,308 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:20:32,308 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2019-11-15 23:20:32,308 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1979, Invalid=7921, Unknown=0, NotChecked=0, Total=9900 [2019-11-15 23:20:32,309 INFO L87 Difference]: Start difference. First operand 3597 states and 3754 transitions. Second operand 100 states. [2019-11-15 23:20:36,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:20:36,467 INFO L93 Difference]: Finished difference Result 4019 states and 4297 transitions. [2019-11-15 23:20:36,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2019-11-15 23:20:36,467 INFO L78 Accepts]: Start accepts. Automaton has 100 states. Word has length 2795 [2019-11-15 23:20:36,469 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:20:36,473 INFO L225 Difference]: With dead ends: 4019 [2019-11-15 23:20:36,473 INFO L226 Difference]: Without dead ends: 4013 [2019-11-15 23:20:36,474 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2979 GetRequests, 2821 SyntacticMatches, 0 SemanticMatches, 158 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6481 ImplicationChecksByTransitivity, 5.1s TimeCoverageRelationStatistics Valid=5647, Invalid=19793, Unknown=0, NotChecked=0, Total=25440 [2019-11-15 23:20:36,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4013 states. [2019-11-15 23:20:36,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4013 to 3602. [2019-11-15 23:20:36,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3602 states. [2019-11-15 23:20:36,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3602 states to 3602 states and 3758 transitions. [2019-11-15 23:20:36,505 INFO L78 Accepts]: Start accepts. Automaton has 3602 states and 3758 transitions. Word has length 2795 [2019-11-15 23:20:36,506 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:20:36,506 INFO L462 AbstractCegarLoop]: Abstraction has 3602 states and 3758 transitions. [2019-11-15 23:20:36,506 INFO L463 AbstractCegarLoop]: Interpolant automaton has 100 states. [2019-11-15 23:20:36,506 INFO L276 IsEmpty]: Start isEmpty. Operand 3602 states and 3758 transitions. [2019-11-15 23:20:36,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2801 [2019-11-15 23:20:36,544 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:20:36,545 INFO L380 BasicCegarLoop]: trace histogram [495, 494, 494, 494, 494, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:20:36,746 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 63 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:20:36,747 INFO L410 AbstractCegarLoop]: === Iteration 70 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:20:36,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:20:36,747 INFO L82 PathProgramCache]: Analyzing trace with hash 601825130, now seen corresponding path program 54 times [2019-11-15 23:20:36,747 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:20:36,747 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175130454] [2019-11-15 23:20:36,747 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:20:36,747 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:20:36,747 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:20:37,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:38,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:39,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:39,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:39,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:39,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:39,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:39,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:39,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:39,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:39,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:39,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:39,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:20:42,862 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 73661 proven. 2524 refuted. 0 times theorem prover too weak. 552566 trivial. 0 not checked. [2019-11-15 23:20:42,862 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175130454] [2019-11-15 23:20:42,862 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1163953548] [2019-11-15 23:20:42,862 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:20:55,751 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 61 check-sat command(s) [2019-11-15 23:20:55,751 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:20:55,772 INFO L256 TraceCheckSpWp]: Trace formula consists of 4895 conjuncts, 34 conjunts are in the unsatisfiable core [2019-11-15 23:20:55,787 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:21:00,340 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 71427 proven. 2235 refuted. 0 times theorem prover too weak. 555089 trivial. 0 not checked. [2019-11-15 23:21:00,340 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:21:00,341 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 33] total 98 [2019-11-15 23:21:00,341 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1257606722] [2019-11-15 23:21:00,342 INFO L442 AbstractCegarLoop]: Interpolant automaton has 99 states [2019-11-15 23:21:00,342 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:21:00,342 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2019-11-15 23:21:00,343 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1563, Invalid=8139, Unknown=0, NotChecked=0, Total=9702 [2019-11-15 23:21:00,343 INFO L87 Difference]: Start difference. First operand 3602 states and 3758 transitions. Second operand 99 states. [2019-11-15 23:21:07,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:21:07,540 INFO L93 Difference]: Finished difference Result 4206 states and 4490 transitions. [2019-11-15 23:21:07,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2019-11-15 23:21:07,540 INFO L78 Accepts]: Start accepts. Automaton has 99 states. Word has length 2800 [2019-11-15 23:21:07,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:21:07,545 INFO L225 Difference]: With dead ends: 4206 [2019-11-15 23:21:07,545 INFO L226 Difference]: Without dead ends: 4206 [2019-11-15 23:21:07,546 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2989 GetRequests, 2827 SyntacticMatches, 0 SemanticMatches, 162 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6563 ImplicationChecksByTransitivity, 6.0s TimeCoverageRelationStatistics Valid=4370, Invalid=22362, Unknown=0, NotChecked=0, Total=26732 [2019-11-15 23:21:07,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4206 states. [2019-11-15 23:21:07,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4206 to 3768. [2019-11-15 23:21:07,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3768 states. [2019-11-15 23:21:07,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3768 states to 3768 states and 3926 transitions. [2019-11-15 23:21:07,587 INFO L78 Accepts]: Start accepts. Automaton has 3768 states and 3926 transitions. Word has length 2800 [2019-11-15 23:21:07,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:21:07,588 INFO L462 AbstractCegarLoop]: Abstraction has 3768 states and 3926 transitions. [2019-11-15 23:21:07,588 INFO L463 AbstractCegarLoop]: Interpolant automaton has 99 states. [2019-11-15 23:21:07,588 INFO L276 IsEmpty]: Start isEmpty. Operand 3768 states and 3926 transitions. [2019-11-15 23:21:07,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2967 [2019-11-15 23:21:07,629 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:21:07,629 INFO L380 BasicCegarLoop]: trace histogram [526, 525, 525, 525, 525, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:21:07,829 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 64 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:21:07,830 INFO L410 AbstractCegarLoop]: === Iteration 71 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:21:07,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:21:07,830 INFO L82 PathProgramCache]: Analyzing trace with hash -643366969, now seen corresponding path program 55 times [2019-11-15 23:21:07,830 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:21:07,830 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477098176] [2019-11-15 23:21:07,830 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:21:07,830 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:21:07,830 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:21:08,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:08,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:09,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:14,451 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 151933 proven. 7797 refuted. 0 times theorem prover too weak. 549725 trivial. 0 not checked. [2019-11-15 23:21:14,451 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477098176] [2019-11-15 23:21:14,451 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [545087373] [2019-11-15 23:21:14,452 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:21:15,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:15,599 INFO L256 TraceCheckSpWp]: Trace formula consists of 7352 conjuncts, 64 conjunts are in the unsatisfiable core [2019-11-15 23:21:15,613 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:21:21,570 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 152268 proven. 2205 refuted. 0 times theorem prover too weak. 554982 trivial. 0 not checked. [2019-11-15 23:21:21,571 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:21:21,572 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 64] total 100 [2019-11-15 23:21:21,572 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246020730] [2019-11-15 23:21:21,573 INFO L442 AbstractCegarLoop]: Interpolant automaton has 100 states [2019-11-15 23:21:21,573 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:21:21,574 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2019-11-15 23:21:21,574 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2060, Invalid=7840, Unknown=0, NotChecked=0, Total=9900 [2019-11-15 23:21:21,574 INFO L87 Difference]: Start difference. First operand 3768 states and 3926 transitions. Second operand 100 states. [2019-11-15 23:21:25,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:21:25,904 INFO L93 Difference]: Finished difference Result 4218 states and 4500 transitions. [2019-11-15 23:21:25,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2019-11-15 23:21:25,904 INFO L78 Accepts]: Start accepts. Automaton has 100 states. Word has length 2966 [2019-11-15 23:21:25,905 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:21:25,910 INFO L225 Difference]: With dead ends: 4218 [2019-11-15 23:21:25,910 INFO L226 Difference]: Without dead ends: 4212 [2019-11-15 23:21:25,911 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3156 GetRequests, 2996 SyntacticMatches, 0 SemanticMatches, 160 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6600 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=5777, Invalid=20305, Unknown=0, NotChecked=0, Total=26082 [2019-11-15 23:21:25,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4212 states. [2019-11-15 23:21:25,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4212 to 3773. [2019-11-15 23:21:25,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3773 states. [2019-11-15 23:21:25,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3773 states to 3773 states and 3930 transitions. [2019-11-15 23:21:25,958 INFO L78 Accepts]: Start accepts. Automaton has 3773 states and 3930 transitions. Word has length 2966 [2019-11-15 23:21:25,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:21:25,960 INFO L462 AbstractCegarLoop]: Abstraction has 3773 states and 3930 transitions. [2019-11-15 23:21:25,960 INFO L463 AbstractCegarLoop]: Interpolant automaton has 100 states. [2019-11-15 23:21:25,961 INFO L276 IsEmpty]: Start isEmpty. Operand 3773 states and 3930 transitions. [2019-11-15 23:21:26,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2972 [2019-11-15 23:21:26,008 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:21:26,008 INFO L380 BasicCegarLoop]: trace histogram [527, 526, 526, 526, 526, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:21:26,208 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 65 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:21:26,209 INFO L410 AbstractCegarLoop]: === Iteration 72 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:21:26,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:21:26,209 INFO L82 PathProgramCache]: Analyzing trace with hash 428252130, now seen corresponding path program 56 times [2019-11-15 23:21:26,209 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:21:26,209 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757083831] [2019-11-15 23:21:26,210 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:21:26,210 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:21:26,210 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:21:26,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:28,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:33,006 INFO L134 CoverageAnalysis]: Checked inductivity of 712112 backedges. 81061 proven. 2701 refuted. 0 times theorem prover too weak. 628350 trivial. 0 not checked. [2019-11-15 23:21:33,006 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757083831] [2019-11-15 23:21:33,006 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [987677291] [2019-11-15 23:21:33,006 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:21:34,111 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-11-15 23:21:34,112 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:21:34,131 INFO L256 TraceCheckSpWp]: Trace formula consists of 7364 conjuncts, 65 conjunts are in the unsatisfiable core [2019-11-15 23:21:34,144 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:21:39,104 INFO L134 CoverageAnalysis]: Checked inductivity of 712112 backedges. 78675 proven. 2387 refuted. 0 times theorem prover too weak. 631050 trivial. 0 not checked. [2019-11-15 23:21:39,105 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:21:39,106 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 33] total 99 [2019-11-15 23:21:39,106 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707444682] [2019-11-15 23:21:39,107 INFO L442 AbstractCegarLoop]: Interpolant automaton has 100 states [2019-11-15 23:21:39,107 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:21:39,107 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2019-11-15 23:21:39,107 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1190, Invalid=8710, Unknown=0, NotChecked=0, Total=9900 [2019-11-15 23:21:39,107 INFO L87 Difference]: Start difference. First operand 3773 states and 3930 transitions. Second operand 100 states. [2019-11-15 23:21:50,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:21:50,726 INFO L93 Difference]: Finished difference Result 4414 states and 4703 transitions. [2019-11-15 23:21:50,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2019-11-15 23:21:50,727 INFO L78 Accepts]: Start accepts. Automaton has 100 states. Word has length 2971 [2019-11-15 23:21:50,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:21:50,733 INFO L225 Difference]: With dead ends: 4414 [2019-11-15 23:21:50,733 INFO L226 Difference]: Without dead ends: 4414 [2019-11-15 23:21:50,734 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3166 GetRequests, 3000 SyntacticMatches, 1 SemanticMatches, 165 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6826 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=2184, Invalid=25538, Unknown=0, NotChecked=0, Total=27722 [2019-11-15 23:21:50,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4414 states. [2019-11-15 23:21:50,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4414 to 3944. [2019-11-15 23:21:50,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3944 states. [2019-11-15 23:21:50,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3944 states to 3944 states and 4103 transitions. [2019-11-15 23:21:50,765 INFO L78 Accepts]: Start accepts. Automaton has 3944 states and 4103 transitions. Word has length 2971 [2019-11-15 23:21:50,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:21:50,766 INFO L462 AbstractCegarLoop]: Abstraction has 3944 states and 4103 transitions. [2019-11-15 23:21:50,766 INFO L463 AbstractCegarLoop]: Interpolant automaton has 100 states. [2019-11-15 23:21:50,767 INFO L276 IsEmpty]: Start isEmpty. Operand 3944 states and 4103 transitions. [2019-11-15 23:21:50,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3143 [2019-11-15 23:21:50,812 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:21:50,813 INFO L380 BasicCegarLoop]: trace histogram [559, 558, 558, 558, 558, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:21:51,013 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 66 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:21:51,013 INFO L410 AbstractCegarLoop]: === Iteration 73 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:21:51,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:21:51,014 INFO L82 PathProgramCache]: Analyzing trace with hash -1867759088, now seen corresponding path program 57 times [2019-11-15 23:21:51,014 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:21:51,014 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074309285] [2019-11-15 23:21:51,014 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:21:51,014 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:21:51,014 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:21:51,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:52,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:21:58,305 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 167042 proven. 8306 refuted. 0 times theorem prover too weak. 625320 trivial. 0 not checked. [2019-11-15 23:21:58,305 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074309285] [2019-11-15 23:21:58,306 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1791502544] [2019-11-15 23:21:58,306 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:22:03,211 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2019-11-15 23:22:03,211 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-11-15 23:22:03,225 INFO L256 TraceCheckSpWp]: Trace formula consists of 3488 conjuncts, 42 conjunts are in the unsatisfiable core [2019-11-15 23:22:03,236 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:22:10,000 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 159788 proven. 7443 refuted. 0 times theorem prover too weak. 633437 trivial. 0 not checked. [2019-11-15 23:22:10,001 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:22:10,002 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [71, 41] total 110 [2019-11-15 23:22:10,002 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [30461803] [2019-11-15 23:22:10,003 INFO L442 AbstractCegarLoop]: Interpolant automaton has 110 states [2019-11-15 23:22:10,003 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:22:10,003 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 110 interpolants. [2019-11-15 23:22:10,004 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2209, Invalid=9781, Unknown=0, NotChecked=0, Total=11990 [2019-11-15 23:22:10,004 INFO L87 Difference]: Start difference. First operand 3944 states and 4103 transitions. Second operand 110 states. [2019-11-15 23:22:20,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:22:20,151 INFO L93 Difference]: Finished difference Result 5111 states and 5415 transitions. [2019-11-15 23:22:20,151 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 168 states. [2019-11-15 23:22:20,151 INFO L78 Accepts]: Start accepts. Automaton has 110 states. Word has length 3142 [2019-11-15 23:22:20,152 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:22:20,158 INFO L225 Difference]: With dead ends: 5111 [2019-11-15 23:22:20,158 INFO L226 Difference]: Without dead ends: 5105 [2019-11-15 23:22:20,161 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3435 GetRequests, 3166 SyntacticMatches, 0 SemanticMatches, 269 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19945 ImplicationChecksByTransitivity, 11.4s TimeCoverageRelationStatistics Valid=12173, Invalid=60997, Unknown=0, NotChecked=0, Total=73170 [2019-11-15 23:22:20,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5105 states. [2019-11-15 23:22:20,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5105 to 3949. [2019-11-15 23:22:20,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3949 states. [2019-11-15 23:22:20,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3949 states to 3949 states and 4107 transitions. [2019-11-15 23:22:20,194 INFO L78 Accepts]: Start accepts. Automaton has 3949 states and 4107 transitions. Word has length 3142 [2019-11-15 23:22:20,195 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:22:20,195 INFO L462 AbstractCegarLoop]: Abstraction has 3949 states and 4107 transitions. [2019-11-15 23:22:20,195 INFO L463 AbstractCegarLoop]: Interpolant automaton has 110 states. [2019-11-15 23:22:20,195 INFO L276 IsEmpty]: Start isEmpty. Operand 3949 states and 4107 transitions. [2019-11-15 23:22:20,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3148 [2019-11-15 23:22:20,242 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:22:20,243 INFO L380 BasicCegarLoop]: trace histogram [560, 559, 559, 559, 559, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:22:20,455 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 67 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:22:20,455 INFO L410 AbstractCegarLoop]: === Iteration 74 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK]=== [2019-11-15 23:22:20,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:22:20,456 INFO L82 PathProgramCache]: Analyzing trace with hash -486718779, now seen corresponding path program 58 times [2019-11-15 23:22:20,456 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:22:20,456 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990953872] [2019-11-15 23:22:20,456 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:22:20,456 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:22:20,456 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:22:24,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 23:22:27,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 23:22:28,426 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 23:22:28,426 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-11-15 23:22:28,924 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 15.11 11:22:28 BoogieIcfgContainer [2019-11-15 23:22:28,924 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-15 23:22:28,925 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-15 23:22:28,925 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-15 23:22:28,926 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-15 23:22:28,926 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 11:09:50" (3/4) ... [2019-11-15 23:22:28,928 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-15 23:22:29,564 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_927ce87f-e2ef-48e1-be75-9dcf227835cd/bin/uautomizer/witness.graphml [2019-11-15 23:22:29,564 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-15 23:22:29,566 INFO L168 Benchmark]: Toolchain (without parser) took 759291.12 ms. Allocated memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: 4.0 GB). Free memory was 944.7 MB in the beginning and 3.0 GB in the end (delta: -2.1 GB). Peak memory consumption was 1.9 GB. Max. memory is 11.5 GB. [2019-11-15 23:22:29,566 INFO L168 Benchmark]: CDTParser took 0.23 ms. Allocated memory is still 1.0 GB. Free memory is still 962.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-15 23:22:29,566 INFO L168 Benchmark]: CACSL2BoogieTranslator took 295.29 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 143.7 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -189.9 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. [2019-11-15 23:22:29,567 INFO L168 Benchmark]: Boogie Preprocessor took 32.88 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-15 23:22:29,567 INFO L168 Benchmark]: RCFGBuilder took 325.27 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 23.8 MB). Peak memory consumption was 23.8 MB. Max. memory is 11.5 GB. [2019-11-15 23:22:29,568 INFO L168 Benchmark]: TraceAbstraction took 757992.03 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 3.1 GB in the end (delta: -2.0 GB). Peak memory consumption was 1.9 GB. Max. memory is 11.5 GB. [2019-11-15 23:22:29,568 INFO L168 Benchmark]: Witness Printer took 639.28 ms. Allocated memory is still 5.0 GB. Free memory was 3.1 GB in the beginning and 3.0 GB in the end (delta: 109.4 MB). Peak memory consumption was 109.4 MB. Max. memory is 11.5 GB. [2019-11-15 23:22:29,570 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23 ms. Allocated memory is still 1.0 GB. Free memory is still 962.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 295.29 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 143.7 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -189.9 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 32.88 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 325.27 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 23.8 MB). Peak memory consumption was 23.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 757992.03 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 3.1 GB in the end (delta: -2.0 GB). Peak memory consumption was 1.9 GB. Max. memory is 11.5 GB. * Witness Printer took 639.28 ms. Allocated memory is still 5.0 GB. Free memory was 3.1 GB in the beginning and 3.0 GB in the end (delta: 109.4 MB). Peak memory consumption was 109.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: array index can be out of bounds array index can be out of bounds We found a FailurePath: [L24] int i, b[32]; [L25] char mask[32]; [L26] i = 0 VAL [b={-1:0}, i=0, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=0, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=1, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={1:0}, b={1:0}, i=0, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={1:0}, b={1:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={1:0}, b={1:0}, i=0, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={1:0}, b={1:0}, b[i]=136, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={1:0}, b={1:0}, i=1, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={1:0}, b={1:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={1:0}, b={1:0}, i=1, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={1:0}, b={1:0}, b[i]=141, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={1:0}, b={1:0}, i=2, size=1] [L17] COND FALSE !(i <= size) VAL [\old(size)=1, b={1:0}, b={1:0}, i=2, size=1] [L20] return i; VAL [\old(size)=1, \result=2, b={1:0}, b={1:0}, i=2, size=1] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=2, i=0, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=2, i=0, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=1, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=1, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=2, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={1:0}, b={1:0}, i=0, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={1:0}, b={1:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={1:0}, b={1:0}, i=0, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={1:0}, b={1:0}, b[i]=136, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={1:0}, b={1:0}, i=1, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={1:0}, b={1:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={1:0}, b={1:0}, i=1, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={1:0}, b={1:0}, b[i]=141, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={1:0}, b={1:0}, i=2, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={1:0}, b={1:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={1:0}, b={1:0}, i=2, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={1:0}, b={1:0}, b[i]=157, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={1:0}, b={1:0}, i=3, size=2] [L17] COND FALSE !(i <= size) VAL [\old(size)=2, b={1:0}, b={1:0}, i=3, size=2] [L20] return i; VAL [\old(size)=2, \result=3, b={1:0}, b={1:0}, i=3, size=2] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=3, i=1, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=3, i=1, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=2, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=2, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=3, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={1:0}, b={1:0}, i=0, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={1:0}, b={1:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={1:0}, b={1:0}, i=0, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={1:0}, b={1:0}, b[i]=136, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={1:0}, b={1:0}, i=1, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={1:0}, b={1:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={1:0}, b={1:0}, i=1, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={1:0}, b={1:0}, b[i]=141, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={1:0}, b={1:0}, i=2, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={1:0}, b={1:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={1:0}, b={1:0}, i=2, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={1:0}, b={1:0}, b[i]=157, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={1:0}, b={1:0}, i=3, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={1:0}, b={1:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={1:0}, b={1:0}, i=3, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={1:0}, b={1:0}, b[i]=160, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={1:0}, b={1:0}, i=4, size=3] [L17] COND FALSE !(i <= size) VAL [\old(size)=3, b={1:0}, b={1:0}, i=4, size=3] [L20] return i; VAL [\old(size)=3, \result=4, b={1:0}, b={1:0}, i=4, size=3] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=4, i=2, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=4, i=2, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=3, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=3, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=4, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={1:0}, b={1:0}, i=0, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={1:0}, b={1:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={1:0}, b={1:0}, i=0, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={1:0}, b={1:0}, b[i]=136, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={1:0}, b={1:0}, i=1, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={1:0}, b={1:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={1:0}, b={1:0}, i=1, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={1:0}, b={1:0}, b[i]=141, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={1:0}, b={1:0}, i=2, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={1:0}, b={1:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={1:0}, b={1:0}, i=2, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={1:0}, b={1:0}, b[i]=157, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={1:0}, b={1:0}, i=3, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={1:0}, b={1:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={1:0}, b={1:0}, i=3, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={1:0}, b={1:0}, b[i]=160, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={1:0}, b={1:0}, i=4, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={1:0}, b={1:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={1:0}, b={1:0}, i=4, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={1:0}, b={1:0}, b[i]=142, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={1:0}, b={1:0}, i=5, size=4] [L17] COND FALSE !(i <= size) VAL [\old(size)=4, b={1:0}, b={1:0}, i=5, size=4] [L20] return i; VAL [\old(size)=4, \result=5, b={1:0}, b={1:0}, i=5, size=4] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=5, i=3, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=5, i=3, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=4, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=4, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=5, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={1:0}, b={1:0}, i=0, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={1:0}, b={1:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={1:0}, b={1:0}, i=0, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={1:0}, b={1:0}, b[i]=136, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={1:0}, b={1:0}, i=1, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={1:0}, b={1:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={1:0}, b={1:0}, i=1, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={1:0}, b={1:0}, b[i]=141, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={1:0}, b={1:0}, i=2, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={1:0}, b={1:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={1:0}, b={1:0}, i=2, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={1:0}, b={1:0}, b[i]=157, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={1:0}, b={1:0}, i=3, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={1:0}, b={1:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={1:0}, b={1:0}, i=3, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={1:0}, b={1:0}, b[i]=160, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={1:0}, b={1:0}, i=4, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={1:0}, b={1:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={1:0}, b={1:0}, i=4, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={1:0}, b={1:0}, b[i]=142, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={1:0}, b={1:0}, i=5, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={1:0}, b={1:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={1:0}, b={1:0}, i=5, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={1:0}, b={1:0}, b[i]=138, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={1:0}, b={1:0}, i=6, size=5] [L17] COND FALSE !(i <= size) VAL [\old(size)=5, b={1:0}, b={1:0}, i=6, size=5] [L20] return i; VAL [\old(size)=5, \result=6, b={1:0}, b={1:0}, i=6, size=5] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=6, i=4, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=6, i=4, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=5, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=5, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=6, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={1:0}, b={1:0}, i=0, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={1:0}, b={1:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={1:0}, b={1:0}, i=0, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={1:0}, b={1:0}, b[i]=136, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={1:0}, b={1:0}, i=1, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={1:0}, b={1:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={1:0}, b={1:0}, i=1, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={1:0}, b={1:0}, b[i]=141, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={1:0}, b={1:0}, i=2, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={1:0}, b={1:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={1:0}, b={1:0}, i=2, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={1:0}, b={1:0}, b[i]=157, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={1:0}, b={1:0}, i=3, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={1:0}, b={1:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={1:0}, b={1:0}, i=3, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={1:0}, b={1:0}, b[i]=160, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={1:0}, b={1:0}, i=4, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={1:0}, b={1:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={1:0}, b={1:0}, i=4, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={1:0}, b={1:0}, b[i]=142, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={1:0}, b={1:0}, i=5, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={1:0}, b={1:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={1:0}, b={1:0}, i=5, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={1:0}, b={1:0}, b[i]=138, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={1:0}, b={1:0}, i=6, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={1:0}, b={1:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={1:0}, b={1:0}, i=6, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={1:0}, b={1:0}, b[i]=146, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={1:0}, b={1:0}, i=7, size=6] [L17] COND FALSE !(i <= size) VAL [\old(size)=6, b={1:0}, b={1:0}, i=7, size=6] [L20] return i; VAL [\old(size)=6, \result=7, b={1:0}, b={1:0}, i=7, size=6] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=7, i=5, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=7, i=5, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=6, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=6, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=7, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={1:0}, b={1:0}, i=0, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={1:0}, b={1:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={1:0}, b={1:0}, i=0, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={1:0}, b={1:0}, b[i]=136, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={1:0}, b={1:0}, i=1, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={1:0}, b={1:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={1:0}, b={1:0}, i=1, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={1:0}, b={1:0}, b[i]=141, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={1:0}, b={1:0}, i=2, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={1:0}, b={1:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={1:0}, b={1:0}, i=2, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={1:0}, b={1:0}, b[i]=157, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={1:0}, b={1:0}, i=3, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={1:0}, b={1:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={1:0}, b={1:0}, i=3, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={1:0}, b={1:0}, b[i]=160, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={1:0}, b={1:0}, i=4, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={1:0}, b={1:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={1:0}, b={1:0}, i=4, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={1:0}, b={1:0}, b[i]=142, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={1:0}, b={1:0}, i=5, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={1:0}, b={1:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={1:0}, b={1:0}, i=5, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={1:0}, b={1:0}, b[i]=138, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={1:0}, b={1:0}, i=6, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={1:0}, b={1:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={1:0}, b={1:0}, i=6, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={1:0}, b={1:0}, b[i]=146, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={1:0}, b={1:0}, i=7, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={1:0}, b={1:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={1:0}, b={1:0}, i=7, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={1:0}, b={1:0}, b[i]=145, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={1:0}, b={1:0}, i=8, size=7] [L17] COND FALSE !(i <= size) VAL [\old(size)=7, b={1:0}, b={1:0}, i=8, size=7] [L20] return i; VAL [\old(size)=7, \result=8, b={1:0}, b={1:0}, i=8, size=7] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=8, i=6, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=8, i=6, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=7, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=7, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=8, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={1:0}, b={1:0}, i=0, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={1:0}, b={1:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={1:0}, b={1:0}, i=0, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={1:0}, b={1:0}, b[i]=136, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={1:0}, b={1:0}, i=1, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={1:0}, b={1:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={1:0}, b={1:0}, i=1, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={1:0}, b={1:0}, b[i]=141, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={1:0}, b={1:0}, i=2, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={1:0}, b={1:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={1:0}, b={1:0}, i=2, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={1:0}, b={1:0}, b[i]=157, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={1:0}, b={1:0}, i=3, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={1:0}, b={1:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={1:0}, b={1:0}, i=3, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={1:0}, b={1:0}, b[i]=160, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={1:0}, b={1:0}, i=4, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={1:0}, b={1:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={1:0}, b={1:0}, i=4, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={1:0}, b={1:0}, b[i]=142, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={1:0}, b={1:0}, i=5, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={1:0}, b={1:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={1:0}, b={1:0}, i=5, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={1:0}, b={1:0}, b[i]=138, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={1:0}, b={1:0}, i=6, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={1:0}, b={1:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={1:0}, b={1:0}, i=6, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={1:0}, b={1:0}, b[i]=146, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={1:0}, b={1:0}, i=7, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={1:0}, b={1:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={1:0}, b={1:0}, i=7, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={1:0}, b={1:0}, b[i]=145, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={1:0}, b={1:0}, i=8, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={1:0}, b={1:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={1:0}, b={1:0}, i=8, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={1:0}, b={1:0}, b[i]=140, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={1:0}, b={1:0}, i=9, size=8] [L17] COND FALSE !(i <= size) VAL [\old(size)=8, b={1:0}, b={1:0}, i=9, size=8] [L20] return i; VAL [\old(size)=8, \result=9, b={1:0}, b={1:0}, i=9, size=8] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=9, i=7, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=9, i=7, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=8, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=8, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=9, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={1:0}, b={1:0}, i=0, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={1:0}, b={1:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={1:0}, b={1:0}, i=0, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={1:0}, b={1:0}, b[i]=136, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={1:0}, b={1:0}, i=1, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={1:0}, b={1:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={1:0}, b={1:0}, i=1, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={1:0}, b={1:0}, b[i]=141, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={1:0}, b={1:0}, i=2, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={1:0}, b={1:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={1:0}, b={1:0}, i=2, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={1:0}, b={1:0}, b[i]=157, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={1:0}, b={1:0}, i=3, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={1:0}, b={1:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={1:0}, b={1:0}, i=3, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={1:0}, b={1:0}, b[i]=160, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={1:0}, b={1:0}, i=4, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={1:0}, b={1:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={1:0}, b={1:0}, i=4, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={1:0}, b={1:0}, b[i]=142, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={1:0}, b={1:0}, i=5, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={1:0}, b={1:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={1:0}, b={1:0}, i=5, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={1:0}, b={1:0}, b[i]=138, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={1:0}, b={1:0}, i=6, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={1:0}, b={1:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={1:0}, b={1:0}, i=6, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={1:0}, b={1:0}, b[i]=146, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={1:0}, b={1:0}, i=7, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={1:0}, b={1:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={1:0}, b={1:0}, i=7, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={1:0}, b={1:0}, b[i]=145, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={1:0}, b={1:0}, i=8, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={1:0}, b={1:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={1:0}, b={1:0}, i=8, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={1:0}, b={1:0}, b[i]=140, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={1:0}, b={1:0}, i=9, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={1:0}, b={1:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={1:0}, b={1:0}, i=9, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={1:0}, b={1:0}, b[i]=134, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={1:0}, b={1:0}, i=10, size=9] [L17] COND FALSE !(i <= size) VAL [\old(size)=9, b={1:0}, b={1:0}, i=10, size=9] [L20] return i; VAL [\old(size)=9, \result=10, b={1:0}, b={1:0}, i=10, size=9] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=10, i=8, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=10, i=8, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=9, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=9, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=10, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={1:0}, b={1:0}, i=0, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={1:0}, b={1:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={1:0}, b={1:0}, i=0, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={1:0}, b={1:0}, b[i]=136, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={1:0}, b={1:0}, i=1, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={1:0}, b={1:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={1:0}, b={1:0}, i=1, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={1:0}, b={1:0}, b[i]=141, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={1:0}, b={1:0}, i=2, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={1:0}, b={1:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={1:0}, b={1:0}, i=2, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={1:0}, b={1:0}, b[i]=157, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={1:0}, b={1:0}, i=3, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={1:0}, b={1:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={1:0}, b={1:0}, i=3, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={1:0}, b={1:0}, b[i]=160, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={1:0}, b={1:0}, i=4, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={1:0}, b={1:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={1:0}, b={1:0}, i=4, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={1:0}, b={1:0}, b[i]=142, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={1:0}, b={1:0}, i=5, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={1:0}, b={1:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={1:0}, b={1:0}, i=5, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={1:0}, b={1:0}, b[i]=138, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={1:0}, b={1:0}, i=6, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={1:0}, b={1:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={1:0}, b={1:0}, i=6, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={1:0}, b={1:0}, b[i]=146, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={1:0}, b={1:0}, i=7, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={1:0}, b={1:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={1:0}, b={1:0}, i=7, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={1:0}, b={1:0}, b[i]=145, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={1:0}, b={1:0}, i=8, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={1:0}, b={1:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={1:0}, b={1:0}, i=8, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={1:0}, b={1:0}, b[i]=140, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={1:0}, b={1:0}, i=9, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={1:0}, b={1:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={1:0}, b={1:0}, i=9, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={1:0}, b={1:0}, b[i]=134, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={1:0}, b={1:0}, i=10, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={1:0}, b={1:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={1:0}, b={1:0}, i=10, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={1:0}, b={1:0}, b[i]=132, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={1:0}, b={1:0}, i=11, size=10] [L17] COND FALSE !(i <= size) VAL [\old(size)=10, b={1:0}, b={1:0}, i=11, size=10] [L20] return i; VAL [\old(size)=10, \result=11, b={1:0}, b={1:0}, i=11, size=10] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=11, i=9, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=11, i=9, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=10, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=10, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=11, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={1:0}, b={1:0}, i=0, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=0, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=136, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=1, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=1, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=141, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=2, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=2, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=157, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=3, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=3, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=160, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=4, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=4, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=142, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=5, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=5, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=138, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=6, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=6, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=146, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=7, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=7, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=145, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=8, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=8, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=140, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=9, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=9, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=134, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=10, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=10, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=132, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=11, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={1:0}, b={1:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={1:0}, b={1:0}, i=11, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={1:0}, b={1:0}, b[i]=135, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={1:0}, b={1:0}, i=12, size=11] [L17] COND FALSE !(i <= size) VAL [\old(size)=11, b={1:0}, b={1:0}, i=12, size=11] [L20] return i; VAL [\old(size)=11, \result=12, b={1:0}, b={1:0}, i=12, size=11] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=12, i=10, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=12, i=10, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=11, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=11, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=12, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={1:0}, b={1:0}, i=0, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=0, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=136, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=1, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=1, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=141, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=2, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=2, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=157, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=3, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=3, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=160, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=4, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=4, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=142, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=5, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=5, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=138, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=6, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=6, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=146, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=7, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=7, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=145, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=8, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=8, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=140, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=9, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=9, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=134, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=10, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=10, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=132, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=11, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=11, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=135, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=12, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={1:0}, b={1:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={1:0}, b={1:0}, i=12, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={1:0}, b={1:0}, b[i]=130, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={1:0}, b={1:0}, i=13, size=12] [L17] COND FALSE !(i <= size) VAL [\old(size)=12, b={1:0}, b={1:0}, i=13, size=12] [L20] return i; VAL [\old(size)=12, \result=13, b={1:0}, b={1:0}, i=13, size=12] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=13, i=11, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=13, i=11, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=12, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=12, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=13, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={1:0}, b={1:0}, i=0, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=0, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=136, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=1, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=1, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=141, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=2, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=2, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=157, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=3, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=3, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=160, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=4, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=4, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=142, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=5, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=5, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=138, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=6, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=6, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=146, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=7, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=7, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=145, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=8, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=8, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=140, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=9, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=9, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=134, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=10, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=10, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=132, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=11, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=11, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=135, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=12, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=12, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=130, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=13, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={1:0}, b={1:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={1:0}, b={1:0}, i=13, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={1:0}, b={1:0}, b[i]=149, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={1:0}, b={1:0}, i=14, size=13] [L17] COND FALSE !(i <= size) VAL [\old(size)=13, b={1:0}, b={1:0}, i=14, size=13] [L20] return i; VAL [\old(size)=13, \result=14, b={1:0}, b={1:0}, i=14, size=13] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=14, i=12, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=14, i=12, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=13, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=13, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=14, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={1:0}, b={1:0}, i=0, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=0, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=136, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=1, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=1, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=141, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=2, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=2, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=157, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=3, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=3, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=160, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=4, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=4, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=142, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=5, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=5, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=138, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=6, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=6, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=146, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=7, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=7, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=145, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=8, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=8, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=140, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=9, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=9, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=134, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=10, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=10, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=132, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=11, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=11, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=135, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=12, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=12, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=130, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=13, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=13, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=149, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=14, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={1:0}, b={1:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={1:0}, b={1:0}, i=14, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={1:0}, b={1:0}, b[i]=161, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={1:0}, b={1:0}, i=15, size=14] [L17] COND FALSE !(i <= size) VAL [\old(size)=14, b={1:0}, b={1:0}, i=15, size=14] [L20] return i; VAL [\old(size)=14, \result=15, b={1:0}, b={1:0}, i=15, size=14] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=15, i=13, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=15, i=13, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=14, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=14, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=15, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={1:0}, b={1:0}, i=0, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=0, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=136, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=1, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=1, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=141, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=2, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=2, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=157, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=3, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=3, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=160, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=4, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=4, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=142, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=5, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=5, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=138, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=6, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=6, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=146, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=7, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=7, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=145, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=8, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=8, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=140, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=9, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=9, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=134, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=10, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=10, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=132, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=11, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=11, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=135, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=12, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=12, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=130, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=13, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=13, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=149, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=14, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=14, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=161, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=15, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={1:0}, b={1:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={1:0}, b={1:0}, i=15, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={1:0}, b={1:0}, b[i]=131, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={1:0}, b={1:0}, i=16, size=15] [L17] COND FALSE !(i <= size) VAL [\old(size)=15, b={1:0}, b={1:0}, i=16, size=15] [L20] return i; VAL [\old(size)=15, \result=16, b={1:0}, b={1:0}, i=16, size=15] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=16, i=14, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=16, i=14, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=15, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=15, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=16, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={1:0}, b={1:0}, i=0, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=0, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=136, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=1, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=1, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=141, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=2, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=2, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=157, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=3, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=3, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=160, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=4, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=4, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=142, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=5, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=5, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=138, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=6, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=6, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=146, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=7, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=7, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=145, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=8, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=8, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=140, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=9, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=9, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=134, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=10, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=10, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=132, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=11, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=11, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=135, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=12, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=12, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=130, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=13, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=13, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=149, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=14, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=14, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=161, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=15, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=15, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=131, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=16, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={1:0}, b={1:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={1:0}, b={1:0}, i=16, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={1:0}, b={1:0}, b[i]=129, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={1:0}, b={1:0}, i=17, size=16] [L17] COND FALSE !(i <= size) VAL [\old(size)=16, b={1:0}, b={1:0}, i=17, size=16] [L20] return i; VAL [\old(size)=16, \result=17, b={1:0}, b={1:0}, i=17, size=16] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=17, i=15, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=17, i=15, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=16, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=16, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=17, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={1:0}, b={1:0}, i=0, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=0, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=136, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=1, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=1, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=141, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=2, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=2, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=157, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=3, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=3, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=160, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=4, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=4, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=142, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=5, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=5, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=138, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=6, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=6, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=146, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=7, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=7, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=145, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=8, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=8, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=140, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=9, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=9, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=134, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=10, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=10, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=132, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=11, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=11, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=135, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=12, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=12, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=130, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=13, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=13, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=149, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=14, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=14, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=161, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=15, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=15, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=131, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=16, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=16, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=129, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=17, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={1:0}, b={1:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={1:0}, b={1:0}, i=17, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={1:0}, b={1:0}, b[i]=147, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={1:0}, b={1:0}, i=18, size=17] [L17] COND FALSE !(i <= size) VAL [\old(size)=17, b={1:0}, b={1:0}, i=18, size=17] [L20] return i; VAL [\old(size)=17, \result=18, b={1:0}, b={1:0}, i=18, size=17] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=18, i=16, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=18, i=16, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=17, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=17, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=18, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={1:0}, b={1:0}, i=0, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=0, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=136, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=1, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=1, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=141, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=2, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=2, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=157, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=3, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=3, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=160, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=4, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=4, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=142, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=5, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=5, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=138, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=6, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=6, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=146, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=7, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=7, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=145, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=8, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=8, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=140, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=9, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=9, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=134, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=10, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=10, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=132, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=11, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=11, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=135, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=12, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=12, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=130, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=13, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=13, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=149, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=14, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=14, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=161, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=15, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=15, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=131, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=16, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=16, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=129, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=17, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=17, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=147, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=18, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={1:0}, b={1:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={1:0}, b={1:0}, i=18, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={1:0}, b={1:0}, b[i]=158, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={1:0}, b={1:0}, i=19, size=18] [L17] COND FALSE !(i <= size) VAL [\old(size)=18, b={1:0}, b={1:0}, i=19, size=18] [L20] return i; VAL [\old(size)=18, \result=19, b={1:0}, b={1:0}, i=19, size=18] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=19, i=17, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=19, i=17, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=18, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=18, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=19, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={1:0}, b={1:0}, i=0, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=0, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=136, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=1, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=1, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=141, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=2, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=2, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=157, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=3, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=3, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=160, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=4, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=4, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=142, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=5, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=5, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=138, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=6, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=6, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=146, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=7, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=7, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=145, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=8, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=8, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=140, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=9, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=9, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=134, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=10, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=10, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=132, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=11, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=11, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=135, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=12, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=12, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=130, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=13, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=13, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=149, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=14, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=14, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=161, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=15, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=15, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=131, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=16, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=16, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=129, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=17, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=17, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=147, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=18, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=18, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=158, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=19, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={1:0}, b={1:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={1:0}, b={1:0}, i=19, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={1:0}, b={1:0}, b[i]=154, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={1:0}, b={1:0}, i=20, size=19] [L17] COND FALSE !(i <= size) VAL [\old(size)=19, b={1:0}, b={1:0}, i=20, size=19] [L20] return i; VAL [\old(size)=19, \result=20, b={1:0}, b={1:0}, i=20, size=19] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=20, i=18, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=20, i=18, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=19, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=19, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=20, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={1:0}, b={1:0}, i=0, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=0, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=136, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=1, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=1, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=141, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=2, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=2, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=157, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=3, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=3, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=160, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=4, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=4, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=142, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=5, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=5, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=138, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=6, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=6, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=146, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=7, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=7, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=145, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=8, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=8, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=140, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=9, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=9, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=134, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=10, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=10, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=132, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=11, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=11, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=135, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=12, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=12, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=130, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=13, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=13, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=149, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=14, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=14, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=161, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=15, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=15, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=131, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=16, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=16, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=129, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=17, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=17, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=147, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=18, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=18, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=158, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=19, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=19, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=154, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=20, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={1:0}, b={1:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={1:0}, b={1:0}, i=20, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={1:0}, b={1:0}, b[i]=151, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={1:0}, b={1:0}, i=21, size=20] [L17] COND FALSE !(i <= size) VAL [\old(size)=20, b={1:0}, b={1:0}, i=21, size=20] [L20] return i; VAL [\old(size)=20, \result=21, b={1:0}, b={1:0}, i=21, size=20] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=21, i=19, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=21, i=19, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=20, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=20, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=21, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={1:0}, b={1:0}, i=0, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=0, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=136, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=1, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=1, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=141, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=2, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=2, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=157, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=3, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=3, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=160, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=4, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=4, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=142, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=5, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=5, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=138, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=6, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=6, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=146, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=7, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=7, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=145, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=8, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=8, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=140, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=9, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=9, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=134, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=10, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=10, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=132, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=11, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=11, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=135, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=12, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=12, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=130, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=13, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=13, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=149, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=14, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=14, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=161, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=15, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=15, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=131, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=16, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=16, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=129, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=17, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=17, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=147, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=18, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=18, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=158, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=19, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=19, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=154, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=20, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=20, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=151, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=21, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={1:0}, b={1:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={1:0}, b={1:0}, i=21, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={1:0}, b={1:0}, b[i]=153, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={1:0}, b={1:0}, i=22, size=21] [L17] COND FALSE !(i <= size) VAL [\old(size)=21, b={1:0}, b={1:0}, i=22, size=21] [L20] return i; VAL [\old(size)=21, \result=22, b={1:0}, b={1:0}, i=22, size=21] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=22, i=20, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=22, i=20, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=21, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=21, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=22, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={1:0}, b={1:0}, i=0, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=0, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=136, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=1, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=1, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=141, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=2, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=2, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=157, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=3, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=3, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=160, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=4, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=4, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=142, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=5, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=5, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=138, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=6, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=6, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=146, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=7, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=7, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=145, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=8, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=8, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=140, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=9, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=9, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=134, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=10, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=10, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=132, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=11, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=11, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=135, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=12, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=12, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=130, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=13, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=13, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=149, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=14, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=14, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=161, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=15, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=15, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=131, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=16, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=16, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=129, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=17, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=17, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=147, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=18, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=18, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=158, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=19, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=19, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=154, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=20, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=20, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=151, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=21, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=21, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=153, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=22, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={1:0}, b={1:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={1:0}, b={1:0}, i=22, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={1:0}, b={1:0}, b[i]=159, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={1:0}, b={1:0}, i=23, size=22] [L17] COND FALSE !(i <= size) VAL [\old(size)=22, b={1:0}, b={1:0}, i=23, size=22] [L20] return i; VAL [\old(size)=22, \result=23, b={1:0}, b={1:0}, i=23, size=22] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=23, i=21, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=23, i=21, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=22, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=22, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=23, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={1:0}, b={1:0}, i=0, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=0, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=136, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=1, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=1, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=141, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=2, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=2, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=157, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=3, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=3, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=160, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=4, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=4, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=142, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=5, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=5, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=138, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=6, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=6, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=146, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=7, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=7, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=145, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=8, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=8, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=140, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=9, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=9, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=134, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=10, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=10, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=132, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=11, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=11, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=135, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=12, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=12, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=130, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=13, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=13, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=149, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=14, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=14, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=161, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=15, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=15, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=131, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=16, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=16, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=129, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=17, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=17, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=147, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=18, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=18, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=158, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=19, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=19, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=154, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=20, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=20, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=151, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=21, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=21, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=153, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=22, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=22, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=159, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=23, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={1:0}, b={1:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={1:0}, b={1:0}, i=23, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={1:0}, b={1:0}, b[i]=162, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={1:0}, b={1:0}, i=24, size=23] [L17] COND FALSE !(i <= size) VAL [\old(size)=23, b={1:0}, b={1:0}, i=24, size=23] [L20] return i; VAL [\old(size)=23, \result=24, b={1:0}, b={1:0}, i=24, size=23] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=24, i=22, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=24, i=22, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=23, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=23, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=24, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={1:0}, b={1:0}, i=0, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=0, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=136, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=1, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=1, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=141, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=2, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=2, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=157, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=3, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=3, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=160, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=4, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=4, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=142, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=5, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=5, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=138, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=6, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=6, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=146, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=7, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=7, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=145, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=8, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=8, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=140, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=9, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=9, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=134, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=10, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=10, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=132, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=11, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=11, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=135, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=12, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=12, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=130, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=13, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=13, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=149, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=14, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=14, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=161, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=15, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=15, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=131, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=16, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=16, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=129, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=17, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=17, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=147, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=18, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=18, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=158, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=19, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=19, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=154, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=20, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=20, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=151, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=21, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=21, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=153, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=22, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=22, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=159, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=23, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=23, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=162, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=24, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={1:0}, b={1:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={1:0}, b={1:0}, i=24, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={1:0}, b={1:0}, b[i]=150, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={1:0}, b={1:0}, i=25, size=24] [L17] COND FALSE !(i <= size) VAL [\old(size)=24, b={1:0}, b={1:0}, i=25, size=24] [L20] return i; VAL [\old(size)=24, \result=25, b={1:0}, b={1:0}, i=25, size=24] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=25, i=23, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=25, i=23, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=24, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=24, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=25, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={1:0}, b={1:0}, i=0, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=0, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=136, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=1, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=1, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=141, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=2, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=2, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=157, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=3, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=3, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=160, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=4, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=4, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=142, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=5, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=5, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=138, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=6, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=6, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=146, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=7, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=7, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=145, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=8, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=8, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=140, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=9, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=9, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=134, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=10, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=10, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=132, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=11, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=11, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=135, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=12, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=12, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=130, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=13, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=13, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=149, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=14, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=14, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=161, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=15, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=15, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=131, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=16, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=16, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=129, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=17, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=17, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=147, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=18, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=18, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=158, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=19, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=19, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=154, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=20, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=20, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=151, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=21, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=21, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=153, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=22, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=22, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=159, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=23, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=23, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=162, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=24, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=24, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=150, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=25, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={1:0}, b={1:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={1:0}, b={1:0}, i=25, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={1:0}, b={1:0}, b[i]=137, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={1:0}, b={1:0}, i=26, size=25] [L17] COND FALSE !(i <= size) VAL [\old(size)=25, b={1:0}, b={1:0}, i=26, size=25] [L20] return i; VAL [\old(size)=25, \result=26, b={1:0}, b={1:0}, i=26, size=25] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=26, i=24, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=26, i=24, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=25, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=25, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=26, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={1:0}, b={1:0}, i=0, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=0, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=136, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=1, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=1, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=141, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=2, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=2, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=157, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=3, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=3, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=160, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=4, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=4, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=142, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=5, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=5, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=138, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=6, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=6, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=146, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=7, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=7, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=145, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=8, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=8, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=140, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=9, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=9, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=134, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=10, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=10, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=132, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=11, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=11, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=135, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=12, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=12, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=130, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=13, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=13, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=149, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=14, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=14, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=161, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=15, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=15, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=131, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=16, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=16, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=129, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=17, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=17, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=147, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=18, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=18, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=158, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=19, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=19, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=154, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=20, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=20, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=151, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=21, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=21, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=153, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=22, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=22, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=159, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=23, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=23, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=162, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=24, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=24, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=150, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=25, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=25, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=137, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=26, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={1:0}, b={1:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={1:0}, b={1:0}, i=26, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={1:0}, b={1:0}, b[i]=143, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={1:0}, b={1:0}, i=27, size=26] [L17] COND FALSE !(i <= size) VAL [\old(size)=26, b={1:0}, b={1:0}, i=27, size=26] [L20] return i; VAL [\old(size)=26, \result=27, b={1:0}, b={1:0}, i=27, size=26] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=27, i=25, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=27, i=25, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=26, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=26, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=27, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={1:0}, b={1:0}, i=0, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=0, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=136, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=1, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=1, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=141, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=2, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=2, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=157, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=3, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=3, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=160, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=4, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=4, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=142, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=5, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=5, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=138, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=6, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=6, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=146, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=7, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=7, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=145, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=8, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=8, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=140, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=9, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=9, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=134, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=10, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=10, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=132, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=11, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=11, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=135, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=12, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=12, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=130, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=13, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=13, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=149, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=14, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=14, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=161, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=15, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=15, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=131, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=16, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=16, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=129, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=17, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=17, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=147, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=18, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=18, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=158, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=19, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=19, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=154, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=20, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=20, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=151, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=21, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=21, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=153, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=22, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=22, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=159, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=23, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=23, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=162, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=24, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=24, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=150, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=25, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=25, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=137, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=26, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=26, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=143, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=27, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={1:0}, b={1:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={1:0}, b={1:0}, i=27, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={1:0}, b={1:0}, b[i]=155, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={1:0}, b={1:0}, i=28, size=27] [L17] COND FALSE !(i <= size) VAL [\old(size)=27, b={1:0}, b={1:0}, i=28, size=27] [L20] return i; VAL [\old(size)=27, \result=28, b={1:0}, b={1:0}, i=28, size=27] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=28, i=26, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=28, i=26, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=27, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=27, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=28, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={1:0}, b={1:0}, i=0, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=0, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=136, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=1, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=1, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=141, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=2, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=2, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=157, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=3, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=3, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=160, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=4, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=4, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=142, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=5, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=5, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=138, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=6, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=6, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=146, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=7, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=7, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=145, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=8, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=8, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=140, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=9, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=9, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=134, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=10, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=10, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=132, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=11, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=11, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=135, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=12, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=12, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=130, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=13, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=13, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=149, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=14, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=14, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=161, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=15, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=15, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=131, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=16, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=16, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=129, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=17, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=17, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=147, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=18, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=18, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=158, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=19, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=19, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=154, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=20, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=20, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=151, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=21, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=21, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=153, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=22, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=22, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=159, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=23, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=23, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=162, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=24, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=24, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=150, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=25, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=25, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=137, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=26, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=26, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=143, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=27, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=27, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=155, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=28, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={1:0}, b={1:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={1:0}, b={1:0}, i=28, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={1:0}, b={1:0}, b[i]=152, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={1:0}, b={1:0}, i=29, size=28] [L17] COND FALSE !(i <= size) VAL [\old(size)=28, b={1:0}, b={1:0}, i=29, size=28] [L20] return i; VAL [\old(size)=28, \result=29, b={1:0}, b={1:0}, i=29, size=28] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=29, i=27, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=29, i=27, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=28, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=28, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=29, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={1:0}, b={1:0}, i=0, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=0, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=136, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=1, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=1, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=141, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=2, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=2, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=157, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=3, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=3, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=160, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=4, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=4, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=142, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=5, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=5, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=138, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=6, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=6, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=146, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=7, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=7, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=145, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=8, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=8, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=140, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=9, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=9, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=134, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=10, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=10, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=132, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=11, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=11, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=135, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=12, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=12, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=130, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=13, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=13, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=149, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=14, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=14, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=161, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=15, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=15, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=131, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=16, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=16, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=129, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=17, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=17, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=147, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=18, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=18, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=158, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=19, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=19, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=154, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=20, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=20, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=151, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=21, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=21, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=153, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=22, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=22, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=159, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=23, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=23, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=162, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=24, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=24, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=150, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=25, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=25, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=137, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=26, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=26, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=143, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=27, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=27, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=155, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=28, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=28, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=152, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=29, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={1:0}, b={1:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={1:0}, b={1:0}, i=29, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={1:0}, b={1:0}, b[i]=139, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={1:0}, b={1:0}, i=30, size=29] [L17] COND FALSE !(i <= size) VAL [\old(size)=29, b={1:0}, b={1:0}, i=30, size=29] [L20] return i; VAL [\old(size)=29, \result=30, b={1:0}, b={1:0}, i=30, size=29] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=30, i=28, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=30, i=28, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=29, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=29, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=30, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={1:0}, b={1:0}, i=0, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=0, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=136, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=1, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=1, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=141, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=2, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=2, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=157, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=3, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=3, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=160, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=4, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=4, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=142, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=5, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=5, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=138, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=6, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=6, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=146, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=7, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=7, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=145, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=8, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=8, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=140, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=9, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=9, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=134, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=10, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=10, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=132, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=11, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=11, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=135, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=12, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=12, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=130, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=13, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=13, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=149, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=14, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=14, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=161, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=15, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=15, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=131, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=16, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=16, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=129, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=17, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=17, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=147, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=18, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=18, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=158, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=19, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=19, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=154, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=20, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=20, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=151, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=21, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=21, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=153, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=22, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=22, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=159, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=23, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=23, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=162, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=24, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=24, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=150, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=25, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=25, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=137, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=26, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=26, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=143, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=27, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=27, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=155, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=28, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=28, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=152, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=29, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=29, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=139, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=30, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={1:0}, b={1:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={1:0}, b={1:0}, i=30, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={1:0}, b={1:0}, b[i]=156, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={1:0}, b={1:0}, i=31, size=30] [L17] COND FALSE !(i <= size) VAL [\old(size)=30, b={1:0}, b={1:0}, i=31, size=30] [L20] return i; VAL [\old(size)=30, \result=31, b={1:0}, b={1:0}, i=31, size=30] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=31, i=29, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=31, i=29, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=30, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=30, mask={1:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=31, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={1:0}, b={1:0}, i=0, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=0, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=136, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=1, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=1, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=141, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=2, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=2, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=157, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=3, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=3, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=160, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=4, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=4, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=142, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=5, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=5, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=138, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=6, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=6, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=146, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=7, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=7, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=145, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=8, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=8, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=140, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=9, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=9, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=134, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=10, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=10, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=132, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=11, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=11, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=135, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=12, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=12, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=130, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=13, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=13, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=149, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=14, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=14, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=161, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=15, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=15, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=131, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=16, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=16, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=129, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=17, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=17, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=147, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=18, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=18, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=158, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=19, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=19, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=154, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=20, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=20, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=151, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=21, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=21, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=153, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=22, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=22, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=159, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=23, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=23, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=162, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=24, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=24, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=150, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=25, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=25, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=137, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=26, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=26, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=143, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=27, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=27, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=155, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=28, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=28, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=152, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=29, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=29, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=139, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=30, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=30, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=156, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=31, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={1:0}, b={1:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={1:0}, b={1:0}, i=31, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={1:0}, b={1:0}, b[i]=133, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={1:0}, b={1:0}, i=32, size=31] [L17] COND FALSE !(i <= size) VAL [\old(size)=31, b={1:0}, b={1:0}, i=32, size=31] [L20] return i; VAL [\old(size)=31, \result=32, b={1:0}, b={1:0}, i=32, size=31] [L27] RET, EXPR foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=32, i=30, mask={1:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={-1:0}, foo(mask, i + 1)=32, i=30, mask={1:0}] [L26] i++ VAL [b={-1:0}, i=31, mask={1:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={-1:0}, i=31, mask={1:0}] [L27] CALL foo(mask, i + 1) VAL [\old(size)=32, b={1:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=32, b={1:0}, b={1:0}, i=0, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=0, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=0, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=136, i=0, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=1, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=1, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=1, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=141, i=1, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=2, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=2, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=2, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=157, i=2, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=3, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=3, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=3, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=160, i=3, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=4, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=4, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=4, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=142, i=4, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=5, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=5, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=5, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=138, i=5, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=6, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=6, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=6, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=146, i=6, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=7, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=7, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=7, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=145, i=7, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=8, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=8, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=8, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=140, i=8, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=9, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=9, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=9, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=134, i=9, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=10, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=10, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=10, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=132, i=10, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=11, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=11, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=11, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=135, i=11, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=12, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=12, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=12, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=130, i=12, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=13, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=13, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=13, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=149, i=13, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=14, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=14, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=14, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=161, i=14, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=15, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=15, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=15, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=131, i=15, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=16, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=16, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=16, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=129, i=16, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=17, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=17, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=17, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=147, i=17, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=18, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=18, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=18, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=158, i=18, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=19, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=19, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=19, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=154, i=19, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=20, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=20, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=20, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=151, i=20, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=21, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=21, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=21, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=153, i=21, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=22, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=22, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=22, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=159, i=22, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=23, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=23, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=23, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=162, i=23, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=24, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=24, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=24, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=150, i=24, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=25, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=25, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=25, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=137, i=25, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=26, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=26, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=26, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=143, i=26, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=27, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=27, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=27, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=155, i=27, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=28, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=28, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=28, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=152, i=28, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=29, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=29, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=29, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=139, i=29, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=30, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=30, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=30, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=156, i=30, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=31, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=31, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=31, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={1:0}, b={1:0}, b[i]=133, i=31, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={1:0}, b={1:0}, i=32, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={1:0}, b={1:0}, i=32, size=32] [L18] a[i] VAL [\old(size)=32, b={1:0}, b={1:0}, i=32, size=32] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 40 locations, 8 error locations. Result: UNSAFE, OverallTime: 757.9s, OverallIterations: 74, TraceHistogramMax: 560, AutomataDifference: 203.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2756 SDtfs, 53243 SDslu, 25254 SDs, 0 SdLazy, 202579 SolverSat, 9363 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 88.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 80448 GetRequests, 74193 SyntacticMatches, 45 SemanticMatches, 6210 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 199002 ImplicationChecksByTransitivity, 177.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3949occurred in iteration=73, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 1.4s AutomataMinimizationTime, 73 MinimizatonAttempts, 21395 StatesRemovedByMinimization, 68 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 5.3s SsaConstructionTime, 285.1s SatisfiabilityAnalysisTime, 166.5s InterpolantComputationTime, 149901 NumberOfCodeBlocks, 138615 NumberOfCodeBlocksAsserted, 1000 NumberOfCheckSat, 146615 ConstructedInterpolants, 320 QuantifiedInterpolants, 398532413 SizeOfPredicates, 137 NumberOfNonLiveVariables, 156877 ConjunctsInSsa, 2049 ConjunctsInUnsatCore, 139 InterpolantComputations, 10 PerfectInterpolantSequences, 21329226/21564779 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...