./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/kundu1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/kundu1.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 532163d21d7e473fbfa4a073427e9fd2a45c7337 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-11-15 23:26:51,288 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-15 23:26:51,290 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-15 23:26:51,306 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-15 23:26:51,306 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-15 23:26:51,308 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-15 23:26:51,310 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-15 23:26:51,320 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-15 23:26:51,325 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-15 23:26:51,329 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-15 23:26:51,329 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-15 23:26:51,331 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-15 23:26:51,331 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-15 23:26:51,332 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-15 23:26:51,333 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-15 23:26:51,334 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-15 23:26:51,334 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-15 23:26:51,335 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-15 23:26:51,337 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-15 23:26:51,341 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-15 23:26:51,346 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-15 23:26:51,348 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-15 23:26:51,352 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-15 23:26:51,353 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-15 23:26:51,358 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-15 23:26:51,359 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-15 23:26:51,359 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-15 23:26:51,361 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-15 23:26:51,361 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-15 23:26:51,363 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-15 23:26:51,364 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-15 23:26:51,365 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-15 23:26:51,366 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-15 23:26:51,367 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-15 23:26:51,369 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-15 23:26:51,369 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-15 23:26:51,370 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-15 23:26:51,370 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-15 23:26:51,370 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-15 23:26:51,371 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-15 23:26:51,372 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-15 23:26:51,373 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-15 23:26:51,409 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-15 23:26:51,410 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-15 23:26:51,411 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-15 23:26:51,411 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-15 23:26:51,412 INFO L138 SettingsManager]: * Use SBE=true [2019-11-15 23:26:51,412 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-15 23:26:51,412 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-15 23:26:51,413 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-15 23:26:51,413 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-15 23:26:51,413 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-15 23:26:51,413 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-15 23:26:51,414 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-15 23:26:51,414 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-15 23:26:51,414 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-15 23:26:51,414 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-15 23:26:51,415 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-15 23:26:51,423 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-15 23:26:51,423 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-15 23:26:51,424 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-15 23:26:51,424 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-15 23:26:51,424 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-15 23:26:51,424 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 23:26:51,425 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-15 23:26:51,425 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-15 23:26:51,426 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-15 23:26:51,426 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-15 23:26:51,427 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-15 23:26:51,427 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-15 23:26:51,427 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 532163d21d7e473fbfa4a073427e9fd2a45c7337 [2019-11-15 23:26:51,476 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-15 23:26:51,495 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-15 23:26:51,499 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-15 23:26:51,501 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-15 23:26:51,501 INFO L275 PluginConnector]: CDTParser initialized [2019-11-15 23:26:51,503 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/../../sv-benchmarks/c/systemc/kundu1.cil.c [2019-11-15 23:26:51,576 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/data/65c6d8c31/775428655fbb414f97a8ebcf51be2a9d/FLAGd55214497 [2019-11-15 23:26:52,075 INFO L306 CDTParser]: Found 1 translation units. [2019-11-15 23:26:52,076 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/sv-benchmarks/c/systemc/kundu1.cil.c [2019-11-15 23:26:52,086 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/data/65c6d8c31/775428655fbb414f97a8ebcf51be2a9d/FLAGd55214497 [2019-11-15 23:26:52,434 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/data/65c6d8c31/775428655fbb414f97a8ebcf51be2a9d [2019-11-15 23:26:52,438 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-15 23:26:52,440 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-15 23:26:52,444 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-15 23:26:52,445 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-15 23:26:52,449 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-15 23:26:52,450 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 11:26:52" (1/1) ... [2019-11-15 23:26:52,453 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@587b9e09 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:52, skipping insertion in model container [2019-11-15 23:26:52,453 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 11:26:52" (1/1) ... [2019-11-15 23:26:52,462 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-15 23:26:52,519 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-15 23:26:52,897 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 23:26:52,906 INFO L188 MainTranslator]: Completed pre-run [2019-11-15 23:26:52,982 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 23:26:53,011 INFO L192 MainTranslator]: Completed translation [2019-11-15 23:26:53,011 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53 WrapperNode [2019-11-15 23:26:53,012 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-15 23:26:53,013 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-15 23:26:53,014 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-15 23:26:53,014 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-15 23:26:53,024 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53" (1/1) ... [2019-11-15 23:26:53,046 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53" (1/1) ... [2019-11-15 23:26:53,082 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-15 23:26:53,083 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-15 23:26:53,083 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-15 23:26:53,083 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-15 23:26:53,093 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53" (1/1) ... [2019-11-15 23:26:53,094 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53" (1/1) ... [2019-11-15 23:26:53,096 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53" (1/1) ... [2019-11-15 23:26:53,097 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53" (1/1) ... [2019-11-15 23:26:53,103 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53" (1/1) ... [2019-11-15 23:26:53,111 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53" (1/1) ... [2019-11-15 23:26:53,114 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53" (1/1) ... [2019-11-15 23:26:53,118 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-15 23:26:53,118 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-15 23:26:53,119 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-15 23:26:53,119 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-15 23:26:53,120 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 23:26:53,204 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-15 23:26:53,204 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-15 23:26:54,134 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-15 23:26:54,134 INFO L284 CfgBuilder]: Removed 72 assume(true) statements. [2019-11-15 23:26:54,135 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 11:26:54 BoogieIcfgContainer [2019-11-15 23:26:54,136 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-15 23:26:54,137 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-15 23:26:54,137 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-15 23:26:54,141 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-15 23:26:54,143 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 15.11 11:26:52" (1/3) ... [2019-11-15 23:26:54,145 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5a1b0272 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 11:26:54, skipping insertion in model container [2019-11-15 23:26:54,145 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:26:53" (2/3) ... [2019-11-15 23:26:54,146 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5a1b0272 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 11:26:54, skipping insertion in model container [2019-11-15 23:26:54,146 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 11:26:54" (3/3) ... [2019-11-15 23:26:54,147 INFO L109 eAbstractionObserver]: Analyzing ICFG kundu1.cil.c [2019-11-15 23:26:54,159 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-15 23:26:54,171 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2019-11-15 23:26:54,186 INFO L249 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2019-11-15 23:26:54,221 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-15 23:26:54,221 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-15 23:26:54,222 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-15 23:26:54,222 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-15 23:26:54,222 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-15 23:26:54,222 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-15 23:26:54,229 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-15 23:26:54,233 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-15 23:26:54,258 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states. [2019-11-15 23:26:54,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-11-15 23:26:54,266 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:54,267 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:54,269 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:54,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:54,275 INFO L82 PathProgramCache]: Analyzing trace with hash 1913091172, now seen corresponding path program 1 times [2019-11-15 23:26:54,283 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:54,284 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083217162] [2019-11-15 23:26:54,284 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:54,284 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:54,284 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:54,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:54,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:26:54,431 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083217162] [2019-11-15 23:26:54,432 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:54,432 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:26:54,432 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1119694411] [2019-11-15 23:26:54,437 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:26:54,438 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:54,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:26:54,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:54,451 INFO L87 Difference]: Start difference. First operand 117 states. Second operand 3 states. [2019-11-15 23:26:54,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:54,500 INFO L93 Difference]: Finished difference Result 228 states and 346 transitions. [2019-11-15 23:26:54,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:26:54,502 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-11-15 23:26:54,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:54,519 INFO L225 Difference]: With dead ends: 228 [2019-11-15 23:26:54,520 INFO L226 Difference]: Without dead ends: 112 [2019-11-15 23:26:54,525 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:54,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2019-11-15 23:26:54,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2019-11-15 23:26:54,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2019-11-15 23:26:54,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 162 transitions. [2019-11-15 23:26:54,569 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 162 transitions. Word has length 33 [2019-11-15 23:26:54,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:26:54,569 INFO L462 AbstractCegarLoop]: Abstraction has 112 states and 162 transitions. [2019-11-15 23:26:54,569 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:26:54,569 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 162 transitions. [2019-11-15 23:26:54,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-11-15 23:26:54,573 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:54,574 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:54,574 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:54,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:54,575 INFO L82 PathProgramCache]: Analyzing trace with hash 526887778, now seen corresponding path program 1 times [2019-11-15 23:26:54,575 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:54,575 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879374130] [2019-11-15 23:26:54,575 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:54,575 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:54,576 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:54,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:54,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:26:54,628 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879374130] [2019-11-15 23:26:54,628 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:54,628 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:26:54,628 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812368290] [2019-11-15 23:26:54,629 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:26:54,629 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:54,630 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:26:54,630 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:54,630 INFO L87 Difference]: Start difference. First operand 112 states and 162 transitions. Second operand 3 states. [2019-11-15 23:26:54,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:54,731 INFO L93 Difference]: Finished difference Result 305 states and 441 transitions. [2019-11-15 23:26:54,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:26:54,732 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-11-15 23:26:54,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:54,734 INFO L225 Difference]: With dead ends: 305 [2019-11-15 23:26:54,735 INFO L226 Difference]: Without dead ends: 200 [2019-11-15 23:26:54,736 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:54,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states. [2019-11-15 23:26:54,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 190. [2019-11-15 23:26:54,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2019-11-15 23:26:54,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 275 transitions. [2019-11-15 23:26:54,769 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 275 transitions. Word has length 33 [2019-11-15 23:26:54,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:26:54,769 INFO L462 AbstractCegarLoop]: Abstraction has 190 states and 275 transitions. [2019-11-15 23:26:54,770 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:26:54,770 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 275 transitions. [2019-11-15 23:26:54,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-11-15 23:26:54,771 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:54,771 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:54,771 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:54,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:54,772 INFO L82 PathProgramCache]: Analyzing trace with hash -1145629853, now seen corresponding path program 1 times [2019-11-15 23:26:54,772 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:54,772 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899895849] [2019-11-15 23:26:54,772 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:54,772 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:54,773 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:54,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:54,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:26:54,816 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899895849] [2019-11-15 23:26:54,816 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:54,817 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:26:54,817 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1476908834] [2019-11-15 23:26:54,817 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:26:54,817 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:54,818 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:26:54,818 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:54,818 INFO L87 Difference]: Start difference. First operand 190 states and 275 transitions. Second operand 3 states. [2019-11-15 23:26:54,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:54,969 INFO L93 Difference]: Finished difference Result 527 states and 762 transitions. [2019-11-15 23:26:54,970 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:26:54,970 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-11-15 23:26:54,970 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:54,974 INFO L225 Difference]: With dead ends: 527 [2019-11-15 23:26:54,975 INFO L226 Difference]: Without dead ends: 350 [2019-11-15 23:26:54,976 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:54,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350 states. [2019-11-15 23:26:55,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350 to 328. [2019-11-15 23:26:55,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 328 states. [2019-11-15 23:26:55,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 328 states to 328 states and 462 transitions. [2019-11-15 23:26:55,018 INFO L78 Accepts]: Start accepts. Automaton has 328 states and 462 transitions. Word has length 33 [2019-11-15 23:26:55,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:26:55,018 INFO L462 AbstractCegarLoop]: Abstraction has 328 states and 462 transitions. [2019-11-15 23:26:55,019 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:26:55,019 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 462 transitions. [2019-11-15 23:26:55,020 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-11-15 23:26:55,020 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:55,021 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:55,021 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:55,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:55,021 INFO L82 PathProgramCache]: Analyzing trace with hash -1045714737, now seen corresponding path program 1 times [2019-11-15 23:26:55,022 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:55,022 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1773534540] [2019-11-15 23:26:55,022 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:55,022 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:55,023 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:55,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:55,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:26:55,124 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1773534540] [2019-11-15 23:26:55,124 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:55,124 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 23:26:55,124 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317507324] [2019-11-15 23:26:55,125 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 23:26:55,125 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:55,125 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 23:26:55,125 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:26:55,125 INFO L87 Difference]: Start difference. First operand 328 states and 462 transitions. Second operand 5 states. [2019-11-15 23:26:55,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:55,287 INFO L93 Difference]: Finished difference Result 1045 states and 1489 transitions. [2019-11-15 23:26:55,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 23:26:55,288 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2019-11-15 23:26:55,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:55,294 INFO L225 Difference]: With dead ends: 1045 [2019-11-15 23:26:55,294 INFO L226 Difference]: Without dead ends: 728 [2019-11-15 23:26:55,297 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 23:26:55,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 728 states. [2019-11-15 23:26:55,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 728 to 340. [2019-11-15 23:26:55,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2019-11-15 23:26:55,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 469 transitions. [2019-11-15 23:26:55,355 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 469 transitions. Word has length 34 [2019-11-15 23:26:55,356 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:26:55,356 INFO L462 AbstractCegarLoop]: Abstraction has 340 states and 469 transitions. [2019-11-15 23:26:55,356 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 23:26:55,356 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 469 transitions. [2019-11-15 23:26:55,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-11-15 23:26:55,358 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:55,359 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:55,359 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:55,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:55,360 INFO L82 PathProgramCache]: Analyzing trace with hash -1179728243, now seen corresponding path program 1 times [2019-11-15 23:26:55,360 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:55,360 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544486191] [2019-11-15 23:26:55,360 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:55,361 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:55,361 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:55,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:55,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:26:55,515 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [544486191] [2019-11-15 23:26:55,516 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:55,516 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 23:26:55,516 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1270000515] [2019-11-15 23:26:55,517 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 23:26:55,517 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:55,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 23:26:55,517 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:26:55,517 INFO L87 Difference]: Start difference. First operand 340 states and 469 transitions. Second operand 5 states. [2019-11-15 23:26:55,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:55,706 INFO L93 Difference]: Finished difference Result 1046 states and 1465 transitions. [2019-11-15 23:26:55,706 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 23:26:55,707 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2019-11-15 23:26:55,707 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:55,711 INFO L225 Difference]: With dead ends: 1046 [2019-11-15 23:26:55,712 INFO L226 Difference]: Without dead ends: 724 [2019-11-15 23:26:55,715 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 23:26:55,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 724 states. [2019-11-15 23:26:55,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 724 to 352. [2019-11-15 23:26:55,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2019-11-15 23:26:55,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 476 transitions. [2019-11-15 23:26:55,777 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 476 transitions. Word has length 34 [2019-11-15 23:26:55,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:26:55,778 INFO L462 AbstractCegarLoop]: Abstraction has 352 states and 476 transitions. [2019-11-15 23:26:55,778 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 23:26:55,779 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 476 transitions. [2019-11-15 23:26:55,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-11-15 23:26:55,787 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:55,787 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:55,788 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:55,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:55,788 INFO L82 PathProgramCache]: Analyzing trace with hash 1526891151, now seen corresponding path program 1 times [2019-11-15 23:26:55,789 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:55,789 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798263108] [2019-11-15 23:26:55,789 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:55,789 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:55,790 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:55,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:55,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:26:55,884 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798263108] [2019-11-15 23:26:55,884 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:55,884 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:26:55,884 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758467357] [2019-11-15 23:26:55,885 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:26:55,885 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:55,885 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:26:55,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:26:55,886 INFO L87 Difference]: Start difference. First operand 352 states and 476 transitions. Second operand 4 states. [2019-11-15 23:26:56,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:56,076 INFO L93 Difference]: Finished difference Result 1638 states and 2239 transitions. [2019-11-15 23:26:56,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:26:56,078 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2019-11-15 23:26:56,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:56,086 INFO L225 Difference]: With dead ends: 1638 [2019-11-15 23:26:56,086 INFO L226 Difference]: Without dead ends: 1304 [2019-11-15 23:26:56,088 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:26:56,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1304 states. [2019-11-15 23:26:56,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1304 to 662. [2019-11-15 23:26:56,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2019-11-15 23:26:56,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 900 transitions. [2019-11-15 23:26:56,180 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 900 transitions. Word has length 34 [2019-11-15 23:26:56,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:26:56,182 INFO L462 AbstractCegarLoop]: Abstraction has 662 states and 900 transitions. [2019-11-15 23:26:56,182 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:26:56,182 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 900 transitions. [2019-11-15 23:26:56,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-11-15 23:26:56,184 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:56,185 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:56,185 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:56,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:56,193 INFO L82 PathProgramCache]: Analyzing trace with hash -1026068075, now seen corresponding path program 1 times [2019-11-15 23:26:56,193 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:56,193 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374264117] [2019-11-15 23:26:56,193 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:56,194 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:56,194 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:56,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:56,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:26:56,247 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374264117] [2019-11-15 23:26:56,247 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:56,247 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:26:56,247 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111087376] [2019-11-15 23:26:56,248 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:26:56,248 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:56,248 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:26:56,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:26:56,248 INFO L87 Difference]: Start difference. First operand 662 states and 900 transitions. Second operand 4 states. [2019-11-15 23:26:56,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:56,366 INFO L93 Difference]: Finished difference Result 1626 states and 2222 transitions. [2019-11-15 23:26:56,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-15 23:26:56,367 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 41 [2019-11-15 23:26:56,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:56,373 INFO L225 Difference]: With dead ends: 1626 [2019-11-15 23:26:56,373 INFO L226 Difference]: Without dead ends: 982 [2019-11-15 23:26:56,375 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:26:56,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 982 states. [2019-11-15 23:26:56,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 982 to 972. [2019-11-15 23:26:56,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 972 states. [2019-11-15 23:26:56,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 972 states to 972 states and 1324 transitions. [2019-11-15 23:26:56,458 INFO L78 Accepts]: Start accepts. Automaton has 972 states and 1324 transitions. Word has length 41 [2019-11-15 23:26:56,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:26:56,458 INFO L462 AbstractCegarLoop]: Abstraction has 972 states and 1324 transitions. [2019-11-15 23:26:56,459 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:26:56,459 INFO L276 IsEmpty]: Start isEmpty. Operand 972 states and 1324 transitions. [2019-11-15 23:26:56,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-11-15 23:26:56,460 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:56,460 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:56,460 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:56,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:56,461 INFO L82 PathProgramCache]: Analyzing trace with hash -305826283, now seen corresponding path program 1 times [2019-11-15 23:26:56,461 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:56,461 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880123696] [2019-11-15 23:26:56,461 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:56,461 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:56,462 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:56,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:56,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:26:56,524 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1880123696] [2019-11-15 23:26:56,524 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:56,524 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 23:26:56,524 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095998581] [2019-11-15 23:26:56,525 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:26:56,525 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:56,525 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:26:56,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-11-15 23:26:56,526 INFO L87 Difference]: Start difference. First operand 972 states and 1324 transitions. Second operand 6 states. [2019-11-15 23:26:56,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:56,909 INFO L93 Difference]: Finished difference Result 3850 states and 5260 transitions. [2019-11-15 23:26:56,910 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-15 23:26:56,910 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2019-11-15 23:26:56,910 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:56,927 INFO L225 Difference]: With dead ends: 3850 [2019-11-15 23:26:56,927 INFO L226 Difference]: Without dead ends: 2896 [2019-11-15 23:26:56,930 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-11-15 23:26:56,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2896 states. [2019-11-15 23:26:57,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2896 to 1606. [2019-11-15 23:26:57,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1606 states. [2019-11-15 23:26:57,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1606 states to 1606 states and 2192 transitions. [2019-11-15 23:26:57,082 INFO L78 Accepts]: Start accepts. Automaton has 1606 states and 2192 transitions. Word has length 44 [2019-11-15 23:26:57,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:26:57,082 INFO L462 AbstractCegarLoop]: Abstraction has 1606 states and 2192 transitions. [2019-11-15 23:26:57,083 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:26:57,083 INFO L276 IsEmpty]: Start isEmpty. Operand 1606 states and 2192 transitions. [2019-11-15 23:26:57,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-15 23:26:57,084 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:57,084 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:57,085 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:57,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:57,085 INFO L82 PathProgramCache]: Analyzing trace with hash -1702134670, now seen corresponding path program 1 times [2019-11-15 23:26:57,085 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:57,086 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166127835] [2019-11-15 23:26:57,086 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:57,086 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:57,086 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:57,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:57,136 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-11-15 23:26:57,136 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166127835] [2019-11-15 23:26:57,137 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:57,137 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:26:57,137 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1486822992] [2019-11-15 23:26:57,137 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:26:57,138 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:57,138 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:26:57,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:57,138 INFO L87 Difference]: Start difference. First operand 1606 states and 2192 transitions. Second operand 3 states. [2019-11-15 23:26:57,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:57,413 INFO L93 Difference]: Finished difference Result 4614 states and 6233 transitions. [2019-11-15 23:26:57,414 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:26:57,414 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-15 23:26:57,415 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:57,435 INFO L225 Difference]: With dead ends: 4614 [2019-11-15 23:26:57,435 INFO L226 Difference]: Without dead ends: 3026 [2019-11-15 23:26:57,438 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:57,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3026 states. [2019-11-15 23:26:57,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3026 to 3022. [2019-11-15 23:26:57,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3022 states. [2019-11-15 23:26:57,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3022 states to 3022 states and 3978 transitions. [2019-11-15 23:26:57,658 INFO L78 Accepts]: Start accepts. Automaton has 3022 states and 3978 transitions. Word has length 46 [2019-11-15 23:26:57,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:26:57,658 INFO L462 AbstractCegarLoop]: Abstraction has 3022 states and 3978 transitions. [2019-11-15 23:26:57,658 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:26:57,659 INFO L276 IsEmpty]: Start isEmpty. Operand 3022 states and 3978 transitions. [2019-11-15 23:26:57,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-15 23:26:57,660 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:57,661 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:57,665 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:57,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:57,666 INFO L82 PathProgramCache]: Analyzing trace with hash 1664931104, now seen corresponding path program 1 times [2019-11-15 23:26:57,666 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:57,667 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333356033] [2019-11-15 23:26:57,667 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:57,667 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:57,667 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:57,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:57,711 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:26:57,711 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333356033] [2019-11-15 23:26:57,711 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:57,711 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:26:57,712 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1614056938] [2019-11-15 23:26:57,712 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:26:57,712 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:57,712 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:26:57,712 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:57,714 INFO L87 Difference]: Start difference. First operand 3022 states and 3978 transitions. Second operand 3 states. [2019-11-15 23:26:58,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:58,117 INFO L93 Difference]: Finished difference Result 8013 states and 10530 transitions. [2019-11-15 23:26:58,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:26:58,118 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-15 23:26:58,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:58,146 INFO L225 Difference]: With dead ends: 8013 [2019-11-15 23:26:58,147 INFO L226 Difference]: Without dead ends: 5023 [2019-11-15 23:26:58,155 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:58,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5023 states. [2019-11-15 23:26:58,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5023 to 4273. [2019-11-15 23:26:58,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4273 states. [2019-11-15 23:26:58,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4273 states to 4273 states and 5593 transitions. [2019-11-15 23:26:58,487 INFO L78 Accepts]: Start accepts. Automaton has 4273 states and 5593 transitions. Word has length 48 [2019-11-15 23:26:58,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:26:58,487 INFO L462 AbstractCegarLoop]: Abstraction has 4273 states and 5593 transitions. [2019-11-15 23:26:58,487 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:26:58,487 INFO L276 IsEmpty]: Start isEmpty. Operand 4273 states and 5593 transitions. [2019-11-15 23:26:58,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-15 23:26:58,489 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:58,489 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:58,489 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:58,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:58,490 INFO L82 PathProgramCache]: Analyzing trace with hash 403090641, now seen corresponding path program 1 times [2019-11-15 23:26:58,490 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:58,490 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23138306] [2019-11-15 23:26:58,490 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:58,491 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:58,491 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:58,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:58,548 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:26:58,549 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23138306] [2019-11-15 23:26:58,549 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:58,549 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:26:58,549 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1761510490] [2019-11-15 23:26:58,550 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:26:58,550 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:58,550 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:26:58,550 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:58,550 INFO L87 Difference]: Start difference. First operand 4273 states and 5593 transitions. Second operand 3 states. [2019-11-15 23:26:58,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:58,937 INFO L93 Difference]: Finished difference Result 8516 states and 11154 transitions. [2019-11-15 23:26:58,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:26:58,938 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-15 23:26:58,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:58,961 INFO L225 Difference]: With dead ends: 8516 [2019-11-15 23:26:58,961 INFO L226 Difference]: Without dead ends: 4275 [2019-11-15 23:26:58,967 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:58,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4275 states. [2019-11-15 23:26:59,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4275 to 4273. [2019-11-15 23:26:59,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4273 states. [2019-11-15 23:26:59,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4273 states to 4273 states and 5518 transitions. [2019-11-15 23:26:59,290 INFO L78 Accepts]: Start accepts. Automaton has 4273 states and 5518 transitions. Word has length 48 [2019-11-15 23:26:59,291 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:26:59,291 INFO L462 AbstractCegarLoop]: Abstraction has 4273 states and 5518 transitions. [2019-11-15 23:26:59,291 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:26:59,291 INFO L276 IsEmpty]: Start isEmpty. Operand 4273 states and 5518 transitions. [2019-11-15 23:26:59,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-15 23:26:59,292 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:26:59,293 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:26:59,293 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:26:59,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:26:59,293 INFO L82 PathProgramCache]: Analyzing trace with hash 57108908, now seen corresponding path program 1 times [2019-11-15 23:26:59,294 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:26:59,294 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [325040558] [2019-11-15 23:26:59,294 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:59,294 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:26:59,294 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:26:59,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:26:59,328 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:26:59,329 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [325040558] [2019-11-15 23:26:59,329 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:26:59,329 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:26:59,329 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181618858] [2019-11-15 23:26:59,329 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:26:59,330 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:26:59,330 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:26:59,330 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:59,330 INFO L87 Difference]: Start difference. First operand 4273 states and 5518 transitions. Second operand 3 states. [2019-11-15 23:26:59,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:26:59,721 INFO L93 Difference]: Finished difference Result 7967 states and 10312 transitions. [2019-11-15 23:26:59,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:26:59,723 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-15 23:26:59,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:26:59,743 INFO L225 Difference]: With dead ends: 7967 [2019-11-15 23:26:59,743 INFO L226 Difference]: Without dead ends: 3610 [2019-11-15 23:26:59,749 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:26:59,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3610 states. [2019-11-15 23:26:59,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3610 to 3465. [2019-11-15 23:26:59,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3465 states. [2019-11-15 23:27:00,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3465 states to 3465 states and 4400 transitions. [2019-11-15 23:27:00,004 INFO L78 Accepts]: Start accepts. Automaton has 3465 states and 4400 transitions. Word has length 49 [2019-11-15 23:27:00,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:00,004 INFO L462 AbstractCegarLoop]: Abstraction has 3465 states and 4400 transitions. [2019-11-15 23:27:00,004 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:27:00,004 INFO L276 IsEmpty]: Start isEmpty. Operand 3465 states and 4400 transitions. [2019-11-15 23:27:00,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2019-11-15 23:27:00,007 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:00,007 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:00,008 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:00,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:00,008 INFO L82 PathProgramCache]: Analyzing trace with hash 652914839, now seen corresponding path program 1 times [2019-11-15 23:27:00,008 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:00,009 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699656936] [2019-11-15 23:27:00,009 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:00,009 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:00,009 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:00,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:00,068 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-15 23:27:00,069 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699656936] [2019-11-15 23:27:00,069 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:27:00,069 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 23:27:00,069 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1350490351] [2019-11-15 23:27:00,070 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:27:00,070 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:00,070 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:27:00,071 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:00,071 INFO L87 Difference]: Start difference. First operand 3465 states and 4400 transitions. Second operand 3 states. [2019-11-15 23:27:00,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:00,306 INFO L93 Difference]: Finished difference Result 6369 states and 8143 transitions. [2019-11-15 23:27:00,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:27:00,307 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 83 [2019-11-15 23:27:00,307 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:00,327 INFO L225 Difference]: With dead ends: 6369 [2019-11-15 23:27:00,327 INFO L226 Difference]: Without dead ends: 3465 [2019-11-15 23:27:00,332 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:00,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3465 states. [2019-11-15 23:27:00,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3465 to 3465. [2019-11-15 23:27:00,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3465 states. [2019-11-15 23:27:00,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3465 states to 3465 states and 4336 transitions. [2019-11-15 23:27:00,654 INFO L78 Accepts]: Start accepts. Automaton has 3465 states and 4336 transitions. Word has length 83 [2019-11-15 23:27:00,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:00,655 INFO L462 AbstractCegarLoop]: Abstraction has 3465 states and 4336 transitions. [2019-11-15 23:27:00,655 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:27:00,655 INFO L276 IsEmpty]: Start isEmpty. Operand 3465 states and 4336 transitions. [2019-11-15 23:27:00,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2019-11-15 23:27:00,664 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:00,664 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:00,664 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:00,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:00,665 INFO L82 PathProgramCache]: Analyzing trace with hash -608848062, now seen corresponding path program 1 times [2019-11-15 23:27:00,665 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:00,665 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573242107] [2019-11-15 23:27:00,666 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:00,666 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:00,666 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:00,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:00,701 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:27:00,702 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573242107] [2019-11-15 23:27:00,702 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:27:00,702 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:27:00,702 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429381216] [2019-11-15 23:27:00,703 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:27:00,703 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:00,703 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:27:00,704 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:00,704 INFO L87 Difference]: Start difference. First operand 3465 states and 4336 transitions. Second operand 3 states. [2019-11-15 23:27:01,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:01,052 INFO L93 Difference]: Finished difference Result 7371 states and 9260 transitions. [2019-11-15 23:27:01,053 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:27:01,053 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 84 [2019-11-15 23:27:01,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:01,072 INFO L225 Difference]: With dead ends: 7371 [2019-11-15 23:27:01,072 INFO L226 Difference]: Without dead ends: 4154 [2019-11-15 23:27:01,077 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:01,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4154 states. [2019-11-15 23:27:01,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4154 to 3700. [2019-11-15 23:27:01,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3700 states. [2019-11-15 23:27:01,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3700 states to 3700 states and 4553 transitions. [2019-11-15 23:27:01,347 INFO L78 Accepts]: Start accepts. Automaton has 3700 states and 4553 transitions. Word has length 84 [2019-11-15 23:27:01,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:01,348 INFO L462 AbstractCegarLoop]: Abstraction has 3700 states and 4553 transitions. [2019-11-15 23:27:01,348 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:27:01,348 INFO L276 IsEmpty]: Start isEmpty. Operand 3700 states and 4553 transitions. [2019-11-15 23:27:01,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-15 23:27:01,351 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:01,351 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:01,351 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:01,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:01,352 INFO L82 PathProgramCache]: Analyzing trace with hash 885528412, now seen corresponding path program 1 times [2019-11-15 23:27:01,352 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:01,352 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205422649] [2019-11-15 23:27:01,352 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:01,353 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:01,353 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:01,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:01,388 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-15 23:27:01,388 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205422649] [2019-11-15 23:27:01,389 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:27:01,389 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 23:27:01,389 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [297700011] [2019-11-15 23:27:01,389 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:27:01,390 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:01,390 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:27:01,390 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:01,390 INFO L87 Difference]: Start difference. First operand 3700 states and 4553 transitions. Second operand 3 states. [2019-11-15 23:27:01,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:01,722 INFO L93 Difference]: Finished difference Result 7674 states and 9427 transitions. [2019-11-15 23:27:01,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:27:01,723 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-11-15 23:27:01,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:01,731 INFO L225 Difference]: With dead ends: 7674 [2019-11-15 23:27:01,731 INFO L226 Difference]: Without dead ends: 4176 [2019-11-15 23:27:01,737 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:01,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4176 states. [2019-11-15 23:27:02,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4176 to 4174. [2019-11-15 23:27:02,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4174 states. [2019-11-15 23:27:02,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4174 states to 4174 states and 5092 transitions. [2019-11-15 23:27:02,074 INFO L78 Accepts]: Start accepts. Automaton has 4174 states and 5092 transitions. Word has length 86 [2019-11-15 23:27:02,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:02,074 INFO L462 AbstractCegarLoop]: Abstraction has 4174 states and 5092 transitions. [2019-11-15 23:27:02,075 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:27:02,075 INFO L276 IsEmpty]: Start isEmpty. Operand 4174 states and 5092 transitions. [2019-11-15 23:27:02,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2019-11-15 23:27:02,077 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:02,077 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:02,077 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:02,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:02,078 INFO L82 PathProgramCache]: Analyzing trace with hash 1836340184, now seen corresponding path program 1 times [2019-11-15 23:27:02,078 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:02,078 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341892511] [2019-11-15 23:27:02,078 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:02,079 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:02,079 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:02,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:02,117 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:27:02,122 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341892511] [2019-11-15 23:27:02,124 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:27:02,124 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:27:02,124 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1409606554] [2019-11-15 23:27:02,124 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:27:02,125 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:02,125 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:27:02,125 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:02,125 INFO L87 Difference]: Start difference. First operand 4174 states and 5092 transitions. Second operand 3 states. [2019-11-15 23:27:02,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:02,347 INFO L93 Difference]: Finished difference Result 7056 states and 8680 transitions. [2019-11-15 23:27:02,348 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:27:02,348 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 98 [2019-11-15 23:27:02,348 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:02,354 INFO L225 Difference]: With dead ends: 7056 [2019-11-15 23:27:02,354 INFO L226 Difference]: Without dead ends: 3227 [2019-11-15 23:27:02,360 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:02,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3227 states. [2019-11-15 23:27:02,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3227 to 3223. [2019-11-15 23:27:02,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3223 states. [2019-11-15 23:27:02,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3223 states to 3223 states and 3862 transitions. [2019-11-15 23:27:02,569 INFO L78 Accepts]: Start accepts. Automaton has 3223 states and 3862 transitions. Word has length 98 [2019-11-15 23:27:02,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:02,569 INFO L462 AbstractCegarLoop]: Abstraction has 3223 states and 3862 transitions. [2019-11-15 23:27:02,569 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:27:02,570 INFO L276 IsEmpty]: Start isEmpty. Operand 3223 states and 3862 transitions. [2019-11-15 23:27:02,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2019-11-15 23:27:02,572 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:02,572 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:02,572 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:02,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:02,573 INFO L82 PathProgramCache]: Analyzing trace with hash 1328739563, now seen corresponding path program 1 times [2019-11-15 23:27:02,573 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:02,573 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919611233] [2019-11-15 23:27:02,573 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:02,574 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:02,574 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:02,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:02,626 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-15 23:27:02,626 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919611233] [2019-11-15 23:27:02,627 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:27:02,627 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 23:27:02,627 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [775686395] [2019-11-15 23:27:02,627 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:27:02,628 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:02,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:27:02,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:02,628 INFO L87 Difference]: Start difference. First operand 3223 states and 3862 transitions. Second operand 3 states. [2019-11-15 23:27:02,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:02,824 INFO L93 Difference]: Finished difference Result 5622 states and 6780 transitions. [2019-11-15 23:27:02,825 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:27:02,825 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 99 [2019-11-15 23:27:02,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:02,831 INFO L225 Difference]: With dead ends: 5622 [2019-11-15 23:27:02,831 INFO L226 Difference]: Without dead ends: 3075 [2019-11-15 23:27:02,835 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:02,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3075 states. [2019-11-15 23:27:03,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3075 to 3075. [2019-11-15 23:27:03,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3075 states. [2019-11-15 23:27:03,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3075 states to 3075 states and 3691 transitions. [2019-11-15 23:27:03,133 INFO L78 Accepts]: Start accepts. Automaton has 3075 states and 3691 transitions. Word has length 99 [2019-11-15 23:27:03,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:03,133 INFO L462 AbstractCegarLoop]: Abstraction has 3075 states and 3691 transitions. [2019-11-15 23:27:03,133 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:27:03,133 INFO L276 IsEmpty]: Start isEmpty. Operand 3075 states and 3691 transitions. [2019-11-15 23:27:03,138 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2019-11-15 23:27:03,139 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:03,139 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:03,139 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:03,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:03,140 INFO L82 PathProgramCache]: Analyzing trace with hash -472369520, now seen corresponding path program 1 times [2019-11-15 23:27:03,140 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:03,140 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2125210866] [2019-11-15 23:27:03,140 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:03,141 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:03,141 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:03,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:03,242 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-11-15 23:27:03,242 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2125210866] [2019-11-15 23:27:03,243 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:27:03,243 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-11-15 23:27:03,243 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803093508] [2019-11-15 23:27:03,244 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-11-15 23:27:03,244 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:03,244 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-15 23:27:03,244 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-11-15 23:27:03,245 INFO L87 Difference]: Start difference. First operand 3075 states and 3691 transitions. Second operand 8 states. [2019-11-15 23:27:03,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:03,642 INFO L93 Difference]: Finished difference Result 5286 states and 6380 transitions. [2019-11-15 23:27:03,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-15 23:27:03,643 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 104 [2019-11-15 23:27:03,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:03,647 INFO L225 Difference]: With dead ends: 5286 [2019-11-15 23:27:03,647 INFO L226 Difference]: Without dead ends: 2229 [2019-11-15 23:27:03,651 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-11-15 23:27:03,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2229 states. [2019-11-15 23:27:03,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2229 to 1920. [2019-11-15 23:27:03,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1920 states. [2019-11-15 23:27:03,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1920 states to 1920 states and 2325 transitions. [2019-11-15 23:27:03,849 INFO L78 Accepts]: Start accepts. Automaton has 1920 states and 2325 transitions. Word has length 104 [2019-11-15 23:27:03,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:03,850 INFO L462 AbstractCegarLoop]: Abstraction has 1920 states and 2325 transitions. [2019-11-15 23:27:03,850 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-11-15 23:27:03,850 INFO L276 IsEmpty]: Start isEmpty. Operand 1920 states and 2325 transitions. [2019-11-15 23:27:03,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2019-11-15 23:27:03,852 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:03,852 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:03,853 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:03,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:03,853 INFO L82 PathProgramCache]: Analyzing trace with hash 663738500, now seen corresponding path program 1 times [2019-11-15 23:27:03,853 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:03,853 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657430026] [2019-11-15 23:27:03,854 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:03,854 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:03,854 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:03,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:03,936 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-15 23:27:03,936 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [657430026] [2019-11-15 23:27:03,937 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:27:03,937 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:27:03,937 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [122554178] [2019-11-15 23:27:03,940 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:27:03,940 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:03,940 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:27:03,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:27:03,941 INFO L87 Difference]: Start difference. First operand 1920 states and 2325 transitions. Second operand 4 states. [2019-11-15 23:27:04,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:04,177 INFO L93 Difference]: Finished difference Result 4180 states and 5082 transitions. [2019-11-15 23:27:04,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-15 23:27:04,177 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 107 [2019-11-15 23:27:04,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:04,182 INFO L225 Difference]: With dead ends: 4180 [2019-11-15 23:27:04,182 INFO L226 Difference]: Without dead ends: 2423 [2019-11-15 23:27:04,186 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:27:04,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2423 states. [2019-11-15 23:27:04,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2423 to 2324. [2019-11-15 23:27:04,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2324 states. [2019-11-15 23:27:04,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2324 states to 2324 states and 2802 transitions. [2019-11-15 23:27:04,368 INFO L78 Accepts]: Start accepts. Automaton has 2324 states and 2802 transitions. Word has length 107 [2019-11-15 23:27:04,368 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:04,368 INFO L462 AbstractCegarLoop]: Abstraction has 2324 states and 2802 transitions. [2019-11-15 23:27:04,368 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:27:04,369 INFO L276 IsEmpty]: Start isEmpty. Operand 2324 states and 2802 transitions. [2019-11-15 23:27:04,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-11-15 23:27:04,370 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:04,371 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:04,371 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:04,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:04,372 INFO L82 PathProgramCache]: Analyzing trace with hash -1105184803, now seen corresponding path program 1 times [2019-11-15 23:27:04,372 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:04,372 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [732793525] [2019-11-15 23:27:04,372 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:04,373 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:04,373 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:04,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:04,411 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:27:04,412 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [732793525] [2019-11-15 23:27:04,412 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:27:04,412 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:27:04,412 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365650437] [2019-11-15 23:27:04,413 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:27:04,413 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:04,413 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:27:04,413 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:04,414 INFO L87 Difference]: Start difference. First operand 2324 states and 2802 transitions. Second operand 3 states. [2019-11-15 23:27:04,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:04,576 INFO L93 Difference]: Finished difference Result 3902 states and 4743 transitions. [2019-11-15 23:27:04,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:27:04,576 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-11-15 23:27:04,577 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:04,579 INFO L225 Difference]: With dead ends: 3902 [2019-11-15 23:27:04,579 INFO L226 Difference]: Without dead ends: 1655 [2019-11-15 23:27:04,582 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:04,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1655 states. [2019-11-15 23:27:04,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1655 to 1653. [2019-11-15 23:27:04,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1653 states. [2019-11-15 23:27:04,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1653 states to 1653 states and 1933 transitions. [2019-11-15 23:27:04,731 INFO L78 Accepts]: Start accepts. Automaton has 1653 states and 1933 transitions. Word has length 113 [2019-11-15 23:27:04,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:04,732 INFO L462 AbstractCegarLoop]: Abstraction has 1653 states and 1933 transitions. [2019-11-15 23:27:04,732 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:27:04,732 INFO L276 IsEmpty]: Start isEmpty. Operand 1653 states and 1933 transitions. [2019-11-15 23:27:04,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2019-11-15 23:27:04,733 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:04,734 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:04,734 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:04,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:04,734 INFO L82 PathProgramCache]: Analyzing trace with hash 1508765653, now seen corresponding path program 1 times [2019-11-15 23:27:04,735 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:04,735 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667116486] [2019-11-15 23:27:04,735 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:04,735 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:04,736 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:04,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:04,809 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-15 23:27:04,809 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667116486] [2019-11-15 23:27:04,809 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:27:04,810 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 23:27:04,810 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293861509] [2019-11-15 23:27:04,811 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 23:27:04,811 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:04,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 23:27:04,811 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:27:04,812 INFO L87 Difference]: Start difference. First operand 1653 states and 1933 transitions. Second operand 5 states. [2019-11-15 23:27:05,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:05,194 INFO L93 Difference]: Finished difference Result 4188 states and 4920 transitions. [2019-11-15 23:27:05,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-15 23:27:05,195 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 114 [2019-11-15 23:27:05,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:05,200 INFO L225 Difference]: With dead ends: 4188 [2019-11-15 23:27:05,200 INFO L226 Difference]: Without dead ends: 2940 [2019-11-15 23:27:05,203 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-15 23:27:05,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2940 states. [2019-11-15 23:27:05,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2940 to 1905. [2019-11-15 23:27:05,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1905 states. [2019-11-15 23:27:05,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1905 states to 1905 states and 2228 transitions. [2019-11-15 23:27:05,350 INFO L78 Accepts]: Start accepts. Automaton has 1905 states and 2228 transitions. Word has length 114 [2019-11-15 23:27:05,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:05,351 INFO L462 AbstractCegarLoop]: Abstraction has 1905 states and 2228 transitions. [2019-11-15 23:27:05,351 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 23:27:05,351 INFO L276 IsEmpty]: Start isEmpty. Operand 1905 states and 2228 transitions. [2019-11-15 23:27:05,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-11-15 23:27:05,352 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:05,352 INFO L380 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:05,353 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:05,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:05,353 INFO L82 PathProgramCache]: Analyzing trace with hash -1919382230, now seen corresponding path program 1 times [2019-11-15 23:27:05,353 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:05,354 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266462213] [2019-11-15 23:27:05,354 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:05,354 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:05,354 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:05,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:05,487 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-15 23:27:05,488 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266462213] [2019-11-15 23:27:05,488 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1654506235] [2019-11-15 23:27:05,488 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:27:05,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:05,589 INFO L256 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 9 conjunts are in the unsatisfiable core [2019-11-15 23:27:05,604 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:27:05,636 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-15 23:27:05,637 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:27:05,637 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2019-11-15 23:27:05,637 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436565840] [2019-11-15 23:27:05,638 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 23:27:05,638 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:05,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 23:27:05,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:27:05,639 INFO L87 Difference]: Start difference. First operand 1905 states and 2228 transitions. Second operand 5 states. [2019-11-15 23:27:05,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:05,973 INFO L93 Difference]: Finished difference Result 4107 states and 4811 transitions. [2019-11-15 23:27:05,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-15 23:27:05,974 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 118 [2019-11-15 23:27:05,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:05,980 INFO L225 Difference]: With dead ends: 4107 [2019-11-15 23:27:05,980 INFO L226 Difference]: Without dead ends: 3084 [2019-11-15 23:27:05,982 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 119 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-11-15 23:27:05,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3084 states. [2019-11-15 23:27:06,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3084 to 2067. [2019-11-15 23:27:06,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2067 states. [2019-11-15 23:27:06,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2067 states to 2067 states and 2410 transitions. [2019-11-15 23:27:06,165 INFO L78 Accepts]: Start accepts. Automaton has 2067 states and 2410 transitions. Word has length 118 [2019-11-15 23:27:06,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:06,166 INFO L462 AbstractCegarLoop]: Abstraction has 2067 states and 2410 transitions. [2019-11-15 23:27:06,166 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 23:27:06,166 INFO L276 IsEmpty]: Start isEmpty. Operand 2067 states and 2410 transitions. [2019-11-15 23:27:06,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2019-11-15 23:27:06,169 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:06,169 INFO L380 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:06,373 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:27:06,373 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:06,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:06,374 INFO L82 PathProgramCache]: Analyzing trace with hash -2045968037, now seen corresponding path program 1 times [2019-11-15 23:27:06,374 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:06,374 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983965913] [2019-11-15 23:27:06,374 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:06,375 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:06,375 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:06,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:06,444 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 129 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2019-11-15 23:27:06,445 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983965913] [2019-11-15 23:27:06,445 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:27:06,445 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:27:06,445 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145821556] [2019-11-15 23:27:06,446 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:27:06,446 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:06,447 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:27:06,447 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:06,447 INFO L87 Difference]: Start difference. First operand 2067 states and 2410 transitions. Second operand 3 states. [2019-11-15 23:27:06,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:06,706 INFO L93 Difference]: Finished difference Result 5041 states and 5868 transitions. [2019-11-15 23:27:06,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:27:06,707 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 172 [2019-11-15 23:27:06,707 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:06,712 INFO L225 Difference]: With dead ends: 5041 [2019-11-15 23:27:06,713 INFO L226 Difference]: Without dead ends: 3137 [2019-11-15 23:27:06,716 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:06,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3137 states. [2019-11-15 23:27:07,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3137 to 3087. [2019-11-15 23:27:07,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3087 states. [2019-11-15 23:27:07,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3087 states to 3087 states and 3575 transitions. [2019-11-15 23:27:07,014 INFO L78 Accepts]: Start accepts. Automaton has 3087 states and 3575 transitions. Word has length 172 [2019-11-15 23:27:07,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:07,015 INFO L462 AbstractCegarLoop]: Abstraction has 3087 states and 3575 transitions. [2019-11-15 23:27:07,015 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:27:07,015 INFO L276 IsEmpty]: Start isEmpty. Operand 3087 states and 3575 transitions. [2019-11-15 23:27:07,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2019-11-15 23:27:07,019 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:07,019 INFO L380 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:07,019 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:07,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:07,020 INFO L82 PathProgramCache]: Analyzing trace with hash 1191161181, now seen corresponding path program 1 times [2019-11-15 23:27:07,020 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:07,020 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124960008] [2019-11-15 23:27:07,020 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:07,021 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:07,021 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:07,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:27:07,068 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 99 proven. 0 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2019-11-15 23:27:07,069 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124960008] [2019-11-15 23:27:07,069 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:27:07,069 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:27:07,069 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1746161537] [2019-11-15 23:27:07,071 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:27:07,071 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:27:07,072 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:27:07,072 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:07,072 INFO L87 Difference]: Start difference. First operand 3087 states and 3575 transitions. Second operand 3 states. [2019-11-15 23:27:07,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:27:07,211 INFO L93 Difference]: Finished difference Result 4589 states and 5331 transitions. [2019-11-15 23:27:07,211 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:27:07,211 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 172 [2019-11-15 23:27:07,212 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:27:07,214 INFO L225 Difference]: With dead ends: 4589 [2019-11-15 23:27:07,215 INFO L226 Difference]: Without dead ends: 1619 [2019-11-15 23:27:07,218 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:27:07,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1619 states. [2019-11-15 23:27:07,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1619 to 1619. [2019-11-15 23:27:07,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1619 states. [2019-11-15 23:27:07,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1619 states to 1619 states and 1839 transitions. [2019-11-15 23:27:07,354 INFO L78 Accepts]: Start accepts. Automaton has 1619 states and 1839 transitions. Word has length 172 [2019-11-15 23:27:07,354 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:27:07,354 INFO L462 AbstractCegarLoop]: Abstraction has 1619 states and 1839 transitions. [2019-11-15 23:27:07,354 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:27:07,355 INFO L276 IsEmpty]: Start isEmpty. Operand 1619 states and 1839 transitions. [2019-11-15 23:27:07,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2019-11-15 23:27:07,357 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:27:07,357 INFO L380 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:27:07,357 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:27:07,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:27:07,358 INFO L82 PathProgramCache]: Analyzing trace with hash 1404970223, now seen corresponding path program 1 times [2019-11-15 23:27:07,358 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:27:07,358 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522293094] [2019-11-15 23:27:07,359 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:07,359 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:27:07,359 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:27:07,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 23:27:07,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 23:27:07,497 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 23:27:07,498 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-11-15 23:27:07,682 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 15.11 11:27:07 BoogieIcfgContainer [2019-11-15 23:27:07,683 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-15 23:27:07,683 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-15 23:27:07,683 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-15 23:27:07,684 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-15 23:27:07,684 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 11:26:54" (3/4) ... [2019-11-15 23:27:07,686 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-15 23:27:07,872 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_b667d6db-4c5a-4c22-a26f-ca3946a3e97b/bin/uautomizer/witness.graphml [2019-11-15 23:27:07,872 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-15 23:27:07,874 INFO L168 Benchmark]: Toolchain (without parser) took 15434.13 ms. Allocated memory was 1.0 GB in the beginning and 2.0 GB in the end (delta: 969.4 MB). Free memory was 950.2 MB in the beginning and 1.6 GB in the end (delta: -627.5 MB). Peak memory consumption was 341.9 MB. Max. memory is 11.5 GB. [2019-11-15 23:27:07,874 INFO L168 Benchmark]: CDTParser took 0.33 ms. Allocated memory is still 1.0 GB. Free memory is still 967.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-15 23:27:07,875 INFO L168 Benchmark]: CACSL2BoogieTranslator took 568.65 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 154.1 MB). Free memory was 950.2 MB in the beginning and 1.1 GB in the end (delta: -197.4 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. [2019-11-15 23:27:07,876 INFO L168 Benchmark]: Boogie Procedure Inliner took 69.28 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-15 23:27:07,876 INFO L168 Benchmark]: Boogie Preprocessor took 35.18 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-15 23:27:07,876 INFO L168 Benchmark]: RCFGBuilder took 1017.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 38.5 MB). Peak memory consumption was 38.5 MB. Max. memory is 11.5 GB. [2019-11-15 23:27:07,877 INFO L168 Benchmark]: TraceAbstraction took 13546.22 ms. Allocated memory was 1.2 GB in the beginning and 2.0 GB in the end (delta: 815.3 MB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -503.1 MB). Peak memory consumption was 312.2 MB. Max. memory is 11.5 GB. [2019-11-15 23:27:07,877 INFO L168 Benchmark]: Witness Printer took 188.84 ms. Allocated memory is still 2.0 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 29.2 MB). Peak memory consumption was 29.2 MB. Max. memory is 11.5 GB. [2019-11-15 23:27:07,879 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.33 ms. Allocated memory is still 1.0 GB. Free memory is still 967.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 568.65 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 154.1 MB). Free memory was 950.2 MB in the beginning and 1.1 GB in the end (delta: -197.4 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 69.28 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 35.18 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 1017.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 38.5 MB). Peak memory consumption was 38.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 13546.22 ms. Allocated memory was 1.2 GB in the beginning and 2.0 GB in the end (delta: 815.3 MB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -503.1 MB). Peak memory consumption was 312.2 MB. Max. memory is 11.5 GB. * Witness Printer took 188.84 ms. Allocated memory is still 2.0 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 29.2 MB). Peak memory consumption was 29.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 9]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int max_loop ; [L16] int num ; [L17] int i ; [L18] int e ; [L19] int timer ; [L20] char data_0 ; [L21] char data_1 ; [L64] int P_1_pc; [L65] int P_1_st ; [L66] int P_1_i ; [L67] int P_1_ev ; [L122] int C_1_pc ; [L123] int C_1_st ; [L124] int C_1_i ; [L125] int C_1_ev ; [L126] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L490] int count ; [L491] int __retres2 ; [L495] num = 0 [L496] i = 0 [L497] max_loop = 2 [L499] timer = 0 [L500] P_1_pc = 0 [L501] C_1_pc = 0 [L503] count = 0 [L483] P_1_i = 1 [L484] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L421] int kernel_st ; [L422] int tmp ; [L423] int tmp___0 ; [L427] kernel_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L226] COND TRUE (int )P_1_i == 1 [L227] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L231] COND TRUE (int )C_1_i == 1 [L232] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L107] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L117] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L119] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L186] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L189] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L209] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L211] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L435] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L294] COND TRUE (int )C_1_st == 0 [L296] tmp___1 = __VERIFIER_nondet_int() [L298] COND TRUE \read(tmp___1) [L300] C_1_st = 1 [L128] char c ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L131] COND TRUE (int )C_1_pc == 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L146] COND TRUE i < max_loop VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L148] COND TRUE num == 0 [L149] timer = 1 [L150] i += 1 [L151] C_1_pc = 1 [L152] C_1_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L72] COND TRUE (int )P_1_pc == 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L49] COND TRUE i___0 == 0 [L50] data_0 = c VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L417] return (__retres2); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L435] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND TRUE i___0 == 1 [L53] data_1 = c VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L417] return (__retres2); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L435] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND FALSE !(i___0 == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L9] __VERIFIER_error() VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 117 locations, 3 error locations. Result: UNSAFE, OverallTime: 13.4s, OverallIterations: 25, TraceHistogramMax: 6, AutomataDifference: 6.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4775 SDtfs, 4830 SDslu, 6046 SDs, 0 SdLazy, 568 SolverSat, 139 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 232 GetRequests, 169 SyntacticMatches, 3 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=4273occurred in iteration=10, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 4.4s AutomataMinimizationTime, 24 MinimizatonAttempts, 6607 StatesRemovedByMinimization, 20 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 2135 NumberOfCodeBlocks, 2135 NumberOfCodeBlocksAsserted, 26 NumberOfCheckSat, 1920 ConstructedInterpolants, 0 QuantifiedInterpolants, 350700 SizeOfPredicates, 2 NumberOfNonLiveVariables, 344 ConjunctsInSsa, 9 ConjunctsInUnsatCore, 25 InterpolantComputations, 23 PerfectInterpolantSequences, 619/689 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...