./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c -s /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2b1be4311b85b6fe57410228c7ae2544fffadecc ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-11-15 23:58:00,770 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-15 23:58:00,772 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-15 23:58:00,786 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-15 23:58:00,787 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-15 23:58:00,788 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-15 23:58:00,790 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-15 23:58:00,800 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-15 23:58:00,804 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-15 23:58:00,806 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-15 23:58:00,807 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-15 23:58:00,808 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-15 23:58:00,808 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-15 23:58:00,809 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-15 23:58:00,810 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-15 23:58:00,811 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-15 23:58:00,811 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-15 23:58:00,812 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-15 23:58:00,814 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-15 23:58:00,816 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-15 23:58:00,817 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-15 23:58:00,818 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-15 23:58:00,819 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-15 23:58:00,820 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-15 23:58:00,822 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-15 23:58:00,822 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-15 23:58:00,823 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-15 23:58:00,824 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-15 23:58:00,824 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-15 23:58:00,825 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-15 23:58:00,825 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-15 23:58:00,826 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-15 23:58:00,827 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-15 23:58:00,828 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-15 23:58:00,829 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-15 23:58:00,829 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-15 23:58:00,830 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-15 23:58:00,830 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-15 23:58:00,830 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-15 23:58:00,831 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-15 23:58:00,832 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-15 23:58:00,832 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-15 23:58:00,845 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-15 23:58:00,845 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-15 23:58:00,847 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-15 23:58:00,847 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-15 23:58:00,847 INFO L138 SettingsManager]: * Use SBE=true [2019-11-15 23:58:00,847 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-15 23:58:00,848 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-15 23:58:00,848 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-15 23:58:00,848 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-15 23:58:00,848 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-15 23:58:00,849 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-15 23:58:00,849 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-15 23:58:00,849 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-15 23:58:00,849 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-15 23:58:00,850 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-15 23:58:00,850 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-15 23:58:00,850 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-15 23:58:00,850 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-15 23:58:00,851 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-15 23:58:00,851 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-15 23:58:00,851 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-15 23:58:00,851 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 23:58:00,852 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-15 23:58:00,852 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-15 23:58:00,852 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-15 23:58:00,852 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-15 23:58:00,853 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-15 23:58:00,853 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-15 23:58:00,853 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2b1be4311b85b6fe57410228c7ae2544fffadecc [2019-11-15 23:58:00,878 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-15 23:58:00,888 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-15 23:58:00,891 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-15 23:58:00,893 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-15 23:58:00,893 INFO L275 PluginConnector]: CDTParser initialized [2019-11-15 23:58:00,894 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2019-11-15 23:58:00,944 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/data/e8d55f7f4/b48d96d8f75447ec95e9ef577391f0b0/FLAG7f4fb6c18 [2019-11-15 23:58:01,425 INFO L306 CDTParser]: Found 1 translation units. [2019-11-15 23:58:01,427 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2019-11-15 23:58:01,440 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/data/e8d55f7f4/b48d96d8f75447ec95e9ef577391f0b0/FLAG7f4fb6c18 [2019-11-15 23:58:01,913 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/data/e8d55f7f4/b48d96d8f75447ec95e9ef577391f0b0 [2019-11-15 23:58:01,915 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-15 23:58:01,916 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-15 23:58:01,917 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-15 23:58:01,917 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-15 23:58:01,921 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-15 23:58:01,922 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 11:58:01" (1/1) ... [2019-11-15 23:58:01,925 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2b053f22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:01, skipping insertion in model container [2019-11-15 23:58:01,925 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 11:58:01" (1/1) ... [2019-11-15 23:58:01,932 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-15 23:58:01,987 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-15 23:58:02,353 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 23:58:02,373 INFO L188 MainTranslator]: Completed pre-run [2019-11-15 23:58:02,454 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 23:58:02,475 INFO L192 MainTranslator]: Completed translation [2019-11-15 23:58:02,477 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02 WrapperNode [2019-11-15 23:58:02,478 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-15 23:58:02,478 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-15 23:58:02,479 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-15 23:58:02,479 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-15 23:58:02,486 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02" (1/1) ... [2019-11-15 23:58:02,497 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02" (1/1) ... [2019-11-15 23:58:02,543 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-15 23:58:02,543 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-15 23:58:02,543 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-15 23:58:02,544 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-15 23:58:02,556 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02" (1/1) ... [2019-11-15 23:58:02,556 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02" (1/1) ... [2019-11-15 23:58:02,563 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02" (1/1) ... [2019-11-15 23:58:02,564 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02" (1/1) ... [2019-11-15 23:58:02,580 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02" (1/1) ... [2019-11-15 23:58:02,592 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02" (1/1) ... [2019-11-15 23:58:02,597 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02" (1/1) ... [2019-11-15 23:58:02,613 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-15 23:58:02,614 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-15 23:58:02,614 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-15 23:58:02,614 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-15 23:58:02,615 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 23:58:02,671 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-15 23:58:02,672 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-15 23:58:03,978 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-15 23:58:03,979 INFO L284 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-15 23:58:03,980 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 11:58:03 BoogieIcfgContainer [2019-11-15 23:58:03,980 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-15 23:58:03,981 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-15 23:58:03,981 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-15 23:58:03,983 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-15 23:58:03,983 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 15.11 11:58:01" (1/3) ... [2019-11-15 23:58:03,983 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@206740b1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 11:58:03, skipping insertion in model container [2019-11-15 23:58:03,983 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 11:58:02" (2/3) ... [2019-11-15 23:58:03,984 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@206740b1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 11:58:03, skipping insertion in model container [2019-11-15 23:58:03,984 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 11:58:03" (3/3) ... [2019-11-15 23:58:03,988 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2019-11-15 23:58:03,998 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-15 23:58:04,006 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-11-15 23:58:04,018 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-11-15 23:58:04,048 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-15 23:58:04,049 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-15 23:58:04,049 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-15 23:58:04,049 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-15 23:58:04,049 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-15 23:58:04,049 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-15 23:58:04,050 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-15 23:58:04,050 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-15 23:58:04,076 INFO L276 IsEmpty]: Start isEmpty. Operand 291 states. [2019-11-15 23:58:04,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-11-15 23:58:04,083 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:04,084 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:04,087 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:04,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:04,092 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-11-15 23:58:04,100 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:04,100 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445843457] [2019-11-15 23:58:04,100 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:04,100 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:04,100 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:04,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:04,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:04,333 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445843457] [2019-11-15 23:58:04,334 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:04,334 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:58:04,334 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [839405934] [2019-11-15 23:58:04,338 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:58:04,339 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:04,351 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:58:04,352 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:04,354 INFO L87 Difference]: Start difference. First operand 291 states. Second operand 3 states. [2019-11-15 23:58:04,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:04,428 INFO L93 Difference]: Finished difference Result 568 states and 884 transitions. [2019-11-15 23:58:04,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:58:04,430 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-11-15 23:58:04,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:04,444 INFO L225 Difference]: With dead ends: 568 [2019-11-15 23:58:04,444 INFO L226 Difference]: Without dead ends: 287 [2019-11-15 23:58:04,449 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:04,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2019-11-15 23:58:04,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 287. [2019-11-15 23:58:04,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 287 states. [2019-11-15 23:58:04,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 287 states to 287 states and 409 transitions. [2019-11-15 23:58:04,501 INFO L78 Accepts]: Start accepts. Automaton has 287 states and 409 transitions. Word has length 31 [2019-11-15 23:58:04,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:04,502 INFO L462 AbstractCegarLoop]: Abstraction has 287 states and 409 transitions. [2019-11-15 23:58:04,502 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:58:04,502 INFO L276 IsEmpty]: Start isEmpty. Operand 287 states and 409 transitions. [2019-11-15 23:58:04,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-11-15 23:58:04,503 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:04,504 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:04,504 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:04,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:04,505 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-11-15 23:58:04,505 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:04,505 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56110064] [2019-11-15 23:58:04,505 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:04,506 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:04,506 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:04,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:04,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:04,680 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56110064] [2019-11-15 23:58:04,680 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:04,680 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:58:04,680 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134668067] [2019-11-15 23:58:04,682 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:58:04,682 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:04,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:58:04,683 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:04,683 INFO L87 Difference]: Start difference. First operand 287 states and 409 transitions. Second operand 3 states. [2019-11-15 23:58:04,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:04,746 INFO L93 Difference]: Finished difference Result 593 states and 853 transitions. [2019-11-15 23:58:04,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:58:04,746 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-11-15 23:58:04,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:04,749 INFO L225 Difference]: With dead ends: 593 [2019-11-15 23:58:04,749 INFO L226 Difference]: Without dead ends: 321 [2019-11-15 23:58:04,751 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:04,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2019-11-15 23:58:04,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 263. [2019-11-15 23:58:04,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 263 states. [2019-11-15 23:58:04,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 263 states to 263 states and 373 transitions. [2019-11-15 23:58:04,767 INFO L78 Accepts]: Start accepts. Automaton has 263 states and 373 transitions. Word has length 42 [2019-11-15 23:58:04,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:04,768 INFO L462 AbstractCegarLoop]: Abstraction has 263 states and 373 transitions. [2019-11-15 23:58:04,768 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:58:04,768 INFO L276 IsEmpty]: Start isEmpty. Operand 263 states and 373 transitions. [2019-11-15 23:58:04,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-15 23:58:04,770 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:04,770 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:04,771 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:04,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:04,772 INFO L82 PathProgramCache]: Analyzing trace with hash -365626229, now seen corresponding path program 1 times [2019-11-15 23:58:04,772 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:04,772 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236266639] [2019-11-15 23:58:04,772 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:04,773 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:04,773 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:04,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:04,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:04,919 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1236266639] [2019-11-15 23:58:04,919 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:04,919 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:58:04,920 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717578480] [2019-11-15 23:58:04,920 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:58:04,920 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:04,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:58:04,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:04,925 INFO L87 Difference]: Start difference. First operand 263 states and 373 transitions. Second operand 3 states. [2019-11-15 23:58:04,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:04,974 INFO L93 Difference]: Finished difference Result 736 states and 1054 transitions. [2019-11-15 23:58:04,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:58:04,975 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-15 23:58:04,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:04,978 INFO L225 Difference]: With dead ends: 736 [2019-11-15 23:58:04,980 INFO L226 Difference]: Without dead ends: 488 [2019-11-15 23:58:04,981 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:04,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states. [2019-11-15 23:58:05,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 296. [2019-11-15 23:58:05,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 296 states. [2019-11-15 23:58:05,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 296 states to 296 states and 421 transitions. [2019-11-15 23:58:05,005 INFO L78 Accepts]: Start accepts. Automaton has 296 states and 421 transitions. Word has length 49 [2019-11-15 23:58:05,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:05,005 INFO L462 AbstractCegarLoop]: Abstraction has 296 states and 421 transitions. [2019-11-15 23:58:05,006 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:58:05,006 INFO L276 IsEmpty]: Start isEmpty. Operand 296 states and 421 transitions. [2019-11-15 23:58:05,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-11-15 23:58:05,008 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:05,008 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:05,009 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:05,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:05,010 INFO L82 PathProgramCache]: Analyzing trace with hash 744745200, now seen corresponding path program 1 times [2019-11-15 23:58:05,010 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:05,010 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171525557] [2019-11-15 23:58:05,010 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:05,011 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:05,011 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:05,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:05,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:05,122 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171525557] [2019-11-15 23:58:05,122 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:05,122 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:58:05,123 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1307989519] [2019-11-15 23:58:05,123 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 23:58:05,124 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:05,124 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 23:58:05,124 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:05,124 INFO L87 Difference]: Start difference. First operand 296 states and 421 transitions. Second operand 5 states. [2019-11-15 23:58:05,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:05,406 INFO L93 Difference]: Finished difference Result 932 states and 1340 transitions. [2019-11-15 23:58:05,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 23:58:05,407 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-11-15 23:58:05,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:05,411 INFO L225 Difference]: With dead ends: 932 [2019-11-15 23:58:05,412 INFO L226 Difference]: Without dead ends: 651 [2019-11-15 23:58:05,413 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-15 23:58:05,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 651 states. [2019-11-15 23:58:05,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 651 to 382. [2019-11-15 23:58:05,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2019-11-15 23:58:05,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 544 transitions. [2019-11-15 23:58:05,436 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 544 transitions. Word has length 50 [2019-11-15 23:58:05,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:05,437 INFO L462 AbstractCegarLoop]: Abstraction has 382 states and 544 transitions. [2019-11-15 23:58:05,437 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 23:58:05,437 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 544 transitions. [2019-11-15 23:58:05,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-11-15 23:58:05,439 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:05,440 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:05,440 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:05,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:05,441 INFO L82 PathProgramCache]: Analyzing trace with hash 1614483527, now seen corresponding path program 1 times [2019-11-15 23:58:05,441 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:05,441 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826639680] [2019-11-15 23:58:05,442 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:05,442 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:05,442 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:05,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:05,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:05,570 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826639680] [2019-11-15 23:58:05,570 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:05,570 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:58:05,571 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852174351] [2019-11-15 23:58:05,571 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 23:58:05,572 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:05,572 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 23:58:05,573 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:05,573 INFO L87 Difference]: Start difference. First operand 382 states and 544 transitions. Second operand 5 states. [2019-11-15 23:58:05,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:05,831 INFO L93 Difference]: Finished difference Result 932 states and 1336 transitions. [2019-11-15 23:58:05,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 23:58:05,832 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-11-15 23:58:05,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:05,838 INFO L225 Difference]: With dead ends: 932 [2019-11-15 23:58:05,839 INFO L226 Difference]: Without dead ends: 651 [2019-11-15 23:58:05,840 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-15 23:58:05,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 651 states. [2019-11-15 23:58:05,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 651 to 382. [2019-11-15 23:58:05,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2019-11-15 23:58:05,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 542 transitions. [2019-11-15 23:58:05,864 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 542 transitions. Word has length 51 [2019-11-15 23:58:05,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:05,865 INFO L462 AbstractCegarLoop]: Abstraction has 382 states and 542 transitions. [2019-11-15 23:58:05,866 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 23:58:05,866 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 542 transitions. [2019-11-15 23:58:05,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-15 23:58:05,874 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:05,874 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:05,875 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:05,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:05,875 INFO L82 PathProgramCache]: Analyzing trace with hash 251892323, now seen corresponding path program 1 times [2019-11-15 23:58:05,876 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:05,876 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077894317] [2019-11-15 23:58:05,876 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:05,876 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:05,877 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:05,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:06,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:06,047 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077894317] [2019-11-15 23:58:06,047 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:06,047 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 23:58:06,048 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705372833] [2019-11-15 23:58:06,048 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 23:58:06,048 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:06,048 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 23:58:06,049 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:06,049 INFO L87 Difference]: Start difference. First operand 382 states and 542 transitions. Second operand 5 states. [2019-11-15 23:58:06,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:06,105 INFO L93 Difference]: Finished difference Result 760 states and 1089 transitions. [2019-11-15 23:58:06,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-15 23:58:06,106 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2019-11-15 23:58:06,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:06,109 INFO L225 Difference]: With dead ends: 760 [2019-11-15 23:58:06,110 INFO L226 Difference]: Without dead ends: 479 [2019-11-15 23:58:06,111 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-11-15 23:58:06,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states. [2019-11-15 23:58:06,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 377. [2019-11-15 23:58:06,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 377 states. [2019-11-15 23:58:06,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 377 states to 377 states and 534 transitions. [2019-11-15 23:58:06,133 INFO L78 Accepts]: Start accepts. Automaton has 377 states and 534 transitions. Word has length 52 [2019-11-15 23:58:06,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:06,133 INFO L462 AbstractCegarLoop]: Abstraction has 377 states and 534 transitions. [2019-11-15 23:58:06,134 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 23:58:06,134 INFO L276 IsEmpty]: Start isEmpty. Operand 377 states and 534 transitions. [2019-11-15 23:58:06,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-15 23:58:06,135 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:06,135 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:06,135 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:06,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:06,143 INFO L82 PathProgramCache]: Analyzing trace with hash -1519937093, now seen corresponding path program 1 times [2019-11-15 23:58:06,143 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:06,143 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539960855] [2019-11-15 23:58:06,143 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:06,144 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:06,144 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:06,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:06,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:06,322 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539960855] [2019-11-15 23:58:06,322 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:06,322 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 23:58:06,323 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1405697409] [2019-11-15 23:58:06,323 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 23:58:06,323 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:06,323 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 23:58:06,323 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:06,324 INFO L87 Difference]: Start difference. First operand 377 states and 534 transitions. Second operand 5 states. [2019-11-15 23:58:06,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:06,455 INFO L93 Difference]: Finished difference Result 791 states and 1138 transitions. [2019-11-15 23:58:06,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:58:06,456 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-11-15 23:58:06,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:06,460 INFO L225 Difference]: With dead ends: 791 [2019-11-15 23:58:06,460 INFO L226 Difference]: Without dead ends: 515 [2019-11-15 23:58:06,461 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-15 23:58:06,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 515 states. [2019-11-15 23:58:06,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 515 to 347. [2019-11-15 23:58:06,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 347 states. [2019-11-15 23:58:06,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 347 states to 347 states and 488 transitions. [2019-11-15 23:58:06,487 INFO L78 Accepts]: Start accepts. Automaton has 347 states and 488 transitions. Word has length 56 [2019-11-15 23:58:06,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:06,488 INFO L462 AbstractCegarLoop]: Abstraction has 347 states and 488 transitions. [2019-11-15 23:58:06,489 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 23:58:06,489 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 488 transitions. [2019-11-15 23:58:06,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-15 23:58:06,490 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:06,490 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:06,491 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:06,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:06,491 INFO L82 PathProgramCache]: Analyzing trace with hash 1786376721, now seen corresponding path program 1 times [2019-11-15 23:58:06,491 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:06,492 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [710358634] [2019-11-15 23:58:06,492 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:06,492 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:06,493 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:06,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:06,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:06,654 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [710358634] [2019-11-15 23:58:06,654 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:06,654 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 23:58:06,655 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168909327] [2019-11-15 23:58:06,655 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 23:58:06,655 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:06,655 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 23:58:06,655 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:06,656 INFO L87 Difference]: Start difference. First operand 347 states and 488 transitions. Second operand 5 states. [2019-11-15 23:58:06,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:06,781 INFO L93 Difference]: Finished difference Result 884 states and 1260 transitions. [2019-11-15 23:58:06,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:58:06,782 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 61 [2019-11-15 23:58:06,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:06,786 INFO L225 Difference]: With dead ends: 884 [2019-11-15 23:58:06,787 INFO L226 Difference]: Without dead ends: 638 [2019-11-15 23:58:06,787 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-15 23:58:06,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 638 states. [2019-11-15 23:58:06,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 638 to 317. [2019-11-15 23:58:06,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2019-11-15 23:58:06,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 442 transitions. [2019-11-15 23:58:06,812 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 442 transitions. Word has length 61 [2019-11-15 23:58:06,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:06,812 INFO L462 AbstractCegarLoop]: Abstraction has 317 states and 442 transitions. [2019-11-15 23:58:06,812 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 23:58:06,812 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 442 transitions. [2019-11-15 23:58:06,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-11-15 23:58:06,813 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:06,813 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:06,814 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:06,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:06,814 INFO L82 PathProgramCache]: Analyzing trace with hash -1245848025, now seen corresponding path program 1 times [2019-11-15 23:58:06,815 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:06,815 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797770349] [2019-11-15 23:58:06,815 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:06,815 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:06,815 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:06,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:06,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:06,964 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797770349] [2019-11-15 23:58:06,965 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:06,965 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 23:58:06,965 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782487731] [2019-11-15 23:58:06,966 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:58:06,966 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:06,966 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:58:06,967 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 23:58:06,967 INFO L87 Difference]: Start difference. First operand 317 states and 442 transitions. Second operand 6 states. [2019-11-15 23:58:07,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:07,232 INFO L93 Difference]: Finished difference Result 1081 states and 1520 transitions. [2019-11-15 23:58:07,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-15 23:58:07,233 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-11-15 23:58:07,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:07,238 INFO L225 Difference]: With dead ends: 1081 [2019-11-15 23:58:07,238 INFO L226 Difference]: Without dead ends: 865 [2019-11-15 23:58:07,239 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-15 23:58:07,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 865 states. [2019-11-15 23:58:07,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 865 to 356. [2019-11-15 23:58:07,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 356 states. [2019-11-15 23:58:07,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 356 states to 356 states and 496 transitions. [2019-11-15 23:58:07,277 INFO L78 Accepts]: Start accepts. Automaton has 356 states and 496 transitions. Word has length 66 [2019-11-15 23:58:07,277 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:07,277 INFO L462 AbstractCegarLoop]: Abstraction has 356 states and 496 transitions. [2019-11-15 23:58:07,277 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:58:07,278 INFO L276 IsEmpty]: Start isEmpty. Operand 356 states and 496 transitions. [2019-11-15 23:58:07,278 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-11-15 23:58:07,278 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:07,279 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:07,279 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:07,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:07,280 INFO L82 PathProgramCache]: Analyzing trace with hash 1591247394, now seen corresponding path program 1 times [2019-11-15 23:58:07,280 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:07,280 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882319572] [2019-11-15 23:58:07,280 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:07,280 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:07,281 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:07,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:07,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:07,370 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882319572] [2019-11-15 23:58:07,370 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:07,370 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:58:07,370 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071447621] [2019-11-15 23:58:07,371 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:58:07,371 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:07,371 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:58:07,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:07,371 INFO L87 Difference]: Start difference. First operand 356 states and 496 transitions. Second operand 3 states. [2019-11-15 23:58:07,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:07,433 INFO L93 Difference]: Finished difference Result 650 states and 915 transitions. [2019-11-15 23:58:07,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:58:07,434 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-11-15 23:58:07,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:07,437 INFO L225 Difference]: With dead ends: 650 [2019-11-15 23:58:07,437 INFO L226 Difference]: Without dead ends: 434 [2019-11-15 23:58:07,437 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:07,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 434 states. [2019-11-15 23:58:07,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 434 to 352. [2019-11-15 23:58:07,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2019-11-15 23:58:07,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 489 transitions. [2019-11-15 23:58:07,463 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 489 transitions. Word has length 67 [2019-11-15 23:58:07,463 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:07,463 INFO L462 AbstractCegarLoop]: Abstraction has 352 states and 489 transitions. [2019-11-15 23:58:07,463 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:58:07,464 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 489 transitions. [2019-11-15 23:58:07,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-11-15 23:58:07,464 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:07,464 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:07,465 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:07,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:07,466 INFO L82 PathProgramCache]: Analyzing trace with hash 480130565, now seen corresponding path program 1 times [2019-11-15 23:58:07,466 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:07,466 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597800996] [2019-11-15 23:58:07,466 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:07,466 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:07,467 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:07,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:07,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:07,518 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597800996] [2019-11-15 23:58:07,518 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:07,519 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:58:07,519 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2054637808] [2019-11-15 23:58:07,519 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:58:07,519 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:07,520 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:58:07,520 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:58:07,520 INFO L87 Difference]: Start difference. First operand 352 states and 489 transitions. Second operand 4 states. [2019-11-15 23:58:07,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:07,665 INFO L93 Difference]: Finished difference Result 937 states and 1304 transitions. [2019-11-15 23:58:07,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:58:07,666 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 70 [2019-11-15 23:58:07,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:07,670 INFO L225 Difference]: With dead ends: 937 [2019-11-15 23:58:07,670 INFO L226 Difference]: Without dead ends: 715 [2019-11-15 23:58:07,671 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:07,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 715 states. [2019-11-15 23:58:07,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 715 to 518. [2019-11-15 23:58:07,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2019-11-15 23:58:07,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 716 transitions. [2019-11-15 23:58:07,708 INFO L78 Accepts]: Start accepts. Automaton has 518 states and 716 transitions. Word has length 70 [2019-11-15 23:58:07,709 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:07,709 INFO L462 AbstractCegarLoop]: Abstraction has 518 states and 716 transitions. [2019-11-15 23:58:07,709 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:58:07,709 INFO L276 IsEmpty]: Start isEmpty. Operand 518 states and 716 transitions. [2019-11-15 23:58:07,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-11-15 23:58:07,710 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:07,710 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:07,711 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:07,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:07,711 INFO L82 PathProgramCache]: Analyzing trace with hash -1523824051, now seen corresponding path program 1 times [2019-11-15 23:58:07,712 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:07,712 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990166097] [2019-11-15 23:58:07,712 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:07,712 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:07,712 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:07,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:07,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:07,753 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990166097] [2019-11-15 23:58:07,753 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:07,754 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:58:07,754 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247239061] [2019-11-15 23:58:07,754 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:58:07,754 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:07,755 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:58:07,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:07,755 INFO L87 Difference]: Start difference. First operand 518 states and 716 transitions. Second operand 3 states. [2019-11-15 23:58:07,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:07,821 INFO L93 Difference]: Finished difference Result 1223 states and 1682 transitions. [2019-11-15 23:58:07,821 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:58:07,822 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-11-15 23:58:07,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:07,826 INFO L225 Difference]: With dead ends: 1223 [2019-11-15 23:58:07,827 INFO L226 Difference]: Without dead ends: 852 [2019-11-15 23:58:07,828 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:07,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 852 states. [2019-11-15 23:58:07,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 852 to 579. [2019-11-15 23:58:07,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 579 states. [2019-11-15 23:58:07,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 579 states to 579 states and 793 transitions. [2019-11-15 23:58:07,870 INFO L78 Accepts]: Start accepts. Automaton has 579 states and 793 transitions. Word has length 70 [2019-11-15 23:58:07,870 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:07,870 INFO L462 AbstractCegarLoop]: Abstraction has 579 states and 793 transitions. [2019-11-15 23:58:07,870 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:58:07,871 INFO L276 IsEmpty]: Start isEmpty. Operand 579 states and 793 transitions. [2019-11-15 23:58:07,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-11-15 23:58:07,872 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:07,872 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:07,872 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:07,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:07,873 INFO L82 PathProgramCache]: Analyzing trace with hash -1383275441, now seen corresponding path program 1 times [2019-11-15 23:58:07,873 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:07,873 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970972085] [2019-11-15 23:58:07,873 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:07,874 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:07,874 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:07,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:07,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:07,916 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970972085] [2019-11-15 23:58:07,917 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:07,917 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:58:07,917 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684018215] [2019-11-15 23:58:07,917 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:58:07,917 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:07,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:58:07,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:07,918 INFO L87 Difference]: Start difference. First operand 579 states and 793 transitions. Second operand 3 states. [2019-11-15 23:58:07,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:07,959 INFO L93 Difference]: Finished difference Result 984 states and 1357 transitions. [2019-11-15 23:58:07,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:58:07,959 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-11-15 23:58:07,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:07,962 INFO L225 Difference]: With dead ends: 984 [2019-11-15 23:58:07,963 INFO L226 Difference]: Without dead ends: 544 [2019-11-15 23:58:07,964 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:07,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 544 states. [2019-11-15 23:58:07,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 544 to 544. [2019-11-15 23:58:07,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2019-11-15 23:58:08,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 744 transitions. [2019-11-15 23:58:08,001 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 744 transitions. Word has length 70 [2019-11-15 23:58:08,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:08,002 INFO L462 AbstractCegarLoop]: Abstraction has 544 states and 744 transitions. [2019-11-15 23:58:08,002 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:58:08,002 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 744 transitions. [2019-11-15 23:58:08,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-11-15 23:58:08,003 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:08,003 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:08,004 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:08,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:08,004 INFO L82 PathProgramCache]: Analyzing trace with hash -1837662732, now seen corresponding path program 1 times [2019-11-15 23:58:08,004 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:08,005 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687872649] [2019-11-15 23:58:08,005 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:08,005 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:08,005 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:08,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:08,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:08,129 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687872649] [2019-11-15 23:58:08,129 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:08,129 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 23:58:08,130 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901217951] [2019-11-15 23:58:08,130 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:58:08,130 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:08,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:58:08,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 23:58:08,131 INFO L87 Difference]: Start difference. First operand 544 states and 744 transitions. Second operand 6 states. [2019-11-15 23:58:08,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:08,505 INFO L93 Difference]: Finished difference Result 1710 states and 2373 transitions. [2019-11-15 23:58:08,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-15 23:58:08,506 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-11-15 23:58:08,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:08,513 INFO L225 Difference]: With dead ends: 1710 [2019-11-15 23:58:08,513 INFO L226 Difference]: Without dead ends: 1386 [2019-11-15 23:58:08,517 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-15 23:58:08,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1386 states. [2019-11-15 23:58:08,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1386 to 548. [2019-11-15 23:58:08,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 548 states. [2019-11-15 23:58:08,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 548 states to 548 states and 749 transitions. [2019-11-15 23:58:08,561 INFO L78 Accepts]: Start accepts. Automaton has 548 states and 749 transitions. Word has length 71 [2019-11-15 23:58:08,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:08,561 INFO L462 AbstractCegarLoop]: Abstraction has 548 states and 749 transitions. [2019-11-15 23:58:08,561 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:58:08,562 INFO L276 IsEmpty]: Start isEmpty. Operand 548 states and 749 transitions. [2019-11-15 23:58:08,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-11-15 23:58:08,563 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:08,563 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:08,563 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:08,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:08,564 INFO L82 PathProgramCache]: Analyzing trace with hash 276642491, now seen corresponding path program 1 times [2019-11-15 23:58:08,564 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:08,564 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590009263] [2019-11-15 23:58:08,564 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:08,565 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:08,565 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:08,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:08,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:08,660 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590009263] [2019-11-15 23:58:08,660 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:08,660 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 23:58:08,660 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207841347] [2019-11-15 23:58:08,660 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 23:58:08,660 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:08,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 23:58:08,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:08,661 INFO L87 Difference]: Start difference. First operand 548 states and 749 transitions. Second operand 5 states. [2019-11-15 23:58:08,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:08,824 INFO L93 Difference]: Finished difference Result 858 states and 1189 transitions. [2019-11-15 23:58:08,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 23:58:08,825 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2019-11-15 23:58:08,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:08,829 INFO L225 Difference]: With dead ends: 858 [2019-11-15 23:58:08,829 INFO L226 Difference]: Without dead ends: 856 [2019-11-15 23:58:08,832 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-15 23:58:08,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 856 states. [2019-11-15 23:58:08,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 856 to 550. [2019-11-15 23:58:08,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 550 states. [2019-11-15 23:58:08,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 751 transitions. [2019-11-15 23:58:08,877 INFO L78 Accepts]: Start accepts. Automaton has 550 states and 751 transitions. Word has length 71 [2019-11-15 23:58:08,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:08,878 INFO L462 AbstractCegarLoop]: Abstraction has 550 states and 751 transitions. [2019-11-15 23:58:08,878 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 23:58:08,878 INFO L276 IsEmpty]: Start isEmpty. Operand 550 states and 751 transitions. [2019-11-15 23:58:08,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-11-15 23:58:08,879 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:08,879 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:08,879 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:08,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:08,880 INFO L82 PathProgramCache]: Analyzing trace with hash -66828782, now seen corresponding path program 1 times [2019-11-15 23:58:08,880 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:08,880 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611982102] [2019-11-15 23:58:08,880 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:08,881 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:08,881 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:08,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:08,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:08,995 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611982102] [2019-11-15 23:58:08,997 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:08,997 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 23:58:08,998 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033683231] [2019-11-15 23:58:08,998 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:58:08,998 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:08,998 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:58:08,999 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 23:58:08,999 INFO L87 Difference]: Start difference. First operand 550 states and 751 transitions. Second operand 6 states. [2019-11-15 23:58:09,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:09,522 INFO L93 Difference]: Finished difference Result 1977 states and 2718 transitions. [2019-11-15 23:58:09,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-15 23:58:09,522 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-11-15 23:58:09,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:09,531 INFO L225 Difference]: With dead ends: 1977 [2019-11-15 23:58:09,531 INFO L226 Difference]: Without dead ends: 1612 [2019-11-15 23:58:09,532 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-15 23:58:09,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1612 states. [2019-11-15 23:58:09,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1612 to 596. [2019-11-15 23:58:09,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 596 states. [2019-11-15 23:58:09,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 596 states and 809 transitions. [2019-11-15 23:58:09,588 INFO L78 Accepts]: Start accepts. Automaton has 596 states and 809 transitions. Word has length 71 [2019-11-15 23:58:09,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:09,588 INFO L462 AbstractCegarLoop]: Abstraction has 596 states and 809 transitions. [2019-11-15 23:58:09,589 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:58:09,589 INFO L276 IsEmpty]: Start isEmpty. Operand 596 states and 809 transitions. [2019-11-15 23:58:09,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 23:58:09,590 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:09,590 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:09,594 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:09,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:09,594 INFO L82 PathProgramCache]: Analyzing trace with hash -624478278, now seen corresponding path program 1 times [2019-11-15 23:58:09,594 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:09,595 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687703716] [2019-11-15 23:58:09,595 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:09,595 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:09,595 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:09,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:09,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:09,712 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687703716] [2019-11-15 23:58:09,713 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:09,713 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 23:58:09,713 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108466779] [2019-11-15 23:58:09,713 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:58:09,714 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:09,714 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:58:09,714 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 23:58:09,714 INFO L87 Difference]: Start difference. First operand 596 states and 809 transitions. Second operand 6 states. [2019-11-15 23:58:10,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:10,185 INFO L93 Difference]: Finished difference Result 2304 states and 3151 transitions. [2019-11-15 23:58:10,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-15 23:58:10,185 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-11-15 23:58:10,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:10,195 INFO L225 Difference]: With dead ends: 2304 [2019-11-15 23:58:10,195 INFO L226 Difference]: Without dead ends: 1931 [2019-11-15 23:58:10,197 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-15 23:58:10,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1931 states. [2019-11-15 23:58:10,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1931 to 674. [2019-11-15 23:58:10,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 674 states. [2019-11-15 23:58:10,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 911 transitions. [2019-11-15 23:58:10,261 INFO L78 Accepts]: Start accepts. Automaton has 674 states and 911 transitions. Word has length 72 [2019-11-15 23:58:10,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:10,262 INFO L462 AbstractCegarLoop]: Abstraction has 674 states and 911 transitions. [2019-11-15 23:58:10,262 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:58:10,262 INFO L276 IsEmpty]: Start isEmpty. Operand 674 states and 911 transitions. [2019-11-15 23:58:10,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 23:58:10,265 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:10,265 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:10,265 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:10,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:10,266 INFO L82 PathProgramCache]: Analyzing trace with hash -2046951303, now seen corresponding path program 1 times [2019-11-15 23:58:10,266 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:10,266 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647104434] [2019-11-15 23:58:10,266 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:10,267 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:10,267 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:10,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:10,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:10,347 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647104434] [2019-11-15 23:58:10,348 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:10,348 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 23:58:10,348 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606541778] [2019-11-15 23:58:10,348 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:58:10,348 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:10,349 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:58:10,349 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 23:58:10,349 INFO L87 Difference]: Start difference. First operand 674 states and 911 transitions. Second operand 6 states. [2019-11-15 23:58:10,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:10,535 INFO L93 Difference]: Finished difference Result 1500 states and 2090 transitions. [2019-11-15 23:58:10,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-15 23:58:10,536 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-11-15 23:58:10,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:10,542 INFO L225 Difference]: With dead ends: 1500 [2019-11-15 23:58:10,542 INFO L226 Difference]: Without dead ends: 1110 [2019-11-15 23:58:10,543 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-11-15 23:58:10,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2019-11-15 23:58:10,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 680. [2019-11-15 23:58:10,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 680 states. [2019-11-15 23:58:10,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 917 transitions. [2019-11-15 23:58:10,604 INFO L78 Accepts]: Start accepts. Automaton has 680 states and 917 transitions. Word has length 72 [2019-11-15 23:58:10,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:10,604 INFO L462 AbstractCegarLoop]: Abstraction has 680 states and 917 transitions. [2019-11-15 23:58:10,604 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:58:10,605 INFO L276 IsEmpty]: Start isEmpty. Operand 680 states and 917 transitions. [2019-11-15 23:58:10,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 23:58:10,606 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:10,606 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:10,606 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:10,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:10,607 INFO L82 PathProgramCache]: Analyzing trace with hash 778464989, now seen corresponding path program 1 times [2019-11-15 23:58:10,607 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:10,607 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459245284] [2019-11-15 23:58:10,607 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:10,608 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:10,608 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:10,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:10,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:10,658 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459245284] [2019-11-15 23:58:10,659 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:10,659 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:58:10,659 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1307960504] [2019-11-15 23:58:10,660 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:58:10,660 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:10,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:58:10,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:10,661 INFO L87 Difference]: Start difference. First operand 680 states and 917 transitions. Second operand 3 states. [2019-11-15 23:58:10,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:10,763 INFO L93 Difference]: Finished difference Result 1334 states and 1821 transitions. [2019-11-15 23:58:10,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:58:10,764 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 23:58:10,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:10,769 INFO L225 Difference]: With dead ends: 1334 [2019-11-15 23:58:10,769 INFO L226 Difference]: Without dead ends: 875 [2019-11-15 23:58:10,770 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:10,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 875 states. [2019-11-15 23:58:10,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 875 to 659. [2019-11-15 23:58:10,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 659 states. [2019-11-15 23:58:10,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 880 transitions. [2019-11-15 23:58:10,828 INFO L78 Accepts]: Start accepts. Automaton has 659 states and 880 transitions. Word has length 72 [2019-11-15 23:58:10,828 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:10,828 INFO L462 AbstractCegarLoop]: Abstraction has 659 states and 880 transitions. [2019-11-15 23:58:10,828 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:58:10,828 INFO L276 IsEmpty]: Start isEmpty. Operand 659 states and 880 transitions. [2019-11-15 23:58:10,829 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 23:58:10,829 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:10,830 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:10,830 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:10,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:10,830 INFO L82 PathProgramCache]: Analyzing trace with hash 449594347, now seen corresponding path program 1 times [2019-11-15 23:58:10,831 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:10,831 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793838307] [2019-11-15 23:58:10,831 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:10,831 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:10,831 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:10,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:10,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:10,894 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793838307] [2019-11-15 23:58:10,894 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:10,894 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:58:10,894 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84661452] [2019-11-15 23:58:10,895 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:58:10,895 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:10,895 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:58:10,896 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:58:10,896 INFO L87 Difference]: Start difference. First operand 659 states and 880 transitions. Second operand 4 states. [2019-11-15 23:58:11,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:11,110 INFO L93 Difference]: Finished difference Result 1702 states and 2282 transitions. [2019-11-15 23:58:11,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:58:11,110 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-11-15 23:58:11,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:11,117 INFO L225 Difference]: With dead ends: 1702 [2019-11-15 23:58:11,117 INFO L226 Difference]: Without dead ends: 1296 [2019-11-15 23:58:11,118 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:11,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1296 states. [2019-11-15 23:58:11,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1296 to 893. [2019-11-15 23:58:11,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 893 states. [2019-11-15 23:58:11,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 893 states to 893 states and 1191 transitions. [2019-11-15 23:58:11,246 INFO L78 Accepts]: Start accepts. Automaton has 893 states and 1191 transitions. Word has length 73 [2019-11-15 23:58:11,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:11,247 INFO L462 AbstractCegarLoop]: Abstraction has 893 states and 1191 transitions. [2019-11-15 23:58:11,247 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:58:11,247 INFO L276 IsEmpty]: Start isEmpty. Operand 893 states and 1191 transitions. [2019-11-15 23:58:11,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 23:58:11,248 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:11,248 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:11,249 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:11,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:11,249 INFO L82 PathProgramCache]: Analyzing trace with hash 1828954211, now seen corresponding path program 1 times [2019-11-15 23:58:11,249 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:11,250 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817115817] [2019-11-15 23:58:11,250 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:11,250 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:11,250 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:11,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:11,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:11,305 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817115817] [2019-11-15 23:58:11,305 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:11,305 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:58:11,305 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806896466] [2019-11-15 23:58:11,306 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:58:11,307 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:11,310 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:58:11,310 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:11,310 INFO L87 Difference]: Start difference. First operand 893 states and 1191 transitions. Second operand 3 states. [2019-11-15 23:58:11,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:11,446 INFO L93 Difference]: Finished difference Result 1870 states and 2511 transitions. [2019-11-15 23:58:11,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:58:11,447 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 23:58:11,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:11,453 INFO L225 Difference]: With dead ends: 1870 [2019-11-15 23:58:11,454 INFO L226 Difference]: Without dead ends: 1281 [2019-11-15 23:58:11,455 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:11,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1281 states. [2019-11-15 23:58:11,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1281 to 849. [2019-11-15 23:58:11,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 849 states. [2019-11-15 23:58:11,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 849 states to 849 states and 1127 transitions. [2019-11-15 23:58:11,532 INFO L78 Accepts]: Start accepts. Automaton has 849 states and 1127 transitions. Word has length 73 [2019-11-15 23:58:11,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:11,532 INFO L462 AbstractCegarLoop]: Abstraction has 849 states and 1127 transitions. [2019-11-15 23:58:11,532 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:58:11,532 INFO L276 IsEmpty]: Start isEmpty. Operand 849 states and 1127 transitions. [2019-11-15 23:58:11,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 23:58:11,533 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:11,533 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:11,535 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:11,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:11,536 INFO L82 PathProgramCache]: Analyzing trace with hash 1948644571, now seen corresponding path program 1 times [2019-11-15 23:58:11,536 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:11,536 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628538060] [2019-11-15 23:58:11,536 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:11,537 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:11,537 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:11,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:11,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:11,595 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628538060] [2019-11-15 23:58:11,596 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:11,596 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:58:11,596 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124047702] [2019-11-15 23:58:11,596 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:58:11,597 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:11,597 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:58:11,598 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:58:11,598 INFO L87 Difference]: Start difference. First operand 849 states and 1127 transitions. Second operand 4 states. [2019-11-15 23:58:11,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:11,798 INFO L93 Difference]: Finished difference Result 1986 states and 2630 transitions. [2019-11-15 23:58:11,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:58:11,800 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-11-15 23:58:11,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:11,807 INFO L225 Difference]: With dead ends: 1986 [2019-11-15 23:58:11,807 INFO L226 Difference]: Without dead ends: 1426 [2019-11-15 23:58:11,809 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:11,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1426 states. [2019-11-15 23:58:11,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1426 to 1131. [2019-11-15 23:58:11,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1131 states. [2019-11-15 23:58:11,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1131 states to 1131 states and 1491 transitions. [2019-11-15 23:58:11,911 INFO L78 Accepts]: Start accepts. Automaton has 1131 states and 1491 transitions. Word has length 73 [2019-11-15 23:58:11,911 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:11,912 INFO L462 AbstractCegarLoop]: Abstraction has 1131 states and 1491 transitions. [2019-11-15 23:58:11,912 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:58:11,912 INFO L276 IsEmpty]: Start isEmpty. Operand 1131 states and 1491 transitions. [2019-11-15 23:58:11,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-15 23:58:11,913 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:11,913 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:11,915 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:11,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:11,915 INFO L82 PathProgramCache]: Analyzing trace with hash 1795806066, now seen corresponding path program 1 times [2019-11-15 23:58:11,915 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:11,915 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824319785] [2019-11-15 23:58:11,915 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:11,916 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:11,916 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:11,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:11,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:11,944 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824319785] [2019-11-15 23:58:11,944 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:11,944 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 23:58:11,944 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576208238] [2019-11-15 23:58:11,946 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 23:58:11,946 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:11,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 23:58:11,946 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:11,946 INFO L87 Difference]: Start difference. First operand 1131 states and 1491 transitions. Second operand 3 states. [2019-11-15 23:58:12,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:12,205 INFO L93 Difference]: Finished difference Result 2794 states and 3673 transitions. [2019-11-15 23:58:12,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 23:58:12,205 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-11-15 23:58:12,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:12,214 INFO L225 Difference]: With dead ends: 2794 [2019-11-15 23:58:12,215 INFO L226 Difference]: Without dead ends: 1896 [2019-11-15 23:58:12,216 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 23:58:12,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1896 states. [2019-11-15 23:58:12,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1896 to 1133. [2019-11-15 23:58:12,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1133 states. [2019-11-15 23:58:12,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1133 states to 1133 states and 1493 transitions. [2019-11-15 23:58:12,359 INFO L78 Accepts]: Start accepts. Automaton has 1133 states and 1493 transitions. Word has length 74 [2019-11-15 23:58:12,359 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:12,359 INFO L462 AbstractCegarLoop]: Abstraction has 1133 states and 1493 transitions. [2019-11-15 23:58:12,359 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 23:58:12,359 INFO L276 IsEmpty]: Start isEmpty. Operand 1133 states and 1493 transitions. [2019-11-15 23:58:12,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-15 23:58:12,360 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:12,361 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:12,361 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:12,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:12,361 INFO L82 PathProgramCache]: Analyzing trace with hash 230569326, now seen corresponding path program 1 times [2019-11-15 23:58:12,362 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:12,362 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61736748] [2019-11-15 23:58:12,362 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:12,362 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:12,362 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:12,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:12,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:12,425 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61736748] [2019-11-15 23:58:12,425 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:12,426 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:58:12,426 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [829136444] [2019-11-15 23:58:12,426 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:58:12,426 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:12,427 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:58:12,427 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:58:12,427 INFO L87 Difference]: Start difference. First operand 1133 states and 1493 transitions. Second operand 4 states. [2019-11-15 23:58:12,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:12,604 INFO L93 Difference]: Finished difference Result 2365 states and 3103 transitions. [2019-11-15 23:58:12,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:58:12,604 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-11-15 23:58:12,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:12,610 INFO L225 Difference]: With dead ends: 2365 [2019-11-15 23:58:12,611 INFO L226 Difference]: Without dead ends: 1287 [2019-11-15 23:58:12,614 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:12,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1287 states. [2019-11-15 23:58:12,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1287 to 946. [2019-11-15 23:58:12,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 946 states. [2019-11-15 23:58:12,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 946 states to 946 states and 1237 transitions. [2019-11-15 23:58:12,716 INFO L78 Accepts]: Start accepts. Automaton has 946 states and 1237 transitions. Word has length 75 [2019-11-15 23:58:12,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:12,717 INFO L462 AbstractCegarLoop]: Abstraction has 946 states and 1237 transitions. [2019-11-15 23:58:12,717 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:58:12,717 INFO L276 IsEmpty]: Start isEmpty. Operand 946 states and 1237 transitions. [2019-11-15 23:58:12,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-11-15 23:58:12,718 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:12,718 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:12,718 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:12,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:12,719 INFO L82 PathProgramCache]: Analyzing trace with hash -818028433, now seen corresponding path program 1 times [2019-11-15 23:58:12,719 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:12,719 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120492698] [2019-11-15 23:58:12,719 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:12,719 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:12,720 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:12,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:12,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:12,788 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2120492698] [2019-11-15 23:58:12,788 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:12,788 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:58:12,788 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418015210] [2019-11-15 23:58:12,789 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:58:12,789 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:12,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:58:12,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:58:12,789 INFO L87 Difference]: Start difference. First operand 946 states and 1237 transitions. Second operand 4 states. [2019-11-15 23:58:12,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:12,970 INFO L93 Difference]: Finished difference Result 2178 states and 2855 transitions. [2019-11-15 23:58:12,970 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:58:12,971 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 76 [2019-11-15 23:58:12,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:12,977 INFO L225 Difference]: With dead ends: 2178 [2019-11-15 23:58:12,977 INFO L226 Difference]: Without dead ends: 1307 [2019-11-15 23:58:12,979 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:12,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1307 states. [2019-11-15 23:58:13,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1307 to 892. [2019-11-15 23:58:13,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-11-15 23:58:13,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1159 transitions. [2019-11-15 23:58:13,077 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1159 transitions. Word has length 76 [2019-11-15 23:58:13,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:13,077 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1159 transitions. [2019-11-15 23:58:13,077 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:58:13,078 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1159 transitions. [2019-11-15 23:58:13,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2019-11-15 23:58:13,080 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:13,080 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:13,080 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:13,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:13,081 INFO L82 PathProgramCache]: Analyzing trace with hash 1542213080, now seen corresponding path program 1 times [2019-11-15 23:58:13,081 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:13,081 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304612950] [2019-11-15 23:58:13,081 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:13,081 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:13,082 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:13,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:13,394 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:13,395 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304612950] [2019-11-15 23:58:13,395 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [292597934] [2019-11-15 23:58:13,395 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:13,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:13,586 INFO L256 TraceCheckSpWp]: Trace formula consists of 724 conjuncts, 9 conjunts are in the unsatisfiable core [2019-11-15 23:58:13,601 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:58:13,697 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-15 23:58:13,699 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 23:58:13,699 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-15 23:58:13,699 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1875096557] [2019-11-15 23:58:13,700 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:58:13,700 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:13,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:58:13,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-15 23:58:13,701 INFO L87 Difference]: Start difference. First operand 892 states and 1159 transitions. Second operand 6 states. [2019-11-15 23:58:14,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:14,121 INFO L93 Difference]: Finished difference Result 2720 states and 3672 transitions. [2019-11-15 23:58:14,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-15 23:58:14,127 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2019-11-15 23:58:14,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:14,137 INFO L225 Difference]: With dead ends: 2720 [2019-11-15 23:58:14,137 INFO L226 Difference]: Without dead ends: 1969 [2019-11-15 23:58:14,138 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 117 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-11-15 23:58:14,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1969 states. [2019-11-15 23:58:14,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1969 to 892. [2019-11-15 23:58:14,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-11-15 23:58:14,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1156 transitions. [2019-11-15 23:58:14,251 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1156 transitions. Word has length 120 [2019-11-15 23:58:14,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:14,251 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1156 transitions. [2019-11-15 23:58:14,251 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:58:14,251 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1156 transitions. [2019-11-15 23:58:14,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2019-11-15 23:58:14,254 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:14,254 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:14,459 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:14,460 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:14,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:14,460 INFO L82 PathProgramCache]: Analyzing trace with hash -1832197229, now seen corresponding path program 1 times [2019-11-15 23:58:14,460 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:14,460 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673595519] [2019-11-15 23:58:14,460 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:14,460 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:14,461 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:14,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:14,772 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:14,773 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673595519] [2019-11-15 23:58:14,773 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [295767144] [2019-11-15 23:58:14,773 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:14,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:14,954 INFO L256 TraceCheckSpWp]: Trace formula consists of 737 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-15 23:58:14,958 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:58:15,083 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-15 23:58:15,083 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 23:58:15,083 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-15 23:58:15,084 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704008832] [2019-11-15 23:58:15,084 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:58:15,084 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:15,084 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:58:15,085 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-15 23:58:15,085 INFO L87 Difference]: Start difference. First operand 892 states and 1156 transitions. Second operand 6 states. [2019-11-15 23:58:15,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:15,469 INFO L93 Difference]: Finished difference Result 2447 states and 3267 transitions. [2019-11-15 23:58:15,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-15 23:58:15,470 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 124 [2019-11-15 23:58:15,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:15,484 INFO L225 Difference]: With dead ends: 2447 [2019-11-15 23:58:15,485 INFO L226 Difference]: Without dead ends: 1696 [2019-11-15 23:58:15,486 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 140 GetRequests, 121 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-11-15 23:58:15,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1696 states. [2019-11-15 23:58:15,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1696 to 892. [2019-11-15 23:58:15,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-11-15 23:58:15,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1153 transitions. [2019-11-15 23:58:15,589 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1153 transitions. Word has length 124 [2019-11-15 23:58:15,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:15,590 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1153 transitions. [2019-11-15 23:58:15,590 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:58:15,590 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1153 transitions. [2019-11-15 23:58:15,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-11-15 23:58:15,594 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:15,595 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:15,799 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:15,801 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:15,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:15,801 INFO L82 PathProgramCache]: Analyzing trace with hash 1668386931, now seen corresponding path program 1 times [2019-11-15 23:58:15,801 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:15,802 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511521443] [2019-11-15 23:58:15,802 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:15,802 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:15,802 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:15,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:16,144 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:16,145 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511521443] [2019-11-15 23:58:16,145 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [919575916] [2019-11-15 23:58:16,145 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:16,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:16,329 INFO L256 TraceCheckSpWp]: Trace formula consists of 749 conjuncts, 12 conjunts are in the unsatisfiable core [2019-11-15 23:58:16,334 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:58:16,439 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-15 23:58:16,439 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 23:58:16,440 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-15 23:58:16,440 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [66684643] [2019-11-15 23:58:16,440 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:58:16,440 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:16,440 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:58:16,441 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-15 23:58:16,441 INFO L87 Difference]: Start difference. First operand 892 states and 1153 transitions. Second operand 6 states. [2019-11-15 23:58:16,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:16,976 INFO L93 Difference]: Finished difference Result 2811 states and 3778 transitions. [2019-11-15 23:58:16,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-15 23:58:16,977 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 127 [2019-11-15 23:58:16,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:16,981 INFO L225 Difference]: With dead ends: 2811 [2019-11-15 23:58:16,981 INFO L226 Difference]: Without dead ends: 2047 [2019-11-15 23:58:16,983 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2019-11-15 23:58:16,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states. [2019-11-15 23:58:17,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 840. [2019-11-15 23:58:17,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2019-11-15 23:58:17,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1075 transitions. [2019-11-15 23:58:17,086 INFO L78 Accepts]: Start accepts. Automaton has 840 states and 1075 transitions. Word has length 127 [2019-11-15 23:58:17,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:17,086 INFO L462 AbstractCegarLoop]: Abstraction has 840 states and 1075 transitions. [2019-11-15 23:58:17,086 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:58:17,086 INFO L276 IsEmpty]: Start isEmpty. Operand 840 states and 1075 transitions. [2019-11-15 23:58:17,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2019-11-15 23:58:17,090 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:17,091 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:17,295 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:17,295 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:17,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:17,296 INFO L82 PathProgramCache]: Analyzing trace with hash -1807241978, now seen corresponding path program 1 times [2019-11-15 23:58:17,296 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:17,296 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632141637] [2019-11-15 23:58:17,296 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:17,297 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:17,297 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:17,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:17,532 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:17,532 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1632141637] [2019-11-15 23:58:17,533 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [829050799] [2019-11-15 23:58:17,533 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:17,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:17,714 INFO L256 TraceCheckSpWp]: Trace formula consists of 750 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-15 23:58:17,718 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:58:17,819 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-15 23:58:17,819 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 23:58:17,820 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [10] total 15 [2019-11-15 23:58:17,820 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224800712] [2019-11-15 23:58:17,820 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:58:17,820 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:17,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:58:17,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=181, Unknown=0, NotChecked=0, Total=210 [2019-11-15 23:58:17,821 INFO L87 Difference]: Start difference. First operand 840 states and 1075 transitions. Second operand 6 states. [2019-11-15 23:58:18,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:18,194 INFO L93 Difference]: Finished difference Result 2163 states and 2880 transitions. [2019-11-15 23:58:18,194 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-15 23:58:18,194 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 128 [2019-11-15 23:58:18,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:18,197 INFO L225 Difference]: With dead ends: 2163 [2019-11-15 23:58:18,197 INFO L226 Difference]: Without dead ends: 1478 [2019-11-15 23:58:18,199 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 142 GetRequests, 125 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=48, Invalid=294, Unknown=0, NotChecked=0, Total=342 [2019-11-15 23:58:18,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1478 states. [2019-11-15 23:58:18,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1478 to 840. [2019-11-15 23:58:18,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2019-11-15 23:58:18,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1074 transitions. [2019-11-15 23:58:18,296 INFO L78 Accepts]: Start accepts. Automaton has 840 states and 1074 transitions. Word has length 128 [2019-11-15 23:58:18,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:18,296 INFO L462 AbstractCegarLoop]: Abstraction has 840 states and 1074 transitions. [2019-11-15 23:58:18,296 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:58:18,296 INFO L276 IsEmpty]: Start isEmpty. Operand 840 states and 1074 transitions. [2019-11-15 23:58:18,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-11-15 23:58:18,299 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:18,299 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:18,502 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:18,505 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:18,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:18,505 INFO L82 PathProgramCache]: Analyzing trace with hash 237584641, now seen corresponding path program 1 times [2019-11-15 23:58:18,505 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:18,506 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632039540] [2019-11-15 23:58:18,506 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:18,506 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:18,506 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:18,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:18,762 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:18,762 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1632039540] [2019-11-15 23:58:18,762 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [359093323] [2019-11-15 23:58:18,762 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:18,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:18,968 INFO L256 TraceCheckSpWp]: Trace formula consists of 764 conjuncts, 45 conjunts are in the unsatisfiable core [2019-11-15 23:58:18,974 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:58:19,304 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:19,304 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:58:19,305 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12] total 17 [2019-11-15 23:58:19,305 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093471468] [2019-11-15 23:58:19,306 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-11-15 23:58:19,306 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:19,306 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-11-15 23:58:19,306 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=251, Unknown=0, NotChecked=0, Total=306 [2019-11-15 23:58:19,307 INFO L87 Difference]: Start difference. First operand 840 states and 1074 transitions. Second operand 18 states. [2019-11-15 23:58:22,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:22,223 INFO L93 Difference]: Finished difference Result 3439 states and 4527 transitions. [2019-11-15 23:58:22,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2019-11-15 23:58:22,224 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 132 [2019-11-15 23:58:22,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:22,228 INFO L225 Difference]: With dead ends: 3439 [2019-11-15 23:58:22,228 INFO L226 Difference]: Without dead ends: 2760 [2019-11-15 23:58:22,232 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 199 GetRequests, 119 SyntacticMatches, 4 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1942 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1261, Invalid=4745, Unknown=0, NotChecked=0, Total=6006 [2019-11-15 23:58:22,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2760 states. [2019-11-15 23:58:22,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2760 to 1325. [2019-11-15 23:58:22,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1325 states. [2019-11-15 23:58:22,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1325 states to 1325 states and 1715 transitions. [2019-11-15 23:58:22,457 INFO L78 Accepts]: Start accepts. Automaton has 1325 states and 1715 transitions. Word has length 132 [2019-11-15 23:58:22,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:22,458 INFO L462 AbstractCegarLoop]: Abstraction has 1325 states and 1715 transitions. [2019-11-15 23:58:22,458 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-11-15 23:58:22,458 INFO L276 IsEmpty]: Start isEmpty. Operand 1325 states and 1715 transitions. [2019-11-15 23:58:22,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-15 23:58:22,461 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:22,462 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:22,665 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:22,665 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:22,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:22,666 INFO L82 PathProgramCache]: Analyzing trace with hash -700555044, now seen corresponding path program 1 times [2019-11-15 23:58:22,666 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:22,666 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533620013] [2019-11-15 23:58:22,666 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:22,666 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:22,666 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:22,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:22,728 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-11-15 23:58:22,728 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533620013] [2019-11-15 23:58:22,728 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:22,729 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:58:22,729 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1120365514] [2019-11-15 23:58:22,729 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:58:22,729 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:22,730 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:58:22,730 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:58:22,730 INFO L87 Difference]: Start difference. First operand 1325 states and 1715 transitions. Second operand 4 states. [2019-11-15 23:58:23,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:23,110 INFO L93 Difference]: Finished difference Result 3265 states and 4250 transitions. [2019-11-15 23:58:23,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:58:23,111 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 133 [2019-11-15 23:58:23,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:23,120 INFO L225 Difference]: With dead ends: 3265 [2019-11-15 23:58:23,120 INFO L226 Difference]: Without dead ends: 2068 [2019-11-15 23:58:23,122 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:23,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2068 states. [2019-11-15 23:58:23,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2068 to 1385. [2019-11-15 23:58:23,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1385 states. [2019-11-15 23:58:23,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1385 states to 1385 states and 1769 transitions. [2019-11-15 23:58:23,311 INFO L78 Accepts]: Start accepts. Automaton has 1385 states and 1769 transitions. Word has length 133 [2019-11-15 23:58:23,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:23,311 INFO L462 AbstractCegarLoop]: Abstraction has 1385 states and 1769 transitions. [2019-11-15 23:58:23,311 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:58:23,312 INFO L276 IsEmpty]: Start isEmpty. Operand 1385 states and 1769 transitions. [2019-11-15 23:58:23,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-15 23:58:23,315 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:23,315 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:23,315 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:23,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:23,316 INFO L82 PathProgramCache]: Analyzing trace with hash -709461544, now seen corresponding path program 1 times [2019-11-15 23:58:23,316 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:23,316 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834374116] [2019-11-15 23:58:23,316 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:23,316 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:23,317 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:23,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:23,431 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-11-15 23:58:23,431 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834374116] [2019-11-15 23:58:23,431 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:23,431 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:58:23,431 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165086237] [2019-11-15 23:58:23,432 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 23:58:23,432 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:23,432 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 23:58:23,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:23,433 INFO L87 Difference]: Start difference. First operand 1385 states and 1769 transitions. Second operand 5 states. [2019-11-15 23:58:23,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:23,680 INFO L93 Difference]: Finished difference Result 2514 states and 3258 transitions. [2019-11-15 23:58:23,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 23:58:23,681 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 133 [2019-11-15 23:58:23,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:23,683 INFO L225 Difference]: With dead ends: 2514 [2019-11-15 23:58:23,683 INFO L226 Difference]: Without dead ends: 1257 [2019-11-15 23:58:23,686 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-15 23:58:23,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1257 states. [2019-11-15 23:58:23,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1257 to 1257. [2019-11-15 23:58:23,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1257 states. [2019-11-15 23:58:23,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1257 states to 1257 states and 1621 transitions. [2019-11-15 23:58:23,860 INFO L78 Accepts]: Start accepts. Automaton has 1257 states and 1621 transitions. Word has length 133 [2019-11-15 23:58:23,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:23,860 INFO L462 AbstractCegarLoop]: Abstraction has 1257 states and 1621 transitions. [2019-11-15 23:58:23,860 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 23:58:23,860 INFO L276 IsEmpty]: Start isEmpty. Operand 1257 states and 1621 transitions. [2019-11-15 23:58:23,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-15 23:58:23,863 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:23,863 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:23,864 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:23,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:23,864 INFO L82 PathProgramCache]: Analyzing trace with hash 77500617, now seen corresponding path program 1 times [2019-11-15 23:58:23,864 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:23,864 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259237391] [2019-11-15 23:58:23,864 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:23,865 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:23,865 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:23,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:23,952 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2019-11-15 23:58:23,953 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259237391] [2019-11-15 23:58:23,953 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:23,953 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 23:58:23,953 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951036789] [2019-11-15 23:58:23,954 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:58:23,954 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:23,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:58:23,954 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 23:58:23,954 INFO L87 Difference]: Start difference. First operand 1257 states and 1621 transitions. Second operand 6 states. [2019-11-15 23:58:24,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:24,948 INFO L93 Difference]: Finished difference Result 6586 states and 8686 transitions. [2019-11-15 23:58:24,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-11-15 23:58:24,948 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 134 [2019-11-15 23:58:24,949 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:24,959 INFO L225 Difference]: With dead ends: 6586 [2019-11-15 23:58:24,960 INFO L226 Difference]: Without dead ends: 5510 [2019-11-15 23:58:24,963 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2019-11-15 23:58:24,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5510 states. [2019-11-15 23:58:25,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5510 to 1599. [2019-11-15 23:58:25,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1599 states. [2019-11-15 23:58:25,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1599 states to 1599 states and 2021 transitions. [2019-11-15 23:58:25,201 INFO L78 Accepts]: Start accepts. Automaton has 1599 states and 2021 transitions. Word has length 134 [2019-11-15 23:58:25,202 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:25,202 INFO L462 AbstractCegarLoop]: Abstraction has 1599 states and 2021 transitions. [2019-11-15 23:58:25,202 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:58:25,202 INFO L276 IsEmpty]: Start isEmpty. Operand 1599 states and 2021 transitions. [2019-11-15 23:58:25,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-15 23:58:25,205 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:25,205 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:25,206 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:25,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:25,206 INFO L82 PathProgramCache]: Analyzing trace with hash -825335127, now seen corresponding path program 1 times [2019-11-15 23:58:25,206 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:25,206 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [120188303] [2019-11-15 23:58:25,207 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:25,207 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:25,207 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:25,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:25,532 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:25,532 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [120188303] [2019-11-15 23:58:25,532 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [19860780] [2019-11-15 23:58:25,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:25,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:25,724 INFO L256 TraceCheckSpWp]: Trace formula consists of 776 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-15 23:58:25,727 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:58:25,826 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-15 23:58:25,827 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 23:58:25,827 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-15 23:58:25,827 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [877925932] [2019-11-15 23:58:25,828 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 23:58:25,829 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:25,829 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 23:58:25,829 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-15 23:58:25,829 INFO L87 Difference]: Start difference. First operand 1599 states and 2021 transitions. Second operand 6 states. [2019-11-15 23:58:26,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:26,468 INFO L93 Difference]: Finished difference Result 4910 states and 6326 transitions. [2019-11-15 23:58:26,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-15 23:58:26,468 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2019-11-15 23:58:26,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:26,477 INFO L225 Difference]: With dead ends: 4910 [2019-11-15 23:58:26,477 INFO L226 Difference]: Without dead ends: 3472 [2019-11-15 23:58:26,479 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 132 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-11-15 23:58:26,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3472 states. [2019-11-15 23:58:26,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3472 to 1599. [2019-11-15 23:58:26,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1599 states. [2019-11-15 23:58:26,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1599 states to 1599 states and 2019 transitions. [2019-11-15 23:58:26,711 INFO L78 Accepts]: Start accepts. Automaton has 1599 states and 2019 transitions. Word has length 135 [2019-11-15 23:58:26,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:26,711 INFO L462 AbstractCegarLoop]: Abstraction has 1599 states and 2019 transitions. [2019-11-15 23:58:26,711 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 23:58:26,711 INFO L276 IsEmpty]: Start isEmpty. Operand 1599 states and 2019 transitions. [2019-11-15 23:58:26,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-15 23:58:26,715 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:26,715 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:26,925 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:26,925 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:26,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:26,926 INFO L82 PathProgramCache]: Analyzing trace with hash -1957396857, now seen corresponding path program 1 times [2019-11-15 23:58:26,926 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:26,926 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139436761] [2019-11-15 23:58:26,926 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:26,926 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:26,926 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:26,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:27,150 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:27,151 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139436761] [2019-11-15 23:58:27,151 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1371486805] [2019-11-15 23:58:27,151 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:27,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:27,341 INFO L256 TraceCheckSpWp]: Trace formula consists of 766 conjuncts, 46 conjunts are in the unsatisfiable core [2019-11-15 23:58:27,344 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 23:58:27,695 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 23:58:27,695 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 23:58:27,695 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-11-15 23:58:27,696 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [291837478] [2019-11-15 23:58:27,696 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-15 23:58:27,696 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:27,697 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-15 23:58:27,697 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2019-11-15 23:58:27,698 INFO L87 Difference]: Start difference. First operand 1599 states and 2019 transitions. Second operand 21 states. [2019-11-15 23:58:28,369 WARN L191 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 27 [2019-11-15 23:58:30,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:30,074 INFO L93 Difference]: Finished difference Result 4391 states and 5566 transitions. [2019-11-15 23:58:30,075 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-11-15 23:58:30,075 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 135 [2019-11-15 23:58:30,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:30,079 INFO L225 Difference]: With dead ends: 4391 [2019-11-15 23:58:30,079 INFO L226 Difference]: Without dead ends: 2973 [2019-11-15 23:58:30,082 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 185 GetRequests, 121 SyntacticMatches, 4 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 997 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=649, Invalid=3133, Unknown=0, NotChecked=0, Total=3782 [2019-11-15 23:58:30,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2973 states. [2019-11-15 23:58:30,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2973 to 1819. [2019-11-15 23:58:30,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1819 states. [2019-11-15 23:58:30,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1819 states to 1819 states and 2290 transitions. [2019-11-15 23:58:30,349 INFO L78 Accepts]: Start accepts. Automaton has 1819 states and 2290 transitions. Word has length 135 [2019-11-15 23:58:30,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:30,349 INFO L462 AbstractCegarLoop]: Abstraction has 1819 states and 2290 transitions. [2019-11-15 23:58:30,349 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-15 23:58:30,350 INFO L276 IsEmpty]: Start isEmpty. Operand 1819 states and 2290 transitions. [2019-11-15 23:58:30,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-15 23:58:30,353 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:30,353 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:30,557 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 23:58:30,557 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:30,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:30,557 INFO L82 PathProgramCache]: Analyzing trace with hash 470861765, now seen corresponding path program 1 times [2019-11-15 23:58:30,558 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:30,558 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1437974283] [2019-11-15 23:58:30,558 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:30,558 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:30,558 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:30,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 23:58:30,613 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2019-11-15 23:58:30,613 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1437974283] [2019-11-15 23:58:30,613 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 23:58:30,614 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 23:58:30,614 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007772653] [2019-11-15 23:58:30,614 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 23:58:30,614 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 23:58:30,615 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 23:58:30,615 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:58:30,615 INFO L87 Difference]: Start difference. First operand 1819 states and 2290 transitions. Second operand 4 states. [2019-11-15 23:58:30,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 23:58:30,847 INFO L93 Difference]: Finished difference Result 3316 states and 4201 transitions. [2019-11-15 23:58:30,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-15 23:58:30,847 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2019-11-15 23:58:30,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 23:58:30,849 INFO L225 Difference]: With dead ends: 3316 [2019-11-15 23:58:30,849 INFO L226 Difference]: Without dead ends: 1623 [2019-11-15 23:58:30,851 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-15 23:58:30,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1623 states. [2019-11-15 23:58:31,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1623 to 1623. [2019-11-15 23:58:31,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1623 states. [2019-11-15 23:58:31,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1623 states to 1623 states and 2029 transitions. [2019-11-15 23:58:31,020 INFO L78 Accepts]: Start accepts. Automaton has 1623 states and 2029 transitions. Word has length 135 [2019-11-15 23:58:31,020 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 23:58:31,020 INFO L462 AbstractCegarLoop]: Abstraction has 1623 states and 2029 transitions. [2019-11-15 23:58:31,020 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 23:58:31,020 INFO L276 IsEmpty]: Start isEmpty. Operand 1623 states and 2029 transitions. [2019-11-15 23:58:31,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-15 23:58:31,023 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 23:58:31,023 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 23:58:31,024 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 23:58:31,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 23:58:31,024 INFO L82 PathProgramCache]: Analyzing trace with hash -1467051729, now seen corresponding path program 1 times [2019-11-15 23:58:31,024 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 23:58:31,024 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804662817] [2019-11-15 23:58:31,025 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:31,025 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 23:58:31,025 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 23:58:31,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 23:58:31,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 23:58:31,202 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 23:58:31,202 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-11-15 23:58:31,381 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 15.11 11:58:31 BoogieIcfgContainer [2019-11-15 23:58:31,381 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-15 23:58:31,382 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-15 23:58:31,382 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-15 23:58:31,382 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-15 23:58:31,383 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 11:58:03" (3/4) ... [2019-11-15 23:58:31,385 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-15 23:58:31,586 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_23b34833-bf0a-4f7f-85bc-5945854fb338/bin/uautomizer/witness.graphml [2019-11-15 23:58:31,586 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-15 23:58:31,587 INFO L168 Benchmark]: Toolchain (without parser) took 29670.70 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 793.8 MB). Free memory was 943.4 MB in the beginning and 1.1 GB in the end (delta: -126.9 MB). Peak memory consumption was 666.9 MB. Max. memory is 11.5 GB. [2019-11-15 23:58:31,587 INFO L168 Benchmark]: CDTParser took 0.26 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-15 23:58:31,588 INFO L168 Benchmark]: CACSL2BoogieTranslator took 560.85 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 111.1 MB). Free memory was 938.0 MB in the beginning and 1.1 GB in the end (delta: -161.3 MB). Peak memory consumption was 17.6 MB. Max. memory is 11.5 GB. [2019-11-15 23:58:31,588 INFO L168 Benchmark]: Boogie Procedure Inliner took 64.73 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-11-15 23:58:31,588 INFO L168 Benchmark]: Boogie Preprocessor took 70.06 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2019-11-15 23:58:31,589 INFO L168 Benchmark]: RCFGBuilder took 1366.26 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 996.3 MB in the end (delta: 86.9 MB). Peak memory consumption was 86.9 MB. Max. memory is 11.5 GB. [2019-11-15 23:58:31,589 INFO L168 Benchmark]: TraceAbstraction took 27401.06 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 682.6 MB). Free memory was 996.3 MB in the beginning and 1.1 GB in the end (delta: -136.9 MB). Peak memory consumption was 545.7 MB. Max. memory is 11.5 GB. [2019-11-15 23:58:31,590 INFO L168 Benchmark]: Witness Printer took 204.07 ms. Allocated memory is still 1.8 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 63.0 MB). Peak memory consumption was 63.0 MB. Max. memory is 11.5 GB. [2019-11-15 23:58:31,591 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.26 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 560.85 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 111.1 MB). Free memory was 938.0 MB in the beginning and 1.1 GB in the end (delta: -161.3 MB). Peak memory consumption was 17.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 64.73 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 70.06 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1366.26 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 996.3 MB in the end (delta: 86.9 MB). Peak memory consumption was 86.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 27401.06 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 682.6 MB). Free memory was 996.3 MB in the beginning and 1.1 GB in the end (delta: -136.9 MB). Peak memory consumption was 545.7 MB. Max. memory is 11.5 GB. * Witness Printer took 204.07 ms. Allocated memory is still 1.8 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 63.0 MB). Peak memory consumption was 63.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 654]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L455] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L577] int c1 ; [L578] int i2 ; [L581] c1 = 0 [L582] side1Failed = __VERIFIER_nondet_bool() [L583] side2Failed = __VERIFIER_nondet_bool() [L584] side1_written = __VERIFIER_nondet_char() [L585] side2_written = __VERIFIER_nondet_char() [L586] side1Failed_History_0 = __VERIFIER_nondet_bool() [L587] side1Failed_History_1 = __VERIFIER_nondet_bool() [L588] side1Failed_History_2 = __VERIFIER_nondet_bool() [L589] side2Failed_History_0 = __VERIFIER_nondet_bool() [L590] side2Failed_History_1 = __VERIFIER_nondet_bool() [L591] side2Failed_History_2 = __VERIFIER_nondet_bool() [L592] active_side_History_0 = __VERIFIER_nondet_char() [L593] active_side_History_1 = __VERIFIER_nondet_char() [L594] active_side_History_2 = __VERIFIER_nondet_char() [L595] manual_selection_History_0 = __VERIFIER_nondet_char() [L596] manual_selection_History_1 = __VERIFIER_nondet_char() [L597] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L598] i2 = init() [L600] cs1_old = nomsg [L601] cs1_new = nomsg [L602] cs2_old = nomsg [L603] cs2_new = nomsg [L604] s1s2_old = nomsg [L605] s1s2_new = nomsg [L606] s1s1_old = nomsg [L607] s1s1_new = nomsg [L608] s2s1_old = nomsg [L609] s2s1_new = nomsg [L610] s2s2_old = nomsg [L611] s2s2_new = nomsg [L612] s1p_old = nomsg [L613] s1p_new = nomsg [L614] s2p_old = nomsg [L615] s2p_new = nomsg [L616] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L485] COND TRUE ! side2Failed [L486] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] tmp___1 = read_side1_failed_history((unsigned char)1) [L494] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L495] tmp___2 = read_side1_failed_history((unsigned char)0) [L496] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] tmp___11 = read_side1_failed_history((unsigned char)1) [L538] COND TRUE ! tmp___11 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L539] tmp___12 = read_side2_failed_history((unsigned char)1) [L540] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L553] tmp___20 = read_active_side_history((unsigned char)2) [L554] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L572] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L652] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L641] i2 ++ VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-128, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-128, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND FALSE !(\read(side1Failed)) [L326] side1 = s1s1_old [L327] s1s1_old = nomsg [L328] side2 = s2s1_old [L329] s2s1_old = nomsg [L330] manual_selection = cs1_old [L331] cs1_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L332] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L335] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L336] COND TRUE (int )side2 != (int )nomsg [L337] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] EXPR next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] s1s1_new = next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new [L357] EXPR next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L357] s1s2_new = next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new [L358] EXPR next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L358] s1p_new = next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new [L359] side1_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND TRUE \read(side2Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] EXPR nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] s2s1_new = nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new [L378] EXPR nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L378] s2s2_new = nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new [L379] EXPR nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L379] s2p_new = nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new [L380] side2_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND TRUE ! side1Failed [L483] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND FALSE !(! tmp___0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND TRUE \read(tmp___7) [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L523] tmp___8 = read_side2_failed_history((unsigned char)1) [L524] COND TRUE ! tmp___8 [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L525] tmp___5 = read_active_side_history((unsigned char)0) [L526] COND TRUE ! ((int )tmp___5 == 2) [L527] return (0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L652] COND TRUE ! arg VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L654] __VERIFIER_error() VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 291 locations, 23 error locations. Result: UNSAFE, OverallTime: 27.3s, OverallIterations: 37, TraceHistogramMax: 2, AutomataDifference: 14.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 15713 SDtfs, 28413 SDslu, 34026 SDs, 0 SdLazy, 5191 SolverSat, 400 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1324 GetRequests, 950 SyntacticMatches, 19 SemanticMatches, 355 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3349 ImplicationChecksByTransitivity, 6.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1819occurred in iteration=35, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 3.2s AutomataMinimizationTime, 36 MinimizatonAttempts, 21934 StatesRemovedByMinimization, 32 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.4s SsaConstructionTime, 1.6s SatisfiabilityAnalysisTime, 4.5s InterpolantComputationTime, 4081 NumberOfCodeBlocks, 4081 NumberOfCodeBlocksAsserted, 44 NumberOfCheckSat, 3902 ConstructedInterpolants, 0 QuantifiedInterpolants, 1566655 SizeOfPredicates, 38 NumberOfNonLiveVariables, 5266 ConjunctsInSsa, 136 ConjunctsInUnsatCore, 43 InterpolantComputations, 34 PerfectInterpolantSequences, 582/673 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...