./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c -s /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 51b120a585d23a491f06d4bb80c2a463453987ac .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-11-16 00:04:59,642 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-16 00:04:59,643 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-16 00:04:59,658 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-16 00:04:59,659 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-16 00:04:59,660 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-16 00:04:59,662 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-16 00:04:59,672 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-16 00:04:59,677 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-16 00:04:59,680 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-16 00:04:59,682 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-16 00:04:59,684 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-16 00:04:59,684 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-16 00:04:59,686 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-16 00:04:59,687 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-16 00:04:59,688 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-16 00:04:59,689 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-16 00:04:59,690 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-16 00:04:59,692 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-16 00:04:59,696 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-16 00:04:59,699 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-16 00:04:59,701 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-16 00:04:59,705 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-16 00:04:59,705 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-16 00:04:59,708 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-16 00:04:59,708 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-16 00:04:59,709 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-16 00:04:59,710 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-16 00:04:59,711 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-16 00:04:59,712 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-16 00:04:59,712 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-16 00:04:59,713 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-16 00:04:59,713 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-16 00:04:59,714 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-16 00:04:59,716 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-16 00:04:59,716 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-16 00:04:59,717 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-16 00:04:59,717 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-16 00:04:59,717 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-16 00:04:59,719 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-16 00:04:59,719 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-16 00:04:59,721 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-16 00:04:59,748 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-16 00:04:59,759 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-16 00:04:59,760 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-16 00:04:59,761 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-16 00:04:59,761 INFO L138 SettingsManager]: * Use SBE=true [2019-11-16 00:04:59,761 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-16 00:04:59,762 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-16 00:04:59,762 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-16 00:04:59,762 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-16 00:04:59,762 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-16 00:04:59,763 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-16 00:04:59,763 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-16 00:04:59,763 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-16 00:04:59,763 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-16 00:04:59,764 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-16 00:04:59,764 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-16 00:04:59,764 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-16 00:04:59,764 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-16 00:04:59,765 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-16 00:04:59,765 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-16 00:04:59,765 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-16 00:04:59,766 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-16 00:04:59,767 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-16 00:04:59,767 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-16 00:04:59,767 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-16 00:04:59,768 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-16 00:04:59,768 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-16 00:04:59,768 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-16 00:04:59,768 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 51b120a585d23a491f06d4bb80c2a463453987ac [2019-11-16 00:04:59,804 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-16 00:04:59,818 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-16 00:04:59,821 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-16 00:04:59,822 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-16 00:04:59,823 INFO L275 PluginConnector]: CDTParser initialized [2019-11-16 00:04:59,823 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2019-11-16 00:04:59,889 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/data/e53689718/f7072d0cadda4985b29c64e31ef1a139/FLAG856dd77ab [2019-11-16 00:05:00,328 INFO L306 CDTParser]: Found 1 translation units. [2019-11-16 00:05:00,331 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2019-11-16 00:05:00,349 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/data/e53689718/f7072d0cadda4985b29c64e31ef1a139/FLAG856dd77ab [2019-11-16 00:05:00,694 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/data/e53689718/f7072d0cadda4985b29c64e31ef1a139 [2019-11-16 00:05:00,697 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-16 00:05:00,698 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-16 00:05:00,699 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-16 00:05:00,699 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-16 00:05:00,703 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-16 00:05:00,704 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:05:00" (1/1) ... [2019-11-16 00:05:00,706 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@70abcff8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:00, skipping insertion in model container [2019-11-16 00:05:00,707 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:05:00" (1/1) ... [2019-11-16 00:05:00,714 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-16 00:05:00,767 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-16 00:05:01,156 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-16 00:05:01,167 INFO L188 MainTranslator]: Completed pre-run [2019-11-16 00:05:01,236 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-16 00:05:01,265 INFO L192 MainTranslator]: Completed translation [2019-11-16 00:05:01,266 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01 WrapperNode [2019-11-16 00:05:01,266 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-16 00:05:01,267 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-16 00:05:01,267 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-16 00:05:01,267 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-16 00:05:01,274 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01" (1/1) ... [2019-11-16 00:05:01,286 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01" (1/1) ... [2019-11-16 00:05:01,341 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-16 00:05:01,342 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-16 00:05:01,342 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-16 00:05:01,342 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-16 00:05:01,351 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01" (1/1) ... [2019-11-16 00:05:01,351 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01" (1/1) ... [2019-11-16 00:05:01,357 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01" (1/1) ... [2019-11-16 00:05:01,358 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01" (1/1) ... [2019-11-16 00:05:01,374 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01" (1/1) ... [2019-11-16 00:05:01,385 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01" (1/1) ... [2019-11-16 00:05:01,390 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01" (1/1) ... [2019-11-16 00:05:01,398 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-16 00:05:01,399 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-16 00:05:01,399 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-16 00:05:01,399 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-16 00:05:01,400 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-16 00:05:01,460 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-16 00:05:01,461 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-16 00:05:02,526 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-16 00:05:02,526 INFO L284 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-16 00:05:02,527 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:05:02 BoogieIcfgContainer [2019-11-16 00:05:02,528 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-16 00:05:02,528 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-16 00:05:02,529 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-16 00:05:02,531 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-16 00:05:02,531 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 16.11 12:05:00" (1/3) ... [2019-11-16 00:05:02,533 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@141df2d0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 12:05:02, skipping insertion in model container [2019-11-16 00:05:02,533 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:01" (2/3) ... [2019-11-16 00:05:02,533 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@141df2d0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 12:05:02, skipping insertion in model container [2019-11-16 00:05:02,533 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:05:02" (3/3) ... [2019-11-16 00:05:02,536 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2019-11-16 00:05:02,543 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-16 00:05:02,549 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-11-16 00:05:02,558 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-11-16 00:05:02,584 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-16 00:05:02,585 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-16 00:05:02,585 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-16 00:05:02,585 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-16 00:05:02,586 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-16 00:05:02,586 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-16 00:05:02,586 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-16 00:05:02,586 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-16 00:05:02,609 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states. [2019-11-16 00:05:02,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-11-16 00:05:02,616 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:02,617 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:02,620 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:02,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:02,624 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-11-16 00:05:02,630 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:02,630 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026543066] [2019-11-16 00:05:02,631 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:02,631 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:02,631 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:02,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:02,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:02,824 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1026543066] [2019-11-16 00:05:02,824 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:02,825 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:05:02,825 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1500430110] [2019-11-16 00:05:02,829 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:05:02,829 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:02,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:05:02,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:02,844 INFO L87 Difference]: Start difference. First operand 290 states. Second operand 3 states. [2019-11-16 00:05:02,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:02,937 INFO L93 Difference]: Finished difference Result 562 states and 879 transitions. [2019-11-16 00:05:02,938 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:05:02,939 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-11-16 00:05:02,939 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:02,954 INFO L225 Difference]: With dead ends: 562 [2019-11-16 00:05:02,954 INFO L226 Difference]: Without dead ends: 286 [2019-11-16 00:05:02,958 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:02,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states. [2019-11-16 00:05:03,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 286. [2019-11-16 00:05:03,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2019-11-16 00:05:03,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 408 transitions. [2019-11-16 00:05:03,014 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 408 transitions. Word has length 31 [2019-11-16 00:05:03,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:03,014 INFO L462 AbstractCegarLoop]: Abstraction has 286 states and 408 transitions. [2019-11-16 00:05:03,014 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:05:03,015 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 408 transitions. [2019-11-16 00:05:03,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-11-16 00:05:03,016 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:03,017 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:03,017 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:03,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:03,018 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-11-16 00:05:03,018 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:03,018 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422883984] [2019-11-16 00:05:03,019 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:03,019 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:03,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:03,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:03,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:03,211 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [422883984] [2019-11-16 00:05:03,212 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:03,212 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:05:03,212 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039046265] [2019-11-16 00:05:03,213 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:05:03,216 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:03,216 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:05:03,216 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:03,217 INFO L87 Difference]: Start difference. First operand 286 states and 408 transitions. Second operand 3 states. [2019-11-16 00:05:03,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:03,293 INFO L93 Difference]: Finished difference Result 590 states and 850 transitions. [2019-11-16 00:05:03,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:05:03,294 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-11-16 00:05:03,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:03,297 INFO L225 Difference]: With dead ends: 590 [2019-11-16 00:05:03,298 INFO L226 Difference]: Without dead ends: 319 [2019-11-16 00:05:03,300 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:03,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2019-11-16 00:05:03,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 262. [2019-11-16 00:05:03,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 262 states. [2019-11-16 00:05:03,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 372 transitions. [2019-11-16 00:05:03,320 INFO L78 Accepts]: Start accepts. Automaton has 262 states and 372 transitions. Word has length 42 [2019-11-16 00:05:03,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:03,320 INFO L462 AbstractCegarLoop]: Abstraction has 262 states and 372 transitions. [2019-11-16 00:05:03,320 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:05:03,321 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 372 transitions. [2019-11-16 00:05:03,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-16 00:05:03,323 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:03,323 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:03,324 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:03,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:03,324 INFO L82 PathProgramCache]: Analyzing trace with hash -365626229, now seen corresponding path program 1 times [2019-11-16 00:05:03,324 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:03,324 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970169303] [2019-11-16 00:05:03,325 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:03,325 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:03,325 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:03,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:03,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:03,519 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970169303] [2019-11-16 00:05:03,519 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:03,519 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:05:03,519 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238958954] [2019-11-16 00:05:03,520 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:05:03,520 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:03,520 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:05:03,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:03,521 INFO L87 Difference]: Start difference. First operand 262 states and 372 transitions. Second operand 3 states. [2019-11-16 00:05:03,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:03,557 INFO L93 Difference]: Finished difference Result 733 states and 1051 transitions. [2019-11-16 00:05:03,557 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:05:03,558 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-16 00:05:03,558 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:03,561 INFO L225 Difference]: With dead ends: 733 [2019-11-16 00:05:03,562 INFO L226 Difference]: Without dead ends: 486 [2019-11-16 00:05:03,563 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:03,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 486 states. [2019-11-16 00:05:03,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 486 to 295. [2019-11-16 00:05:03,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 295 states. [2019-11-16 00:05:03,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 295 states to 295 states and 420 transitions. [2019-11-16 00:05:03,605 INFO L78 Accepts]: Start accepts. Automaton has 295 states and 420 transitions. Word has length 49 [2019-11-16 00:05:03,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:03,607 INFO L462 AbstractCegarLoop]: Abstraction has 295 states and 420 transitions. [2019-11-16 00:05:03,607 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:05:03,607 INFO L276 IsEmpty]: Start isEmpty. Operand 295 states and 420 transitions. [2019-11-16 00:05:03,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-11-16 00:05:03,614 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:03,614 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:03,615 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:03,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:03,615 INFO L82 PathProgramCache]: Analyzing trace with hash 744745200, now seen corresponding path program 1 times [2019-11-16 00:05:03,616 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:03,616 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721121879] [2019-11-16 00:05:03,616 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:03,616 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:03,617 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:03,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:03,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:03,793 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1721121879] [2019-11-16 00:05:03,793 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:03,794 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:05:03,794 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905899193] [2019-11-16 00:05:03,794 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:05:03,795 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:03,796 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:05:03,796 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:03,796 INFO L87 Difference]: Start difference. First operand 295 states and 420 transitions. Second operand 5 states. [2019-11-16 00:05:04,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:04,111 INFO L93 Difference]: Finished difference Result 929 states and 1337 transitions. [2019-11-16 00:05:04,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:05:04,112 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-11-16 00:05:04,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:04,119 INFO L225 Difference]: With dead ends: 929 [2019-11-16 00:05:04,119 INFO L226 Difference]: Without dead ends: 649 [2019-11-16 00:05:04,121 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-16 00:05:04,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 649 states. [2019-11-16 00:05:04,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 649 to 381. [2019-11-16 00:05:04,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 381 states. [2019-11-16 00:05:04,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 543 transitions. [2019-11-16 00:05:04,155 INFO L78 Accepts]: Start accepts. Automaton has 381 states and 543 transitions. Word has length 50 [2019-11-16 00:05:04,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:04,157 INFO L462 AbstractCegarLoop]: Abstraction has 381 states and 543 transitions. [2019-11-16 00:05:04,158 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:05:04,158 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 543 transitions. [2019-11-16 00:05:04,164 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-11-16 00:05:04,164 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:04,165 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:04,165 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:04,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:04,166 INFO L82 PathProgramCache]: Analyzing trace with hash 1614483527, now seen corresponding path program 1 times [2019-11-16 00:05:04,166 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:04,166 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696850423] [2019-11-16 00:05:04,167 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:04,167 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:04,167 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:04,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:04,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:04,281 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696850423] [2019-11-16 00:05:04,281 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:04,281 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:05:04,282 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1152906153] [2019-11-16 00:05:04,282 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:05:04,283 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:04,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:05:04,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:04,284 INFO L87 Difference]: Start difference. First operand 381 states and 543 transitions. Second operand 5 states. [2019-11-16 00:05:04,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:04,578 INFO L93 Difference]: Finished difference Result 929 states and 1333 transitions. [2019-11-16 00:05:04,579 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:05:04,579 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-11-16 00:05:04,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:04,585 INFO L225 Difference]: With dead ends: 929 [2019-11-16 00:05:04,585 INFO L226 Difference]: Without dead ends: 649 [2019-11-16 00:05:04,586 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-16 00:05:04,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 649 states. [2019-11-16 00:05:04,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 649 to 381. [2019-11-16 00:05:04,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 381 states. [2019-11-16 00:05:04,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 541 transitions. [2019-11-16 00:05:04,612 INFO L78 Accepts]: Start accepts. Automaton has 381 states and 541 transitions. Word has length 51 [2019-11-16 00:05:04,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:04,613 INFO L462 AbstractCegarLoop]: Abstraction has 381 states and 541 transitions. [2019-11-16 00:05:04,613 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:05:04,613 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 541 transitions. [2019-11-16 00:05:04,615 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-16 00:05:04,615 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:04,615 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:04,616 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:04,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:04,616 INFO L82 PathProgramCache]: Analyzing trace with hash 251892323, now seen corresponding path program 1 times [2019-11-16 00:05:04,617 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:04,617 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664923554] [2019-11-16 00:05:04,617 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:04,617 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:04,618 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:04,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:04,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:04,813 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664923554] [2019-11-16 00:05:04,813 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:04,813 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:05:04,813 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [658517990] [2019-11-16 00:05:04,814 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:05:04,814 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:04,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:05:04,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:04,815 INFO L87 Difference]: Start difference. First operand 381 states and 541 transitions. Second operand 5 states. [2019-11-16 00:05:04,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:04,881 INFO L93 Difference]: Finished difference Result 757 states and 1086 transitions. [2019-11-16 00:05:04,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-16 00:05:04,882 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2019-11-16 00:05:04,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:04,887 INFO L225 Difference]: With dead ends: 757 [2019-11-16 00:05:04,887 INFO L226 Difference]: Without dead ends: 477 [2019-11-16 00:05:04,888 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:05:04,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 477 states. [2019-11-16 00:05:04,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 477 to 376. [2019-11-16 00:05:04,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 376 states. [2019-11-16 00:05:04,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 376 states to 376 states and 533 transitions. [2019-11-16 00:05:04,949 INFO L78 Accepts]: Start accepts. Automaton has 376 states and 533 transitions. Word has length 52 [2019-11-16 00:05:04,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:04,949 INFO L462 AbstractCegarLoop]: Abstraction has 376 states and 533 transitions. [2019-11-16 00:05:04,950 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:05:04,950 INFO L276 IsEmpty]: Start isEmpty. Operand 376 states and 533 transitions. [2019-11-16 00:05:04,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-16 00:05:04,951 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:04,951 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:04,952 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:04,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:04,960 INFO L82 PathProgramCache]: Analyzing trace with hash -1519937093, now seen corresponding path program 1 times [2019-11-16 00:05:04,960 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:04,960 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055183568] [2019-11-16 00:05:04,961 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:04,961 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:04,961 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:05,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:05,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:05,152 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055183568] [2019-11-16 00:05:05,153 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:05,153 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:05:05,153 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454119542] [2019-11-16 00:05:05,153 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:05:05,153 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:05,154 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:05:05,154 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:05,154 INFO L87 Difference]: Start difference. First operand 376 states and 533 transitions. Second operand 5 states. [2019-11-16 00:05:05,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:05,293 INFO L93 Difference]: Finished difference Result 788 states and 1135 transitions. [2019-11-16 00:05:05,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:05:05,294 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-11-16 00:05:05,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:05,298 INFO L225 Difference]: With dead ends: 788 [2019-11-16 00:05:05,299 INFO L226 Difference]: Without dead ends: 513 [2019-11-16 00:05:05,300 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:05:05,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 513 states. [2019-11-16 00:05:05,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 513 to 346. [2019-11-16 00:05:05,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 346 states. [2019-11-16 00:05:05,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346 states to 346 states and 487 transitions. [2019-11-16 00:05:05,322 INFO L78 Accepts]: Start accepts. Automaton has 346 states and 487 transitions. Word has length 56 [2019-11-16 00:05:05,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:05,323 INFO L462 AbstractCegarLoop]: Abstraction has 346 states and 487 transitions. [2019-11-16 00:05:05,323 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:05:05,323 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 487 transitions. [2019-11-16 00:05:05,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-16 00:05:05,324 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:05,324 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:05,325 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:05,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:05,326 INFO L82 PathProgramCache]: Analyzing trace with hash 1786376721, now seen corresponding path program 1 times [2019-11-16 00:05:05,326 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:05,326 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1042332623] [2019-11-16 00:05:05,326 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:05,326 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:05,327 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:05,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:05,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:05,451 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1042332623] [2019-11-16 00:05:05,452 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:05,452 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:05:05,452 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982032104] [2019-11-16 00:05:05,452 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:05:05,453 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:05,453 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:05:05,453 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:05,453 INFO L87 Difference]: Start difference. First operand 346 states and 487 transitions. Second operand 5 states. [2019-11-16 00:05:05,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:05,590 INFO L93 Difference]: Finished difference Result 880 states and 1256 transitions. [2019-11-16 00:05:05,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:05:05,591 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 61 [2019-11-16 00:05:05,591 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:05,594 INFO L225 Difference]: With dead ends: 880 [2019-11-16 00:05:05,595 INFO L226 Difference]: Without dead ends: 635 [2019-11-16 00:05:05,596 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:05:05,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 635 states. [2019-11-16 00:05:05,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 635 to 316. [2019-11-16 00:05:05,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 316 states. [2019-11-16 00:05:05,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 316 states and 441 transitions. [2019-11-16 00:05:05,619 INFO L78 Accepts]: Start accepts. Automaton has 316 states and 441 transitions. Word has length 61 [2019-11-16 00:05:05,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:05,619 INFO L462 AbstractCegarLoop]: Abstraction has 316 states and 441 transitions. [2019-11-16 00:05:05,619 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:05:05,619 INFO L276 IsEmpty]: Start isEmpty. Operand 316 states and 441 transitions. [2019-11-16 00:05:05,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-11-16 00:05:05,620 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:05,620 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:05,621 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:05,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:05,622 INFO L82 PathProgramCache]: Analyzing trace with hash -1245848025, now seen corresponding path program 1 times [2019-11-16 00:05:05,622 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:05,622 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109409901] [2019-11-16 00:05:05,622 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:05,622 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:05,623 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:05,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:05,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:05,780 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109409901] [2019-11-16 00:05:05,780 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:05,780 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:05:05,781 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1353839678] [2019-11-16 00:05:05,781 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:05:05,781 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:05,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:05:05,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:05:05,782 INFO L87 Difference]: Start difference. First operand 316 states and 441 transitions. Second operand 6 states. [2019-11-16 00:05:06,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:06,046 INFO L93 Difference]: Finished difference Result 1074 states and 1513 transitions. [2019-11-16 00:05:06,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-16 00:05:06,047 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-11-16 00:05:06,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:06,053 INFO L225 Difference]: With dead ends: 1074 [2019-11-16 00:05:06,053 INFO L226 Difference]: Without dead ends: 859 [2019-11-16 00:05:06,054 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-16 00:05:06,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 859 states. [2019-11-16 00:05:06,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 859 to 355. [2019-11-16 00:05:06,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 355 states. [2019-11-16 00:05:06,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 355 states to 355 states and 495 transitions. [2019-11-16 00:05:06,085 INFO L78 Accepts]: Start accepts. Automaton has 355 states and 495 transitions. Word has length 66 [2019-11-16 00:05:06,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:06,085 INFO L462 AbstractCegarLoop]: Abstraction has 355 states and 495 transitions. [2019-11-16 00:05:06,085 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:05:06,085 INFO L276 IsEmpty]: Start isEmpty. Operand 355 states and 495 transitions. [2019-11-16 00:05:06,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-11-16 00:05:06,086 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:06,086 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:06,087 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:06,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:06,088 INFO L82 PathProgramCache]: Analyzing trace with hash 1591247394, now seen corresponding path program 1 times [2019-11-16 00:05:06,088 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:06,088 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166006706] [2019-11-16 00:05:06,088 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:06,088 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:06,089 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:06,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:06,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:06,145 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166006706] [2019-11-16 00:05:06,145 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:06,145 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:05:06,145 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930395850] [2019-11-16 00:05:06,145 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:05:06,146 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:06,146 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:05:06,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:06,146 INFO L87 Difference]: Start difference. First operand 355 states and 495 transitions. Second operand 3 states. [2019-11-16 00:05:06,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:06,209 INFO L93 Difference]: Finished difference Result 647 states and 912 transitions. [2019-11-16 00:05:06,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:05:06,210 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-11-16 00:05:06,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:06,213 INFO L225 Difference]: With dead ends: 647 [2019-11-16 00:05:06,213 INFO L226 Difference]: Without dead ends: 432 [2019-11-16 00:05:06,214 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:06,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432 states. [2019-11-16 00:05:06,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432 to 351. [2019-11-16 00:05:06,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 351 states. [2019-11-16 00:05:06,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 351 states to 351 states and 488 transitions. [2019-11-16 00:05:06,239 INFO L78 Accepts]: Start accepts. Automaton has 351 states and 488 transitions. Word has length 67 [2019-11-16 00:05:06,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:06,240 INFO L462 AbstractCegarLoop]: Abstraction has 351 states and 488 transitions. [2019-11-16 00:05:06,240 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:05:06,240 INFO L276 IsEmpty]: Start isEmpty. Operand 351 states and 488 transitions. [2019-11-16 00:05:06,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-11-16 00:05:06,241 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:06,241 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:06,244 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:06,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:06,245 INFO L82 PathProgramCache]: Analyzing trace with hash 480130565, now seen corresponding path program 1 times [2019-11-16 00:05:06,245 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:06,245 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439009800] [2019-11-16 00:05:06,245 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:06,246 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:06,246 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:06,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:06,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:06,317 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439009800] [2019-11-16 00:05:06,317 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:06,318 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:05:06,318 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1270036394] [2019-11-16 00:05:06,318 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:05:06,319 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:06,319 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:05:06,319 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:05:06,319 INFO L87 Difference]: Start difference. First operand 351 states and 488 transitions. Second operand 4 states. [2019-11-16 00:05:06,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:06,472 INFO L93 Difference]: Finished difference Result 933 states and 1300 transitions. [2019-11-16 00:05:06,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:05:06,473 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 70 [2019-11-16 00:05:06,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:06,477 INFO L225 Difference]: With dead ends: 933 [2019-11-16 00:05:06,478 INFO L226 Difference]: Without dead ends: 712 [2019-11-16 00:05:06,478 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:06,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 712 states. [2019-11-16 00:05:06,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 712 to 517. [2019-11-16 00:05:06,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 517 states. [2019-11-16 00:05:06,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 517 states to 517 states and 715 transitions. [2019-11-16 00:05:06,517 INFO L78 Accepts]: Start accepts. Automaton has 517 states and 715 transitions. Word has length 70 [2019-11-16 00:05:06,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:06,518 INFO L462 AbstractCegarLoop]: Abstraction has 517 states and 715 transitions. [2019-11-16 00:05:06,518 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:05:06,518 INFO L276 IsEmpty]: Start isEmpty. Operand 517 states and 715 transitions. [2019-11-16 00:05:06,519 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-11-16 00:05:06,519 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:06,519 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:06,520 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:06,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:06,520 INFO L82 PathProgramCache]: Analyzing trace with hash -1523824051, now seen corresponding path program 1 times [2019-11-16 00:05:06,521 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:06,521 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762329910] [2019-11-16 00:05:06,521 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:06,521 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:06,521 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:06,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:06,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:06,564 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762329910] [2019-11-16 00:05:06,564 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:06,564 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:05:06,564 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738346878] [2019-11-16 00:05:06,565 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:05:06,565 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:06,565 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:05:06,565 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:06,565 INFO L87 Difference]: Start difference. First operand 517 states and 715 transitions. Second operand 3 states. [2019-11-16 00:05:06,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:06,635 INFO L93 Difference]: Finished difference Result 1220 states and 1679 transitions. [2019-11-16 00:05:06,635 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:05:06,636 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-11-16 00:05:06,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:06,641 INFO L225 Difference]: With dead ends: 1220 [2019-11-16 00:05:06,641 INFO L226 Difference]: Without dead ends: 850 [2019-11-16 00:05:06,642 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:06,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 850 states. [2019-11-16 00:05:06,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 850 to 578. [2019-11-16 00:05:06,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 578 states. [2019-11-16 00:05:06,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 578 states to 578 states and 792 transitions. [2019-11-16 00:05:06,696 INFO L78 Accepts]: Start accepts. Automaton has 578 states and 792 transitions. Word has length 70 [2019-11-16 00:05:06,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:06,696 INFO L462 AbstractCegarLoop]: Abstraction has 578 states and 792 transitions. [2019-11-16 00:05:06,696 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:05:06,696 INFO L276 IsEmpty]: Start isEmpty. Operand 578 states and 792 transitions. [2019-11-16 00:05:06,697 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-11-16 00:05:06,698 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:06,698 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:06,699 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:06,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:06,699 INFO L82 PathProgramCache]: Analyzing trace with hash -1383275441, now seen corresponding path program 1 times [2019-11-16 00:05:06,699 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:06,700 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949908279] [2019-11-16 00:05:06,700 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:06,700 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:06,700 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:06,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:06,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:06,759 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949908279] [2019-11-16 00:05:06,760 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:06,760 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:05:06,760 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [409216227] [2019-11-16 00:05:06,760 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:05:06,761 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:06,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:05:06,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:06,762 INFO L87 Difference]: Start difference. First operand 578 states and 792 transitions. Second operand 3 states. [2019-11-16 00:05:06,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:06,815 INFO L93 Difference]: Finished difference Result 982 states and 1355 transitions. [2019-11-16 00:05:06,815 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:05:06,815 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-11-16 00:05:06,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:06,819 INFO L225 Difference]: With dead ends: 982 [2019-11-16 00:05:06,819 INFO L226 Difference]: Without dead ends: 543 [2019-11-16 00:05:06,820 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:06,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2019-11-16 00:05:06,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 543. [2019-11-16 00:05:06,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 543 states. [2019-11-16 00:05:06,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 543 states to 543 states and 743 transitions. [2019-11-16 00:05:06,870 INFO L78 Accepts]: Start accepts. Automaton has 543 states and 743 transitions. Word has length 70 [2019-11-16 00:05:06,870 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:06,870 INFO L462 AbstractCegarLoop]: Abstraction has 543 states and 743 transitions. [2019-11-16 00:05:06,870 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:05:06,871 INFO L276 IsEmpty]: Start isEmpty. Operand 543 states and 743 transitions. [2019-11-16 00:05:06,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-11-16 00:05:06,872 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:06,872 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:06,873 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:06,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:06,873 INFO L82 PathProgramCache]: Analyzing trace with hash -1837662732, now seen corresponding path program 1 times [2019-11-16 00:05:06,874 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:06,874 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55656225] [2019-11-16 00:05:06,874 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:06,874 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:06,874 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:06,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:07,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:07,076 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55656225] [2019-11-16 00:05:07,077 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:07,077 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:05:07,077 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7260981] [2019-11-16 00:05:07,077 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:05:07,078 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:07,078 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:05:07,078 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:05:07,078 INFO L87 Difference]: Start difference. First operand 543 states and 743 transitions. Second operand 6 states. [2019-11-16 00:05:07,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:07,415 INFO L93 Difference]: Finished difference Result 1703 states and 2366 transitions. [2019-11-16 00:05:07,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-16 00:05:07,416 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-11-16 00:05:07,416 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:07,423 INFO L225 Difference]: With dead ends: 1703 [2019-11-16 00:05:07,424 INFO L226 Difference]: Without dead ends: 1380 [2019-11-16 00:05:07,425 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-16 00:05:07,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1380 states. [2019-11-16 00:05:07,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1380 to 547. [2019-11-16 00:05:07,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 547 states. [2019-11-16 00:05:07,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 547 states to 547 states and 748 transitions. [2019-11-16 00:05:07,471 INFO L78 Accepts]: Start accepts. Automaton has 547 states and 748 transitions. Word has length 71 [2019-11-16 00:05:07,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:07,472 INFO L462 AbstractCegarLoop]: Abstraction has 547 states and 748 transitions. [2019-11-16 00:05:07,472 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:05:07,472 INFO L276 IsEmpty]: Start isEmpty. Operand 547 states and 748 transitions. [2019-11-16 00:05:07,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-11-16 00:05:07,473 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:07,473 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:07,474 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:07,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:07,474 INFO L82 PathProgramCache]: Analyzing trace with hash 276642491, now seen corresponding path program 1 times [2019-11-16 00:05:07,474 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:07,475 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783850274] [2019-11-16 00:05:07,475 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:07,475 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:07,475 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:07,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:07,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:07,581 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783850274] [2019-11-16 00:05:07,581 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:07,581 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:05:07,581 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1722454687] [2019-11-16 00:05:07,582 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:05:07,582 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:07,582 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:05:07,582 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:07,582 INFO L87 Difference]: Start difference. First operand 547 states and 748 transitions. Second operand 5 states. [2019-11-16 00:05:07,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:07,744 INFO L93 Difference]: Finished difference Result 856 states and 1187 transitions. [2019-11-16 00:05:07,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:05:07,745 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2019-11-16 00:05:07,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:07,750 INFO L225 Difference]: With dead ends: 856 [2019-11-16 00:05:07,750 INFO L226 Difference]: Without dead ends: 854 [2019-11-16 00:05:07,751 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-16 00:05:07,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 854 states. [2019-11-16 00:05:07,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 854 to 549. [2019-11-16 00:05:07,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 549 states. [2019-11-16 00:05:07,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 549 states and 750 transitions. [2019-11-16 00:05:07,794 INFO L78 Accepts]: Start accepts. Automaton has 549 states and 750 transitions. Word has length 71 [2019-11-16 00:05:07,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:07,795 INFO L462 AbstractCegarLoop]: Abstraction has 549 states and 750 transitions. [2019-11-16 00:05:07,795 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:05:07,795 INFO L276 IsEmpty]: Start isEmpty. Operand 549 states and 750 transitions. [2019-11-16 00:05:07,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-11-16 00:05:07,796 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:07,796 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:07,797 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:07,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:07,797 INFO L82 PathProgramCache]: Analyzing trace with hash -66828782, now seen corresponding path program 1 times [2019-11-16 00:05:07,798 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:07,798 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506975379] [2019-11-16 00:05:07,798 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:07,798 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:07,798 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:07,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:07,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:07,901 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [506975379] [2019-11-16 00:05:07,903 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:07,903 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:05:07,903 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [487315577] [2019-11-16 00:05:07,904 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:05:07,904 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:07,904 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:05:07,904 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:05:07,905 INFO L87 Difference]: Start difference. First operand 549 states and 750 transitions. Second operand 6 states. [2019-11-16 00:05:08,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:08,438 INFO L93 Difference]: Finished difference Result 1970 states and 2711 transitions. [2019-11-16 00:05:08,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-16 00:05:08,440 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-11-16 00:05:08,440 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:08,449 INFO L225 Difference]: With dead ends: 1970 [2019-11-16 00:05:08,449 INFO L226 Difference]: Without dead ends: 1606 [2019-11-16 00:05:08,451 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-16 00:05:08,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1606 states. [2019-11-16 00:05:08,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1606 to 595. [2019-11-16 00:05:08,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 595 states. [2019-11-16 00:05:08,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 595 states to 595 states and 808 transitions. [2019-11-16 00:05:08,513 INFO L78 Accepts]: Start accepts. Automaton has 595 states and 808 transitions. Word has length 71 [2019-11-16 00:05:08,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:08,514 INFO L462 AbstractCegarLoop]: Abstraction has 595 states and 808 transitions. [2019-11-16 00:05:08,514 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:05:08,514 INFO L276 IsEmpty]: Start isEmpty. Operand 595 states and 808 transitions. [2019-11-16 00:05:08,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-16 00:05:08,516 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:08,516 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:08,520 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:08,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:08,521 INFO L82 PathProgramCache]: Analyzing trace with hash -624478278, now seen corresponding path program 1 times [2019-11-16 00:05:08,521 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:08,521 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801434635] [2019-11-16 00:05:08,521 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:08,521 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:08,522 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:08,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:08,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:08,647 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801434635] [2019-11-16 00:05:08,647 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:08,647 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:05:08,647 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1720333343] [2019-11-16 00:05:08,648 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:05:08,648 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:08,648 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:05:08,649 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:05:08,649 INFO L87 Difference]: Start difference. First operand 595 states and 808 transitions. Second operand 6 states. [2019-11-16 00:05:09,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:09,188 INFO L93 Difference]: Finished difference Result 2296 states and 3143 transitions. [2019-11-16 00:05:09,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-16 00:05:09,189 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-11-16 00:05:09,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:09,199 INFO L225 Difference]: With dead ends: 2296 [2019-11-16 00:05:09,200 INFO L226 Difference]: Without dead ends: 1924 [2019-11-16 00:05:09,201 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-16 00:05:09,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1924 states. [2019-11-16 00:05:09,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1924 to 673. [2019-11-16 00:05:09,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 673 states. [2019-11-16 00:05:09,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 673 states to 673 states and 910 transitions. [2019-11-16 00:05:09,268 INFO L78 Accepts]: Start accepts. Automaton has 673 states and 910 transitions. Word has length 72 [2019-11-16 00:05:09,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:09,269 INFO L462 AbstractCegarLoop]: Abstraction has 673 states and 910 transitions. [2019-11-16 00:05:09,269 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:05:09,269 INFO L276 IsEmpty]: Start isEmpty. Operand 673 states and 910 transitions. [2019-11-16 00:05:09,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-16 00:05:09,272 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:09,272 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:09,273 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:09,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:09,273 INFO L82 PathProgramCache]: Analyzing trace with hash -2046951303, now seen corresponding path program 1 times [2019-11-16 00:05:09,273 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:09,273 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257870379] [2019-11-16 00:05:09,274 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:09,274 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:09,274 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:09,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:09,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:09,360 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257870379] [2019-11-16 00:05:09,360 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:09,360 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:05:09,360 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797803522] [2019-11-16 00:05:09,361 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:05:09,361 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:09,361 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:05:09,361 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:05:09,362 INFO L87 Difference]: Start difference. First operand 673 states and 910 transitions. Second operand 6 states. [2019-11-16 00:05:09,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:09,568 INFO L93 Difference]: Finished difference Result 1495 states and 2085 transitions. [2019-11-16 00:05:09,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-16 00:05:09,569 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-11-16 00:05:09,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:09,575 INFO L225 Difference]: With dead ends: 1495 [2019-11-16 00:05:09,575 INFO L226 Difference]: Without dead ends: 1106 [2019-11-16 00:05:09,576 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-11-16 00:05:09,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1106 states. [2019-11-16 00:05:09,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1106 to 679. [2019-11-16 00:05:09,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 679 states. [2019-11-16 00:05:09,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 679 states to 679 states and 916 transitions. [2019-11-16 00:05:09,638 INFO L78 Accepts]: Start accepts. Automaton has 679 states and 916 transitions. Word has length 72 [2019-11-16 00:05:09,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:09,639 INFO L462 AbstractCegarLoop]: Abstraction has 679 states and 916 transitions. [2019-11-16 00:05:09,639 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:05:09,639 INFO L276 IsEmpty]: Start isEmpty. Operand 679 states and 916 transitions. [2019-11-16 00:05:09,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-16 00:05:09,640 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:09,640 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:09,641 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:09,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:09,641 INFO L82 PathProgramCache]: Analyzing trace with hash 778464989, now seen corresponding path program 1 times [2019-11-16 00:05:09,641 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:09,642 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686451984] [2019-11-16 00:05:09,642 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:09,642 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:09,642 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:09,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:09,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:09,693 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686451984] [2019-11-16 00:05:09,693 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:09,693 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:05:09,693 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661639525] [2019-11-16 00:05:09,694 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:05:09,695 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:09,695 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:05:09,695 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:09,695 INFO L87 Difference]: Start difference. First operand 679 states and 916 transitions. Second operand 3 states. [2019-11-16 00:05:09,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:09,813 INFO L93 Difference]: Finished difference Result 1331 states and 1818 transitions. [2019-11-16 00:05:09,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:05:09,813 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-16 00:05:09,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:09,818 INFO L225 Difference]: With dead ends: 1331 [2019-11-16 00:05:09,818 INFO L226 Difference]: Without dead ends: 873 [2019-11-16 00:05:09,820 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:09,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 873 states. [2019-11-16 00:05:09,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 873 to 658. [2019-11-16 00:05:09,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 658 states. [2019-11-16 00:05:09,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 879 transitions. [2019-11-16 00:05:09,881 INFO L78 Accepts]: Start accepts. Automaton has 658 states and 879 transitions. Word has length 72 [2019-11-16 00:05:09,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:09,881 INFO L462 AbstractCegarLoop]: Abstraction has 658 states and 879 transitions. [2019-11-16 00:05:09,882 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:05:09,882 INFO L276 IsEmpty]: Start isEmpty. Operand 658 states and 879 transitions. [2019-11-16 00:05:09,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-16 00:05:09,883 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:09,883 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:09,883 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:09,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:09,884 INFO L82 PathProgramCache]: Analyzing trace with hash 449594347, now seen corresponding path program 1 times [2019-11-16 00:05:09,884 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:09,884 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152867573] [2019-11-16 00:05:09,884 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:09,885 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:09,885 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:09,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:09,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:09,938 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152867573] [2019-11-16 00:05:09,939 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:09,939 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:05:09,939 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1716581730] [2019-11-16 00:05:09,940 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:05:09,940 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:09,940 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:05:09,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:05:09,940 INFO L87 Difference]: Start difference. First operand 658 states and 879 transitions. Second operand 4 states. [2019-11-16 00:05:10,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:10,146 INFO L93 Difference]: Finished difference Result 1698 states and 2278 transitions. [2019-11-16 00:05:10,147 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:05:10,147 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-11-16 00:05:10,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:10,154 INFO L225 Difference]: With dead ends: 1698 [2019-11-16 00:05:10,154 INFO L226 Difference]: Without dead ends: 1293 [2019-11-16 00:05:10,155 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:10,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1293 states. [2019-11-16 00:05:10,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1293 to 892. [2019-11-16 00:05:10,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-11-16 00:05:10,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1190 transitions. [2019-11-16 00:05:10,238 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1190 transitions. Word has length 73 [2019-11-16 00:05:10,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:10,239 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1190 transitions. [2019-11-16 00:05:10,239 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:05:10,239 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1190 transitions. [2019-11-16 00:05:10,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-16 00:05:10,240 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:10,240 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:10,241 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:10,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:10,241 INFO L82 PathProgramCache]: Analyzing trace with hash 1828954211, now seen corresponding path program 1 times [2019-11-16 00:05:10,241 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:10,242 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389768109] [2019-11-16 00:05:10,242 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:10,242 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:10,242 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:10,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:10,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:10,304 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [389768109] [2019-11-16 00:05:10,304 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:10,304 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:05:10,304 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560833656] [2019-11-16 00:05:10,305 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:05:10,306 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:10,309 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:05:10,309 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:10,310 INFO L87 Difference]: Start difference. First operand 892 states and 1190 transitions. Second operand 3 states. [2019-11-16 00:05:10,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:10,454 INFO L93 Difference]: Finished difference Result 1867 states and 2508 transitions. [2019-11-16 00:05:10,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:05:10,454 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-16 00:05:10,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:10,461 INFO L225 Difference]: With dead ends: 1867 [2019-11-16 00:05:10,461 INFO L226 Difference]: Without dead ends: 1279 [2019-11-16 00:05:10,463 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:10,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1279 states. [2019-11-16 00:05:10,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1279 to 848. [2019-11-16 00:05:10,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 848 states. [2019-11-16 00:05:10,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 848 states to 848 states and 1126 transitions. [2019-11-16 00:05:10,545 INFO L78 Accepts]: Start accepts. Automaton has 848 states and 1126 transitions. Word has length 73 [2019-11-16 00:05:10,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:10,545 INFO L462 AbstractCegarLoop]: Abstraction has 848 states and 1126 transitions. [2019-11-16 00:05:10,545 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:05:10,546 INFO L276 IsEmpty]: Start isEmpty. Operand 848 states and 1126 transitions. [2019-11-16 00:05:10,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-16 00:05:10,569 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:10,569 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:10,569 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:10,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:10,570 INFO L82 PathProgramCache]: Analyzing trace with hash 1948644571, now seen corresponding path program 1 times [2019-11-16 00:05:10,570 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:10,570 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877798114] [2019-11-16 00:05:10,570 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:10,570 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:10,570 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:10,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:10,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:10,628 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1877798114] [2019-11-16 00:05:10,629 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:10,629 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:05:10,629 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648389185] [2019-11-16 00:05:10,629 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:05:10,630 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:10,630 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:05:10,630 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:05:10,630 INFO L87 Difference]: Start difference. First operand 848 states and 1126 transitions. Second operand 4 states. [2019-11-16 00:05:10,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:10,855 INFO L93 Difference]: Finished difference Result 1982 states and 2626 transitions. [2019-11-16 00:05:10,857 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:05:10,857 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-11-16 00:05:10,857 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:10,864 INFO L225 Difference]: With dead ends: 1982 [2019-11-16 00:05:10,865 INFO L226 Difference]: Without dead ends: 1423 [2019-11-16 00:05:10,866 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:10,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1423 states. [2019-11-16 00:05:10,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1423 to 1130. [2019-11-16 00:05:10,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1130 states. [2019-11-16 00:05:10,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1130 states to 1130 states and 1490 transitions. [2019-11-16 00:05:10,972 INFO L78 Accepts]: Start accepts. Automaton has 1130 states and 1490 transitions. Word has length 73 [2019-11-16 00:05:10,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:10,972 INFO L462 AbstractCegarLoop]: Abstraction has 1130 states and 1490 transitions. [2019-11-16 00:05:10,973 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:05:10,973 INFO L276 IsEmpty]: Start isEmpty. Operand 1130 states and 1490 transitions. [2019-11-16 00:05:10,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-16 00:05:10,974 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:10,974 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:10,976 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:10,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:10,976 INFO L82 PathProgramCache]: Analyzing trace with hash 1795806066, now seen corresponding path program 1 times [2019-11-16 00:05:10,976 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:10,976 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949090352] [2019-11-16 00:05:10,977 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:10,977 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:10,977 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:10,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:11,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:11,005 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949090352] [2019-11-16 00:05:11,005 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:11,005 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:05:11,005 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1562374115] [2019-11-16 00:05:11,007 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:05:11,007 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:11,007 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:05:11,007 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:11,008 INFO L87 Difference]: Start difference. First operand 1130 states and 1490 transitions. Second operand 3 states. [2019-11-16 00:05:11,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:11,286 INFO L93 Difference]: Finished difference Result 2791 states and 3670 transitions. [2019-11-16 00:05:11,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:05:11,287 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-11-16 00:05:11,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:11,297 INFO L225 Difference]: With dead ends: 2791 [2019-11-16 00:05:11,297 INFO L226 Difference]: Without dead ends: 1894 [2019-11-16 00:05:11,299 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:05:11,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1894 states. [2019-11-16 00:05:11,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1894 to 1132. [2019-11-16 00:05:11,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1132 states. [2019-11-16 00:05:11,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1132 states to 1132 states and 1492 transitions. [2019-11-16 00:05:11,415 INFO L78 Accepts]: Start accepts. Automaton has 1132 states and 1492 transitions. Word has length 74 [2019-11-16 00:05:11,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:11,415 INFO L462 AbstractCegarLoop]: Abstraction has 1132 states and 1492 transitions. [2019-11-16 00:05:11,416 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:05:11,416 INFO L276 IsEmpty]: Start isEmpty. Operand 1132 states and 1492 transitions. [2019-11-16 00:05:11,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-16 00:05:11,417 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:11,417 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:11,418 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:11,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:11,418 INFO L82 PathProgramCache]: Analyzing trace with hash 230569326, now seen corresponding path program 1 times [2019-11-16 00:05:11,419 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:11,419 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256274226] [2019-11-16 00:05:11,419 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:11,419 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:11,419 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:11,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:11,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:11,488 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256274226] [2019-11-16 00:05:11,488 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:11,488 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:05:11,488 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [138771448] [2019-11-16 00:05:11,489 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:05:11,489 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:11,489 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:05:11,490 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:05:11,490 INFO L87 Difference]: Start difference. First operand 1132 states and 1492 transitions. Second operand 4 states. [2019-11-16 00:05:11,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:11,670 INFO L93 Difference]: Finished difference Result 2362 states and 3100 transitions. [2019-11-16 00:05:11,671 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:05:11,671 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-11-16 00:05:11,671 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:11,677 INFO L225 Difference]: With dead ends: 2362 [2019-11-16 00:05:11,678 INFO L226 Difference]: Without dead ends: 1285 [2019-11-16 00:05:11,680 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:11,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1285 states. [2019-11-16 00:05:11,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1285 to 945. [2019-11-16 00:05:11,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 945 states. [2019-11-16 00:05:11,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 945 states to 945 states and 1236 transitions. [2019-11-16 00:05:11,782 INFO L78 Accepts]: Start accepts. Automaton has 945 states and 1236 transitions. Word has length 75 [2019-11-16 00:05:11,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:11,783 INFO L462 AbstractCegarLoop]: Abstraction has 945 states and 1236 transitions. [2019-11-16 00:05:11,783 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:05:11,783 INFO L276 IsEmpty]: Start isEmpty. Operand 945 states and 1236 transitions. [2019-11-16 00:05:11,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-11-16 00:05:11,784 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:11,784 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:11,785 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:11,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:11,785 INFO L82 PathProgramCache]: Analyzing trace with hash -818028433, now seen corresponding path program 1 times [2019-11-16 00:05:11,785 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:11,785 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864155943] [2019-11-16 00:05:11,786 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:11,786 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:11,786 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:11,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:11,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:11,851 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864155943] [2019-11-16 00:05:11,851 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:11,851 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:05:11,852 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202004692] [2019-11-16 00:05:11,852 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:05:11,852 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:11,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:05:11,853 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:05:11,853 INFO L87 Difference]: Start difference. First operand 945 states and 1236 transitions. Second operand 4 states. [2019-11-16 00:05:12,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:12,043 INFO L93 Difference]: Finished difference Result 2175 states and 2852 transitions. [2019-11-16 00:05:12,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:05:12,044 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 76 [2019-11-16 00:05:12,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:12,051 INFO L225 Difference]: With dead ends: 2175 [2019-11-16 00:05:12,051 INFO L226 Difference]: Without dead ends: 1305 [2019-11-16 00:05:12,053 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:12,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1305 states. [2019-11-16 00:05:12,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1305 to 891. [2019-11-16 00:05:12,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 891 states. [2019-11-16 00:05:12,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 891 states and 1158 transitions. [2019-11-16 00:05:12,179 INFO L78 Accepts]: Start accepts. Automaton has 891 states and 1158 transitions. Word has length 76 [2019-11-16 00:05:12,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:12,180 INFO L462 AbstractCegarLoop]: Abstraction has 891 states and 1158 transitions. [2019-11-16 00:05:12,180 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:05:12,180 INFO L276 IsEmpty]: Start isEmpty. Operand 891 states and 1158 transitions. [2019-11-16 00:05:12,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2019-11-16 00:05:12,183 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:12,183 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:12,183 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:12,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:12,184 INFO L82 PathProgramCache]: Analyzing trace with hash 231668988, now seen corresponding path program 1 times [2019-11-16 00:05:12,184 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:12,184 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60377126] [2019-11-16 00:05:12,185 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:12,185 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:12,185 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:12,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:12,526 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:12,526 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60377126] [2019-11-16 00:05:12,526 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1024235103] [2019-11-16 00:05:12,527 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:12,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:12,740 INFO L256 TraceCheckSpWp]: Trace formula consists of 720 conjuncts, 9 conjunts are in the unsatisfiable core [2019-11-16 00:05:12,760 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:05:12,855 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-16 00:05:12,856 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-16 00:05:12,857 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-16 00:05:12,857 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1437595831] [2019-11-16 00:05:12,858 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:05:12,858 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:12,859 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:05:12,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-16 00:05:12,860 INFO L87 Difference]: Start difference. First operand 891 states and 1158 transitions. Second operand 6 states. [2019-11-16 00:05:13,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:13,336 INFO L93 Difference]: Finished difference Result 2714 states and 3666 transitions. [2019-11-16 00:05:13,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-16 00:05:13,337 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 119 [2019-11-16 00:05:13,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:13,361 INFO L225 Difference]: With dead ends: 2714 [2019-11-16 00:05:13,367 INFO L226 Difference]: Without dead ends: 1964 [2019-11-16 00:05:13,369 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 116 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-11-16 00:05:13,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1964 states. [2019-11-16 00:05:13,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1964 to 891. [2019-11-16 00:05:13,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 891 states. [2019-11-16 00:05:13,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 891 states and 1155 transitions. [2019-11-16 00:05:13,523 INFO L78 Accepts]: Start accepts. Automaton has 891 states and 1155 transitions. Word has length 119 [2019-11-16 00:05:13,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:13,524 INFO L462 AbstractCegarLoop]: Abstraction has 891 states and 1155 transitions. [2019-11-16 00:05:13,524 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:05:13,524 INFO L276 IsEmpty]: Start isEmpty. Operand 891 states and 1155 transitions. [2019-11-16 00:05:13,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2019-11-16 00:05:13,526 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:13,526 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:13,732 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:13,732 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:13,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:13,733 INFO L82 PathProgramCache]: Analyzing trace with hash -1539750943, now seen corresponding path program 1 times [2019-11-16 00:05:13,733 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:13,733 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139410972] [2019-11-16 00:05:13,733 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:13,733 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:13,734 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:13,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:14,094 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:14,094 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139410972] [2019-11-16 00:05:14,094 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1143149958] [2019-11-16 00:05:14,094 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:14,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:14,282 INFO L256 TraceCheckSpWp]: Trace formula consists of 733 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-16 00:05:14,287 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:05:14,386 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-16 00:05:14,387 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-16 00:05:14,387 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-16 00:05:14,387 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463203183] [2019-11-16 00:05:14,388 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:05:14,388 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:14,388 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:05:14,388 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-16 00:05:14,389 INFO L87 Difference]: Start difference. First operand 891 states and 1155 transitions. Second operand 6 states. [2019-11-16 00:05:14,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:14,900 INFO L93 Difference]: Finished difference Result 2443 states and 3263 transitions. [2019-11-16 00:05:14,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-16 00:05:14,900 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 123 [2019-11-16 00:05:14,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:14,904 INFO L225 Difference]: With dead ends: 2443 [2019-11-16 00:05:14,904 INFO L226 Difference]: Without dead ends: 1693 [2019-11-16 00:05:14,906 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-11-16 00:05:14,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1693 states. [2019-11-16 00:05:15,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1693 to 891. [2019-11-16 00:05:15,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 891 states. [2019-11-16 00:05:15,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 891 states and 1152 transitions. [2019-11-16 00:05:15,094 INFO L78 Accepts]: Start accepts. Automaton has 891 states and 1152 transitions. Word has length 123 [2019-11-16 00:05:15,095 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:15,095 INFO L462 AbstractCegarLoop]: Abstraction has 891 states and 1152 transitions. [2019-11-16 00:05:15,095 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:05:15,095 INFO L276 IsEmpty]: Start isEmpty. Operand 891 states and 1152 transitions. [2019-11-16 00:05:15,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2019-11-16 00:05:15,099 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:15,100 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:15,312 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:15,312 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:15,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:15,313 INFO L82 PathProgramCache]: Analyzing trace with hash 1067023105, now seen corresponding path program 1 times [2019-11-16 00:05:15,313 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:15,313 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48256048] [2019-11-16 00:05:15,313 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:15,313 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:15,314 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:15,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:15,611 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:15,611 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [48256048] [2019-11-16 00:05:15,612 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [732914339] [2019-11-16 00:05:15,612 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:15,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:15,806 INFO L256 TraceCheckSpWp]: Trace formula consists of 745 conjuncts, 12 conjunts are in the unsatisfiable core [2019-11-16 00:05:15,817 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:05:15,919 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-16 00:05:15,919 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-16 00:05:15,920 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-16 00:05:15,920 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [980005405] [2019-11-16 00:05:15,920 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:05:15,921 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:15,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:05:15,921 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-16 00:05:15,921 INFO L87 Difference]: Start difference. First operand 891 states and 1152 transitions. Second operand 6 states. [2019-11-16 00:05:16,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:16,488 INFO L93 Difference]: Finished difference Result 2805 states and 3772 transitions. [2019-11-16 00:05:16,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-16 00:05:16,488 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 126 [2019-11-16 00:05:16,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:16,492 INFO L225 Difference]: With dead ends: 2805 [2019-11-16 00:05:16,492 INFO L226 Difference]: Without dead ends: 2042 [2019-11-16 00:05:16,494 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2019-11-16 00:05:16,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2042 states. [2019-11-16 00:05:16,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2042 to 839. [2019-11-16 00:05:16,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 839 states. [2019-11-16 00:05:16,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 839 states to 839 states and 1074 transitions. [2019-11-16 00:05:16,608 INFO L78 Accepts]: Start accepts. Automaton has 839 states and 1074 transitions. Word has length 126 [2019-11-16 00:05:16,609 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:16,609 INFO L462 AbstractCegarLoop]: Abstraction has 839 states and 1074 transitions. [2019-11-16 00:05:16,609 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:05:16,609 INFO L276 IsEmpty]: Start isEmpty. Operand 839 states and 1074 transitions. [2019-11-16 00:05:16,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-11-16 00:05:16,611 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:16,612 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:16,816 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:16,817 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:16,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:16,817 INFO L82 PathProgramCache]: Analyzing trace with hash -569114610, now seen corresponding path program 1 times [2019-11-16 00:05:16,817 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:16,818 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31120619] [2019-11-16 00:05:16,818 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:16,818 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:16,818 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:16,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:17,051 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:17,052 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31120619] [2019-11-16 00:05:17,052 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [906903924] [2019-11-16 00:05:17,052 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:17,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:17,252 INFO L256 TraceCheckSpWp]: Trace formula consists of 746 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-16 00:05:17,258 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:05:17,361 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-16 00:05:17,361 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-16 00:05:17,362 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 13 [2019-11-16 00:05:17,362 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [913863446] [2019-11-16 00:05:17,362 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:05:17,363 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:17,363 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:05:17,363 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2019-11-16 00:05:17,364 INFO L87 Difference]: Start difference. First operand 839 states and 1074 transitions. Second operand 6 states. [2019-11-16 00:05:17,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:17,807 INFO L93 Difference]: Finished difference Result 2159 states and 2876 transitions. [2019-11-16 00:05:17,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-16 00:05:17,807 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 127 [2019-11-16 00:05:17,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:17,811 INFO L225 Difference]: With dead ends: 2159 [2019-11-16 00:05:17,811 INFO L226 Difference]: Without dead ends: 1475 [2019-11-16 00:05:17,814 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=44, Invalid=228, Unknown=0, NotChecked=0, Total=272 [2019-11-16 00:05:17,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1475 states. [2019-11-16 00:05:17,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1475 to 839. [2019-11-16 00:05:17,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 839 states. [2019-11-16 00:05:17,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 839 states to 839 states and 1073 transitions. [2019-11-16 00:05:17,955 INFO L78 Accepts]: Start accepts. Automaton has 839 states and 1073 transitions. Word has length 127 [2019-11-16 00:05:17,955 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:17,955 INFO L462 AbstractCegarLoop]: Abstraction has 839 states and 1073 transitions. [2019-11-16 00:05:17,955 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:05:17,955 INFO L276 IsEmpty]: Start isEmpty. Operand 839 states and 1073 transitions. [2019-11-16 00:05:17,958 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-11-16 00:05:17,958 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:17,958 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:18,163 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:18,165 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:18,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:18,165 INFO L82 PathProgramCache]: Analyzing trace with hash -503152461, now seen corresponding path program 1 times [2019-11-16 00:05:18,165 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:18,165 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287862890] [2019-11-16 00:05:18,165 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:18,165 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:18,166 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:18,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:18,449 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:18,449 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287862890] [2019-11-16 00:05:18,450 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [261273708] [2019-11-16 00:05:18,450 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:18,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:18,652 INFO L256 TraceCheckSpWp]: Trace formula consists of 760 conjuncts, 45 conjunts are in the unsatisfiable core [2019-11-16 00:05:18,658 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:05:18,979 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:18,982 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-16 00:05:18,982 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12] total 17 [2019-11-16 00:05:18,983 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2118867628] [2019-11-16 00:05:18,984 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-11-16 00:05:18,984 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:18,985 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-11-16 00:05:18,985 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=251, Unknown=0, NotChecked=0, Total=306 [2019-11-16 00:05:18,985 INFO L87 Difference]: Start difference. First operand 839 states and 1073 transitions. Second operand 18 states. [2019-11-16 00:05:22,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:22,205 INFO L93 Difference]: Finished difference Result 3430 states and 4518 transitions. [2019-11-16 00:05:22,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2019-11-16 00:05:22,205 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 131 [2019-11-16 00:05:22,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:22,209 INFO L225 Difference]: With dead ends: 3430 [2019-11-16 00:05:22,209 INFO L226 Difference]: Without dead ends: 2752 [2019-11-16 00:05:22,213 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 118 SyntacticMatches, 4 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1942 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1261, Invalid=4745, Unknown=0, NotChecked=0, Total=6006 [2019-11-16 00:05:22,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2752 states. [2019-11-16 00:05:22,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2752 to 1322. [2019-11-16 00:05:22,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1322 states. [2019-11-16 00:05:22,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1322 states to 1322 states and 1712 transitions. [2019-11-16 00:05:22,403 INFO L78 Accepts]: Start accepts. Automaton has 1322 states and 1712 transitions. Word has length 131 [2019-11-16 00:05:22,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:22,403 INFO L462 AbstractCegarLoop]: Abstraction has 1322 states and 1712 transitions. [2019-11-16 00:05:22,403 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-11-16 00:05:22,403 INFO L276 IsEmpty]: Start isEmpty. Operand 1322 states and 1712 transitions. [2019-11-16 00:05:22,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-11-16 00:05:22,406 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:22,407 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:22,611 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:22,611 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:22,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:22,612 INFO L82 PathProgramCache]: Analyzing trace with hash -1629002450, now seen corresponding path program 1 times [2019-11-16 00:05:22,612 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:22,612 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966149129] [2019-11-16 00:05:22,612 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:22,612 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:22,613 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:22,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:22,671 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-11-16 00:05:22,671 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1966149129] [2019-11-16 00:05:22,671 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:22,672 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:05:22,672 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [98775009] [2019-11-16 00:05:22,673 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:05:22,673 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:22,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:05:22,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:05:22,674 INFO L87 Difference]: Start difference. First operand 1322 states and 1712 transitions. Second operand 4 states. [2019-11-16 00:05:23,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:23,084 INFO L93 Difference]: Finished difference Result 3257 states and 4242 transitions. [2019-11-16 00:05:23,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:05:23,085 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 132 [2019-11-16 00:05:23,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:23,088 INFO L225 Difference]: With dead ends: 3257 [2019-11-16 00:05:23,088 INFO L226 Difference]: Without dead ends: 2063 [2019-11-16 00:05:23,091 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:23,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2063 states. [2019-11-16 00:05:23,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2063 to 1382. [2019-11-16 00:05:23,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1382 states. [2019-11-16 00:05:23,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1382 states to 1382 states and 1766 transitions. [2019-11-16 00:05:23,278 INFO L78 Accepts]: Start accepts. Automaton has 1382 states and 1766 transitions. Word has length 132 [2019-11-16 00:05:23,279 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:23,279 INFO L462 AbstractCegarLoop]: Abstraction has 1382 states and 1766 transitions. [2019-11-16 00:05:23,279 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:05:23,279 INFO L276 IsEmpty]: Start isEmpty. Operand 1382 states and 1766 transitions. [2019-11-16 00:05:23,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-11-16 00:05:23,282 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:23,283 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:23,283 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:23,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:23,284 INFO L82 PathProgramCache]: Analyzing trace with hash 1003109554, now seen corresponding path program 1 times [2019-11-16 00:05:23,284 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:23,284 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051734349] [2019-11-16 00:05:23,284 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:23,284 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:23,285 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:23,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:23,408 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-11-16 00:05:23,408 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051734349] [2019-11-16 00:05:23,408 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:23,409 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:05:23,409 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993303577] [2019-11-16 00:05:23,409 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:05:23,409 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:23,410 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:05:23,410 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:23,410 INFO L87 Difference]: Start difference. First operand 1382 states and 1766 transitions. Second operand 5 states. [2019-11-16 00:05:23,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:23,688 INFO L93 Difference]: Finished difference Result 2508 states and 3252 transitions. [2019-11-16 00:05:23,688 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:05:23,688 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-11-16 00:05:23,689 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:23,691 INFO L225 Difference]: With dead ends: 2508 [2019-11-16 00:05:23,691 INFO L226 Difference]: Without dead ends: 1254 [2019-11-16 00:05:23,694 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:05:23,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1254 states. [2019-11-16 00:05:23,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1254 to 1254. [2019-11-16 00:05:23,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1254 states. [2019-11-16 00:05:23,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1254 states to 1254 states and 1618 transitions. [2019-11-16 00:05:23,865 INFO L78 Accepts]: Start accepts. Automaton has 1254 states and 1618 transitions. Word has length 132 [2019-11-16 00:05:23,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:23,865 INFO L462 AbstractCegarLoop]: Abstraction has 1254 states and 1618 transitions. [2019-11-16 00:05:23,865 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:05:23,865 INFO L276 IsEmpty]: Start isEmpty. Operand 1254 states and 1618 transitions. [2019-11-16 00:05:23,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-16 00:05:23,868 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:23,868 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:23,869 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:23,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:23,869 INFO L82 PathProgramCache]: Analyzing trace with hash 1193716731, now seen corresponding path program 1 times [2019-11-16 00:05:23,869 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:23,869 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1669308506] [2019-11-16 00:05:23,869 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:23,870 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:23,870 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:23,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:23,960 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2019-11-16 00:05:23,960 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1669308506] [2019-11-16 00:05:23,961 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:23,961 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:05:23,961 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829268503] [2019-11-16 00:05:23,961 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:05:23,962 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:23,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:05:23,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:05:23,962 INFO L87 Difference]: Start difference. First operand 1254 states and 1618 transitions. Second operand 6 states. [2019-11-16 00:05:24,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:24,747 INFO L93 Difference]: Finished difference Result 6564 states and 8664 transitions. [2019-11-16 00:05:24,747 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-11-16 00:05:24,747 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 133 [2019-11-16 00:05:24,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:24,756 INFO L225 Difference]: With dead ends: 6564 [2019-11-16 00:05:24,756 INFO L226 Difference]: Without dead ends: 5491 [2019-11-16 00:05:24,758 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2019-11-16 00:05:24,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5491 states. [2019-11-16 00:05:25,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5491 to 1596. [2019-11-16 00:05:25,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1596 states. [2019-11-16 00:05:25,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1596 states to 1596 states and 2018 transitions. [2019-11-16 00:05:25,009 INFO L78 Accepts]: Start accepts. Automaton has 1596 states and 2018 transitions. Word has length 133 [2019-11-16 00:05:25,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:25,010 INFO L462 AbstractCegarLoop]: Abstraction has 1596 states and 2018 transitions. [2019-11-16 00:05:25,010 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:05:25,010 INFO L276 IsEmpty]: Start isEmpty. Operand 1596 states and 2018 transitions. [2019-11-16 00:05:25,013 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-16 00:05:25,013 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:25,013 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:25,014 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:25,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:25,014 INFO L82 PathProgramCache]: Analyzing trace with hash 2094959115, now seen corresponding path program 1 times [2019-11-16 00:05:25,014 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:25,014 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435906189] [2019-11-16 00:05:25,015 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:25,015 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:25,015 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:25,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:25,306 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:25,306 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [435906189] [2019-11-16 00:05:25,306 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [747650417] [2019-11-16 00:05:25,307 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:25,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:25,501 INFO L256 TraceCheckSpWp]: Trace formula consists of 772 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-16 00:05:25,504 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:05:25,586 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-16 00:05:25,586 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-16 00:05:25,587 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-16 00:05:25,587 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188109465] [2019-11-16 00:05:25,588 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:05:25,588 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:25,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:05:25,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-16 00:05:25,588 INFO L87 Difference]: Start difference. First operand 1596 states and 2018 transitions. Second operand 6 states. [2019-11-16 00:05:26,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:26,314 INFO L93 Difference]: Finished difference Result 4898 states and 6314 transitions. [2019-11-16 00:05:26,315 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-16 00:05:26,315 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 134 [2019-11-16 00:05:26,315 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:26,321 INFO L225 Difference]: With dead ends: 4898 [2019-11-16 00:05:26,321 INFO L226 Difference]: Without dead ends: 3463 [2019-11-16 00:05:26,323 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 131 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-11-16 00:05:26,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3463 states. [2019-11-16 00:05:26,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3463 to 1596. [2019-11-16 00:05:26,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1596 states. [2019-11-16 00:05:26,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1596 states to 1596 states and 2016 transitions. [2019-11-16 00:05:26,519 INFO L78 Accepts]: Start accepts. Automaton has 1596 states and 2016 transitions. Word has length 134 [2019-11-16 00:05:26,519 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:26,519 INFO L462 AbstractCegarLoop]: Abstraction has 1596 states and 2016 transitions. [2019-11-16 00:05:26,519 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:05:26,520 INFO L276 IsEmpty]: Start isEmpty. Operand 1596 states and 2016 transitions. [2019-11-16 00:05:26,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-16 00:05:26,524 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:26,524 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:26,727 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:26,728 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:26,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:26,728 INFO L82 PathProgramCache]: Analyzing trace with hash -1714435691, now seen corresponding path program 1 times [2019-11-16 00:05:26,729 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:26,729 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441922304] [2019-11-16 00:05:26,729 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:26,729 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:26,729 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:26,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:26,973 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:26,974 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1441922304] [2019-11-16 00:05:26,974 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1536798318] [2019-11-16 00:05:26,974 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:27,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:27,241 INFO L256 TraceCheckSpWp]: Trace formula consists of 762 conjuncts, 46 conjunts are in the unsatisfiable core [2019-11-16 00:05:27,243 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:05:27,581 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:05:27,582 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-16 00:05:27,582 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-11-16 00:05:27,582 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949508889] [2019-11-16 00:05:27,583 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-16 00:05:27,583 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:27,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-16 00:05:27,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2019-11-16 00:05:27,584 INFO L87 Difference]: Start difference. First operand 1596 states and 2016 transitions. Second operand 21 states. [2019-11-16 00:05:30,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:30,027 INFO L93 Difference]: Finished difference Result 4380 states and 5555 transitions. [2019-11-16 00:05:30,027 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-11-16 00:05:30,027 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 134 [2019-11-16 00:05:30,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:30,033 INFO L225 Difference]: With dead ends: 4380 [2019-11-16 00:05:30,033 INFO L226 Difference]: Without dead ends: 2965 [2019-11-16 00:05:30,036 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 120 SyntacticMatches, 4 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 997 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=649, Invalid=3133, Unknown=0, NotChecked=0, Total=3782 [2019-11-16 00:05:30,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2965 states. [2019-11-16 00:05:30,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2965 to 1815. [2019-11-16 00:05:30,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1815 states. [2019-11-16 00:05:30,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1815 states to 1815 states and 2286 transitions. [2019-11-16 00:05:30,309 INFO L78 Accepts]: Start accepts. Automaton has 1815 states and 2286 transitions. Word has length 134 [2019-11-16 00:05:30,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:30,309 INFO L462 AbstractCegarLoop]: Abstraction has 1815 states and 2286 transitions. [2019-11-16 00:05:30,309 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-16 00:05:30,309 INFO L276 IsEmpty]: Start isEmpty. Operand 1815 states and 2286 transitions. [2019-11-16 00:05:30,312 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-16 00:05:30,312 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:30,312 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:30,517 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:05:30,517 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:30,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:30,517 INFO L82 PathProgramCache]: Analyzing trace with hash 1273389207, now seen corresponding path program 1 times [2019-11-16 00:05:30,517 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:30,517 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422042369] [2019-11-16 00:05:30,517 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:30,517 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:30,518 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:30,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:05:30,581 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2019-11-16 00:05:30,581 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1422042369] [2019-11-16 00:05:30,582 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:05:30,582 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:05:30,582 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547889643] [2019-11-16 00:05:30,582 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:05:30,583 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:05:30,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:05:30,583 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:05:30,583 INFO L87 Difference]: Start difference. First operand 1815 states and 2286 transitions. Second operand 4 states. [2019-11-16 00:05:30,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:05:30,826 INFO L93 Difference]: Finished difference Result 3309 states and 4194 transitions. [2019-11-16 00:05:30,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-16 00:05:30,826 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 134 [2019-11-16 00:05:30,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:05:30,828 INFO L225 Difference]: With dead ends: 3309 [2019-11-16 00:05:30,828 INFO L226 Difference]: Without dead ends: 1620 [2019-11-16 00:05:30,829 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:05:30,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1620 states. [2019-11-16 00:05:30,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1620 to 1620. [2019-11-16 00:05:30,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1620 states. [2019-11-16 00:05:30,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1620 states to 1620 states and 2026 transitions. [2019-11-16 00:05:30,991 INFO L78 Accepts]: Start accepts. Automaton has 1620 states and 2026 transitions. Word has length 134 [2019-11-16 00:05:30,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:05:30,992 INFO L462 AbstractCegarLoop]: Abstraction has 1620 states and 2026 transitions. [2019-11-16 00:05:30,992 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:05:30,992 INFO L276 IsEmpty]: Start isEmpty. Operand 1620 states and 2026 transitions. [2019-11-16 00:05:30,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-16 00:05:30,994 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:05:30,995 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:05:30,995 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:05:30,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:05:30,995 INFO L82 PathProgramCache]: Analyzing trace with hash 1769777121, now seen corresponding path program 1 times [2019-11-16 00:05:30,995 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:05:30,996 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798276522] [2019-11-16 00:05:30,996 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:30,996 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:05:30,996 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:05:31,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-16 00:05:31,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-16 00:05:31,203 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-16 00:05:31,204 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-11-16 00:05:31,425 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 16.11 12:05:31 BoogieIcfgContainer [2019-11-16 00:05:31,429 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-16 00:05:31,430 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-16 00:05:31,430 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-16 00:05:31,431 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-16 00:05:31,431 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:05:02" (3/4) ... [2019-11-16 00:05:31,434 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-16 00:05:31,648 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_b5441b85-899f-48d3-9f4f-0498fdbaba44/bin/uautomizer/witness.graphml [2019-11-16 00:05:31,649 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-16 00:05:31,651 INFO L168 Benchmark]: Toolchain (without parser) took 30952.08 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 810.5 MB). Free memory was 951.5 MB in the beginning and 1.1 GB in the end (delta: -181.6 MB). Peak memory consumption was 628.9 MB. Max. memory is 11.5 GB. [2019-11-16 00:05:31,651 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 967.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-16 00:05:31,651 INFO L168 Benchmark]: CACSL2BoogieTranslator took 567.39 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.6 MB). Free memory was 946.2 MB in the beginning and 1.1 GB in the end (delta: -178.6 MB). Peak memory consumption was 19.4 MB. Max. memory is 11.5 GB. [2019-11-16 00:05:31,652 INFO L168 Benchmark]: Boogie Procedure Inliner took 74.58 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.9 MB). Peak memory consumption was 8.9 MB. Max. memory is 11.5 GB. [2019-11-16 00:05:31,652 INFO L168 Benchmark]: Boogie Preprocessor took 57.11 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-16 00:05:31,652 INFO L168 Benchmark]: RCFGBuilder took 1128.65 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 100.8 MB). Peak memory consumption was 100.8 MB. Max. memory is 11.5 GB. [2019-11-16 00:05:31,653 INFO L168 Benchmark]: TraceAbstraction took 28901.15 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 669.0 MB). Free memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: -164.2 MB). Peak memory consumption was 504.8 MB. Max. memory is 11.5 GB. [2019-11-16 00:05:31,653 INFO L168 Benchmark]: Witness Printer took 218.48 ms. Allocated memory is still 1.8 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 46.2 MB). Peak memory consumption was 46.2 MB. Max. memory is 11.5 GB. [2019-11-16 00:05:31,655 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 967.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 567.39 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.6 MB). Free memory was 946.2 MB in the beginning and 1.1 GB in the end (delta: -178.6 MB). Peak memory consumption was 19.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 74.58 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.9 MB). Peak memory consumption was 8.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 57.11 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 1128.65 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 100.8 MB). Peak memory consumption was 100.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 28901.15 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 669.0 MB). Free memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: -164.2 MB). Peak memory consumption was 504.8 MB. Max. memory is 11.5 GB. * Witness Printer took 218.48 ms. Allocated memory is still 1.8 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 46.2 MB). Peak memory consumption was 46.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 653]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L455] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L577] int c1 ; [L578] int i2 ; [L581] c1 = 0 [L582] side1Failed = __VERIFIER_nondet_bool() [L583] side2Failed = __VERIFIER_nondet_bool() [L584] side1_written = __VERIFIER_nondet_char() [L585] side2_written = __VERIFIER_nondet_char() [L586] side1Failed_History_0 = __VERIFIER_nondet_bool() [L587] side1Failed_History_1 = __VERIFIER_nondet_bool() [L588] side1Failed_History_2 = __VERIFIER_nondet_bool() [L589] side2Failed_History_0 = __VERIFIER_nondet_bool() [L590] side2Failed_History_1 = __VERIFIER_nondet_bool() [L591] side2Failed_History_2 = __VERIFIER_nondet_bool() [L592] active_side_History_0 = __VERIFIER_nondet_char() [L593] active_side_History_1 = __VERIFIER_nondet_char() [L594] active_side_History_2 = __VERIFIER_nondet_char() [L595] manual_selection_History_0 = __VERIFIER_nondet_char() [L596] manual_selection_History_1 = __VERIFIER_nondet_char() [L597] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L598] i2 = init() [L600] cs1_old = nomsg [L601] cs1_new = nomsg [L602] cs2_old = nomsg [L603] cs2_new = nomsg [L604] s1s2_old = nomsg [L605] s1s2_new = nomsg [L606] s1s1_old = nomsg [L607] s1s1_new = nomsg [L608] s2s1_old = nomsg [L609] s2s1_new = nomsg [L610] s2s2_old = nomsg [L611] s2s2_new = nomsg [L612] s1p_old = nomsg [L613] s1p_new = nomsg [L614] s2p_old = nomsg [L615] s2p_new = nomsg [L616] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE 1 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L485] COND TRUE ! side2Failed [L486] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] tmp___1 = read_side1_failed_history((unsigned char)1) [L494] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L495] tmp___2 = read_side1_failed_history((unsigned char)0) [L496] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] tmp___11 = read_side1_failed_history((unsigned char)1) [L538] COND TRUE ! tmp___11 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L539] tmp___12 = read_side2_failed_history((unsigned char)1) [L540] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L553] tmp___20 = read_active_side_history((unsigned char)2) [L554] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L572] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L651] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE 1 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND FALSE !(\read(side1Failed)) [L326] side1 = s1s1_old [L327] s1s1_old = nomsg [L328] side2 = s2s1_old [L329] s2s1_old = nomsg [L330] manual_selection = cs1_old [L331] cs1_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L332] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L335] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L336] COND TRUE (int )side2 != (int )nomsg [L337] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] EXPR next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] s1s1_new = next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new [L357] EXPR next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L357] s1s2_new = next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new [L358] EXPR next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L358] s1p_new = next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new [L359] side1_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND TRUE \read(side2Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] EXPR nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] s2s1_new = nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new [L378] EXPR nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L378] s2s2_new = nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new [L379] EXPR nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L379] s2p_new = nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new [L380] side2_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND TRUE ! side1Failed [L483] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND FALSE !(! tmp___0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND TRUE \read(tmp___7) [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L523] tmp___8 = read_side2_failed_history((unsigned char)1) [L524] COND TRUE ! tmp___8 [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L525] tmp___5 = read_active_side_history((unsigned char)0) [L526] COND TRUE ! ((int )tmp___5 == 2) [L527] return (0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L651] COND TRUE ! arg VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L653] __VERIFIER_error() VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 290 locations, 23 error locations. Result: UNSAFE, OverallTime: 28.8s, OverallIterations: 37, TraceHistogramMax: 2, AutomataDifference: 15.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 15650 SDtfs, 27851 SDslu, 35782 SDs, 0 SdLazy, 5608 SolverSat, 397 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1315 GetRequests, 943 SyntacticMatches, 19 SemanticMatches, 353 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3347 ImplicationChecksByTransitivity, 6.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1815occurred in iteration=35, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 3.4s AutomataMinimizationTime, 36 MinimizatonAttempts, 21843 StatesRemovedByMinimization, 32 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.5s SsaConstructionTime, 1.6s SatisfiabilityAnalysisTime, 4.7s InterpolantComputationTime, 4062 NumberOfCodeBlocks, 4062 NumberOfCodeBlocksAsserted, 44 NumberOfCheckSat, 3884 ConstructedInterpolants, 0 QuantifiedInterpolants, 1555146 SizeOfPredicates, 38 NumberOfNonLiveVariables, 5238 ConjunctsInSsa, 136 ConjunctsInUnsatCore, 43 InterpolantComputations, 34 PerfectInterpolantSequences, 576/673 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...