./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c -s /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 75de94c5f78b6878c3cbd09fac99b01e14f23f29 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-11-16 00:17:56,576 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-16 00:17:56,577 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-16 00:17:56,591 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-16 00:17:56,592 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-16 00:17:56,593 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-16 00:17:56,595 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-16 00:17:56,604 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-16 00:17:56,609 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-16 00:17:56,613 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-16 00:17:56,614 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-16 00:17:56,616 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-16 00:17:56,616 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-16 00:17:56,618 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-16 00:17:56,619 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-16 00:17:56,620 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-16 00:17:56,621 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-16 00:17:56,622 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-16 00:17:56,624 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-16 00:17:56,628 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-16 00:17:56,631 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-16 00:17:56,633 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-16 00:17:56,636 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-16 00:17:56,637 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-16 00:17:56,640 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-16 00:17:56,640 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-16 00:17:56,640 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-16 00:17:56,642 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-16 00:17:56,642 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-16 00:17:56,643 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-16 00:17:56,644 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-16 00:17:56,644 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-16 00:17:56,645 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-16 00:17:56,645 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-16 00:17:56,647 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-16 00:17:56,647 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-16 00:17:56,648 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-16 00:17:56,649 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-16 00:17:56,649 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-16 00:17:56,651 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-16 00:17:56,651 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-16 00:17:56,653 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-16 00:17:56,678 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-16 00:17:56,689 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-16 00:17:56,690 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-16 00:17:56,690 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-16 00:17:56,690 INFO L138 SettingsManager]: * Use SBE=true [2019-11-16 00:17:56,691 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-16 00:17:56,691 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-16 00:17:56,691 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-16 00:17:56,691 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-16 00:17:56,692 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-16 00:17:56,692 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-16 00:17:56,692 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-16 00:17:56,692 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-16 00:17:56,693 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-16 00:17:56,693 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-16 00:17:56,693 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-16 00:17:56,694 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-16 00:17:56,694 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-16 00:17:56,695 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-16 00:17:56,695 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-16 00:17:56,695 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-16 00:17:56,695 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-16 00:17:56,696 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-16 00:17:56,696 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-16 00:17:56,697 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-16 00:17:56,697 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-16 00:17:56,697 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-16 00:17:56,698 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-16 00:17:56,698 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 75de94c5f78b6878c3cbd09fac99b01e14f23f29 [2019-11-16 00:17:56,730 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-16 00:17:56,742 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-16 00:17:56,745 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-16 00:17:56,746 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-16 00:17:56,747 INFO L275 PluginConnector]: CDTParser initialized [2019-11-16 00:17:56,747 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c [2019-11-16 00:17:56,800 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/data/64a453a4b/4be54cef5fc44fd6b6323e832cd33152/FLAG5367e5ea4 [2019-11-16 00:17:57,248 INFO L306 CDTParser]: Found 1 translation units. [2019-11-16 00:17:57,249 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c [2019-11-16 00:17:57,260 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/data/64a453a4b/4be54cef5fc44fd6b6323e832cd33152/FLAG5367e5ea4 [2019-11-16 00:17:57,522 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/data/64a453a4b/4be54cef5fc44fd6b6323e832cd33152 [2019-11-16 00:17:57,525 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-16 00:17:57,527 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-16 00:17:57,531 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-16 00:17:57,532 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-16 00:17:57,535 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-16 00:17:57,536 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:17:57" (1/1) ... [2019-11-16 00:17:57,539 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4defbc2c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57, skipping insertion in model container [2019-11-16 00:17:57,540 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:17:57" (1/1) ... [2019-11-16 00:17:57,549 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-16 00:17:57,613 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-16 00:17:57,903 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-16 00:17:57,914 INFO L188 MainTranslator]: Completed pre-run [2019-11-16 00:17:57,977 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-16 00:17:57,998 INFO L192 MainTranslator]: Completed translation [2019-11-16 00:17:57,999 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57 WrapperNode [2019-11-16 00:17:57,999 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-16 00:17:58,000 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-16 00:17:58,000 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-16 00:17:58,000 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-16 00:17:58,008 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57" (1/1) ... [2019-11-16 00:17:58,022 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57" (1/1) ... [2019-11-16 00:17:58,076 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-16 00:17:58,076 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-16 00:17:58,076 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-16 00:17:58,077 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-16 00:17:58,086 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57" (1/1) ... [2019-11-16 00:17:58,087 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57" (1/1) ... [2019-11-16 00:17:58,093 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57" (1/1) ... [2019-11-16 00:17:58,093 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57" (1/1) ... [2019-11-16 00:17:58,111 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57" (1/1) ... [2019-11-16 00:17:58,124 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57" (1/1) ... [2019-11-16 00:17:58,130 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57" (1/1) ... [2019-11-16 00:17:58,137 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-16 00:17:58,141 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-16 00:17:58,141 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-16 00:17:58,146 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-16 00:17:58,147 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-16 00:17:58,213 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-16 00:17:58,214 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-16 00:17:59,317 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-16 00:17:59,317 INFO L284 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-16 00:17:59,319 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:17:59 BoogieIcfgContainer [2019-11-16 00:17:59,319 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-16 00:17:59,320 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-16 00:17:59,320 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-16 00:17:59,322 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-16 00:17:59,323 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 16.11 12:17:57" (1/3) ... [2019-11-16 00:17:59,323 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@70be530b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 12:17:59, skipping insertion in model container [2019-11-16 00:17:59,324 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:17:57" (2/3) ... [2019-11-16 00:17:59,327 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@70be530b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 12:17:59, skipping insertion in model container [2019-11-16 00:17:59,327 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:17:59" (3/3) ... [2019-11-16 00:17:59,330 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c [2019-11-16 00:17:59,338 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-16 00:17:59,344 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-11-16 00:17:59,351 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-11-16 00:17:59,375 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-16 00:17:59,375 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-16 00:17:59,375 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-16 00:17:59,375 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-16 00:17:59,376 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-16 00:17:59,376 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-16 00:17:59,376 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-16 00:17:59,376 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-16 00:17:59,405 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states. [2019-11-16 00:17:59,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-11-16 00:17:59,413 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:17:59,414 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:17:59,417 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:17:59,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:17:59,423 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-11-16 00:17:59,428 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:17:59,429 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827846222] [2019-11-16 00:17:59,429 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:17:59,429 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:17:59,429 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:17:59,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:17:59,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:17:59,634 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827846222] [2019-11-16 00:17:59,635 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:17:59,635 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:17:59,635 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131332633] [2019-11-16 00:17:59,640 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:17:59,640 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:17:59,653 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:17:59,654 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:17:59,656 INFO L87 Difference]: Start difference. First operand 293 states. Second operand 3 states. [2019-11-16 00:17:59,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:17:59,783 INFO L93 Difference]: Finished difference Result 572 states and 892 transitions. [2019-11-16 00:17:59,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:17:59,789 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-11-16 00:17:59,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:17:59,819 INFO L225 Difference]: With dead ends: 572 [2019-11-16 00:17:59,819 INFO L226 Difference]: Without dead ends: 289 [2019-11-16 00:17:59,828 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:17:59,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states. [2019-11-16 00:17:59,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 289. [2019-11-16 00:17:59,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 289 states. [2019-11-16 00:17:59,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 289 states to 289 states and 413 transitions. [2019-11-16 00:17:59,881 INFO L78 Accepts]: Start accepts. Automaton has 289 states and 413 transitions. Word has length 31 [2019-11-16 00:17:59,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:17:59,881 INFO L462 AbstractCegarLoop]: Abstraction has 289 states and 413 transitions. [2019-11-16 00:17:59,881 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:17:59,882 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states and 413 transitions. [2019-11-16 00:17:59,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-11-16 00:17:59,884 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:17:59,884 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:17:59,885 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:17:59,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:17:59,885 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-11-16 00:17:59,886 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:17:59,886 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519506806] [2019-11-16 00:17:59,886 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:17:59,886 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:17:59,887 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:17:59,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:00,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:00,088 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519506806] [2019-11-16 00:18:00,088 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:00,088 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:18:00,089 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306570193] [2019-11-16 00:18:00,090 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:18:00,091 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:00,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:18:00,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:00,091 INFO L87 Difference]: Start difference. First operand 289 states and 413 transitions. Second operand 3 states. [2019-11-16 00:18:00,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:00,157 INFO L93 Difference]: Finished difference Result 597 states and 861 transitions. [2019-11-16 00:18:00,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:18:00,158 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-11-16 00:18:00,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:00,161 INFO L225 Difference]: With dead ends: 597 [2019-11-16 00:18:00,161 INFO L226 Difference]: Without dead ends: 323 [2019-11-16 00:18:00,163 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:00,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states. [2019-11-16 00:18:00,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 265. [2019-11-16 00:18:00,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2019-11-16 00:18:00,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 377 transitions. [2019-11-16 00:18:00,184 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 377 transitions. Word has length 42 [2019-11-16 00:18:00,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:00,185 INFO L462 AbstractCegarLoop]: Abstraction has 265 states and 377 transitions. [2019-11-16 00:18:00,185 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:18:00,185 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 377 transitions. [2019-11-16 00:18:00,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-16 00:18:00,187 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:00,187 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:00,188 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:00,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:00,188 INFO L82 PathProgramCache]: Analyzing trace with hash 1273755287, now seen corresponding path program 1 times [2019-11-16 00:18:00,189 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:00,189 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577011443] [2019-11-16 00:18:00,189 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:00,189 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:00,189 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:00,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:00,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:00,367 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577011443] [2019-11-16 00:18:00,367 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:00,367 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:18:00,368 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419055286] [2019-11-16 00:18:00,369 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:18:00,370 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:00,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:18:00,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:00,374 INFO L87 Difference]: Start difference. First operand 265 states and 377 transitions. Second operand 3 states. [2019-11-16 00:18:00,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:00,426 INFO L93 Difference]: Finished difference Result 742 states and 1066 transitions. [2019-11-16 00:18:00,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:18:00,427 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-16 00:18:00,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:00,431 INFO L225 Difference]: With dead ends: 742 [2019-11-16 00:18:00,432 INFO L226 Difference]: Without dead ends: 492 [2019-11-16 00:18:00,433 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:00,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 492 states. [2019-11-16 00:18:00,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 492 to 300. [2019-11-16 00:18:00,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 300 states. [2019-11-16 00:18:00,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 300 states to 300 states and 429 transitions. [2019-11-16 00:18:00,474 INFO L78 Accepts]: Start accepts. Automaton has 300 states and 429 transitions. Word has length 49 [2019-11-16 00:18:00,474 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:00,474 INFO L462 AbstractCegarLoop]: Abstraction has 300 states and 429 transitions. [2019-11-16 00:18:00,474 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:18:00,475 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 429 transitions. [2019-11-16 00:18:00,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-11-16 00:18:00,477 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:00,477 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:00,478 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:00,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:00,478 INFO L82 PathProgramCache]: Analyzing trace with hash -1910840580, now seen corresponding path program 1 times [2019-11-16 00:18:00,478 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:00,479 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219192530] [2019-11-16 00:18:00,479 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:00,479 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:00,479 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:00,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:00,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:00,644 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [219192530] [2019-11-16 00:18:00,644 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:00,645 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:00,645 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [69583716] [2019-11-16 00:18:00,645 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:18:00,645 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:00,646 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:18:00,647 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:00,647 INFO L87 Difference]: Start difference. First operand 300 states and 429 transitions. Second operand 5 states. [2019-11-16 00:18:00,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:00,979 INFO L93 Difference]: Finished difference Result 942 states and 1360 transitions. [2019-11-16 00:18:00,980 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:18:00,980 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-11-16 00:18:00,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:00,987 INFO L225 Difference]: With dead ends: 942 [2019-11-16 00:18:00,987 INFO L226 Difference]: Without dead ends: 657 [2019-11-16 00:18:00,989 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-16 00:18:00,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states. [2019-11-16 00:18:01,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 386. [2019-11-16 00:18:01,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 386 states. [2019-11-16 00:18:01,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 386 states and 552 transitions. [2019-11-16 00:18:01,018 INFO L78 Accepts]: Start accepts. Automaton has 386 states and 552 transitions. Word has length 50 [2019-11-16 00:18:01,020 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:01,020 INFO L462 AbstractCegarLoop]: Abstraction has 386 states and 552 transitions. [2019-11-16 00:18:01,020 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:18:01,020 INFO L276 IsEmpty]: Start isEmpty. Operand 386 states and 552 transitions. [2019-11-16 00:18:01,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-11-16 00:18:01,027 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:01,028 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:01,028 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:01,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:01,029 INFO L82 PathProgramCache]: Analyzing trace with hash -1041102253, now seen corresponding path program 1 times [2019-11-16 00:18:01,029 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:01,029 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749730821] [2019-11-16 00:18:01,030 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:01,030 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:01,030 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:01,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:01,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:01,160 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749730821] [2019-11-16 00:18:01,161 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:01,161 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:01,161 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1649392554] [2019-11-16 00:18:01,161 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:18:01,162 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:01,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:18:01,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:01,162 INFO L87 Difference]: Start difference. First operand 386 states and 552 transitions. Second operand 5 states. [2019-11-16 00:18:01,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:01,463 INFO L93 Difference]: Finished difference Result 944 states and 1360 transitions. [2019-11-16 00:18:01,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:18:01,463 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-11-16 00:18:01,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:01,469 INFO L225 Difference]: With dead ends: 944 [2019-11-16 00:18:01,469 INFO L226 Difference]: Without dead ends: 659 [2019-11-16 00:18:01,470 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-16 00:18:01,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states. [2019-11-16 00:18:01,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 390. [2019-11-16 00:18:01,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 390 states. [2019-11-16 00:18:01,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 390 states to 390 states and 556 transitions. [2019-11-16 00:18:01,494 INFO L78 Accepts]: Start accepts. Automaton has 390 states and 556 transitions. Word has length 51 [2019-11-16 00:18:01,494 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:01,494 INFO L462 AbstractCegarLoop]: Abstraction has 390 states and 556 transitions. [2019-11-16 00:18:01,494 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:18:01,495 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 556 transitions. [2019-11-16 00:18:01,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-16 00:18:01,497 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:01,497 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:01,498 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:01,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:01,498 INFO L82 PathProgramCache]: Analyzing trace with hash -458607163, now seen corresponding path program 1 times [2019-11-16 00:18:01,498 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:01,499 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823834751] [2019-11-16 00:18:01,499 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:01,499 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:01,499 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:01,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:01,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:01,651 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1823834751] [2019-11-16 00:18:01,651 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:01,652 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:01,652 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647434178] [2019-11-16 00:18:01,652 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:18:01,652 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:01,653 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:18:01,653 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:01,653 INFO L87 Difference]: Start difference. First operand 390 states and 556 transitions. Second operand 4 states. [2019-11-16 00:18:01,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:01,912 INFO L93 Difference]: Finished difference Result 944 states and 1356 transitions. [2019-11-16 00:18:01,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:01,913 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 53 [2019-11-16 00:18:01,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:01,919 INFO L225 Difference]: With dead ends: 944 [2019-11-16 00:18:01,919 INFO L226 Difference]: Without dead ends: 659 [2019-11-16 00:18:01,920 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:01,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states. [2019-11-16 00:18:01,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 390. [2019-11-16 00:18:01,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 390 states. [2019-11-16 00:18:01,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 390 states to 390 states and 554 transitions. [2019-11-16 00:18:01,945 INFO L78 Accepts]: Start accepts. Automaton has 390 states and 554 transitions. Word has length 53 [2019-11-16 00:18:01,945 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:01,945 INFO L462 AbstractCegarLoop]: Abstraction has 390 states and 554 transitions. [2019-11-16 00:18:01,945 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:18:01,945 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 554 transitions. [2019-11-16 00:18:01,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-16 00:18:01,947 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:01,947 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:01,948 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:01,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:01,958 INFO L82 PathProgramCache]: Analyzing trace with hash 1789775306, now seen corresponding path program 1 times [2019-11-16 00:18:01,958 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:01,958 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420123273] [2019-11-16 00:18:01,958 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:01,959 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:01,959 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:01,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:02,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:02,123 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1420123273] [2019-11-16 00:18:02,123 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:02,123 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:18:02,124 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765085181] [2019-11-16 00:18:02,124 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:18:02,124 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:02,124 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:18:02,125 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:02,125 INFO L87 Difference]: Start difference. First operand 390 states and 554 transitions. Second operand 5 states. [2019-11-16 00:18:02,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:02,189 INFO L93 Difference]: Finished difference Result 776 states and 1117 transitions. [2019-11-16 00:18:02,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-16 00:18:02,190 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2019-11-16 00:18:02,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:02,193 INFO L225 Difference]: With dead ends: 776 [2019-11-16 00:18:02,193 INFO L226 Difference]: Without dead ends: 491 [2019-11-16 00:18:02,194 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:18:02,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 491 states. [2019-11-16 00:18:02,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 491 to 385. [2019-11-16 00:18:02,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 385 states. [2019-11-16 00:18:02,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385 states to 385 states and 546 transitions. [2019-11-16 00:18:02,215 INFO L78 Accepts]: Start accepts. Automaton has 385 states and 546 transitions. Word has length 54 [2019-11-16 00:18:02,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:02,216 INFO L462 AbstractCegarLoop]: Abstraction has 385 states and 546 transitions. [2019-11-16 00:18:02,216 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:18:02,216 INFO L276 IsEmpty]: Start isEmpty. Operand 385 states and 546 transitions. [2019-11-16 00:18:02,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-16 00:18:02,217 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:02,217 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:02,218 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:02,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:02,218 INFO L82 PathProgramCache]: Analyzing trace with hash 1630366882, now seen corresponding path program 1 times [2019-11-16 00:18:02,218 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:02,219 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182051076] [2019-11-16 00:18:02,219 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:02,219 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:02,219 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:02,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:02,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:02,369 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [182051076] [2019-11-16 00:18:02,370 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:02,370 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:18:02,370 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977688732] [2019-11-16 00:18:02,370 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:18:02,371 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:02,371 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:18:02,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:02,371 INFO L87 Difference]: Start difference. First operand 385 states and 546 transitions. Second operand 5 states. [2019-11-16 00:18:02,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:02,514 INFO L93 Difference]: Finished difference Result 807 states and 1166 transitions. [2019-11-16 00:18:02,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:02,514 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-11-16 00:18:02,514 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:02,517 INFO L225 Difference]: With dead ends: 807 [2019-11-16 00:18:02,518 INFO L226 Difference]: Without dead ends: 527 [2019-11-16 00:18:02,519 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:18:02,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states. [2019-11-16 00:18:02,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 355. [2019-11-16 00:18:02,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 355 states. [2019-11-16 00:18:02,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 355 states to 355 states and 500 transitions. [2019-11-16 00:18:02,540 INFO L78 Accepts]: Start accepts. Automaton has 355 states and 500 transitions. Word has length 58 [2019-11-16 00:18:02,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:02,541 INFO L462 AbstractCegarLoop]: Abstraction has 355 states and 500 transitions. [2019-11-16 00:18:02,541 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:18:02,541 INFO L276 IsEmpty]: Start isEmpty. Operand 355 states and 500 transitions. [2019-11-16 00:18:02,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-16 00:18:02,542 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:02,542 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:02,543 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:02,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:02,543 INFO L82 PathProgramCache]: Analyzing trace with hash 644191382, now seen corresponding path program 1 times [2019-11-16 00:18:02,543 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:02,543 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801939136] [2019-11-16 00:18:02,543 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:02,544 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:02,544 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:02,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:02,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:02,651 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [801939136] [2019-11-16 00:18:02,651 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:02,651 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:18:02,651 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [867673875] [2019-11-16 00:18:02,652 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:18:02,652 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:02,652 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:18:02,653 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:02,653 INFO L87 Difference]: Start difference. First operand 355 states and 500 transitions. Second operand 5 states. [2019-11-16 00:18:02,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:02,814 INFO L93 Difference]: Finished difference Result 904 states and 1296 transitions. [2019-11-16 00:18:02,815 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:02,815 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 63 [2019-11-16 00:18:02,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:02,819 INFO L225 Difference]: With dead ends: 904 [2019-11-16 00:18:02,819 INFO L226 Difference]: Without dead ends: 654 [2019-11-16 00:18:02,820 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:18:02,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2019-11-16 00:18:02,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 325. [2019-11-16 00:18:02,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 325 states. [2019-11-16 00:18:02,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 325 states to 325 states and 454 transitions. [2019-11-16 00:18:02,879 INFO L78 Accepts]: Start accepts. Automaton has 325 states and 454 transitions. Word has length 63 [2019-11-16 00:18:02,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:02,880 INFO L462 AbstractCegarLoop]: Abstraction has 325 states and 454 transitions. [2019-11-16 00:18:02,880 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:18:02,880 INFO L276 IsEmpty]: Start isEmpty. Operand 325 states and 454 transitions. [2019-11-16 00:18:02,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-11-16 00:18:02,881 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:02,881 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:02,881 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:02,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:02,882 INFO L82 PathProgramCache]: Analyzing trace with hash 157991886, now seen corresponding path program 1 times [2019-11-16 00:18:02,882 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:02,882 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003967406] [2019-11-16 00:18:02,883 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:02,883 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:02,883 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:02,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:03,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:03,006 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2003967406] [2019-11-16 00:18:03,006 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:03,006 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:18:03,007 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [971646705] [2019-11-16 00:18:03,007 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:03,007 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:03,008 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:03,008 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:18:03,008 INFO L87 Difference]: Start difference. First operand 325 states and 454 transitions. Second operand 6 states. [2019-11-16 00:18:03,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:03,275 INFO L93 Difference]: Finished difference Result 1105 states and 1564 transitions. [2019-11-16 00:18:03,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-16 00:18:03,275 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-11-16 00:18:03,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:03,280 INFO L225 Difference]: With dead ends: 1105 [2019-11-16 00:18:03,280 INFO L226 Difference]: Without dead ends: 885 [2019-11-16 00:18:03,285 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-16 00:18:03,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 885 states. [2019-11-16 00:18:03,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 885 to 364. [2019-11-16 00:18:03,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364 states. [2019-11-16 00:18:03,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 508 transitions. [2019-11-16 00:18:03,313 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 508 transitions. Word has length 68 [2019-11-16 00:18:03,314 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:03,314 INFO L462 AbstractCegarLoop]: Abstraction has 364 states and 508 transitions. [2019-11-16 00:18:03,314 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:03,314 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 508 transitions. [2019-11-16 00:18:03,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-11-16 00:18:03,320 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:03,320 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:03,321 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:03,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:03,322 INFO L82 PathProgramCache]: Analyzing trace with hash -2134355609, now seen corresponding path program 1 times [2019-11-16 00:18:03,322 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:03,322 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1603800788] [2019-11-16 00:18:03,323 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:03,323 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:03,323 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:03,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:03,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:03,396 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1603800788] [2019-11-16 00:18:03,396 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:03,397 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:18:03,397 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1402515623] [2019-11-16 00:18:03,397 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:18:03,397 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:03,397 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:18:03,397 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:03,398 INFO L87 Difference]: Start difference. First operand 364 states and 508 transitions. Second operand 3 states. [2019-11-16 00:18:03,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:03,455 INFO L93 Difference]: Finished difference Result 662 states and 935 transitions. [2019-11-16 00:18:03,456 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:18:03,456 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-11-16 00:18:03,456 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:03,459 INFO L225 Difference]: With dead ends: 662 [2019-11-16 00:18:03,459 INFO L226 Difference]: Without dead ends: 442 [2019-11-16 00:18:03,460 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:03,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 442 states. [2019-11-16 00:18:03,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 442 to 360. [2019-11-16 00:18:03,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 360 states. [2019-11-16 00:18:03,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 360 states to 360 states and 501 transitions. [2019-11-16 00:18:03,486 INFO L78 Accepts]: Start accepts. Automaton has 360 states and 501 transitions. Word has length 69 [2019-11-16 00:18:03,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:03,486 INFO L462 AbstractCegarLoop]: Abstraction has 360 states and 501 transitions. [2019-11-16 00:18:03,486 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:18:03,486 INFO L276 IsEmpty]: Start isEmpty. Operand 360 states and 501 transitions. [2019-11-16 00:18:03,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-16 00:18:03,487 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:03,488 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:03,492 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:03,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:03,493 INFO L82 PathProgramCache]: Analyzing trace with hash 1585943340, now seen corresponding path program 1 times [2019-11-16 00:18:03,493 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:03,493 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400940411] [2019-11-16 00:18:03,493 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:03,493 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:03,494 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:03,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:03,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:03,573 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400940411] [2019-11-16 00:18:03,573 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:03,574 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:03,574 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387642941] [2019-11-16 00:18:03,574 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:18:03,574 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:03,575 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:18:03,575 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:03,575 INFO L87 Difference]: Start difference. First operand 360 states and 501 transitions. Second operand 4 states. [2019-11-16 00:18:03,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:03,741 INFO L93 Difference]: Finished difference Result 953 states and 1330 transitions. [2019-11-16 00:18:03,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:03,742 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2019-11-16 00:18:03,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:03,746 INFO L225 Difference]: With dead ends: 953 [2019-11-16 00:18:03,746 INFO L226 Difference]: Without dead ends: 727 [2019-11-16 00:18:03,747 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:03,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 727 states. [2019-11-16 00:18:03,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 727 to 530. [2019-11-16 00:18:03,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 530 states. [2019-11-16 00:18:03,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 734 transitions. [2019-11-16 00:18:03,789 INFO L78 Accepts]: Start accepts. Automaton has 530 states and 734 transitions. Word has length 72 [2019-11-16 00:18:03,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:03,790 INFO L462 AbstractCegarLoop]: Abstraction has 530 states and 734 transitions. [2019-11-16 00:18:03,790 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:18:03,790 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 734 transitions. [2019-11-16 00:18:03,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-16 00:18:03,791 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:03,791 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:03,792 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:03,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:03,792 INFO L82 PathProgramCache]: Analyzing trace with hash -2083950892, now seen corresponding path program 1 times [2019-11-16 00:18:03,792 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:03,793 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119321727] [2019-11-16 00:18:03,793 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:03,793 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:03,793 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:03,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:03,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:03,840 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119321727] [2019-11-16 00:18:03,840 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:03,840 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:18:03,840 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1839580457] [2019-11-16 00:18:03,841 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:18:03,841 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:03,841 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:18:03,841 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:03,841 INFO L87 Difference]: Start difference. First operand 530 states and 734 transitions. Second operand 3 states. [2019-11-16 00:18:03,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:03,882 INFO L93 Difference]: Finished difference Result 909 states and 1264 transitions. [2019-11-16 00:18:03,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:18:03,882 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-16 00:18:03,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:03,886 INFO L225 Difference]: With dead ends: 909 [2019-11-16 00:18:03,886 INFO L226 Difference]: Without dead ends: 530 [2019-11-16 00:18:03,887 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:03,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 530 states. [2019-11-16 00:18:03,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 530 to 530. [2019-11-16 00:18:03,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 530 states. [2019-11-16 00:18:03,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 730 transitions. [2019-11-16 00:18:03,922 INFO L78 Accepts]: Start accepts. Automaton has 530 states and 730 transitions. Word has length 72 [2019-11-16 00:18:03,922 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:03,922 INFO L462 AbstractCegarLoop]: Abstraction has 530 states and 730 transitions. [2019-11-16 00:18:03,922 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:18:03,922 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 730 transitions. [2019-11-16 00:18:03,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-16 00:18:03,923 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:03,924 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:03,924 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:03,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:03,924 INFO L82 PathProgramCache]: Analyzing trace with hash 2070467794, now seen corresponding path program 1 times [2019-11-16 00:18:03,925 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:03,925 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911025383] [2019-11-16 00:18:03,925 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:03,925 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:03,925 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:03,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:03,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:03,966 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911025383] [2019-11-16 00:18:03,966 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:03,966 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:18:03,966 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1234866673] [2019-11-16 00:18:03,967 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:18:03,967 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:03,967 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:18:03,967 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:03,968 INFO L87 Difference]: Start difference. First operand 530 states and 730 transitions. Second operand 3 states. [2019-11-16 00:18:04,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:04,040 INFO L93 Difference]: Finished difference Result 1253 states and 1720 transitions. [2019-11-16 00:18:04,040 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:18:04,041 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-16 00:18:04,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:04,046 INFO L225 Difference]: With dead ends: 1253 [2019-11-16 00:18:04,046 INFO L226 Difference]: Without dead ends: 837 [2019-11-16 00:18:04,047 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:04,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 837 states. [2019-11-16 00:18:04,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 837 to 564. [2019-11-16 00:18:04,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 564 states. [2019-11-16 00:18:04,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 564 states to 564 states and 774 transitions. [2019-11-16 00:18:04,107 INFO L78 Accepts]: Start accepts. Automaton has 564 states and 774 transitions. Word has length 72 [2019-11-16 00:18:04,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:04,108 INFO L462 AbstractCegarLoop]: Abstraction has 564 states and 774 transitions. [2019-11-16 00:18:04,108 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:18:04,108 INFO L276 IsEmpty]: Start isEmpty. Operand 564 states and 774 transitions. [2019-11-16 00:18:04,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-16 00:18:04,109 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:04,110 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:04,110 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:04,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:04,111 INFO L82 PathProgramCache]: Analyzing trace with hash -1917205063, now seen corresponding path program 1 times [2019-11-16 00:18:04,111 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:04,111 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [705330564] [2019-11-16 00:18:04,112 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:04,112 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:04,112 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:04,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:04,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:04,264 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [705330564] [2019-11-16 00:18:04,264 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:04,265 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:18:04,265 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1216606842] [2019-11-16 00:18:04,265 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:04,265 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:04,266 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:04,266 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:18:04,266 INFO L87 Difference]: Start difference. First operand 564 states and 774 transitions. Second operand 6 states. [2019-11-16 00:18:04,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:04,596 INFO L93 Difference]: Finished difference Result 1770 states and 2483 transitions. [2019-11-16 00:18:04,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-16 00:18:04,597 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-11-16 00:18:04,597 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:04,605 INFO L225 Difference]: With dead ends: 1770 [2019-11-16 00:18:04,605 INFO L226 Difference]: Without dead ends: 1436 [2019-11-16 00:18:04,606 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-16 00:18:04,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1436 states. [2019-11-16 00:18:04,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1436 to 568. [2019-11-16 00:18:04,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 568 states. [2019-11-16 00:18:04,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 568 states to 568 states and 779 transitions. [2019-11-16 00:18:04,652 INFO L78 Accepts]: Start accepts. Automaton has 568 states and 779 transitions. Word has length 73 [2019-11-16 00:18:04,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:04,653 INFO L462 AbstractCegarLoop]: Abstraction has 568 states and 779 transitions. [2019-11-16 00:18:04,653 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:04,653 INFO L276 IsEmpty]: Start isEmpty. Operand 568 states and 779 transitions. [2019-11-16 00:18:04,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-16 00:18:04,654 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:04,654 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:04,655 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:04,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:04,655 INFO L82 PathProgramCache]: Analyzing trace with hash 197100160, now seen corresponding path program 1 times [2019-11-16 00:18:04,656 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:04,656 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032868088] [2019-11-16 00:18:04,656 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:04,656 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:04,656 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:04,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:04,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:04,732 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032868088] [2019-11-16 00:18:04,732 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:04,732 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:18:04,732 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677989613] [2019-11-16 00:18:04,732 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:18:04,732 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:04,733 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:18:04,733 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:04,733 INFO L87 Difference]: Start difference. First operand 568 states and 779 transitions. Second operand 5 states. [2019-11-16 00:18:04,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:04,887 INFO L93 Difference]: Finished difference Result 888 states and 1239 transitions. [2019-11-16 00:18:04,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:18:04,887 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2019-11-16 00:18:04,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:04,893 INFO L225 Difference]: With dead ends: 888 [2019-11-16 00:18:04,893 INFO L226 Difference]: Without dead ends: 886 [2019-11-16 00:18:04,894 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-16 00:18:04,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886 states. [2019-11-16 00:18:04,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886 to 570. [2019-11-16 00:18:04,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 570 states. [2019-11-16 00:18:04,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 570 states to 570 states and 781 transitions. [2019-11-16 00:18:04,944 INFO L78 Accepts]: Start accepts. Automaton has 570 states and 781 transitions. Word has length 73 [2019-11-16 00:18:04,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:04,944 INFO L462 AbstractCegarLoop]: Abstraction has 570 states and 781 transitions. [2019-11-16 00:18:04,944 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:18:04,945 INFO L276 IsEmpty]: Start isEmpty. Operand 570 states and 781 transitions. [2019-11-16 00:18:04,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-16 00:18:04,946 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:04,946 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:04,947 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:04,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:04,947 INFO L82 PathProgramCache]: Analyzing trace with hash 2083582807, now seen corresponding path program 1 times [2019-11-16 00:18:04,947 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:04,947 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405278484] [2019-11-16 00:18:04,948 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:04,948 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:04,948 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:04,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:05,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:05,048 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405278484] [2019-11-16 00:18:05,048 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:05,048 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:18:05,049 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1609046293] [2019-11-16 00:18:05,049 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:05,049 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:05,049 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:05,050 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:18:05,050 INFO L87 Difference]: Start difference. First operand 570 states and 781 transitions. Second operand 6 states. [2019-11-16 00:18:05,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:05,642 INFO L93 Difference]: Finished difference Result 2037 states and 2828 transitions. [2019-11-16 00:18:05,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-16 00:18:05,643 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-11-16 00:18:05,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:05,654 INFO L225 Difference]: With dead ends: 2037 [2019-11-16 00:18:05,654 INFO L226 Difference]: Without dead ends: 1662 [2019-11-16 00:18:05,655 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-16 00:18:05,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1662 states. [2019-11-16 00:18:05,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1662 to 616. [2019-11-16 00:18:05,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 616 states. [2019-11-16 00:18:05,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 616 states to 616 states and 839 transitions. [2019-11-16 00:18:05,721 INFO L78 Accepts]: Start accepts. Automaton has 616 states and 839 transitions. Word has length 73 [2019-11-16 00:18:05,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:05,721 INFO L462 AbstractCegarLoop]: Abstraction has 616 states and 839 transitions. [2019-11-16 00:18:05,721 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:05,721 INFO L276 IsEmpty]: Start isEmpty. Operand 616 states and 839 transitions. [2019-11-16 00:18:05,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-16 00:18:05,722 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:05,723 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:05,723 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:05,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:05,724 INFO L82 PathProgramCache]: Analyzing trace with hash 1204676769, now seen corresponding path program 1 times [2019-11-16 00:18:05,724 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:05,724 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032624828] [2019-11-16 00:18:05,724 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:05,724 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:05,725 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:05,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:05,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:05,818 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032624828] [2019-11-16 00:18:05,818 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:05,819 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:18:05,819 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481847603] [2019-11-16 00:18:05,819 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:05,819 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:05,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:05,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:18:05,820 INFO L87 Difference]: Start difference. First operand 616 states and 839 transitions. Second operand 6 states. [2019-11-16 00:18:06,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:06,320 INFO L93 Difference]: Finished difference Result 2364 states and 3261 transitions. [2019-11-16 00:18:06,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-16 00:18:06,320 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-11-16 00:18:06,321 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:06,331 INFO L225 Difference]: With dead ends: 2364 [2019-11-16 00:18:06,331 INFO L226 Difference]: Without dead ends: 1981 [2019-11-16 00:18:06,333 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-16 00:18:06,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1981 states. [2019-11-16 00:18:06,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1981 to 694. [2019-11-16 00:18:06,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 694 states. [2019-11-16 00:18:06,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 694 states to 694 states and 941 transitions. [2019-11-16 00:18:06,405 INFO L78 Accepts]: Start accepts. Automaton has 694 states and 941 transitions. Word has length 74 [2019-11-16 00:18:06,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:06,406 INFO L462 AbstractCegarLoop]: Abstraction has 694 states and 941 transitions. [2019-11-16 00:18:06,406 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:06,406 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 941 transitions. [2019-11-16 00:18:06,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-16 00:18:06,407 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:06,407 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:06,407 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:06,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:06,408 INFO L82 PathProgramCache]: Analyzing trace with hash -217796256, now seen corresponding path program 1 times [2019-11-16 00:18:06,408 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:06,408 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639574767] [2019-11-16 00:18:06,408 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:06,409 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:06,409 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:06,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:06,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:06,502 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1639574767] [2019-11-16 00:18:06,502 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:06,502 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:18:06,503 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [756888921] [2019-11-16 00:18:06,504 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:06,504 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:06,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:06,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:18:06,505 INFO L87 Difference]: Start difference. First operand 694 states and 941 transitions. Second operand 6 states. [2019-11-16 00:18:06,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:06,758 INFO L93 Difference]: Finished difference Result 1560 states and 2200 transitions. [2019-11-16 00:18:06,759 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-16 00:18:06,759 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-11-16 00:18:06,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:06,767 INFO L225 Difference]: With dead ends: 1560 [2019-11-16 00:18:06,767 INFO L226 Difference]: Without dead ends: 1160 [2019-11-16 00:18:06,768 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-11-16 00:18:06,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1160 states. [2019-11-16 00:18:06,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1160 to 700. [2019-11-16 00:18:06,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 700 states. [2019-11-16 00:18:06,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 700 states to 700 states and 947 transitions. [2019-11-16 00:18:06,857 INFO L78 Accepts]: Start accepts. Automaton has 700 states and 947 transitions. Word has length 74 [2019-11-16 00:18:06,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:06,857 INFO L462 AbstractCegarLoop]: Abstraction has 700 states and 947 transitions. [2019-11-16 00:18:06,857 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:06,858 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 947 transitions. [2019-11-16 00:18:06,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-16 00:18:06,859 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:06,859 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:06,860 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:06,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:06,860 INFO L82 PathProgramCache]: Analyzing trace with hash -1278252476, now seen corresponding path program 1 times [2019-11-16 00:18:06,860 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:06,860 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [859463036] [2019-11-16 00:18:06,861 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:06,861 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:06,861 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:06,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:06,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:06,922 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [859463036] [2019-11-16 00:18:06,922 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:06,922 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:18:06,922 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [447941100] [2019-11-16 00:18:06,923 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:18:06,923 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:06,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:18:06,923 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:06,924 INFO L87 Difference]: Start difference. First operand 700 states and 947 transitions. Second operand 3 states. [2019-11-16 00:18:07,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:07,061 INFO L93 Difference]: Finished difference Result 1374 states and 1891 transitions. [2019-11-16 00:18:07,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:18:07,061 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-11-16 00:18:07,062 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:07,066 INFO L225 Difference]: With dead ends: 1374 [2019-11-16 00:18:07,066 INFO L226 Difference]: Without dead ends: 905 [2019-11-16 00:18:07,068 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:07,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 905 states. [2019-11-16 00:18:07,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 905 to 679. [2019-11-16 00:18:07,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 679 states. [2019-11-16 00:18:07,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 679 states to 679 states and 910 transitions. [2019-11-16 00:18:07,164 INFO L78 Accepts]: Start accepts. Automaton has 679 states and 910 transitions. Word has length 74 [2019-11-16 00:18:07,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:07,165 INFO L462 AbstractCegarLoop]: Abstraction has 679 states and 910 transitions. [2019-11-16 00:18:07,165 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:18:07,165 INFO L276 IsEmpty]: Start isEmpty. Operand 679 states and 910 transitions. [2019-11-16 00:18:07,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-16 00:18:07,166 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:07,167 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:07,167 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:07,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:07,167 INFO L82 PathProgramCache]: Analyzing trace with hash -1698648942, now seen corresponding path program 1 times [2019-11-16 00:18:07,168 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:07,168 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873523547] [2019-11-16 00:18:07,168 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:07,168 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:07,168 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:07,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:07,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:07,246 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873523547] [2019-11-16 00:18:07,246 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:07,246 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:07,246 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460153159] [2019-11-16 00:18:07,247 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:18:07,248 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:07,248 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:18:07,249 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:07,249 INFO L87 Difference]: Start difference. First operand 679 states and 910 transitions. Second operand 4 states. [2019-11-16 00:18:07,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:07,458 INFO L93 Difference]: Finished difference Result 1744 states and 2350 transitions. [2019-11-16 00:18:07,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:07,458 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-11-16 00:18:07,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:07,465 INFO L225 Difference]: With dead ends: 1744 [2019-11-16 00:18:07,466 INFO L226 Difference]: Without dead ends: 1328 [2019-11-16 00:18:07,467 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:07,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1328 states. [2019-11-16 00:18:07,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1328 to 923. [2019-11-16 00:18:07,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 923 states. [2019-11-16 00:18:07,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 923 states to 923 states and 1237 transitions. [2019-11-16 00:18:07,551 INFO L78 Accepts]: Start accepts. Automaton has 923 states and 1237 transitions. Word has length 75 [2019-11-16 00:18:07,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:07,551 INFO L462 AbstractCegarLoop]: Abstraction has 923 states and 1237 transitions. [2019-11-16 00:18:07,551 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:18:07,552 INFO L276 IsEmpty]: Start isEmpty. Operand 923 states and 1237 transitions. [2019-11-16 00:18:07,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-16 00:18:07,553 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:07,553 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:07,553 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:07,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:07,554 INFO L82 PathProgramCache]: Analyzing trace with hash -1596781464, now seen corresponding path program 1 times [2019-11-16 00:18:07,554 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:07,554 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399743546] [2019-11-16 00:18:07,554 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:07,554 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:07,555 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:07,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:07,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:07,607 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399743546] [2019-11-16 00:18:07,607 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:07,607 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:18:07,607 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675486546] [2019-11-16 00:18:07,608 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:18:07,608 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:07,608 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:18:07,608 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:07,608 INFO L87 Difference]: Start difference. First operand 923 states and 1237 transitions. Second operand 3 states. [2019-11-16 00:18:07,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:07,780 INFO L93 Difference]: Finished difference Result 1932 states and 2621 transitions. [2019-11-16 00:18:07,780 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:18:07,781 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2019-11-16 00:18:07,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:07,788 INFO L225 Difference]: With dead ends: 1932 [2019-11-16 00:18:07,788 INFO L226 Difference]: Without dead ends: 1327 [2019-11-16 00:18:07,790 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:07,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states. [2019-11-16 00:18:07,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 877. [2019-11-16 00:18:07,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 877 states. [2019-11-16 00:18:07,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 877 states to 877 states and 1171 transitions. [2019-11-16 00:18:07,882 INFO L78 Accepts]: Start accepts. Automaton has 877 states and 1171 transitions. Word has length 75 [2019-11-16 00:18:07,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:07,883 INFO L462 AbstractCegarLoop]: Abstraction has 877 states and 1171 transitions. [2019-11-16 00:18:07,883 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:18:07,883 INFO L276 IsEmpty]: Start isEmpty. Operand 877 states and 1171 transitions. [2019-11-16 00:18:07,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-16 00:18:07,885 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:07,885 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:07,885 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:07,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:07,886 INFO L82 PathProgramCache]: Analyzing trace with hash -216337278, now seen corresponding path program 1 times [2019-11-16 00:18:07,886 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:07,886 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510916728] [2019-11-16 00:18:07,886 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:07,886 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:07,887 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:07,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:07,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:07,938 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510916728] [2019-11-16 00:18:07,938 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:07,938 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:07,939 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388839857] [2019-11-16 00:18:07,939 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:18:07,939 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:07,939 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:18:07,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:07,940 INFO L87 Difference]: Start difference. First operand 877 states and 1171 transitions. Second operand 4 states. [2019-11-16 00:18:08,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:08,167 INFO L93 Difference]: Finished difference Result 2042 states and 2724 transitions. [2019-11-16 00:18:08,168 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:08,168 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-11-16 00:18:08,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:08,176 INFO L225 Difference]: With dead ends: 2042 [2019-11-16 00:18:08,176 INFO L226 Difference]: Without dead ends: 1466 [2019-11-16 00:18:08,178 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:08,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1466 states. [2019-11-16 00:18:08,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1466 to 1169. [2019-11-16 00:18:08,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1169 states. [2019-11-16 00:18:08,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1169 states to 1169 states and 1551 transitions. [2019-11-16 00:18:08,353 INFO L78 Accepts]: Start accepts. Automaton has 1169 states and 1551 transitions. Word has length 75 [2019-11-16 00:18:08,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:08,354 INFO L462 AbstractCegarLoop]: Abstraction has 1169 states and 1551 transitions. [2019-11-16 00:18:08,354 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:18:08,354 INFO L276 IsEmpty]: Start isEmpty. Operand 1169 states and 1551 transitions. [2019-11-16 00:18:08,355 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-11-16 00:18:08,356 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:08,356 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:08,356 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:08,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:08,357 INFO L82 PathProgramCache]: Analyzing trace with hash -1065252519, now seen corresponding path program 1 times [2019-11-16 00:18:08,357 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:08,357 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123968167] [2019-11-16 00:18:08,357 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:08,358 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:08,358 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:08,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:08,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:08,402 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123968167] [2019-11-16 00:18:08,402 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:08,402 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:18:08,403 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024993753] [2019-11-16 00:18:08,403 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:18:08,403 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:08,403 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:18:08,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:08,404 INFO L87 Difference]: Start difference. First operand 1169 states and 1551 transitions. Second operand 3 states. [2019-11-16 00:18:08,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:08,682 INFO L93 Difference]: Finished difference Result 2882 states and 3817 transitions. [2019-11-16 00:18:08,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:18:08,683 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2019-11-16 00:18:08,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:08,692 INFO L225 Difference]: With dead ends: 2882 [2019-11-16 00:18:08,692 INFO L226 Difference]: Without dead ends: 1956 [2019-11-16 00:18:08,694 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:18:08,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1956 states. [2019-11-16 00:18:08,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1956 to 1171. [2019-11-16 00:18:08,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1171 states. [2019-11-16 00:18:08,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1171 states to 1171 states and 1553 transitions. [2019-11-16 00:18:08,812 INFO L78 Accepts]: Start accepts. Automaton has 1171 states and 1553 transitions. Word has length 76 [2019-11-16 00:18:08,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:08,812 INFO L462 AbstractCegarLoop]: Abstraction has 1171 states and 1553 transitions. [2019-11-16 00:18:08,812 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:18:08,812 INFO L276 IsEmpty]: Start isEmpty. Operand 1171 states and 1553 transitions. [2019-11-16 00:18:08,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2019-11-16 00:18:08,814 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:08,814 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:08,814 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:08,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:08,815 INFO L82 PathProgramCache]: Analyzing trace with hash -2019206059, now seen corresponding path program 1 times [2019-11-16 00:18:08,815 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:08,815 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331965993] [2019-11-16 00:18:08,815 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:08,816 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:08,816 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:08,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:08,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:08,879 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [331965993] [2019-11-16 00:18:08,879 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:08,879 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:08,880 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1904862667] [2019-11-16 00:18:08,880 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:18:08,880 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:08,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:18:08,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:08,881 INFO L87 Difference]: Start difference. First operand 1171 states and 1553 transitions. Second operand 4 states. [2019-11-16 00:18:09,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:09,049 INFO L93 Difference]: Finished difference Result 2437 states and 3225 transitions. [2019-11-16 00:18:09,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:09,049 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 77 [2019-11-16 00:18:09,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:09,056 INFO L225 Difference]: With dead ends: 2437 [2019-11-16 00:18:09,056 INFO L226 Difference]: Without dead ends: 1323 [2019-11-16 00:18:09,058 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:09,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1323 states. [2019-11-16 00:18:09,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1323 to 976. [2019-11-16 00:18:09,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 976 states. [2019-11-16 00:18:09,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 976 states to 976 states and 1289 transitions. [2019-11-16 00:18:09,165 INFO L78 Accepts]: Start accepts. Automaton has 976 states and 1289 transitions. Word has length 77 [2019-11-16 00:18:09,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:09,165 INFO L462 AbstractCegarLoop]: Abstraction has 976 states and 1289 transitions. [2019-11-16 00:18:09,166 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:18:09,166 INFO L276 IsEmpty]: Start isEmpty. Operand 976 states and 1289 transitions. [2019-11-16 00:18:09,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2019-11-16 00:18:09,167 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:09,167 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:09,167 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:09,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:09,168 INFO L82 PathProgramCache]: Analyzing trace with hash -113428458, now seen corresponding path program 1 times [2019-11-16 00:18:09,168 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:09,168 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347395673] [2019-11-16 00:18:09,168 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:09,168 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:09,169 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:09,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:09,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:09,238 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347395673] [2019-11-16 00:18:09,238 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:09,239 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:09,239 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [412481601] [2019-11-16 00:18:09,239 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:18:09,239 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:09,240 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:18:09,240 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:09,240 INFO L87 Difference]: Start difference. First operand 976 states and 1289 transitions. Second operand 4 states. [2019-11-16 00:18:09,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:09,457 INFO L93 Difference]: Finished difference Result 2242 states and 2971 transitions. [2019-11-16 00:18:09,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:09,457 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 78 [2019-11-16 00:18:09,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:09,465 INFO L225 Difference]: With dead ends: 2242 [2019-11-16 00:18:09,465 INFO L226 Difference]: Without dead ends: 1343 [2019-11-16 00:18:09,467 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:09,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1343 states. [2019-11-16 00:18:09,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1343 to 920. [2019-11-16 00:18:09,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. [2019-11-16 00:18:09,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1209 transitions. [2019-11-16 00:18:09,611 INFO L78 Accepts]: Start accepts. Automaton has 920 states and 1209 transitions. Word has length 78 [2019-11-16 00:18:09,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:09,611 INFO L462 AbstractCegarLoop]: Abstraction has 920 states and 1209 transitions. [2019-11-16 00:18:09,611 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:18:09,611 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1209 transitions. [2019-11-16 00:18:09,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2019-11-16 00:18:09,614 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:09,614 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:09,615 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:09,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:09,615 INFO L82 PathProgramCache]: Analyzing trace with hash 831151167, now seen corresponding path program 1 times [2019-11-16 00:18:09,615 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:09,616 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738301867] [2019-11-16 00:18:09,616 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:09,616 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:09,616 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:09,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:10,031 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:10,031 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738301867] [2019-11-16 00:18:10,032 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1959350280] [2019-11-16 00:18:10,032 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:10,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:10,244 INFO L256 TraceCheckSpWp]: Trace formula consists of 727 conjuncts, 9 conjunts are in the unsatisfiable core [2019-11-16 00:18:10,262 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:10,382 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-16 00:18:10,382 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-16 00:18:10,383 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-16 00:18:10,383 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703436268] [2019-11-16 00:18:10,384 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:10,384 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:10,384 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:10,385 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-16 00:18:10,386 INFO L87 Difference]: Start difference. First operand 920 states and 1209 transitions. Second operand 6 states. [2019-11-16 00:18:10,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:10,750 INFO L93 Difference]: Finished difference Result 2836 states and 3898 transitions. [2019-11-16 00:18:10,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-16 00:18:10,750 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 122 [2019-11-16 00:18:10,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:10,769 INFO L225 Difference]: With dead ends: 2836 [2019-11-16 00:18:10,776 INFO L226 Difference]: Without dead ends: 2063 [2019-11-16 00:18:10,778 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 119 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-11-16 00:18:10,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2063 states. [2019-11-16 00:18:10,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2063 to 920. [2019-11-16 00:18:10,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. [2019-11-16 00:18:10,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1206 transitions. [2019-11-16 00:18:10,887 INFO L78 Accepts]: Start accepts. Automaton has 920 states and 1206 transitions. Word has length 122 [2019-11-16 00:18:10,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:10,888 INFO L462 AbstractCegarLoop]: Abstraction has 920 states and 1206 transitions. [2019-11-16 00:18:10,888 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:10,888 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1206 transitions. [2019-11-16 00:18:10,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2019-11-16 00:18:10,891 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:10,891 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:11,097 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:11,097 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:11,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:11,098 INFO L82 PathProgramCache]: Analyzing trace with hash -1351562886, now seen corresponding path program 1 times [2019-11-16 00:18:11,098 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:11,099 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1370958305] [2019-11-16 00:18:11,099 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:11,100 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:11,101 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:11,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:11,502 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:11,502 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1370958305] [2019-11-16 00:18:11,502 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [968040614] [2019-11-16 00:18:11,502 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:11,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:11,693 INFO L256 TraceCheckSpWp]: Trace formula consists of 740 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-16 00:18:11,697 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:11,834 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-16 00:18:11,835 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-16 00:18:11,835 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-16 00:18:11,835 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [482027250] [2019-11-16 00:18:11,835 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:11,836 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:11,836 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:11,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=208, Unknown=0, NotChecked=0, Total=240 [2019-11-16 00:18:11,836 INFO L87 Difference]: Start difference. First operand 920 states and 1206 transitions. Second operand 6 states. [2019-11-16 00:18:12,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:12,317 INFO L93 Difference]: Finished difference Result 2541 states and 3449 transitions. [2019-11-16 00:18:12,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-16 00:18:12,318 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 126 [2019-11-16 00:18:12,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:12,322 INFO L225 Difference]: With dead ends: 2541 [2019-11-16 00:18:12,322 INFO L226 Difference]: Without dead ends: 1768 [2019-11-16 00:18:12,324 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 142 GetRequests, 123 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=56, Invalid=364, Unknown=0, NotChecked=0, Total=420 [2019-11-16 00:18:12,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1768 states. [2019-11-16 00:18:12,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1768 to 920. [2019-11-16 00:18:12,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. [2019-11-16 00:18:12,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1203 transitions. [2019-11-16 00:18:12,480 INFO L78 Accepts]: Start accepts. Automaton has 920 states and 1203 transitions. Word has length 126 [2019-11-16 00:18:12,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:12,481 INFO L462 AbstractCegarLoop]: Abstraction has 920 states and 1203 transitions. [2019-11-16 00:18:12,481 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:12,481 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1203 transitions. [2019-11-16 00:18:12,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2019-11-16 00:18:12,487 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:12,487 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:12,692 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:12,692 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:12,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:12,693 INFO L82 PathProgramCache]: Analyzing trace with hash -1119292744, now seen corresponding path program 1 times [2019-11-16 00:18:12,693 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:12,693 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [701392169] [2019-11-16 00:18:12,693 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:12,693 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:12,694 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:12,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:12,988 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:12,989 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [701392169] [2019-11-16 00:18:12,989 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [984730713] [2019-11-16 00:18:12,989 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:13,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:13,204 INFO L256 TraceCheckSpWp]: Trace formula consists of 752 conjuncts, 12 conjunts are in the unsatisfiable core [2019-11-16 00:18:13,209 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:13,301 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-16 00:18:13,301 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-16 00:18:13,302 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-16 00:18:13,302 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [646365169] [2019-11-16 00:18:13,302 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:13,303 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:13,303 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:13,303 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-16 00:18:13,303 INFO L87 Difference]: Start difference. First operand 920 states and 1203 transitions. Second operand 6 states. [2019-11-16 00:18:13,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:13,859 INFO L93 Difference]: Finished difference Result 2927 states and 4004 transitions. [2019-11-16 00:18:13,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-16 00:18:13,859 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 129 [2019-11-16 00:18:13,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:13,863 INFO L225 Difference]: With dead ends: 2927 [2019-11-16 00:18:13,863 INFO L226 Difference]: Without dead ends: 2141 [2019-11-16 00:18:13,865 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 129 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2019-11-16 00:18:13,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2141 states. [2019-11-16 00:18:13,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2141 to 868. [2019-11-16 00:18:13,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 868 states. [2019-11-16 00:18:13,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 868 states to 868 states and 1125 transitions. [2019-11-16 00:18:13,977 INFO L78 Accepts]: Start accepts. Automaton has 868 states and 1125 transitions. Word has length 129 [2019-11-16 00:18:13,977 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:13,977 INFO L462 AbstractCegarLoop]: Abstraction has 868 states and 1125 transitions. [2019-11-16 00:18:13,977 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:13,978 INFO L276 IsEmpty]: Start isEmpty. Operand 868 states and 1125 transitions. [2019-11-16 00:18:13,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2019-11-16 00:18:13,980 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:13,980 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:14,184 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:14,184 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:14,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:14,185 INFO L82 PathProgramCache]: Analyzing trace with hash 406746349, now seen corresponding path program 1 times [2019-11-16 00:18:14,185 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:14,185 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [203263681] [2019-11-16 00:18:14,185 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:14,186 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:14,186 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:14,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:14,433 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:14,433 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [203263681] [2019-11-16 00:18:14,434 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [392164391] [2019-11-16 00:18:14,434 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:14,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:14,662 INFO L256 TraceCheckSpWp]: Trace formula consists of 753 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-16 00:18:14,668 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:14,783 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-16 00:18:14,784 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-16 00:18:14,784 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [10] total 15 [2019-11-16 00:18:14,784 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [590844252] [2019-11-16 00:18:14,785 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:14,787 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:14,788 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:14,791 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=181, Unknown=0, NotChecked=0, Total=210 [2019-11-16 00:18:14,792 INFO L87 Difference]: Start difference. First operand 868 states and 1125 transitions. Second operand 6 states. [2019-11-16 00:18:15,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:15,227 INFO L93 Difference]: Finished difference Result 2257 states and 3062 transitions. [2019-11-16 00:18:15,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-16 00:18:15,227 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 130 [2019-11-16 00:18:15,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:15,230 INFO L225 Difference]: With dead ends: 2257 [2019-11-16 00:18:15,230 INFO L226 Difference]: Without dead ends: 1550 [2019-11-16 00:18:15,232 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=48, Invalid=294, Unknown=0, NotChecked=0, Total=342 [2019-11-16 00:18:15,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1550 states. [2019-11-16 00:18:15,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1550 to 868. [2019-11-16 00:18:15,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 868 states. [2019-11-16 00:18:15,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 868 states to 868 states and 1124 transitions. [2019-11-16 00:18:15,337 INFO L78 Accepts]: Start accepts. Automaton has 868 states and 1124 transitions. Word has length 130 [2019-11-16 00:18:15,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:15,338 INFO L462 AbstractCegarLoop]: Abstraction has 868 states and 1124 transitions. [2019-11-16 00:18:15,338 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:15,338 INFO L276 IsEmpty]: Start isEmpty. Operand 868 states and 1124 transitions. [2019-11-16 00:18:15,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-16 00:18:15,340 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:15,340 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:15,545 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:15,546 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:15,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:15,547 INFO L82 PathProgramCache]: Analyzing trace with hash 590291048, now seen corresponding path program 1 times [2019-11-16 00:18:15,547 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:15,547 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461671379] [2019-11-16 00:18:15,547 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:15,547 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:15,548 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:15,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:15,798 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:15,798 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1461671379] [2019-11-16 00:18:15,798 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [531595164] [2019-11-16 00:18:15,799 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:15,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:15,987 INFO L256 TraceCheckSpWp]: Trace formula consists of 767 conjuncts, 45 conjunts are in the unsatisfiable core [2019-11-16 00:18:15,991 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:16,392 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:16,392 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-16 00:18:16,393 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-11-16 00:18:16,393 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053412296] [2019-11-16 00:18:16,394 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-16 00:18:16,394 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:16,395 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-16 00:18:16,395 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=354, Unknown=0, NotChecked=0, Total=420 [2019-11-16 00:18:16,395 INFO L87 Difference]: Start difference. First operand 868 states and 1124 transitions. Second operand 21 states. [2019-11-16 00:18:18,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:18,669 INFO L93 Difference]: Finished difference Result 2305 states and 3042 transitions. [2019-11-16 00:18:18,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-11-16 00:18:18,669 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 134 [2019-11-16 00:18:18,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:18,673 INFO L225 Difference]: With dead ends: 2305 [2019-11-16 00:18:18,673 INFO L226 Difference]: Without dead ends: 1604 [2019-11-16 00:18:18,675 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 120 SyntacticMatches, 4 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 392 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=376, Invalid=1516, Unknown=0, NotChecked=0, Total=1892 [2019-11-16 00:18:18,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1604 states. [2019-11-16 00:18:18,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1604 to 1037. [2019-11-16 00:18:18,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1037 states. [2019-11-16 00:18:18,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1037 states to 1037 states and 1339 transitions. [2019-11-16 00:18:18,797 INFO L78 Accepts]: Start accepts. Automaton has 1037 states and 1339 transitions. Word has length 134 [2019-11-16 00:18:18,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:18,798 INFO L462 AbstractCegarLoop]: Abstraction has 1037 states and 1339 transitions. [2019-11-16 00:18:18,798 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-16 00:18:18,798 INFO L276 IsEmpty]: Start isEmpty. Operand 1037 states and 1339 transitions. [2019-11-16 00:18:18,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-16 00:18:18,801 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:18,801 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:19,004 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:19,005 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:19,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:19,005 INFO L82 PathProgramCache]: Analyzing trace with hash -1443102998, now seen corresponding path program 1 times [2019-11-16 00:18:19,005 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:19,006 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838138389] [2019-11-16 00:18:19,006 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:19,006 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:19,006 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:19,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:19,059 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-16 00:18:19,059 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838138389] [2019-11-16 00:18:19,059 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:19,059 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:19,060 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1641139017] [2019-11-16 00:18:19,060 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:18:19,060 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:19,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:18:19,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:19,061 INFO L87 Difference]: Start difference. First operand 1037 states and 1339 transitions. Second operand 4 states. [2019-11-16 00:18:19,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:19,398 INFO L93 Difference]: Finished difference Result 2513 states and 3271 transitions. [2019-11-16 00:18:19,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:19,399 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 134 [2019-11-16 00:18:19,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:19,402 INFO L225 Difference]: With dead ends: 2513 [2019-11-16 00:18:19,402 INFO L226 Difference]: Without dead ends: 1608 [2019-11-16 00:18:19,405 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:19,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1608 states. [2019-11-16 00:18:19,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1608 to 1069. [2019-11-16 00:18:19,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1069 states. [2019-11-16 00:18:19,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1069 states to 1069 states and 1367 transitions. [2019-11-16 00:18:19,578 INFO L78 Accepts]: Start accepts. Automaton has 1069 states and 1367 transitions. Word has length 134 [2019-11-16 00:18:19,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:19,579 INFO L462 AbstractCegarLoop]: Abstraction has 1069 states and 1367 transitions. [2019-11-16 00:18:19,579 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:18:19,579 INFO L276 IsEmpty]: Start isEmpty. Operand 1069 states and 1367 transitions. [2019-11-16 00:18:19,582 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-16 00:18:19,582 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:19,583 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:19,583 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:19,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:19,583 INFO L82 PathProgramCache]: Analyzing trace with hash -1719204498, now seen corresponding path program 1 times [2019-11-16 00:18:19,584 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:19,584 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985127740] [2019-11-16 00:18:19,584 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:19,584 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:19,584 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:19,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:19,717 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-16 00:18:19,717 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [985127740] [2019-11-16 00:18:19,718 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:19,718 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:19,718 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1994488302] [2019-11-16 00:18:19,718 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:18:19,719 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:19,719 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:18:19,719 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:19,719 INFO L87 Difference]: Start difference. First operand 1069 states and 1367 transitions. Second operand 5 states. [2019-11-16 00:18:19,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:19,984 INFO L93 Difference]: Finished difference Result 1931 states and 2505 transitions. [2019-11-16 00:18:19,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:19,984 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 134 [2019-11-16 00:18:19,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:19,986 INFO L225 Difference]: With dead ends: 1931 [2019-11-16 00:18:19,987 INFO L226 Difference]: Without dead ends: 994 [2019-11-16 00:18:19,989 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:19,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 994 states. [2019-11-16 00:18:20,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 994 to 994. [2019-11-16 00:18:20,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 994 states. [2019-11-16 00:18:20,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 994 states to 994 states and 1278 transitions. [2019-11-16 00:18:20,127 INFO L78 Accepts]: Start accepts. Automaton has 994 states and 1278 transitions. Word has length 134 [2019-11-16 00:18:20,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:20,127 INFO L462 AbstractCegarLoop]: Abstraction has 994 states and 1278 transitions. [2019-11-16 00:18:20,127 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:18:20,127 INFO L276 IsEmpty]: Start isEmpty. Operand 994 states and 1278 transitions. [2019-11-16 00:18:20,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-16 00:18:20,130 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:20,130 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:20,131 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:20,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:20,131 INFO L82 PathProgramCache]: Analyzing trace with hash 1616018719, now seen corresponding path program 1 times [2019-11-16 00:18:20,131 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:20,131 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414052217] [2019-11-16 00:18:20,132 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:20,132 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:20,132 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:20,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:20,361 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 16 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:20,362 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414052217] [2019-11-16 00:18:20,362 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [568341702] [2019-11-16 00:18:20,362 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:20,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:20,602 INFO L256 TraceCheckSpWp]: Trace formula consists of 768 conjuncts, 47 conjunts are in the unsatisfiable core [2019-11-16 00:18:20,606 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:20,958 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 26 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:20,958 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-16 00:18:20,958 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12] total 18 [2019-11-16 00:18:20,958 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [865409125] [2019-11-16 00:18:20,959 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-11-16 00:18:20,959 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:20,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-11-16 00:18:20,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2019-11-16 00:18:20,960 INFO L87 Difference]: Start difference. First operand 994 states and 1278 transitions. Second operand 19 states. [2019-11-16 00:18:24,160 WARN L191 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 32 [2019-11-16 00:18:25,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:25,129 INFO L93 Difference]: Finished difference Result 3827 states and 4980 transitions. [2019-11-16 00:18:25,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2019-11-16 00:18:25,130 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 135 [2019-11-16 00:18:25,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:25,135 INFO L225 Difference]: With dead ends: 3827 [2019-11-16 00:18:25,135 INFO L226 Difference]: Without dead ends: 3020 [2019-11-16 00:18:25,141 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 224 GetRequests, 121 SyntacticMatches, 4 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3526 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=1965, Invalid=8135, Unknown=0, NotChecked=0, Total=10100 [2019-11-16 00:18:25,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3020 states. [2019-11-16 00:18:25,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3020 to 1479. [2019-11-16 00:18:25,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1479 states. [2019-11-16 00:18:25,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1479 states to 1479 states and 1914 transitions. [2019-11-16 00:18:25,459 INFO L78 Accepts]: Start accepts. Automaton has 1479 states and 1914 transitions. Word has length 135 [2019-11-16 00:18:25,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:25,460 INFO L462 AbstractCegarLoop]: Abstraction has 1479 states and 1914 transitions. [2019-11-16 00:18:25,460 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-11-16 00:18:25,460 INFO L276 IsEmpty]: Start isEmpty. Operand 1479 states and 1914 transitions. [2019-11-16 00:18:25,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-16 00:18:25,462 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:25,463 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:25,666 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:25,667 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:25,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:25,667 INFO L82 PathProgramCache]: Analyzing trace with hash 1144223334, now seen corresponding path program 1 times [2019-11-16 00:18:25,667 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:25,667 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799397598] [2019-11-16 00:18:25,668 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:25,668 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:25,668 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:25,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:25,730 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-11-16 00:18:25,731 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799397598] [2019-11-16 00:18:25,731 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:25,731 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:25,731 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [493647623] [2019-11-16 00:18:25,732 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:18:25,732 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:25,732 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:18:25,732 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:25,733 INFO L87 Difference]: Start difference. First operand 1479 states and 1914 transitions. Second operand 4 states. [2019-11-16 00:18:26,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:26,051 INFO L93 Difference]: Finished difference Result 2656 states and 3470 transitions. [2019-11-16 00:18:26,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-16 00:18:26,052 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 136 [2019-11-16 00:18:26,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:26,056 INFO L225 Difference]: With dead ends: 2656 [2019-11-16 00:18:26,057 INFO L226 Difference]: Without dead ends: 1307 [2019-11-16 00:18:26,058 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:26,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1307 states. [2019-11-16 00:18:26,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1307 to 1307. [2019-11-16 00:18:26,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1307 states. [2019-11-16 00:18:26,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1307 states to 1307 states and 1679 transitions. [2019-11-16 00:18:26,276 INFO L78 Accepts]: Start accepts. Automaton has 1307 states and 1679 transitions. Word has length 136 [2019-11-16 00:18:26,276 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:26,276 INFO L462 AbstractCegarLoop]: Abstraction has 1307 states and 1679 transitions. [2019-11-16 00:18:26,276 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:18:26,277 INFO L276 IsEmpty]: Start isEmpty. Operand 1307 states and 1679 transitions. [2019-11-16 00:18:26,278 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-16 00:18:26,279 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:26,279 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:26,279 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:26,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:26,280 INFO L82 PathProgramCache]: Analyzing trace with hash 844297710, now seen corresponding path program 1 times [2019-11-16 00:18:26,280 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:26,280 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061592391] [2019-11-16 00:18:26,280 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:26,280 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:26,280 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:26,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:26,616 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:26,617 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1061592391] [2019-11-16 00:18:26,617 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1136206207] [2019-11-16 00:18:26,617 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:26,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:26,817 INFO L256 TraceCheckSpWp]: Trace formula consists of 779 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-16 00:18:26,820 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:26,932 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-16 00:18:26,932 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-16 00:18:26,932 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-16 00:18:26,933 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886804600] [2019-11-16 00:18:26,933 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:26,933 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:26,933 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:26,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=208, Unknown=0, NotChecked=0, Total=240 [2019-11-16 00:18:26,934 INFO L87 Difference]: Start difference. First operand 1307 states and 1679 transitions. Second operand 6 states. [2019-11-16 00:18:27,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:27,538 INFO L93 Difference]: Finished difference Result 4085 states and 5399 transitions. [2019-11-16 00:18:27,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-16 00:18:27,538 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 137 [2019-11-16 00:18:27,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:27,543 INFO L225 Difference]: With dead ends: 4085 [2019-11-16 00:18:27,543 INFO L226 Difference]: Without dead ends: 2945 [2019-11-16 00:18:27,545 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 153 GetRequests, 134 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=56, Invalid=364, Unknown=0, NotChecked=0, Total=420 [2019-11-16 00:18:27,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2945 states. [2019-11-16 00:18:27,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2945 to 1307. [2019-11-16 00:18:27,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1307 states. [2019-11-16 00:18:27,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1307 states to 1307 states and 1677 transitions. [2019-11-16 00:18:27,722 INFO L78 Accepts]: Start accepts. Automaton has 1307 states and 1677 transitions. Word has length 137 [2019-11-16 00:18:27,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:27,722 INFO L462 AbstractCegarLoop]: Abstraction has 1307 states and 1677 transitions. [2019-11-16 00:18:27,722 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:27,722 INFO L276 IsEmpty]: Start isEmpty. Operand 1307 states and 1677 transitions. [2019-11-16 00:18:27,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-16 00:18:27,723 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:27,723 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:27,926 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:27,927 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:27,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:27,927 INFO L82 PathProgramCache]: Analyzing trace with hash 2032965332, now seen corresponding path program 1 times [2019-11-16 00:18:27,927 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:27,927 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1684976000] [2019-11-16 00:18:27,927 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:27,927 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:27,927 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:27,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:28,025 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-16 00:18:28,025 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1684976000] [2019-11-16 00:18:28,025 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:28,026 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:18:28,026 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [127243415] [2019-11-16 00:18:28,026 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:28,027 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:28,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:28,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:18:28,027 INFO L87 Difference]: Start difference. First operand 1307 states and 1677 transitions. Second operand 6 states. [2019-11-16 00:18:29,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:29,090 INFO L93 Difference]: Finished difference Result 6856 states and 8970 transitions. [2019-11-16 00:18:29,090 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-11-16 00:18:29,090 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 137 [2019-11-16 00:18:29,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:29,097 INFO L225 Difference]: With dead ends: 6856 [2019-11-16 00:18:29,097 INFO L226 Difference]: Without dead ends: 5736 [2019-11-16 00:18:29,100 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2019-11-16 00:18:29,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5736 states. [2019-11-16 00:18:29,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5736 to 1649. [2019-11-16 00:18:29,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1649 states. [2019-11-16 00:18:29,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1649 states to 1649 states and 2077 transitions. [2019-11-16 00:18:29,371 INFO L78 Accepts]: Start accepts. Automaton has 1649 states and 2077 transitions. Word has length 137 [2019-11-16 00:18:29,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:29,371 INFO L462 AbstractCegarLoop]: Abstraction has 1649 states and 2077 transitions. [2019-11-16 00:18:29,371 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:29,371 INFO L276 IsEmpty]: Start isEmpty. Operand 1649 states and 2077 transitions. [2019-11-16 00:18:29,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2019-11-16 00:18:29,374 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:29,374 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:29,374 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:29,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:29,375 INFO L82 PathProgramCache]: Analyzing trace with hash -122865786, now seen corresponding path program 1 times [2019-11-16 00:18:29,375 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:29,375 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029083204] [2019-11-16 00:18:29,375 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:29,375 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:29,375 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:29,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:29,859 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 15 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:29,859 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029083204] [2019-11-16 00:18:29,859 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1510958994] [2019-11-16 00:18:29,860 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:30,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:30,056 INFO L256 TraceCheckSpWp]: Trace formula consists of 771 conjuncts, 25 conjunts are in the unsatisfiable core [2019-11-16 00:18:30,059 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:30,265 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 15 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:30,265 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-16 00:18:30,266 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 9] total 11 [2019-11-16 00:18:30,266 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906578025] [2019-11-16 00:18:30,267 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-11-16 00:18:30,267 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:30,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-11-16 00:18:30,268 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2019-11-16 00:18:30,268 INFO L87 Difference]: Start difference. First operand 1649 states and 2077 transitions. Second operand 12 states. [2019-11-16 00:18:31,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:31,859 INFO L93 Difference]: Finished difference Result 4818 states and 6122 transitions. [2019-11-16 00:18:31,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-11-16 00:18:31,875 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 139 [2019-11-16 00:18:31,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:31,879 INFO L225 Difference]: With dead ends: 4818 [2019-11-16 00:18:31,879 INFO L226 Difference]: Without dead ends: 3356 [2019-11-16 00:18:31,882 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 167 GetRequests, 129 SyntacticMatches, 7 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 256 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=278, Invalid=778, Unknown=0, NotChecked=0, Total=1056 [2019-11-16 00:18:31,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3356 states. [2019-11-16 00:18:32,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3356 to 1680. [2019-11-16 00:18:32,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1680 states. [2019-11-16 00:18:32,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1680 states to 1680 states and 2116 transitions. [2019-11-16 00:18:32,116 INFO L78 Accepts]: Start accepts. Automaton has 1680 states and 2116 transitions. Word has length 139 [2019-11-16 00:18:32,116 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:32,116 INFO L462 AbstractCegarLoop]: Abstraction has 1680 states and 2116 transitions. [2019-11-16 00:18:32,116 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-11-16 00:18:32,116 INFO L276 IsEmpty]: Start isEmpty. Operand 1680 states and 2116 transitions. [2019-11-16 00:18:32,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-11-16 00:18:32,118 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:32,119 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:32,322 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:32,323 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:32,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:32,323 INFO L82 PathProgramCache]: Analyzing trace with hash -982040414, now seen corresponding path program 1 times [2019-11-16 00:18:32,323 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:32,324 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [893916092] [2019-11-16 00:18:32,324 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:32,324 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:32,324 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:32,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:32,582 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:32,582 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [893916092] [2019-11-16 00:18:32,583 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [714354264] [2019-11-16 00:18:32,583 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:32,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:32,749 INFO L256 TraceCheckSpWp]: Trace formula consists of 791 conjuncts, 14 conjunts are in the unsatisfiable core [2019-11-16 00:18:32,751 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:32,838 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 8 proven. 33 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:32,838 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-16 00:18:32,838 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 7] total 17 [2019-11-16 00:18:32,838 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1064327357] [2019-11-16 00:18:32,839 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-11-16 00:18:32,839 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:32,839 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-11-16 00:18:32,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-11-16 00:18:32,840 INFO L87 Difference]: Start difference. First operand 1680 states and 2116 transitions. Second operand 17 states. [2019-11-16 00:18:40,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:40,676 INFO L93 Difference]: Finished difference Result 8464 states and 10895 transitions. [2019-11-16 00:18:40,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 128 states. [2019-11-16 00:18:40,676 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 140 [2019-11-16 00:18:40,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:40,683 INFO L225 Difference]: With dead ends: 8464 [2019-11-16 00:18:40,684 INFO L226 Difference]: Without dead ends: 6971 [2019-11-16 00:18:40,693 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 298 GetRequests, 158 SyntacticMatches, 0 SemanticMatches, 140 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8040 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=3885, Invalid=16137, Unknown=0, NotChecked=0, Total=20022 [2019-11-16 00:18:40,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6971 states. [2019-11-16 00:18:41,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6971 to 2239. [2019-11-16 00:18:41,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2239 states. [2019-11-16 00:18:41,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2239 states to 2239 states and 2790 transitions. [2019-11-16 00:18:41,186 INFO L78 Accepts]: Start accepts. Automaton has 2239 states and 2790 transitions. Word has length 140 [2019-11-16 00:18:41,186 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:41,186 INFO L462 AbstractCegarLoop]: Abstraction has 2239 states and 2790 transitions. [2019-11-16 00:18:41,187 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-11-16 00:18:41,187 INFO L276 IsEmpty]: Start isEmpty. Operand 2239 states and 2790 transitions. [2019-11-16 00:18:41,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-11-16 00:18:41,190 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:41,192 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:41,404 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:41,404 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:41,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:41,404 INFO L82 PathProgramCache]: Analyzing trace with hash 1504281713, now seen corresponding path program 1 times [2019-11-16 00:18:41,405 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:41,405 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183521256] [2019-11-16 00:18:41,405 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:41,405 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:41,405 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:41,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:41,550 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:41,551 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183521256] [2019-11-16 00:18:41,551 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1078333338] [2019-11-16 00:18:41,551 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:41,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:41,768 INFO L256 TraceCheckSpWp]: Trace formula consists of 773 conjuncts, 18 conjunts are in the unsatisfiable core [2019-11-16 00:18:41,771 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:41,811 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:41,811 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-16 00:18:41,812 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 8 [2019-11-16 00:18:41,812 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2123318927] [2019-11-16 00:18:41,813 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-11-16 00:18:41,813 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:41,813 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-16 00:18:41,813 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-11-16 00:18:41,813 INFO L87 Difference]: Start difference. First operand 2239 states and 2790 transitions. Second operand 8 states. [2019-11-16 00:18:43,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:43,360 INFO L93 Difference]: Finished difference Result 7935 states and 10019 transitions. [2019-11-16 00:18:43,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-11-16 00:18:43,360 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 140 [2019-11-16 00:18:43,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:43,366 INFO L225 Difference]: With dead ends: 7935 [2019-11-16 00:18:43,366 INFO L226 Difference]: Without dead ends: 5946 [2019-11-16 00:18:43,370 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 144 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=129, Invalid=423, Unknown=0, NotChecked=0, Total=552 [2019-11-16 00:18:43,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5946 states. [2019-11-16 00:18:44,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5946 to 3391. [2019-11-16 00:18:44,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3391 states. [2019-11-16 00:18:44,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3391 states to 3391 states and 4245 transitions. [2019-11-16 00:18:44,082 INFO L78 Accepts]: Start accepts. Automaton has 3391 states and 4245 transitions. Word has length 140 [2019-11-16 00:18:44,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:44,082 INFO L462 AbstractCegarLoop]: Abstraction has 3391 states and 4245 transitions. [2019-11-16 00:18:44,082 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-11-16 00:18:44,082 INFO L276 IsEmpty]: Start isEmpty. Operand 3391 states and 4245 transitions. [2019-11-16 00:18:44,085 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-11-16 00:18:44,086 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:44,086 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:44,290 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:44,294 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:44,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:44,295 INFO L82 PathProgramCache]: Analyzing trace with hash 1622723187, now seen corresponding path program 1 times [2019-11-16 00:18:44,295 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:44,295 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [845547583] [2019-11-16 00:18:44,295 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:44,295 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:44,295 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:44,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:44,352 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-16 00:18:44,353 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [845547583] [2019-11-16 00:18:44,353 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:44,353 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:44,353 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440605774] [2019-11-16 00:18:44,355 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:18:44,357 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:44,357 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:18:44,357 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:44,357 INFO L87 Difference]: Start difference. First operand 3391 states and 4245 transitions. Second operand 4 states. [2019-11-16 00:18:44,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:44,943 INFO L93 Difference]: Finished difference Result 5881 states and 7429 transitions. [2019-11-16 00:18:44,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-16 00:18:44,943 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 140 [2019-11-16 00:18:44,944 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:44,947 INFO L225 Difference]: With dead ends: 5881 [2019-11-16 00:18:44,947 INFO L226 Difference]: Without dead ends: 2740 [2019-11-16 00:18:44,952 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:44,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2740 states. [2019-11-16 00:18:45,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2740 to 2728. [2019-11-16 00:18:45,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2728 states. [2019-11-16 00:18:45,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2728 states to 2728 states and 3407 transitions. [2019-11-16 00:18:45,376 INFO L78 Accepts]: Start accepts. Automaton has 2728 states and 3407 transitions. Word has length 140 [2019-11-16 00:18:45,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:45,376 INFO L462 AbstractCegarLoop]: Abstraction has 2728 states and 3407 transitions. [2019-11-16 00:18:45,376 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:18:45,376 INFO L276 IsEmpty]: Start isEmpty. Operand 2728 states and 3407 transitions. [2019-11-16 00:18:45,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2019-11-16 00:18:45,379 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:45,379 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:45,379 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:45,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:45,380 INFO L82 PathProgramCache]: Analyzing trace with hash -1882876842, now seen corresponding path program 1 times [2019-11-16 00:18:45,380 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:45,380 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1805310534] [2019-11-16 00:18:45,380 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:45,380 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:45,380 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:45,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:45,515 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-16 00:18:45,515 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1805310534] [2019-11-16 00:18:45,516 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:45,516 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-16 00:18:45,516 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [46518880] [2019-11-16 00:18:45,516 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-16 00:18:45,517 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:45,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-16 00:18:45,517 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-16 00:18:45,517 INFO L87 Difference]: Start difference. First operand 2728 states and 3407 transitions. Second operand 6 states. [2019-11-16 00:18:47,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:47,113 INFO L93 Difference]: Finished difference Result 9314 states and 11912 transitions. [2019-11-16 00:18:47,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-16 00:18:47,114 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 144 [2019-11-16 00:18:47,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:47,120 INFO L225 Difference]: With dead ends: 9314 [2019-11-16 00:18:47,120 INFO L226 Difference]: Without dead ends: 6856 [2019-11-16 00:18:47,123 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-16 00:18:47,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6856 states. [2019-11-16 00:18:47,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6856 to 2808. [2019-11-16 00:18:47,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2808 states. [2019-11-16 00:18:47,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2808 states to 2808 states and 3500 transitions. [2019-11-16 00:18:47,696 INFO L78 Accepts]: Start accepts. Automaton has 2808 states and 3500 transitions. Word has length 144 [2019-11-16 00:18:47,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:47,697 INFO L462 AbstractCegarLoop]: Abstraction has 2808 states and 3500 transitions. [2019-11-16 00:18:47,697 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-16 00:18:47,697 INFO L276 IsEmpty]: Start isEmpty. Operand 2808 states and 3500 transitions. [2019-11-16 00:18:47,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-11-16 00:18:47,698 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:47,699 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:47,699 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:47,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:47,699 INFO L82 PathProgramCache]: Analyzing trace with hash 27749283, now seen corresponding path program 1 times [2019-11-16 00:18:47,699 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:47,699 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128952394] [2019-11-16 00:18:47,699 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:47,699 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:47,700 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:47,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:47,750 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-11-16 00:18:47,751 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128952394] [2019-11-16 00:18:47,751 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:18:47,751 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-16 00:18:47,751 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418260271] [2019-11-16 00:18:47,752 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-16 00:18:47,752 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:47,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-16 00:18:47,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-16 00:18:47,753 INFO L87 Difference]: Start difference. First operand 2808 states and 3500 transitions. Second operand 4 states. [2019-11-16 00:18:48,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:48,427 INFO L93 Difference]: Finished difference Result 7151 states and 8947 transitions. [2019-11-16 00:18:48,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:48,428 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 145 [2019-11-16 00:18:48,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:48,431 INFO L225 Difference]: With dead ends: 7151 [2019-11-16 00:18:48,431 INFO L226 Difference]: Without dead ends: 4491 [2019-11-16 00:18:48,434 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:18:48,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4491 states. [2019-11-16 00:18:48,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4491 to 2836. [2019-11-16 00:18:48,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2836 states. [2019-11-16 00:18:48,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2836 states to 2836 states and 3520 transitions. [2019-11-16 00:18:48,872 INFO L78 Accepts]: Start accepts. Automaton has 2836 states and 3520 transitions. Word has length 145 [2019-11-16 00:18:48,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:48,872 INFO L462 AbstractCegarLoop]: Abstraction has 2836 states and 3520 transitions. [2019-11-16 00:18:48,872 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-16 00:18:48,873 INFO L276 IsEmpty]: Start isEmpty. Operand 2836 states and 3520 transitions. [2019-11-16 00:18:48,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-11-16 00:18:48,875 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:48,875 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:48,875 INFO L410 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:48,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:48,876 INFO L82 PathProgramCache]: Analyzing trace with hash 1387605663, now seen corresponding path program 1 times [2019-11-16 00:18:48,876 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:48,876 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1419287165] [2019-11-16 00:18:48,876 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:48,876 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:48,876 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:48,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:48,965 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 41 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:48,966 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1419287165] [2019-11-16 00:18:48,966 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1125508898] [2019-11-16 00:18:48,966 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:49,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:49,155 INFO L256 TraceCheckSpWp]: Trace formula consists of 798 conjuncts, 5 conjunts are in the unsatisfiable core [2019-11-16 00:18:49,158 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:49,198 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-11-16 00:18:49,199 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-16 00:18:49,199 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 10 [2019-11-16 00:18:49,199 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371260377] [2019-11-16 00:18:49,199 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:18:49,199 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:49,199 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:18:49,200 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-11-16 00:18:49,200 INFO L87 Difference]: Start difference. First operand 2836 states and 3520 transitions. Second operand 5 states. [2019-11-16 00:18:49,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:49,578 INFO L93 Difference]: Finished difference Result 5372 states and 6705 transitions. [2019-11-16 00:18:49,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:18:49,579 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 145 [2019-11-16 00:18:49,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:49,581 INFO L225 Difference]: With dead ends: 5372 [2019-11-16 00:18:49,581 INFO L226 Difference]: Without dead ends: 2615 [2019-11-16 00:18:49,583 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-11-16 00:18:49,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2615 states. [2019-11-16 00:18:50,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2615 to 2615. [2019-11-16 00:18:50,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2615 states. [2019-11-16 00:18:50,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2615 states to 2615 states and 3261 transitions. [2019-11-16 00:18:50,091 INFO L78 Accepts]: Start accepts. Automaton has 2615 states and 3261 transitions. Word has length 145 [2019-11-16 00:18:50,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:50,091 INFO L462 AbstractCegarLoop]: Abstraction has 2615 states and 3261 transitions. [2019-11-16 00:18:50,091 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:18:50,092 INFO L276 IsEmpty]: Start isEmpty. Operand 2615 states and 3261 transitions. [2019-11-16 00:18:50,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-11-16 00:18:50,093 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:50,093 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:50,294 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:50,294 INFO L410 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:50,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:50,294 INFO L82 PathProgramCache]: Analyzing trace with hash 439953908, now seen corresponding path program 1 times [2019-11-16 00:18:50,294 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:50,295 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451597471] [2019-11-16 00:18:50,295 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:50,295 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:50,295 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:50,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:50,455 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 17 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:50,455 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451597471] [2019-11-16 00:18:50,455 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1291670493] [2019-11-16 00:18:50,455 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:50,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:18:50,623 INFO L256 TraceCheckSpWp]: Trace formula consists of 787 conjuncts, 14 conjunts are in the unsatisfiable core [2019-11-16 00:18:50,626 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-16 00:18:50,687 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 17 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:18:50,688 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-16 00:18:50,688 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2019-11-16 00:18:50,688 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020464516] [2019-11-16 00:18:50,688 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-16 00:18:50,688 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:18:50,688 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-16 00:18:50,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:18:50,689 INFO L87 Difference]: Start difference. First operand 2615 states and 3261 transitions. Second operand 7 states. [2019-11-16 00:18:51,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:18:51,783 INFO L93 Difference]: Finished difference Result 7727 states and 9807 transitions. [2019-11-16 00:18:51,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-11-16 00:18:51,783 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 145 [2019-11-16 00:18:51,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:18:51,788 INFO L225 Difference]: With dead ends: 7727 [2019-11-16 00:18:51,788 INFO L226 Difference]: Without dead ends: 5319 [2019-11-16 00:18:51,790 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 150 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=138, Invalid=324, Unknown=0, NotChecked=0, Total=462 [2019-11-16 00:18:51,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5319 states. [2019-11-16 00:18:52,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5319 to 2615. [2019-11-16 00:18:52,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2615 states. [2019-11-16 00:18:52,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2615 states to 2615 states and 3237 transitions. [2019-11-16 00:18:52,165 INFO L78 Accepts]: Start accepts. Automaton has 2615 states and 3237 transitions. Word has length 145 [2019-11-16 00:18:52,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:18:52,165 INFO L462 AbstractCegarLoop]: Abstraction has 2615 states and 3237 transitions. [2019-11-16 00:18:52,165 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-16 00:18:52,166 INFO L276 IsEmpty]: Start isEmpty. Operand 2615 states and 3237 transitions. [2019-11-16 00:18:52,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-11-16 00:18:52,167 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:18:52,167 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:18:52,367 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-16 00:18:52,368 INFO L410 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:18:52,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:18:52,368 INFO L82 PathProgramCache]: Analyzing trace with hash -372990953, now seen corresponding path program 1 times [2019-11-16 00:18:52,368 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:18:52,368 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989851465] [2019-11-16 00:18:52,368 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:52,369 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:18:52,369 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:18:52,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-16 00:18:52,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-16 00:18:52,595 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-16 00:18:52,595 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-11-16 00:18:52,832 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 16.11 12:18:52 BoogieIcfgContainer [2019-11-16 00:18:52,832 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-16 00:18:52,832 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-16 00:18:52,833 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-16 00:18:52,833 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-16 00:18:52,833 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:17:59" (3/4) ... [2019-11-16 00:18:52,836 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-16 00:18:53,066 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_402c5286-971f-4e85-a91e-a02d9777a2c0/bin/uautomizer/witness.graphml [2019-11-16 00:18:53,066 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-16 00:18:53,068 INFO L168 Benchmark]: Toolchain (without parser) took 55541.00 ms. Allocated memory was 1.0 GB in the beginning and 2.5 GB in the end (delta: 1.5 GB). Free memory was 939.4 MB in the beginning and 1.0 GB in the end (delta: -80.3 MB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2019-11-16 00:18:53,068 INFO L168 Benchmark]: CDTParser took 0.25 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-16 00:18:53,068 INFO L168 Benchmark]: CACSL2BoogieTranslator took 467.82 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.7 MB). Free memory was 939.4 MB in the beginning and 1.1 GB in the end (delta: -183.4 MB). Peak memory consumption was 17.8 MB. Max. memory is 11.5 GB. [2019-11-16 00:18:53,069 INFO L168 Benchmark]: Boogie Procedure Inliner took 76.21 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-11-16 00:18:53,069 INFO L168 Benchmark]: Boogie Preprocessor took 62.90 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-11-16 00:18:53,069 INFO L168 Benchmark]: RCFGBuilder took 1177.97 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 88.2 MB). Peak memory consumption was 88.2 MB. Max. memory is 11.5 GB. [2019-11-16 00:18:53,070 INFO L168 Benchmark]: TraceAbstraction took 53512.53 ms. Allocated memory was 1.2 GB in the beginning and 2.5 GB in the end (delta: 1.4 GB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -38.7 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2019-11-16 00:18:53,070 INFO L168 Benchmark]: Witness Printer took 233.72 ms. Allocated memory is still 2.5 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 42.9 MB). Peak memory consumption was 42.9 MB. Max. memory is 11.5 GB. [2019-11-16 00:18:53,072 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 467.82 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.7 MB). Free memory was 939.4 MB in the beginning and 1.1 GB in the end (delta: -183.4 MB). Peak memory consumption was 17.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 76.21 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 62.90 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1177.97 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 88.2 MB). Peak memory consumption was 88.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 53512.53 ms. Allocated memory was 1.2 GB in the beginning and 2.5 GB in the end (delta: 1.4 GB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -38.7 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. * Witness Printer took 233.72 ms. Allocated memory is still 2.5 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 42.9 MB). Peak memory consumption was 42.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 662]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L463] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L585] int c1 ; [L586] int i2 ; [L589] c1 = 0 [L590] side1Failed = __VERIFIER_nondet_bool() [L591] side2Failed = __VERIFIER_nondet_bool() [L592] side1_written = __VERIFIER_nondet_char() [L593] side2_written = __VERIFIER_nondet_char() [L594] side1Failed_History_0 = __VERIFIER_nondet_bool() [L595] side1Failed_History_1 = __VERIFIER_nondet_bool() [L596] side1Failed_History_2 = __VERIFIER_nondet_bool() [L597] side2Failed_History_0 = __VERIFIER_nondet_bool() [L598] side2Failed_History_1 = __VERIFIER_nondet_bool() [L599] side2Failed_History_2 = __VERIFIER_nondet_bool() [L600] active_side_History_0 = __VERIFIER_nondet_char() [L601] active_side_History_1 = __VERIFIER_nondet_char() [L602] active_side_History_2 = __VERIFIER_nondet_char() [L603] manual_selection_History_0 = __VERIFIER_nondet_char() [L604] manual_selection_History_1 = __VERIFIER_nondet_char() [L605] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L606] i2 = init() [L608] cs1_old = nomsg [L609] cs1_new = nomsg [L610] cs2_old = nomsg [L611] cs2_new = nomsg [L612] s1s2_old = nomsg [L613] s1s2_new = nomsg [L614] s1s1_old = nomsg [L615] s1s1_new = nomsg [L616] s2s1_old = nomsg [L617] s2s1_new = nomsg [L618] s2s2_old = nomsg [L619] s2s2_new = nomsg [L620] s1p_old = nomsg [L621] s1p_new = nomsg [L622] s2p_old = nomsg [L623] s2p_new = nomsg [L624] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND FALSE !((int )side2 == 0) [L454] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L501] tmp___1 = read_side1_failed_history((unsigned char)1) [L502] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L503] tmp___2 = read_side1_failed_history((unsigned char)0) [L504] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L545] tmp___11 = read_side1_failed_history((unsigned char)1) [L546] COND TRUE ! tmp___11 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L547] tmp___12 = read_side2_failed_history((unsigned char)1) [L548] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L561] tmp___20 = read_active_side_history((unsigned char)2) [L562] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L580] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L660] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L649] i2 ++ VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L392] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L393] COND TRUE (int )side2 != (int )nomsg [L394] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND TRUE (int )side2 == 0 [L452] active_side = (int8_t )2 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND FALSE !(! tmp___0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND TRUE \read(tmp___7) [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L531] tmp___8 = read_side2_failed_history((unsigned char)1) [L532] COND TRUE ! tmp___8 [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L533] tmp___5 = read_active_side_history((unsigned char)0) [L534] COND FALSE !(! ((int )tmp___5 == 2)) [L160] COND TRUE (int )index == 0 [L161] return (side2Failed_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] tmp___6 = read_side2_failed_history((unsigned char)0) [L538] COND TRUE ! tmp___6 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L539] COND TRUE ! ((int )side2_written == 1) [L540] return (0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L660] COND TRUE ! arg VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L662] __VERIFIER_error() VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 293 locations, 23 error locations. Result: UNSAFE, OverallTime: 53.4s, OverallIterations: 46, TraceHistogramMax: 2, AutomataDifference: 31.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 20637 SDtfs, 43165 SDslu, 53254 SDs, 0 SdLazy, 10392 SolverSat, 622 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 8.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2329 GetRequests, 1700 SyntacticMatches, 29 SemanticMatches, 600 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12786 ImplicationChecksByTransitivity, 12.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3391occurred in iteration=40, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 7.2s AutomataMinimizationTime, 45 MinimizatonAttempts, 39349 StatesRemovedByMinimization, 40 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.7s SsaConstructionTime, 2.3s SatisfiabilityAnalysisTime, 6.1s InterpolantComputationTime, 6060 NumberOfCodeBlocks, 6060 NumberOfCodeBlocksAsserted, 58 NumberOfCheckSat, 5858 ConstructedInterpolants, 0 QuantifiedInterpolants, 2923532 SizeOfPredicates, 60 NumberOfNonLiveVariables, 9206 ConjunctsInSsa, 213 ConjunctsInUnsatCore, 57 InterpolantComputations, 39 PerfectInterpolantSequences, 915/1156 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...