./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c -s /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bd3b02b89b8fe5eebc8d5c8d901354afb3132de1 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-11-15 22:51:03,625 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-15 22:51:03,627 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-15 22:51:03,639 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-15 22:51:03,639 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-15 22:51:03,641 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-15 22:51:03,642 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-15 22:51:03,645 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-15 22:51:03,647 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-15 22:51:03,648 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-15 22:51:03,649 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-15 22:51:03,651 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-15 22:51:03,651 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-15 22:51:03,652 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-15 22:51:03,653 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-15 22:51:03,655 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-15 22:51:03,656 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-15 22:51:03,657 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-15 22:51:03,659 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-15 22:51:03,661 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-15 22:51:03,665 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-15 22:51:03,669 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-15 22:51:03,672 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-15 22:51:03,674 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-15 22:51:03,677 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-15 22:51:03,679 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-15 22:51:03,679 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-15 22:51:03,680 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-15 22:51:03,682 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-15 22:51:03,683 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-15 22:51:03,684 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-15 22:51:03,685 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-15 22:51:03,686 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-15 22:51:03,687 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-15 22:51:03,689 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-15 22:51:03,689 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-15 22:51:03,690 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-15 22:51:03,691 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-15 22:51:03,691 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-15 22:51:03,694 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-15 22:51:03,695 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-15 22:51:03,697 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-15 22:51:03,718 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-15 22:51:03,718 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-15 22:51:03,720 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-15 22:51:03,720 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-15 22:51:03,720 INFO L138 SettingsManager]: * Use SBE=true [2019-11-15 22:51:03,721 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-15 22:51:03,721 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-15 22:51:03,721 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-15 22:51:03,722 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-15 22:51:03,722 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-15 22:51:03,723 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-15 22:51:03,723 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-15 22:51:03,724 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-15 22:51:03,724 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-15 22:51:03,724 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-15 22:51:03,725 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-15 22:51:03,725 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-15 22:51:03,725 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-15 22:51:03,726 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-15 22:51:03,726 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-15 22:51:03,726 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-15 22:51:03,726 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 22:51:03,727 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-15 22:51:03,727 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-15 22:51:03,728 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-15 22:51:03,728 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-15 22:51:03,728 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-15 22:51:03,728 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-15 22:51:03,729 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bd3b02b89b8fe5eebc8d5c8d901354afb3132de1 [2019-11-15 22:51:03,790 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-15 22:51:03,801 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-15 22:51:03,816 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-15 22:51:03,818 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-15 22:51:03,818 INFO L275 PluginConnector]: CDTParser initialized [2019-11-15 22:51:03,820 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2019-11-15 22:51:03,891 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/data/68eba6242/e40c842da5fc4b339ceaf381432dcf6e/FLAG7191a778a [2019-11-15 22:51:04,332 INFO L306 CDTParser]: Found 1 translation units. [2019-11-15 22:51:04,333 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2019-11-15 22:51:04,344 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/data/68eba6242/e40c842da5fc4b339ceaf381432dcf6e/FLAG7191a778a [2019-11-15 22:51:04,651 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/data/68eba6242/e40c842da5fc4b339ceaf381432dcf6e [2019-11-15 22:51:04,653 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-15 22:51:04,654 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-15 22:51:04,655 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-15 22:51:04,655 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-15 22:51:04,658 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-15 22:51:04,659 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 10:51:04" (1/1) ... [2019-11-15 22:51:04,661 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1ba2d5c5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:04, skipping insertion in model container [2019-11-15 22:51:04,661 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 10:51:04" (1/1) ... [2019-11-15 22:51:04,668 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-15 22:51:04,715 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-15 22:51:05,066 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 22:51:05,077 INFO L188 MainTranslator]: Completed pre-run [2019-11-15 22:51:05,151 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 22:51:05,174 INFO L192 MainTranslator]: Completed translation [2019-11-15 22:51:05,175 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05 WrapperNode [2019-11-15 22:51:05,175 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-15 22:51:05,176 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-15 22:51:05,176 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-15 22:51:05,176 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-15 22:51:05,183 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05" (1/1) ... [2019-11-15 22:51:05,198 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05" (1/1) ... [2019-11-15 22:51:05,278 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-15 22:51:05,278 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-15 22:51:05,278 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-15 22:51:05,278 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-15 22:51:05,286 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05" (1/1) ... [2019-11-15 22:51:05,287 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05" (1/1) ... [2019-11-15 22:51:05,293 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05" (1/1) ... [2019-11-15 22:51:05,293 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05" (1/1) ... [2019-11-15 22:51:05,310 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05" (1/1) ... [2019-11-15 22:51:05,322 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05" (1/1) ... [2019-11-15 22:51:05,327 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05" (1/1) ... [2019-11-15 22:51:05,335 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-15 22:51:05,336 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-15 22:51:05,336 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-15 22:51:05,336 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-15 22:51:05,349 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 22:51:05,427 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-15 22:51:05,427 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-15 22:51:06,884 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-15 22:51:06,885 INFO L284 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-15 22:51:06,886 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 10:51:06 BoogieIcfgContainer [2019-11-15 22:51:06,886 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-15 22:51:06,887 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-15 22:51:06,887 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-15 22:51:06,893 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-15 22:51:06,894 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 15.11 10:51:04" (1/3) ... [2019-11-15 22:51:06,897 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4d262de9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 10:51:06, skipping insertion in model container [2019-11-15 22:51:06,898 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:51:05" (2/3) ... [2019-11-15 22:51:06,899 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4d262de9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 10:51:06, skipping insertion in model container [2019-11-15 22:51:06,899 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 10:51:06" (3/3) ... [2019-11-15 22:51:06,902 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2019-11-15 22:51:06,913 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-15 22:51:06,926 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-11-15 22:51:06,938 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-11-15 22:51:06,980 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-15 22:51:06,980 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-15 22:51:06,981 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-15 22:51:06,981 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-15 22:51:06,981 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-15 22:51:06,982 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-15 22:51:06,982 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-15 22:51:06,982 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-15 22:51:07,018 INFO L276 IsEmpty]: Start isEmpty. Operand 292 states. [2019-11-15 22:51:07,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-11-15 22:51:07,026 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:07,026 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:07,030 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:07,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:07,036 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-11-15 22:51:07,045 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:07,046 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [88200400] [2019-11-15 22:51:07,046 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:07,046 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:07,047 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:07,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:07,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:07,253 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [88200400] [2019-11-15 22:51:07,253 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:07,254 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:51:07,254 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1969050248] [2019-11-15 22:51:07,258 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:51:07,258 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:07,270 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:51:07,271 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:07,273 INFO L87 Difference]: Start difference. First operand 292 states. Second operand 3 states. [2019-11-15 22:51:07,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:07,357 INFO L93 Difference]: Finished difference Result 566 states and 887 transitions. [2019-11-15 22:51:07,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:51:07,359 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-11-15 22:51:07,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:07,375 INFO L225 Difference]: With dead ends: 566 [2019-11-15 22:51:07,375 INFO L226 Difference]: Without dead ends: 288 [2019-11-15 22:51:07,380 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:07,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2019-11-15 22:51:07,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2019-11-15 22:51:07,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 288 states. [2019-11-15 22:51:07,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 412 transitions. [2019-11-15 22:51:07,452 INFO L78 Accepts]: Start accepts. Automaton has 288 states and 412 transitions. Word has length 31 [2019-11-15 22:51:07,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:07,453 INFO L462 AbstractCegarLoop]: Abstraction has 288 states and 412 transitions. [2019-11-15 22:51:07,453 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:51:07,453 INFO L276 IsEmpty]: Start isEmpty. Operand 288 states and 412 transitions. [2019-11-15 22:51:07,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-11-15 22:51:07,455 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:07,456 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:07,456 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:07,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:07,457 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-11-15 22:51:07,457 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:07,458 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653307423] [2019-11-15 22:51:07,458 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:07,458 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:07,458 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:07,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:07,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:07,618 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1653307423] [2019-11-15 22:51:07,618 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:07,618 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:51:07,619 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379450967] [2019-11-15 22:51:07,620 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:51:07,620 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:07,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:51:07,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:07,621 INFO L87 Difference]: Start difference. First operand 288 states and 412 transitions. Second operand 3 states. [2019-11-15 22:51:07,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:07,701 INFO L93 Difference]: Finished difference Result 594 states and 858 transitions. [2019-11-15 22:51:07,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:51:07,701 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-11-15 22:51:07,702 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:07,706 INFO L225 Difference]: With dead ends: 594 [2019-11-15 22:51:07,707 INFO L226 Difference]: Without dead ends: 321 [2019-11-15 22:51:07,710 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:07,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2019-11-15 22:51:07,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 264. [2019-11-15 22:51:07,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 264 states. [2019-11-15 22:51:07,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 264 states to 264 states and 376 transitions. [2019-11-15 22:51:07,739 INFO L78 Accepts]: Start accepts. Automaton has 264 states and 376 transitions. Word has length 42 [2019-11-15 22:51:07,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:07,740 INFO L462 AbstractCegarLoop]: Abstraction has 264 states and 376 transitions. [2019-11-15 22:51:07,740 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:51:07,740 INFO L276 IsEmpty]: Start isEmpty. Operand 264 states and 376 transitions. [2019-11-15 22:51:07,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-15 22:51:07,743 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:07,743 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:07,744 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:07,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:07,745 INFO L82 PathProgramCache]: Analyzing trace with hash 1273755287, now seen corresponding path program 1 times [2019-11-15 22:51:07,745 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:07,745 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228975313] [2019-11-15 22:51:07,746 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:07,746 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:07,746 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:07,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:07,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:07,894 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228975313] [2019-11-15 22:51:07,895 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:07,895 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:51:07,895 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [340258279] [2019-11-15 22:51:07,896 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:51:07,896 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:07,896 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:51:07,897 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:07,897 INFO L87 Difference]: Start difference. First operand 264 states and 376 transitions. Second operand 3 states. [2019-11-15 22:51:07,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:07,961 INFO L93 Difference]: Finished difference Result 739 states and 1063 transitions. [2019-11-15 22:51:07,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:51:07,962 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-15 22:51:07,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:07,972 INFO L225 Difference]: With dead ends: 739 [2019-11-15 22:51:07,972 INFO L226 Difference]: Without dead ends: 490 [2019-11-15 22:51:07,975 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:07,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490 states. [2019-11-15 22:51:08,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490 to 299. [2019-11-15 22:51:08,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 299 states. [2019-11-15 22:51:08,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 299 states to 299 states and 428 transitions. [2019-11-15 22:51:08,020 INFO L78 Accepts]: Start accepts. Automaton has 299 states and 428 transitions. Word has length 49 [2019-11-15 22:51:08,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:08,021 INFO L462 AbstractCegarLoop]: Abstraction has 299 states and 428 transitions. [2019-11-15 22:51:08,021 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:51:08,022 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 428 transitions. [2019-11-15 22:51:08,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-11-15 22:51:08,035 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:08,035 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:08,036 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:08,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:08,036 INFO L82 PathProgramCache]: Analyzing trace with hash -1910840580, now seen corresponding path program 1 times [2019-11-15 22:51:08,037 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:08,037 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501774603] [2019-11-15 22:51:08,037 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:08,037 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:08,038 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:08,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:08,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:08,172 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501774603] [2019-11-15 22:51:08,172 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:08,172 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:08,172 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [871011955] [2019-11-15 22:51:08,173 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:51:08,173 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:08,175 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:51:08,175 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:08,176 INFO L87 Difference]: Start difference. First operand 299 states and 428 transitions. Second operand 5 states. [2019-11-15 22:51:08,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:08,558 INFO L93 Difference]: Finished difference Result 939 states and 1357 transitions. [2019-11-15 22:51:08,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 22:51:08,559 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-11-15 22:51:08,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:08,566 INFO L225 Difference]: With dead ends: 939 [2019-11-15 22:51:08,567 INFO L226 Difference]: Without dead ends: 655 [2019-11-15 22:51:08,568 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-15 22:51:08,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 655 states. [2019-11-15 22:51:08,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 655 to 385. [2019-11-15 22:51:08,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 385 states. [2019-11-15 22:51:08,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385 states to 385 states and 551 transitions. [2019-11-15 22:51:08,598 INFO L78 Accepts]: Start accepts. Automaton has 385 states and 551 transitions. Word has length 50 [2019-11-15 22:51:08,600 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:08,601 INFO L462 AbstractCegarLoop]: Abstraction has 385 states and 551 transitions. [2019-11-15 22:51:08,601 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:51:08,602 INFO L276 IsEmpty]: Start isEmpty. Operand 385 states and 551 transitions. [2019-11-15 22:51:08,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-11-15 22:51:08,610 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:08,610 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:08,611 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:08,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:08,611 INFO L82 PathProgramCache]: Analyzing trace with hash -1041102253, now seen corresponding path program 1 times [2019-11-15 22:51:08,612 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:08,612 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258206217] [2019-11-15 22:51:08,612 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:08,612 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:08,613 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:08,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:08,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:08,743 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [258206217] [2019-11-15 22:51:08,743 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:08,744 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:08,744 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568175766] [2019-11-15 22:51:08,744 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:51:08,745 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:08,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:51:08,745 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:08,746 INFO L87 Difference]: Start difference. First operand 385 states and 551 transitions. Second operand 5 states. [2019-11-15 22:51:09,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:09,100 INFO L93 Difference]: Finished difference Result 941 states and 1357 transitions. [2019-11-15 22:51:09,102 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 22:51:09,102 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-11-15 22:51:09,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:09,110 INFO L225 Difference]: With dead ends: 941 [2019-11-15 22:51:09,110 INFO L226 Difference]: Without dead ends: 657 [2019-11-15 22:51:09,112 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-15 22:51:09,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states. [2019-11-15 22:51:09,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 389. [2019-11-15 22:51:09,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389 states. [2019-11-15 22:51:09,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 555 transitions. [2019-11-15 22:51:09,145 INFO L78 Accepts]: Start accepts. Automaton has 389 states and 555 transitions. Word has length 51 [2019-11-15 22:51:09,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:09,146 INFO L462 AbstractCegarLoop]: Abstraction has 389 states and 555 transitions. [2019-11-15 22:51:09,146 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:51:09,146 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 555 transitions. [2019-11-15 22:51:09,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-15 22:51:09,148 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:09,149 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:09,150 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:09,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:09,150 INFO L82 PathProgramCache]: Analyzing trace with hash -458607163, now seen corresponding path program 1 times [2019-11-15 22:51:09,151 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:09,151 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796441577] [2019-11-15 22:51:09,151 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:09,152 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:09,152 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:09,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:09,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:09,309 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796441577] [2019-11-15 22:51:09,310 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:09,310 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:09,310 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [528526991] [2019-11-15 22:51:09,311 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 22:51:09,311 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:09,312 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 22:51:09,312 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:09,312 INFO L87 Difference]: Start difference. First operand 389 states and 555 transitions. Second operand 4 states. [2019-11-15 22:51:09,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:09,657 INFO L93 Difference]: Finished difference Result 941 states and 1353 transitions. [2019-11-15 22:51:09,659 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:51:09,659 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 53 [2019-11-15 22:51:09,661 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:09,666 INFO L225 Difference]: With dead ends: 941 [2019-11-15 22:51:09,667 INFO L226 Difference]: Without dead ends: 657 [2019-11-15 22:51:09,669 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:09,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states. [2019-11-15 22:51:09,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 389. [2019-11-15 22:51:09,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389 states. [2019-11-15 22:51:09,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 553 transitions. [2019-11-15 22:51:09,698 INFO L78 Accepts]: Start accepts. Automaton has 389 states and 553 transitions. Word has length 53 [2019-11-15 22:51:09,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:09,699 INFO L462 AbstractCegarLoop]: Abstraction has 389 states and 553 transitions. [2019-11-15 22:51:09,700 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 22:51:09,700 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 553 transitions. [2019-11-15 22:51:09,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-15 22:51:09,701 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:09,702 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:09,702 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:09,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:09,713 INFO L82 PathProgramCache]: Analyzing trace with hash 1789775306, now seen corresponding path program 1 times [2019-11-15 22:51:09,714 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:09,714 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483052166] [2019-11-15 22:51:09,714 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:09,715 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:09,715 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:09,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:09,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:09,918 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [483052166] [2019-11-15 22:51:09,919 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:09,919 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 22:51:09,919 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799788637] [2019-11-15 22:51:09,919 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:51:09,920 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:09,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:51:09,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:09,920 INFO L87 Difference]: Start difference. First operand 389 states and 553 transitions. Second operand 5 states. [2019-11-15 22:51:09,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:09,999 INFO L93 Difference]: Finished difference Result 773 states and 1114 transitions. [2019-11-15 22:51:10,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-15 22:51:10,000 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2019-11-15 22:51:10,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:10,004 INFO L225 Difference]: With dead ends: 773 [2019-11-15 22:51:10,005 INFO L226 Difference]: Without dead ends: 489 [2019-11-15 22:51:10,006 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-11-15 22:51:10,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 489 states. [2019-11-15 22:51:10,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 489 to 384. [2019-11-15 22:51:10,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 384 states. [2019-11-15 22:51:10,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 545 transitions. [2019-11-15 22:51:10,031 INFO L78 Accepts]: Start accepts. Automaton has 384 states and 545 transitions. Word has length 54 [2019-11-15 22:51:10,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:10,032 INFO L462 AbstractCegarLoop]: Abstraction has 384 states and 545 transitions. [2019-11-15 22:51:10,032 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:51:10,032 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 545 transitions. [2019-11-15 22:51:10,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-15 22:51:10,033 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:10,033 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:10,034 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:10,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:10,035 INFO L82 PathProgramCache]: Analyzing trace with hash 1630366882, now seen corresponding path program 1 times [2019-11-15 22:51:10,035 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:10,035 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906586684] [2019-11-15 22:51:10,035 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:10,036 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:10,036 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:10,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:10,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:10,181 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906586684] [2019-11-15 22:51:10,181 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:10,181 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 22:51:10,181 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1476841478] [2019-11-15 22:51:10,181 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:51:10,182 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:10,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:51:10,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:10,182 INFO L87 Difference]: Start difference. First operand 384 states and 545 transitions. Second operand 5 states. [2019-11-15 22:51:10,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:10,315 INFO L93 Difference]: Finished difference Result 804 states and 1163 transitions. [2019-11-15 22:51:10,315 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:51:10,316 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-11-15 22:51:10,316 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:10,319 INFO L225 Difference]: With dead ends: 804 [2019-11-15 22:51:10,320 INFO L226 Difference]: Without dead ends: 525 [2019-11-15 22:51:10,321 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-15 22:51:10,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states. [2019-11-15 22:51:10,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 354. [2019-11-15 22:51:10,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354 states. [2019-11-15 22:51:10,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 499 transitions. [2019-11-15 22:51:10,344 INFO L78 Accepts]: Start accepts. Automaton has 354 states and 499 transitions. Word has length 58 [2019-11-15 22:51:10,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:10,344 INFO L462 AbstractCegarLoop]: Abstraction has 354 states and 499 transitions. [2019-11-15 22:51:10,344 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:51:10,344 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 499 transitions. [2019-11-15 22:51:10,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-15 22:51:10,345 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:10,346 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:10,346 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:10,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:10,347 INFO L82 PathProgramCache]: Analyzing trace with hash 644191382, now seen corresponding path program 1 times [2019-11-15 22:51:10,347 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:10,347 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234621080] [2019-11-15 22:51:10,347 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:10,347 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:10,348 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:10,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:10,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:10,484 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1234621080] [2019-11-15 22:51:10,484 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:10,485 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 22:51:10,485 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005690777] [2019-11-15 22:51:10,485 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:51:10,485 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:10,486 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:51:10,486 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:10,486 INFO L87 Difference]: Start difference. First operand 354 states and 499 transitions. Second operand 5 states. [2019-11-15 22:51:10,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:10,649 INFO L93 Difference]: Finished difference Result 900 states and 1292 transitions. [2019-11-15 22:51:10,649 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:51:10,650 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 63 [2019-11-15 22:51:10,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:10,655 INFO L225 Difference]: With dead ends: 900 [2019-11-15 22:51:10,655 INFO L226 Difference]: Without dead ends: 651 [2019-11-15 22:51:10,656 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-15 22:51:10,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 651 states. [2019-11-15 22:51:10,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 651 to 324. [2019-11-15 22:51:10,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 324 states. [2019-11-15 22:51:10,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324 states to 324 states and 453 transitions. [2019-11-15 22:51:10,687 INFO L78 Accepts]: Start accepts. Automaton has 324 states and 453 transitions. Word has length 63 [2019-11-15 22:51:10,688 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:10,688 INFO L462 AbstractCegarLoop]: Abstraction has 324 states and 453 transitions. [2019-11-15 22:51:10,688 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:51:10,688 INFO L276 IsEmpty]: Start isEmpty. Operand 324 states and 453 transitions. [2019-11-15 22:51:10,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-11-15 22:51:10,689 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:10,690 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:10,695 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:10,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:10,695 INFO L82 PathProgramCache]: Analyzing trace with hash 157991886, now seen corresponding path program 1 times [2019-11-15 22:51:10,696 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:10,696 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912069964] [2019-11-15 22:51:10,696 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:10,697 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:10,697 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:10,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:10,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:10,876 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912069964] [2019-11-15 22:51:10,876 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:10,876 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 22:51:10,876 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451727900] [2019-11-15 22:51:10,877 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:10,877 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:10,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:10,878 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 22:51:10,878 INFO L87 Difference]: Start difference. First operand 324 states and 453 transitions. Second operand 6 states. [2019-11-15 22:51:11,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:11,189 INFO L93 Difference]: Finished difference Result 1098 states and 1557 transitions. [2019-11-15 22:51:11,190 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-15 22:51:11,190 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-11-15 22:51:11,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:11,197 INFO L225 Difference]: With dead ends: 1098 [2019-11-15 22:51:11,197 INFO L226 Difference]: Without dead ends: 879 [2019-11-15 22:51:11,202 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-15 22:51:11,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 879 states. [2019-11-15 22:51:11,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 879 to 363. [2019-11-15 22:51:11,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 363 states. [2019-11-15 22:51:11,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 363 states to 363 states and 507 transitions. [2019-11-15 22:51:11,236 INFO L78 Accepts]: Start accepts. Automaton has 363 states and 507 transitions. Word has length 68 [2019-11-15 22:51:11,236 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:11,237 INFO L462 AbstractCegarLoop]: Abstraction has 363 states and 507 transitions. [2019-11-15 22:51:11,237 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:11,237 INFO L276 IsEmpty]: Start isEmpty. Operand 363 states and 507 transitions. [2019-11-15 22:51:11,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-11-15 22:51:11,243 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:11,243 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:11,244 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:11,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:11,245 INFO L82 PathProgramCache]: Analyzing trace with hash -2134355609, now seen corresponding path program 1 times [2019-11-15 22:51:11,245 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:11,245 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098253026] [2019-11-15 22:51:11,245 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:11,246 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:11,246 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:11,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:11,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:11,344 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2098253026] [2019-11-15 22:51:11,344 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:11,344 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:51:11,344 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1226626083] [2019-11-15 22:51:11,344 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:51:11,345 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:11,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:51:11,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:11,345 INFO L87 Difference]: Start difference. First operand 363 states and 507 transitions. Second operand 3 states. [2019-11-15 22:51:11,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:11,410 INFO L93 Difference]: Finished difference Result 659 states and 932 transitions. [2019-11-15 22:51:11,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:51:11,411 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-11-15 22:51:11,411 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:11,414 INFO L225 Difference]: With dead ends: 659 [2019-11-15 22:51:11,414 INFO L226 Difference]: Without dead ends: 440 [2019-11-15 22:51:11,415 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:11,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 440 states. [2019-11-15 22:51:11,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 440 to 359. [2019-11-15 22:51:11,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 359 states. [2019-11-15 22:51:11,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 359 states to 359 states and 500 transitions. [2019-11-15 22:51:11,444 INFO L78 Accepts]: Start accepts. Automaton has 359 states and 500 transitions. Word has length 69 [2019-11-15 22:51:11,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:11,444 INFO L462 AbstractCegarLoop]: Abstraction has 359 states and 500 transitions. [2019-11-15 22:51:11,444 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:51:11,444 INFO L276 IsEmpty]: Start isEmpty. Operand 359 states and 500 transitions. [2019-11-15 22:51:11,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 22:51:11,445 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:11,446 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:11,451 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:11,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:11,451 INFO L82 PathProgramCache]: Analyzing trace with hash 1585943340, now seen corresponding path program 1 times [2019-11-15 22:51:11,451 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:11,452 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842189789] [2019-11-15 22:51:11,452 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:11,452 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:11,452 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:11,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:11,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:11,529 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842189789] [2019-11-15 22:51:11,530 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:11,530 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:11,530 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743375844] [2019-11-15 22:51:11,531 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 22:51:11,531 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:11,532 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 22:51:11,532 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:11,532 INFO L87 Difference]: Start difference. First operand 359 states and 500 transitions. Second operand 4 states. [2019-11-15 22:51:11,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:11,726 INFO L93 Difference]: Finished difference Result 949 states and 1326 transitions. [2019-11-15 22:51:11,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:51:11,727 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2019-11-15 22:51:11,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:11,732 INFO L225 Difference]: With dead ends: 949 [2019-11-15 22:51:11,733 INFO L226 Difference]: Without dead ends: 724 [2019-11-15 22:51:11,734 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:11,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 724 states. [2019-11-15 22:51:11,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 724 to 529. [2019-11-15 22:51:11,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 529 states. [2019-11-15 22:51:11,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 529 states to 529 states and 733 transitions. [2019-11-15 22:51:11,792 INFO L78 Accepts]: Start accepts. Automaton has 529 states and 733 transitions. Word has length 72 [2019-11-15 22:51:11,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:11,793 INFO L462 AbstractCegarLoop]: Abstraction has 529 states and 733 transitions. [2019-11-15 22:51:11,793 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 22:51:11,793 INFO L276 IsEmpty]: Start isEmpty. Operand 529 states and 733 transitions. [2019-11-15 22:51:11,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 22:51:11,795 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:11,795 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:11,796 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:11,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:11,796 INFO L82 PathProgramCache]: Analyzing trace with hash -2083950892, now seen corresponding path program 1 times [2019-11-15 22:51:11,796 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:11,797 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11852750] [2019-11-15 22:51:11,797 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:11,797 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:11,798 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:11,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:11,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:11,903 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11852750] [2019-11-15 22:51:11,904 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:11,904 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:51:11,904 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834036451] [2019-11-15 22:51:11,905 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:51:11,905 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:11,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:51:11,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:11,906 INFO L87 Difference]: Start difference. First operand 529 states and 733 transitions. Second operand 3 states. [2019-11-15 22:51:11,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:11,959 INFO L93 Difference]: Finished difference Result 907 states and 1262 transitions. [2019-11-15 22:51:11,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:51:11,960 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 22:51:11,961 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:11,964 INFO L225 Difference]: With dead ends: 907 [2019-11-15 22:51:11,965 INFO L226 Difference]: Without dead ends: 529 [2019-11-15 22:51:11,966 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:11,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 529 states. [2019-11-15 22:51:12,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 529 to 529. [2019-11-15 22:51:12,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 529 states. [2019-11-15 22:51:12,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 529 states to 529 states and 729 transitions. [2019-11-15 22:51:12,036 INFO L78 Accepts]: Start accepts. Automaton has 529 states and 729 transitions. Word has length 72 [2019-11-15 22:51:12,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:12,037 INFO L462 AbstractCegarLoop]: Abstraction has 529 states and 729 transitions. [2019-11-15 22:51:12,037 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:51:12,037 INFO L276 IsEmpty]: Start isEmpty. Operand 529 states and 729 transitions. [2019-11-15 22:51:12,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 22:51:12,038 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:12,038 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:12,039 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:12,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:12,039 INFO L82 PathProgramCache]: Analyzing trace with hash 2070467794, now seen corresponding path program 1 times [2019-11-15 22:51:12,039 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:12,040 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338244324] [2019-11-15 22:51:12,040 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:12,040 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:12,040 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:12,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:12,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:12,095 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338244324] [2019-11-15 22:51:12,095 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:12,095 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:51:12,095 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1064612407] [2019-11-15 22:51:12,096 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:51:12,096 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:12,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:51:12,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:12,096 INFO L87 Difference]: Start difference. First operand 529 states and 729 transitions. Second operand 3 states. [2019-11-15 22:51:12,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:12,165 INFO L93 Difference]: Finished difference Result 1250 states and 1717 transitions. [2019-11-15 22:51:12,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:51:12,165 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 22:51:12,166 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:12,170 INFO L225 Difference]: With dead ends: 1250 [2019-11-15 22:51:12,170 INFO L226 Difference]: Without dead ends: 835 [2019-11-15 22:51:12,171 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:12,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states. [2019-11-15 22:51:12,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 563. [2019-11-15 22:51:12,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 563 states. [2019-11-15 22:51:12,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 773 transitions. [2019-11-15 22:51:12,212 INFO L78 Accepts]: Start accepts. Automaton has 563 states and 773 transitions. Word has length 72 [2019-11-15 22:51:12,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:12,212 INFO L462 AbstractCegarLoop]: Abstraction has 563 states and 773 transitions. [2019-11-15 22:51:12,212 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:51:12,212 INFO L276 IsEmpty]: Start isEmpty. Operand 563 states and 773 transitions. [2019-11-15 22:51:12,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:51:12,213 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:12,214 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:12,214 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:12,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:12,214 INFO L82 PathProgramCache]: Analyzing trace with hash -1917205063, now seen corresponding path program 1 times [2019-11-15 22:51:12,215 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:12,215 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301114458] [2019-11-15 22:51:12,215 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:12,215 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:12,215 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:12,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:12,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:12,331 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301114458] [2019-11-15 22:51:12,331 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:12,331 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 22:51:12,331 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1882977045] [2019-11-15 22:51:12,331 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:12,332 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:12,332 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:12,332 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 22:51:12,332 INFO L87 Difference]: Start difference. First operand 563 states and 773 transitions. Second operand 6 states. [2019-11-15 22:51:12,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:12,717 INFO L93 Difference]: Finished difference Result 1763 states and 2476 transitions. [2019-11-15 22:51:12,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-15 22:51:12,718 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-11-15 22:51:12,718 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:12,728 INFO L225 Difference]: With dead ends: 1763 [2019-11-15 22:51:12,728 INFO L226 Difference]: Without dead ends: 1430 [2019-11-15 22:51:12,731 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-15 22:51:12,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1430 states. [2019-11-15 22:51:12,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1430 to 567. [2019-11-15 22:51:12,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 567 states. [2019-11-15 22:51:12,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 567 states to 567 states and 778 transitions. [2019-11-15 22:51:12,788 INFO L78 Accepts]: Start accepts. Automaton has 567 states and 778 transitions. Word has length 73 [2019-11-15 22:51:12,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:12,789 INFO L462 AbstractCegarLoop]: Abstraction has 567 states and 778 transitions. [2019-11-15 22:51:12,789 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:12,789 INFO L276 IsEmpty]: Start isEmpty. Operand 567 states and 778 transitions. [2019-11-15 22:51:12,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:51:12,790 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:12,791 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:12,791 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:12,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:12,792 INFO L82 PathProgramCache]: Analyzing trace with hash 197100160, now seen corresponding path program 1 times [2019-11-15 22:51:12,792 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:12,792 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313777275] [2019-11-15 22:51:12,792 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:12,793 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:12,793 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:12,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:12,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:12,911 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [313777275] [2019-11-15 22:51:12,913 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:12,914 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 22:51:12,914 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920648158] [2019-11-15 22:51:12,914 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:51:12,915 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:12,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:51:12,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:12,915 INFO L87 Difference]: Start difference. First operand 567 states and 778 transitions. Second operand 5 states. [2019-11-15 22:51:13,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:13,111 INFO L93 Difference]: Finished difference Result 886 states and 1237 transitions. [2019-11-15 22:51:13,111 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 22:51:13,112 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2019-11-15 22:51:13,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:13,117 INFO L225 Difference]: With dead ends: 886 [2019-11-15 22:51:13,118 INFO L226 Difference]: Without dead ends: 884 [2019-11-15 22:51:13,119 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-15 22:51:13,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 884 states. [2019-11-15 22:51:13,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 884 to 569. [2019-11-15 22:51:13,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 569 states. [2019-11-15 22:51:13,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 780 transitions. [2019-11-15 22:51:13,172 INFO L78 Accepts]: Start accepts. Automaton has 569 states and 780 transitions. Word has length 73 [2019-11-15 22:51:13,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:13,172 INFO L462 AbstractCegarLoop]: Abstraction has 569 states and 780 transitions. [2019-11-15 22:51:13,172 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:51:13,172 INFO L276 IsEmpty]: Start isEmpty. Operand 569 states and 780 transitions. [2019-11-15 22:51:13,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:51:13,174 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:13,174 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:13,174 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:13,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:13,175 INFO L82 PathProgramCache]: Analyzing trace with hash 2083582807, now seen corresponding path program 1 times [2019-11-15 22:51:13,175 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:13,175 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715335122] [2019-11-15 22:51:13,176 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:13,176 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:13,176 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:13,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:13,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:13,295 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715335122] [2019-11-15 22:51:13,295 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:13,295 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 22:51:13,295 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1377243246] [2019-11-15 22:51:13,296 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:13,296 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:13,296 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:13,296 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 22:51:13,296 INFO L87 Difference]: Start difference. First operand 569 states and 780 transitions. Second operand 6 states. [2019-11-15 22:51:13,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:13,932 INFO L93 Difference]: Finished difference Result 2030 states and 2821 transitions. [2019-11-15 22:51:13,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-15 22:51:13,933 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-11-15 22:51:13,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:13,945 INFO L225 Difference]: With dead ends: 2030 [2019-11-15 22:51:13,945 INFO L226 Difference]: Without dead ends: 1656 [2019-11-15 22:51:13,947 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-15 22:51:13,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1656 states. [2019-11-15 22:51:14,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1656 to 615. [2019-11-15 22:51:14,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 615 states. [2019-11-15 22:51:14,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 615 states to 615 states and 838 transitions. [2019-11-15 22:51:14,038 INFO L78 Accepts]: Start accepts. Automaton has 615 states and 838 transitions. Word has length 73 [2019-11-15 22:51:14,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:14,039 INFO L462 AbstractCegarLoop]: Abstraction has 615 states and 838 transitions. [2019-11-15 22:51:14,039 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:14,039 INFO L276 IsEmpty]: Start isEmpty. Operand 615 states and 838 transitions. [2019-11-15 22:51:14,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-15 22:51:14,041 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:14,041 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:14,041 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:14,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:14,043 INFO L82 PathProgramCache]: Analyzing trace with hash 1204676769, now seen corresponding path program 1 times [2019-11-15 22:51:14,043 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:14,044 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071907112] [2019-11-15 22:51:14,044 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:14,044 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:14,044 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:14,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:14,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:14,205 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2071907112] [2019-11-15 22:51:14,206 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:14,206 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 22:51:14,206 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854329634] [2019-11-15 22:51:14,207 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:14,207 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:14,207 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:14,207 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 22:51:14,207 INFO L87 Difference]: Start difference. First operand 615 states and 838 transitions. Second operand 6 states. [2019-11-15 22:51:14,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:14,760 INFO L93 Difference]: Finished difference Result 2356 states and 3253 transitions. [2019-11-15 22:51:14,760 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-15 22:51:14,761 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-11-15 22:51:14,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:14,773 INFO L225 Difference]: With dead ends: 2356 [2019-11-15 22:51:14,773 INFO L226 Difference]: Without dead ends: 1974 [2019-11-15 22:51:14,775 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-15 22:51:14,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1974 states. [2019-11-15 22:51:14,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1974 to 693. [2019-11-15 22:51:14,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 693 states. [2019-11-15 22:51:14,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 940 transitions. [2019-11-15 22:51:14,860 INFO L78 Accepts]: Start accepts. Automaton has 693 states and 940 transitions. Word has length 74 [2019-11-15 22:51:14,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:14,860 INFO L462 AbstractCegarLoop]: Abstraction has 693 states and 940 transitions. [2019-11-15 22:51:14,860 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:14,860 INFO L276 IsEmpty]: Start isEmpty. Operand 693 states and 940 transitions. [2019-11-15 22:51:14,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-15 22:51:14,862 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:14,862 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:14,862 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:14,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:14,863 INFO L82 PathProgramCache]: Analyzing trace with hash -217796256, now seen corresponding path program 1 times [2019-11-15 22:51:14,863 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:14,863 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167587372] [2019-11-15 22:51:14,863 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:14,864 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:14,864 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:14,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:14,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:14,957 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [167587372] [2019-11-15 22:51:14,958 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:14,958 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 22:51:14,958 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1226094423] [2019-11-15 22:51:14,958 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:14,959 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:14,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:14,959 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 22:51:14,959 INFO L87 Difference]: Start difference. First operand 693 states and 940 transitions. Second operand 6 states. [2019-11-15 22:51:15,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:15,204 INFO L93 Difference]: Finished difference Result 1555 states and 2195 transitions. [2019-11-15 22:51:15,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-15 22:51:15,205 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-11-15 22:51:15,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:15,211 INFO L225 Difference]: With dead ends: 1555 [2019-11-15 22:51:15,212 INFO L226 Difference]: Without dead ends: 1156 [2019-11-15 22:51:15,213 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-11-15 22:51:15,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1156 states. [2019-11-15 22:51:15,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1156 to 699. [2019-11-15 22:51:15,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 699 states. [2019-11-15 22:51:15,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 699 states to 699 states and 946 transitions. [2019-11-15 22:51:15,278 INFO L78 Accepts]: Start accepts. Automaton has 699 states and 946 transitions. Word has length 74 [2019-11-15 22:51:15,279 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:15,279 INFO L462 AbstractCegarLoop]: Abstraction has 699 states and 946 transitions. [2019-11-15 22:51:15,279 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:15,279 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 946 transitions. [2019-11-15 22:51:15,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-15 22:51:15,280 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:15,280 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:15,281 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:15,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:15,281 INFO L82 PathProgramCache]: Analyzing trace with hash -1278252476, now seen corresponding path program 1 times [2019-11-15 22:51:15,281 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:15,282 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250820807] [2019-11-15 22:51:15,282 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:15,282 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:15,282 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:15,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:15,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:15,328 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250820807] [2019-11-15 22:51:15,328 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:15,328 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:51:15,328 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209944653] [2019-11-15 22:51:15,329 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:51:15,329 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:15,329 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:51:15,329 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:15,329 INFO L87 Difference]: Start difference. First operand 699 states and 946 transitions. Second operand 3 states. [2019-11-15 22:51:15,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:15,453 INFO L93 Difference]: Finished difference Result 1371 states and 1888 transitions. [2019-11-15 22:51:15,453 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:51:15,454 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-11-15 22:51:15,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:15,459 INFO L225 Difference]: With dead ends: 1371 [2019-11-15 22:51:15,460 INFO L226 Difference]: Without dead ends: 903 [2019-11-15 22:51:15,461 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:15,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 903 states. [2019-11-15 22:51:15,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 903 to 678. [2019-11-15 22:51:15,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 678 states. [2019-11-15 22:51:15,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678 states to 678 states and 909 transitions. [2019-11-15 22:51:15,534 INFO L78 Accepts]: Start accepts. Automaton has 678 states and 909 transitions. Word has length 74 [2019-11-15 22:51:15,535 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:15,535 INFO L462 AbstractCegarLoop]: Abstraction has 678 states and 909 transitions. [2019-11-15 22:51:15,535 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:51:15,535 INFO L276 IsEmpty]: Start isEmpty. Operand 678 states and 909 transitions. [2019-11-15 22:51:15,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-15 22:51:15,536 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:15,537 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:15,537 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:15,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:15,537 INFO L82 PathProgramCache]: Analyzing trace with hash -1698648942, now seen corresponding path program 1 times [2019-11-15 22:51:15,538 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:15,538 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515039042] [2019-11-15 22:51:15,538 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:15,538 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:15,538 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:15,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:15,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:15,598 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [515039042] [2019-11-15 22:51:15,599 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:15,599 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:15,599 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704510325] [2019-11-15 22:51:15,600 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 22:51:15,600 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:15,600 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 22:51:15,600 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:15,601 INFO L87 Difference]: Start difference. First operand 678 states and 909 transitions. Second operand 4 states. [2019-11-15 22:51:15,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:15,830 INFO L93 Difference]: Finished difference Result 1740 states and 2346 transitions. [2019-11-15 22:51:15,830 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:51:15,830 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-11-15 22:51:15,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:15,839 INFO L225 Difference]: With dead ends: 1740 [2019-11-15 22:51:15,839 INFO L226 Difference]: Without dead ends: 1325 [2019-11-15 22:51:15,841 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:15,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1325 states. [2019-11-15 22:51:15,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1325 to 922. [2019-11-15 22:51:15,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 922 states. [2019-11-15 22:51:15,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 922 states to 922 states and 1236 transitions. [2019-11-15 22:51:15,978 INFO L78 Accepts]: Start accepts. Automaton has 922 states and 1236 transitions. Word has length 75 [2019-11-15 22:51:15,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:15,978 INFO L462 AbstractCegarLoop]: Abstraction has 922 states and 1236 transitions. [2019-11-15 22:51:15,978 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 22:51:15,979 INFO L276 IsEmpty]: Start isEmpty. Operand 922 states and 1236 transitions. [2019-11-15 22:51:15,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-15 22:51:15,980 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:15,980 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:15,981 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:15,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:15,981 INFO L82 PathProgramCache]: Analyzing trace with hash -1596781464, now seen corresponding path program 1 times [2019-11-15 22:51:15,981 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:15,982 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444672658] [2019-11-15 22:51:15,982 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:15,982 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:15,982 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:16,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:16,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:16,036 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [444672658] [2019-11-15 22:51:16,037 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:16,037 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:51:16,037 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547371717] [2019-11-15 22:51:16,037 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:51:16,037 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:16,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:51:16,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:16,038 INFO L87 Difference]: Start difference. First operand 922 states and 1236 transitions. Second operand 3 states. [2019-11-15 22:51:16,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:16,201 INFO L93 Difference]: Finished difference Result 1929 states and 2618 transitions. [2019-11-15 22:51:16,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:51:16,201 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2019-11-15 22:51:16,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:16,209 INFO L225 Difference]: With dead ends: 1929 [2019-11-15 22:51:16,209 INFO L226 Difference]: Without dead ends: 1325 [2019-11-15 22:51:16,210 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:16,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1325 states. [2019-11-15 22:51:16,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1325 to 876. [2019-11-15 22:51:16,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 876 states. [2019-11-15 22:51:16,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 876 states to 876 states and 1170 transitions. [2019-11-15 22:51:16,292 INFO L78 Accepts]: Start accepts. Automaton has 876 states and 1170 transitions. Word has length 75 [2019-11-15 22:51:16,293 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:16,293 INFO L462 AbstractCegarLoop]: Abstraction has 876 states and 1170 transitions. [2019-11-15 22:51:16,293 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:51:16,293 INFO L276 IsEmpty]: Start isEmpty. Operand 876 states and 1170 transitions. [2019-11-15 22:51:16,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-15 22:51:16,294 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:16,295 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:16,295 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:16,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:16,295 INFO L82 PathProgramCache]: Analyzing trace with hash -216337278, now seen corresponding path program 1 times [2019-11-15 22:51:16,296 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:16,296 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027024853] [2019-11-15 22:51:16,296 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:16,296 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:16,296 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:16,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:16,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:16,347 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027024853] [2019-11-15 22:51:16,347 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:16,347 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:16,347 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [109943006] [2019-11-15 22:51:16,348 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 22:51:16,348 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:16,348 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 22:51:16,348 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:16,348 INFO L87 Difference]: Start difference. First operand 876 states and 1170 transitions. Second operand 4 states. [2019-11-15 22:51:16,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:16,592 INFO L93 Difference]: Finished difference Result 2038 states and 2720 transitions. [2019-11-15 22:51:16,593 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:51:16,593 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-11-15 22:51:16,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:16,602 INFO L225 Difference]: With dead ends: 2038 [2019-11-15 22:51:16,602 INFO L226 Difference]: Without dead ends: 1463 [2019-11-15 22:51:16,604 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:16,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1463 states. [2019-11-15 22:51:16,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1463 to 1168. [2019-11-15 22:51:16,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1168 states. [2019-11-15 22:51:16,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1168 states to 1168 states and 1550 transitions. [2019-11-15 22:51:16,736 INFO L78 Accepts]: Start accepts. Automaton has 1168 states and 1550 transitions. Word has length 75 [2019-11-15 22:51:16,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:16,736 INFO L462 AbstractCegarLoop]: Abstraction has 1168 states and 1550 transitions. [2019-11-15 22:51:16,736 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 22:51:16,737 INFO L276 IsEmpty]: Start isEmpty. Operand 1168 states and 1550 transitions. [2019-11-15 22:51:16,738 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-11-15 22:51:16,738 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:16,738 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:16,739 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:16,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:16,740 INFO L82 PathProgramCache]: Analyzing trace with hash -1065252519, now seen corresponding path program 1 times [2019-11-15 22:51:16,740 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:16,740 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973462656] [2019-11-15 22:51:16,740 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:16,740 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:16,741 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:16,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:16,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:16,774 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973462656] [2019-11-15 22:51:16,774 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:16,774 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:51:16,774 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [344887290] [2019-11-15 22:51:16,775 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:51:16,775 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:16,776 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:51:16,776 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:16,776 INFO L87 Difference]: Start difference. First operand 1168 states and 1550 transitions. Second operand 3 states. [2019-11-15 22:51:17,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:17,080 INFO L93 Difference]: Finished difference Result 2879 states and 3814 transitions. [2019-11-15 22:51:17,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:51:17,081 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2019-11-15 22:51:17,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:17,090 INFO L225 Difference]: With dead ends: 2879 [2019-11-15 22:51:17,091 INFO L226 Difference]: Without dead ends: 1954 [2019-11-15 22:51:17,094 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:51:17,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1954 states. [2019-11-15 22:51:17,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1954 to 1170. [2019-11-15 22:51:17,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1170 states. [2019-11-15 22:51:17,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1552 transitions. [2019-11-15 22:51:17,204 INFO L78 Accepts]: Start accepts. Automaton has 1170 states and 1552 transitions. Word has length 76 [2019-11-15 22:51:17,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:17,205 INFO L462 AbstractCegarLoop]: Abstraction has 1170 states and 1552 transitions. [2019-11-15 22:51:17,205 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:51:17,205 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1552 transitions. [2019-11-15 22:51:17,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2019-11-15 22:51:17,207 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:17,207 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:17,207 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:17,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:17,208 INFO L82 PathProgramCache]: Analyzing trace with hash -2019206059, now seen corresponding path program 1 times [2019-11-15 22:51:17,208 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:17,208 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2521933] [2019-11-15 22:51:17,208 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:17,208 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:17,209 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:17,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:17,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:17,287 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2521933] [2019-11-15 22:51:17,287 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:17,287 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:17,287 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743597329] [2019-11-15 22:51:17,288 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 22:51:17,288 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:17,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 22:51:17,289 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:17,289 INFO L87 Difference]: Start difference. First operand 1170 states and 1552 transitions. Second operand 4 states. [2019-11-15 22:51:17,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:17,545 INFO L93 Difference]: Finished difference Result 2434 states and 3222 transitions. [2019-11-15 22:51:17,545 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:51:17,546 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 77 [2019-11-15 22:51:17,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:17,553 INFO L225 Difference]: With dead ends: 2434 [2019-11-15 22:51:17,554 INFO L226 Difference]: Without dead ends: 1321 [2019-11-15 22:51:17,556 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:17,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1321 states. [2019-11-15 22:51:17,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1321 to 975. [2019-11-15 22:51:17,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 975 states. [2019-11-15 22:51:17,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 975 states to 975 states and 1288 transitions. [2019-11-15 22:51:17,777 INFO L78 Accepts]: Start accepts. Automaton has 975 states and 1288 transitions. Word has length 77 [2019-11-15 22:51:17,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:17,777 INFO L462 AbstractCegarLoop]: Abstraction has 975 states and 1288 transitions. [2019-11-15 22:51:17,778 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 22:51:17,778 INFO L276 IsEmpty]: Start isEmpty. Operand 975 states and 1288 transitions. [2019-11-15 22:51:17,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2019-11-15 22:51:17,779 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:17,779 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:17,780 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:17,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:17,780 INFO L82 PathProgramCache]: Analyzing trace with hash -113428458, now seen corresponding path program 1 times [2019-11-15 22:51:17,780 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:17,781 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [813324264] [2019-11-15 22:51:17,781 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:17,781 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:17,781 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:17,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:17,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:17,870 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [813324264] [2019-11-15 22:51:17,870 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:17,870 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:17,870 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1631686502] [2019-11-15 22:51:17,871 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 22:51:17,871 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:17,872 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 22:51:17,872 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:17,872 INFO L87 Difference]: Start difference. First operand 975 states and 1288 transitions. Second operand 4 states. [2019-11-15 22:51:18,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:18,073 INFO L93 Difference]: Finished difference Result 2239 states and 2968 transitions. [2019-11-15 22:51:18,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:51:18,074 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 78 [2019-11-15 22:51:18,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:18,080 INFO L225 Difference]: With dead ends: 2239 [2019-11-15 22:51:18,081 INFO L226 Difference]: Without dead ends: 1341 [2019-11-15 22:51:18,082 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:18,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1341 states. [2019-11-15 22:51:18,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1341 to 919. [2019-11-15 22:51:18,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 919 states. [2019-11-15 22:51:18,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 919 states to 919 states and 1208 transitions. [2019-11-15 22:51:18,186 INFO L78 Accepts]: Start accepts. Automaton has 919 states and 1208 transitions. Word has length 78 [2019-11-15 22:51:18,186 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:18,187 INFO L462 AbstractCegarLoop]: Abstraction has 919 states and 1208 transitions. [2019-11-15 22:51:18,187 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 22:51:18,187 INFO L276 IsEmpty]: Start isEmpty. Operand 919 states and 1208 transitions. [2019-11-15 22:51:18,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2019-11-15 22:51:18,189 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:18,190 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:18,190 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:18,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:18,190 INFO L82 PathProgramCache]: Analyzing trace with hash 691547713, now seen corresponding path program 1 times [2019-11-15 22:51:18,191 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:18,191 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563868826] [2019-11-15 22:51:18,191 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:18,191 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:18,191 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:18,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:18,581 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:18,581 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563868826] [2019-11-15 22:51:18,581 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1926919092] [2019-11-15 22:51:18,582 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:18,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:18,804 INFO L256 TraceCheckSpWp]: Trace formula consists of 723 conjuncts, 9 conjunts are in the unsatisfiable core [2019-11-15 22:51:18,823 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:51:18,934 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-15 22:51:18,935 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 22:51:18,935 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-15 22:51:18,935 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259877799] [2019-11-15 22:51:18,936 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:18,936 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:18,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:18,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-15 22:51:18,937 INFO L87 Difference]: Start difference. First operand 919 states and 1208 transitions. Second operand 6 states. [2019-11-15 22:51:19,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:19,342 INFO L93 Difference]: Finished difference Result 2830 states and 3892 transitions. [2019-11-15 22:51:19,342 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-15 22:51:19,342 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 121 [2019-11-15 22:51:19,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:19,364 INFO L225 Difference]: With dead ends: 2830 [2019-11-15 22:51:19,365 INFO L226 Difference]: Without dead ends: 2058 [2019-11-15 22:51:19,367 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 118 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-11-15 22:51:19,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2058 states. [2019-11-15 22:51:19,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2058 to 919. [2019-11-15 22:51:19,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 919 states. [2019-11-15 22:51:19,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 919 states to 919 states and 1205 transitions. [2019-11-15 22:51:19,517 INFO L78 Accepts]: Start accepts. Automaton has 919 states and 1205 transitions. Word has length 121 [2019-11-15 22:51:19,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:19,518 INFO L462 AbstractCegarLoop]: Abstraction has 919 states and 1205 transitions. [2019-11-15 22:51:19,518 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:19,518 INFO L276 IsEmpty]: Start isEmpty. Operand 919 states and 1205 transitions. [2019-11-15 22:51:19,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2019-11-15 22:51:19,524 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:19,524 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:19,730 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:19,731 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:19,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:19,732 INFO L82 PathProgramCache]: Analyzing trace with hash 344042918, now seen corresponding path program 1 times [2019-11-15 22:51:19,732 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:19,732 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1546677636] [2019-11-15 22:51:19,733 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:19,733 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:19,733 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:19,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:20,079 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:20,080 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1546677636] [2019-11-15 22:51:20,080 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [899989148] [2019-11-15 22:51:20,081 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:20,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:20,350 INFO L256 TraceCheckSpWp]: Trace formula consists of 736 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-15 22:51:20,356 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:51:20,514 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-15 22:51:20,514 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 22:51:20,515 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-15 22:51:20,515 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148346487] [2019-11-15 22:51:20,515 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:20,516 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:20,516 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:20,516 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-15 22:51:20,517 INFO L87 Difference]: Start difference. First operand 919 states and 1205 transitions. Second operand 6 states. [2019-11-15 22:51:20,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:20,963 INFO L93 Difference]: Finished difference Result 2537 states and 3445 transitions. [2019-11-15 22:51:20,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-15 22:51:20,963 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 125 [2019-11-15 22:51:20,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:20,980 INFO L225 Difference]: With dead ends: 2537 [2019-11-15 22:51:20,980 INFO L226 Difference]: Without dead ends: 1765 [2019-11-15 22:51:20,982 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 141 GetRequests, 122 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-11-15 22:51:20,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1765 states. [2019-11-15 22:51:21,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1765 to 919. [2019-11-15 22:51:21,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 919 states. [2019-11-15 22:51:21,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 919 states to 919 states and 1202 transitions. [2019-11-15 22:51:21,111 INFO L78 Accepts]: Start accepts. Automaton has 919 states and 1202 transitions. Word has length 125 [2019-11-15 22:51:21,112 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:21,112 INFO L462 AbstractCegarLoop]: Abstraction has 919 states and 1202 transitions. [2019-11-15 22:51:21,112 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:21,112 INFO L276 IsEmpty]: Start isEmpty. Operand 919 states and 1202 transitions. [2019-11-15 22:51:21,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2019-11-15 22:51:21,115 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:21,116 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:21,321 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:21,321 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:21,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:21,322 INFO L82 PathProgramCache]: Analyzing trace with hash 1182819496, now seen corresponding path program 1 times [2019-11-15 22:51:21,322 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:21,322 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875900935] [2019-11-15 22:51:21,323 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:21,323 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:21,323 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:21,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:21,694 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:21,694 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1875900935] [2019-11-15 22:51:21,694 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1938159851] [2019-11-15 22:51:21,695 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:21,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:21,906 INFO L256 TraceCheckSpWp]: Trace formula consists of 748 conjuncts, 12 conjunts are in the unsatisfiable core [2019-11-15 22:51:21,912 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:51:22,037 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-15 22:51:22,038 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 22:51:22,038 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-15 22:51:22,038 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [340859242] [2019-11-15 22:51:22,039 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:22,039 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:22,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:22,040 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-15 22:51:22,040 INFO L87 Difference]: Start difference. First operand 919 states and 1202 transitions. Second operand 6 states. [2019-11-15 22:51:22,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:22,672 INFO L93 Difference]: Finished difference Result 2921 states and 3998 transitions. [2019-11-15 22:51:22,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-15 22:51:22,673 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 128 [2019-11-15 22:51:22,673 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:22,678 INFO L225 Difference]: With dead ends: 2921 [2019-11-15 22:51:22,678 INFO L226 Difference]: Without dead ends: 2136 [2019-11-15 22:51:22,683 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 128 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2019-11-15 22:51:22,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2136 states. [2019-11-15 22:51:22,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2136 to 867. [2019-11-15 22:51:22,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 867 states. [2019-11-15 22:51:22,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 867 states to 867 states and 1124 transitions. [2019-11-15 22:51:22,840 INFO L78 Accepts]: Start accepts. Automaton has 867 states and 1124 transitions. Word has length 128 [2019-11-15 22:51:22,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:22,841 INFO L462 AbstractCegarLoop]: Abstraction has 867 states and 1124 transitions. [2019-11-15 22:51:22,841 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:22,841 INFO L276 IsEmpty]: Start isEmpty. Operand 867 states and 1124 transitions. [2019-11-15 22:51:22,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2019-11-15 22:51:22,845 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:22,846 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:23,055 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:23,056 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:23,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:23,056 INFO L82 PathProgramCache]: Analyzing trace with hash 677857235, now seen corresponding path program 1 times [2019-11-15 22:51:23,056 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:23,057 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272591971] [2019-11-15 22:51:23,057 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:23,057 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:23,057 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:23,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:23,361 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:23,361 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272591971] [2019-11-15 22:51:23,362 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1488564235] [2019-11-15 22:51:23,362 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:23,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:23,550 INFO L256 TraceCheckSpWp]: Trace formula consists of 749 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-15 22:51:23,560 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:51:23,765 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-15 22:51:23,765 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 22:51:23,765 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 13 [2019-11-15 22:51:23,765 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1759203534] [2019-11-15 22:51:23,766 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:23,766 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:23,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:23,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2019-11-15 22:51:23,767 INFO L87 Difference]: Start difference. First operand 867 states and 1124 transitions. Second operand 6 states. [2019-11-15 22:51:24,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:24,260 INFO L93 Difference]: Finished difference Result 2253 states and 3058 transitions. [2019-11-15 22:51:24,261 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-15 22:51:24,261 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 129 [2019-11-15 22:51:24,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:24,265 INFO L225 Difference]: With dead ends: 2253 [2019-11-15 22:51:24,265 INFO L226 Difference]: Without dead ends: 1547 [2019-11-15 22:51:24,267 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 141 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=44, Invalid=228, Unknown=0, NotChecked=0, Total=272 [2019-11-15 22:51:24,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1547 states. [2019-11-15 22:51:24,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1547 to 867. [2019-11-15 22:51:24,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 867 states. [2019-11-15 22:51:24,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 867 states to 867 states and 1123 transitions. [2019-11-15 22:51:24,398 INFO L78 Accepts]: Start accepts. Automaton has 867 states and 1123 transitions. Word has length 129 [2019-11-15 22:51:24,399 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:24,399 INFO L462 AbstractCegarLoop]: Abstraction has 867 states and 1123 transitions. [2019-11-15 22:51:24,399 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:24,399 INFO L276 IsEmpty]: Start isEmpty. Operand 867 states and 1123 transitions. [2019-11-15 22:51:24,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-15 22:51:24,401 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:24,402 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:24,606 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:24,615 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:24,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:24,615 INFO L82 PathProgramCache]: Analyzing trace with hash 960872696, now seen corresponding path program 1 times [2019-11-15 22:51:24,615 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:24,615 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528656784] [2019-11-15 22:51:24,616 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:24,616 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:24,616 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:24,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:24,930 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:24,930 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528656784] [2019-11-15 22:51:24,930 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1730442890] [2019-11-15 22:51:24,930 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:25,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:25,147 INFO L256 TraceCheckSpWp]: Trace formula consists of 763 conjuncts, 45 conjunts are in the unsatisfiable core [2019-11-15 22:51:25,151 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:51:25,568 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:25,568 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 22:51:25,569 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-11-15 22:51:25,569 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204471352] [2019-11-15 22:51:25,570 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-15 22:51:25,571 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:25,571 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-15 22:51:25,571 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=354, Unknown=0, NotChecked=0, Total=420 [2019-11-15 22:51:25,572 INFO L87 Difference]: Start difference. First operand 867 states and 1123 transitions. Second operand 21 states. [2019-11-15 22:51:28,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:28,244 INFO L93 Difference]: Finished difference Result 2300 states and 3037 transitions. [2019-11-15 22:51:28,246 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-11-15 22:51:28,246 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 133 [2019-11-15 22:51:28,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:28,249 INFO L225 Difference]: With dead ends: 2300 [2019-11-15 22:51:28,250 INFO L226 Difference]: Without dead ends: 1600 [2019-11-15 22:51:28,252 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 119 SyntacticMatches, 4 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 392 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=376, Invalid=1516, Unknown=0, NotChecked=0, Total=1892 [2019-11-15 22:51:28,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1600 states. [2019-11-15 22:51:28,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1600 to 1035. [2019-11-15 22:51:28,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1035 states. [2019-11-15 22:51:28,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1035 states to 1035 states and 1337 transitions. [2019-11-15 22:51:28,441 INFO L78 Accepts]: Start accepts. Automaton has 1035 states and 1337 transitions. Word has length 133 [2019-11-15 22:51:28,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:28,441 INFO L462 AbstractCegarLoop]: Abstraction has 1035 states and 1337 transitions. [2019-11-15 22:51:28,441 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-15 22:51:28,441 INFO L276 IsEmpty]: Start isEmpty. Operand 1035 states and 1337 transitions. [2019-11-15 22:51:28,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-15 22:51:28,444 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:28,444 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:28,648 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:28,649 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:28,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:28,649 INFO L82 PathProgramCache]: Analyzing trace with hash -905835978, now seen corresponding path program 1 times [2019-11-15 22:51:28,649 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:28,649 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699060291] [2019-11-15 22:51:28,650 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:28,650 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:28,650 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:28,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:28,740 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-15 22:51:28,740 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [699060291] [2019-11-15 22:51:28,741 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:28,741 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:28,741 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2059916596] [2019-11-15 22:51:28,742 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 22:51:28,742 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:28,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 22:51:28,743 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:28,743 INFO L87 Difference]: Start difference. First operand 1035 states and 1337 transitions. Second operand 4 states. [2019-11-15 22:51:29,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:29,097 INFO L93 Difference]: Finished difference Result 2508 states and 3266 transitions. [2019-11-15 22:51:29,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:51:29,098 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 133 [2019-11-15 22:51:29,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:29,101 INFO L225 Difference]: With dead ends: 2508 [2019-11-15 22:51:29,101 INFO L226 Difference]: Without dead ends: 1605 [2019-11-15 22:51:29,104 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:29,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1605 states. [2019-11-15 22:51:29,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1605 to 1067. [2019-11-15 22:51:29,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1067 states. [2019-11-15 22:51:29,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1067 states to 1067 states and 1365 transitions. [2019-11-15 22:51:29,258 INFO L78 Accepts]: Start accepts. Automaton has 1067 states and 1365 transitions. Word has length 133 [2019-11-15 22:51:29,259 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:29,259 INFO L462 AbstractCegarLoop]: Abstraction has 1067 states and 1365 transitions. [2019-11-15 22:51:29,259 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 22:51:29,259 INFO L276 IsEmpty]: Start isEmpty. Operand 1067 states and 1365 transitions. [2019-11-15 22:51:29,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-15 22:51:29,262 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:29,262 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:29,262 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:29,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:29,263 INFO L82 PathProgramCache]: Analyzing trace with hash -914742478, now seen corresponding path program 1 times [2019-11-15 22:51:29,263 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:29,263 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763136848] [2019-11-15 22:51:29,264 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:29,264 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:29,264 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:29,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:29,410 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-15 22:51:29,410 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763136848] [2019-11-15 22:51:29,410 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:29,410 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:29,411 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593505124] [2019-11-15 22:51:29,411 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:51:29,411 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:29,412 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:51:29,412 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:29,412 INFO L87 Difference]: Start difference. First operand 1067 states and 1365 transitions. Second operand 5 states. [2019-11-15 22:51:29,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:29,700 INFO L93 Difference]: Finished difference Result 1927 states and 2501 transitions. [2019-11-15 22:51:29,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:51:29,701 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 133 [2019-11-15 22:51:29,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:29,703 INFO L225 Difference]: With dead ends: 1927 [2019-11-15 22:51:29,703 INFO L226 Difference]: Without dead ends: 992 [2019-11-15 22:51:29,707 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:51:29,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 992 states. [2019-11-15 22:51:29,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 992 to 992. [2019-11-15 22:51:29,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 992 states. [2019-11-15 22:51:29,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 992 states to 992 states and 1276 transitions. [2019-11-15 22:51:29,857 INFO L78 Accepts]: Start accepts. Automaton has 992 states and 1276 transitions. Word has length 133 [2019-11-15 22:51:29,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:29,858 INFO L462 AbstractCegarLoop]: Abstraction has 992 states and 1276 transitions. [2019-11-15 22:51:29,858 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:51:29,858 INFO L276 IsEmpty]: Start isEmpty. Operand 992 states and 1276 transitions. [2019-11-15 22:51:29,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-15 22:51:29,860 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:29,860 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:29,861 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:29,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:29,861 INFO L82 PathProgramCache]: Analyzing trace with hash 219147919, now seen corresponding path program 1 times [2019-11-15 22:51:29,861 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:29,861 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369651683] [2019-11-15 22:51:29,862 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:29,862 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:29,862 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:29,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:30,132 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 26 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:30,132 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369651683] [2019-11-15 22:51:30,133 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [282604906] [2019-11-15 22:51:30,133 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:30,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:30,357 INFO L256 TraceCheckSpWp]: Trace formula consists of 764 conjuncts, 47 conjunts are in the unsatisfiable core [2019-11-15 22:51:30,360 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:51:30,718 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 26 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:30,719 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 22:51:30,719 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-11-15 22:51:30,719 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [995189712] [2019-11-15 22:51:30,719 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-15 22:51:30,720 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:30,720 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-15 22:51:30,720 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2019-11-15 22:51:30,720 INFO L87 Difference]: Start difference. First operand 992 states and 1276 transitions. Second operand 21 states. [2019-11-15 22:51:34,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:34,081 INFO L93 Difference]: Finished difference Result 2980 states and 3873 transitions. [2019-11-15 22:51:34,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2019-11-15 22:51:34,082 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 134 [2019-11-15 22:51:34,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:34,085 INFO L225 Difference]: With dead ends: 2980 [2019-11-15 22:51:34,086 INFO L226 Difference]: Without dead ends: 2175 [2019-11-15 22:51:34,089 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 194 GetRequests, 120 SyntacticMatches, 4 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1431 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=927, Invalid=4185, Unknown=0, NotChecked=0, Total=5112 [2019-11-15 22:51:34,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2175 states. [2019-11-15 22:51:34,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2175 to 1178. [2019-11-15 22:51:34,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1178 states. [2019-11-15 22:51:34,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1178 states to 1178 states and 1510 transitions. [2019-11-15 22:51:34,291 INFO L78 Accepts]: Start accepts. Automaton has 1178 states and 1510 transitions. Word has length 134 [2019-11-15 22:51:34,291 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:34,291 INFO L462 AbstractCegarLoop]: Abstraction has 1178 states and 1510 transitions. [2019-11-15 22:51:34,291 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-15 22:51:34,292 INFO L276 IsEmpty]: Start isEmpty. Operand 1178 states and 1510 transitions. [2019-11-15 22:51:34,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-15 22:51:34,294 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:34,294 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:34,499 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:34,499 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:34,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:34,501 INFO L82 PathProgramCache]: Analyzing trace with hash -1087994479, now seen corresponding path program 1 times [2019-11-15 22:51:34,501 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:34,501 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162726817] [2019-11-15 22:51:34,501 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:34,501 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:34,502 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:34,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:34,557 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-15 22:51:34,558 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [162726817] [2019-11-15 22:51:34,558 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:34,558 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:34,558 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371486805] [2019-11-15 22:51:34,559 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 22:51:34,559 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:34,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 22:51:34,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:34,560 INFO L87 Difference]: Start difference. First operand 1178 states and 1510 transitions. Second operand 4 states. [2019-11-15 22:51:34,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:34,828 INFO L93 Difference]: Finished difference Result 2062 states and 2671 transitions. [2019-11-15 22:51:34,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-15 22:51:34,829 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 134 [2019-11-15 22:51:34,829 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:34,831 INFO L225 Difference]: With dead ends: 2062 [2019-11-15 22:51:34,831 INFO L226 Difference]: Without dead ends: 1014 [2019-11-15 22:51:34,833 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:34,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1014 states. [2019-11-15 22:51:34,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1014 to 1014. [2019-11-15 22:51:34,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1014 states. [2019-11-15 22:51:34,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1014 states to 1014 states and 1292 transitions. [2019-11-15 22:51:34,998 INFO L78 Accepts]: Start accepts. Automaton has 1014 states and 1292 transitions. Word has length 134 [2019-11-15 22:51:34,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:34,998 INFO L462 AbstractCegarLoop]: Abstraction has 1014 states and 1292 transitions. [2019-11-15 22:51:34,998 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 22:51:34,999 INFO L276 IsEmpty]: Start isEmpty. Operand 1014 states and 1292 transitions. [2019-11-15 22:51:35,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-15 22:51:35,001 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:35,001 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:35,002 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:35,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:35,002 INFO L82 PathProgramCache]: Analyzing trace with hash 440475699, now seen corresponding path program 1 times [2019-11-15 22:51:35,002 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:35,003 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36452156] [2019-11-15 22:51:35,003 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:35,003 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:35,003 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:35,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:35,254 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:35,255 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [36452156] [2019-11-15 22:51:35,255 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [861960966] [2019-11-15 22:51:35,255 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:35,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:35,457 INFO L256 TraceCheckSpWp]: Trace formula consists of 765 conjuncts, 31 conjunts are in the unsatisfiable core [2019-11-15 22:51:35,460 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:51:35,782 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:35,782 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 22:51:35,783 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 11] total 17 [2019-11-15 22:51:35,783 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [98650236] [2019-11-15 22:51:35,784 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-11-15 22:51:35,784 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:35,784 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-11-15 22:51:35,784 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=239, Unknown=0, NotChecked=0, Total=306 [2019-11-15 22:51:35,785 INFO L87 Difference]: Start difference. First operand 1014 states and 1292 transitions. Second operand 18 states. [2019-11-15 22:51:38,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:38,647 INFO L93 Difference]: Finished difference Result 4336 states and 5610 transitions. [2019-11-15 22:51:38,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-11-15 22:51:38,648 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 135 [2019-11-15 22:51:38,648 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:38,655 INFO L225 Difference]: With dead ends: 4336 [2019-11-15 22:51:38,656 INFO L226 Difference]: Without dead ends: 3509 [2019-11-15 22:51:38,660 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 189 GetRequests, 123 SyntacticMatches, 3 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1399 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=942, Invalid=3218, Unknown=0, NotChecked=0, Total=4160 [2019-11-15 22:51:38,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3509 states. [2019-11-15 22:51:38,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3509 to 1471. [2019-11-15 22:51:38,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1471 states. [2019-11-15 22:51:38,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1471 states to 1471 states and 1889 transitions. [2019-11-15 22:51:38,939 INFO L78 Accepts]: Start accepts. Automaton has 1471 states and 1889 transitions. Word has length 135 [2019-11-15 22:51:38,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:38,939 INFO L462 AbstractCegarLoop]: Abstraction has 1471 states and 1889 transitions. [2019-11-15 22:51:38,939 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-11-15 22:51:38,940 INFO L276 IsEmpty]: Start isEmpty. Operand 1471 states and 1889 transitions. [2019-11-15 22:51:38,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-15 22:51:38,942 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:38,943 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:39,147 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:39,147 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:39,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:39,147 INFO L82 PathProgramCache]: Analyzing trace with hash -416406862, now seen corresponding path program 1 times [2019-11-15 22:51:39,147 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:39,148 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942901938] [2019-11-15 22:51:39,148 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:39,148 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:39,148 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:39,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:39,455 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:39,456 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942901938] [2019-11-15 22:51:39,456 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2139412809] [2019-11-15 22:51:39,456 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:39,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:39,662 INFO L256 TraceCheckSpWp]: Trace formula consists of 775 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-15 22:51:39,664 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:51:39,743 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-15 22:51:39,744 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 22:51:39,744 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-15 22:51:39,744 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992336516] [2019-11-15 22:51:39,745 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:39,745 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:39,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:39,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-15 22:51:39,746 INFO L87 Difference]: Start difference. First operand 1471 states and 1889 transitions. Second operand 6 states. [2019-11-15 22:51:40,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:40,441 INFO L93 Difference]: Finished difference Result 4365 states and 5753 transitions. [2019-11-15 22:51:40,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-15 22:51:40,441 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 136 [2019-11-15 22:51:40,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:40,450 INFO L225 Difference]: With dead ends: 4365 [2019-11-15 22:51:40,450 INFO L226 Difference]: Without dead ends: 3228 [2019-11-15 22:51:40,453 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 152 GetRequests, 133 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-11-15 22:51:40,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3228 states. [2019-11-15 22:51:40,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3228 to 1471. [2019-11-15 22:51:40,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1471 states. [2019-11-15 22:51:40,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1471 states to 1471 states and 1887 transitions. [2019-11-15 22:51:40,778 INFO L78 Accepts]: Start accepts. Automaton has 1471 states and 1887 transitions. Word has length 136 [2019-11-15 22:51:40,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:40,778 INFO L462 AbstractCegarLoop]: Abstraction has 1471 states and 1887 transitions. [2019-11-15 22:51:40,778 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:40,778 INFO L276 IsEmpty]: Start isEmpty. Operand 1471 states and 1887 transitions. [2019-11-15 22:51:40,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-15 22:51:40,780 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:40,781 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:40,985 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:40,985 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:40,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:40,986 INFO L82 PathProgramCache]: Analyzing trace with hash -330077116, now seen corresponding path program 1 times [2019-11-15 22:51:40,986 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:40,986 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831592374] [2019-11-15 22:51:40,986 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:40,986 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:40,987 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:41,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:41,119 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-15 22:51:41,120 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1831592374] [2019-11-15 22:51:41,120 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:41,121 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 22:51:41,121 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011450284] [2019-11-15 22:51:41,122 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:41,123 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:41,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:41,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 22:51:41,123 INFO L87 Difference]: Start difference. First operand 1471 states and 1887 transitions. Second operand 6 states. [2019-11-15 22:51:42,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:42,559 INFO L93 Difference]: Finished difference Result 7797 states and 10159 transitions. [2019-11-15 22:51:42,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-11-15 22:51:42,574 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 136 [2019-11-15 22:51:42,574 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:42,585 INFO L225 Difference]: With dead ends: 7797 [2019-11-15 22:51:42,585 INFO L226 Difference]: Without dead ends: 6513 [2019-11-15 22:51:42,589 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2019-11-15 22:51:42,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6513 states. [2019-11-15 22:51:42,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6513 to 1841. [2019-11-15 22:51:42,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1841 states. [2019-11-15 22:51:42,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1841 states to 1841 states and 2319 transitions. [2019-11-15 22:51:42,974 INFO L78 Accepts]: Start accepts. Automaton has 1841 states and 2319 transitions. Word has length 136 [2019-11-15 22:51:42,975 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:42,975 INFO L462 AbstractCegarLoop]: Abstraction has 1841 states and 2319 transitions. [2019-11-15 22:51:42,975 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:42,975 INFO L276 IsEmpty]: Start isEmpty. Operand 1841 states and 2319 transitions. [2019-11-15 22:51:42,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2019-11-15 22:51:42,978 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:42,978 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:42,979 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:42,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:42,979 INFO L82 PathProgramCache]: Analyzing trace with hash 633057662, now seen corresponding path program 1 times [2019-11-15 22:51:42,981 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:42,982 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346847057] [2019-11-15 22:51:42,982 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:42,982 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:42,982 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:43,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:43,324 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:43,324 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [346847057] [2019-11-15 22:51:43,324 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2009011441] [2019-11-15 22:51:43,324 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:43,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:43,495 INFO L256 TraceCheckSpWp]: Trace formula consists of 787 conjuncts, 14 conjunts are in the unsatisfiable core [2019-11-15 22:51:43,497 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:51:43,586 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 8 proven. 33 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:43,587 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 22:51:43,587 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 7] total 17 [2019-11-15 22:51:43,587 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126776567] [2019-11-15 22:51:43,587 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-11-15 22:51:43,588 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:43,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-11-15 22:51:43,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-11-15 22:51:43,588 INFO L87 Difference]: Start difference. First operand 1841 states and 2319 transitions. Second operand 17 states. [2019-11-15 22:51:52,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:52,629 INFO L93 Difference]: Finished difference Result 9713 states and 12603 transitions. [2019-11-15 22:51:52,629 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 147 states. [2019-11-15 22:51:52,629 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 139 [2019-11-15 22:51:52,630 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:52,639 INFO L225 Difference]: With dead ends: 9713 [2019-11-15 22:51:52,640 INFO L226 Difference]: Without dead ends: 8254 [2019-11-15 22:51:52,651 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 320 GetRequests, 161 SyntacticMatches, 0 SemanticMatches, 159 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10632 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=4619, Invalid=21141, Unknown=0, NotChecked=0, Total=25760 [2019-11-15 22:51:52,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8254 states. [2019-11-15 22:51:53,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8254 to 2444. [2019-11-15 22:51:53,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2444 states. [2019-11-15 22:51:53,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2444 states to 2444 states and 3084 transitions. [2019-11-15 22:51:53,172 INFO L78 Accepts]: Start accepts. Automaton has 2444 states and 3084 transitions. Word has length 139 [2019-11-15 22:51:53,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:53,172 INFO L462 AbstractCegarLoop]: Abstraction has 2444 states and 3084 transitions. [2019-11-15 22:51:53,172 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-11-15 22:51:53,173 INFO L276 IsEmpty]: Start isEmpty. Operand 2444 states and 3084 transitions. [2019-11-15 22:51:53,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2019-11-15 22:51:53,175 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:53,176 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:53,380 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:53,382 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:53,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:53,382 INFO L82 PathProgramCache]: Analyzing trace with hash -1379305215, now seen corresponding path program 1 times [2019-11-15 22:51:53,382 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:53,383 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804256067] [2019-11-15 22:51:53,383 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:53,383 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:53,383 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:53,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:53,531 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:53,532 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [804256067] [2019-11-15 22:51:53,532 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1362613045] [2019-11-15 22:51:53,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:53,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:53,777 INFO L256 TraceCheckSpWp]: Trace formula consists of 769 conjuncts, 18 conjunts are in the unsatisfiable core [2019-11-15 22:51:53,781 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:51:53,818 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:51:53,819 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 22:51:53,819 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 8 [2019-11-15 22:51:53,819 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [157800197] [2019-11-15 22:51:53,820 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-11-15 22:51:53,820 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:53,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-15 22:51:53,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-11-15 22:51:53,821 INFO L87 Difference]: Start difference. First operand 2444 states and 3084 transitions. Second operand 8 states. [2019-11-15 22:51:55,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:55,202 INFO L93 Difference]: Finished difference Result 9037 states and 11497 transitions. [2019-11-15 22:51:55,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-11-15 22:51:55,203 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 139 [2019-11-15 22:51:55,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:55,209 INFO L225 Difference]: With dead ends: 9037 [2019-11-15 22:51:55,209 INFO L226 Difference]: Without dead ends: 6843 [2019-11-15 22:51:55,212 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=129, Invalid=423, Unknown=0, NotChecked=0, Total=552 [2019-11-15 22:51:55,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6843 states. [2019-11-15 22:51:55,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6843 to 3832. [2019-11-15 22:51:55,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3832 states. [2019-11-15 22:51:55,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3832 states to 3832 states and 4851 transitions. [2019-11-15 22:51:55,833 INFO L78 Accepts]: Start accepts. Automaton has 3832 states and 4851 transitions. Word has length 139 [2019-11-15 22:51:55,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:55,833 INFO L462 AbstractCegarLoop]: Abstraction has 3832 states and 4851 transitions. [2019-11-15 22:51:55,833 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-11-15 22:51:55,833 INFO L276 IsEmpty]: Start isEmpty. Operand 3832 states and 4851 transitions. [2019-11-15 22:51:55,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2019-11-15 22:51:55,837 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:55,838 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:56,041 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:51:56,042 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:56,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:56,042 INFO L82 PathProgramCache]: Analyzing trace with hash 9988799, now seen corresponding path program 1 times [2019-11-15 22:51:56,042 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:56,042 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [576215650] [2019-11-15 22:51:56,042 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:56,042 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:56,042 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:56,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:56,099 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-15 22:51:56,099 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [576215650] [2019-11-15 22:51:56,099 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:56,100 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:56,100 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242915352] [2019-11-15 22:51:56,101 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 22:51:56,102 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:56,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 22:51:56,102 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:56,102 INFO L87 Difference]: Start difference. First operand 3832 states and 4851 transitions. Second operand 4 states. [2019-11-15 22:51:56,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:56,758 INFO L93 Difference]: Finished difference Result 6501 states and 8303 transitions. [2019-11-15 22:51:56,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-15 22:51:56,758 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 139 [2019-11-15 22:51:56,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:56,761 INFO L225 Difference]: With dead ends: 6501 [2019-11-15 22:51:56,761 INFO L226 Difference]: Without dead ends: 2919 [2019-11-15 22:51:56,764 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:56,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2919 states. [2019-11-15 22:51:57,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2919 to 2907. [2019-11-15 22:51:57,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2907 states. [2019-11-15 22:51:57,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2907 states to 2907 states and 3673 transitions. [2019-11-15 22:51:57,326 INFO L78 Accepts]: Start accepts. Automaton has 2907 states and 3673 transitions. Word has length 139 [2019-11-15 22:51:57,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:57,326 INFO L462 AbstractCegarLoop]: Abstraction has 2907 states and 3673 transitions. [2019-11-15 22:51:57,326 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 22:51:57,326 INFO L276 IsEmpty]: Start isEmpty. Operand 2907 states and 3673 transitions. [2019-11-15 22:51:57,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2019-11-15 22:51:57,329 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:57,330 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:57,330 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:57,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:57,331 INFO L82 PathProgramCache]: Analyzing trace with hash 850968806, now seen corresponding path program 1 times [2019-11-15 22:51:57,331 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:57,331 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1571348301] [2019-11-15 22:51:57,331 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:57,332 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:57,332 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:57,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:57,501 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-15 22:51:57,501 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1571348301] [2019-11-15 22:51:57,501 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:57,502 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 22:51:57,502 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1687028070] [2019-11-15 22:51:57,502 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-15 22:51:57,503 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:57,503 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-15 22:51:57,503 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-15 22:51:57,503 INFO L87 Difference]: Start difference. First operand 2907 states and 3673 transitions. Second operand 6 states. [2019-11-15 22:51:59,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:51:59,096 INFO L93 Difference]: Finished difference Result 9661 states and 12524 transitions. [2019-11-15 22:51:59,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-15 22:51:59,096 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 143 [2019-11-15 22:51:59,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:51:59,103 INFO L225 Difference]: With dead ends: 9661 [2019-11-15 22:51:59,103 INFO L226 Difference]: Without dead ends: 7191 [2019-11-15 22:51:59,107 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-15 22:51:59,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7191 states. [2019-11-15 22:51:59,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7191 to 2987. [2019-11-15 22:51:59,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2987 states. [2019-11-15 22:51:59,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2987 states to 2987 states and 3766 transitions. [2019-11-15 22:51:59,537 INFO L78 Accepts]: Start accepts. Automaton has 2987 states and 3766 transitions. Word has length 143 [2019-11-15 22:51:59,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:51:59,537 INFO L462 AbstractCegarLoop]: Abstraction has 2987 states and 3766 transitions. [2019-11-15 22:51:59,537 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-15 22:51:59,537 INFO L276 IsEmpty]: Start isEmpty. Operand 2987 states and 3766 transitions. [2019-11-15 22:51:59,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2019-11-15 22:51:59,539 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:51:59,540 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:51:59,540 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:51:59,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:51:59,540 INFO L82 PathProgramCache]: Analyzing trace with hash 1499523083, now seen corresponding path program 1 times [2019-11-15 22:51:59,540 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:51:59,541 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106846313] [2019-11-15 22:51:59,541 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:59,541 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:51:59,541 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:51:59,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:51:59,590 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-11-15 22:51:59,590 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106846313] [2019-11-15 22:51:59,591 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:51:59,591 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-15 22:51:59,591 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1809313965] [2019-11-15 22:51:59,592 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-15 22:51:59,592 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:51:59,592 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-15 22:51:59,592 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-15 22:51:59,592 INFO L87 Difference]: Start difference. First operand 2987 states and 3766 transitions. Second operand 4 states. [2019-11-15 22:52:00,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:52:00,516 INFO L93 Difference]: Finished difference Result 7420 states and 9386 transitions. [2019-11-15 22:52:00,517 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:52:00,517 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 144 [2019-11-15 22:52:00,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:52:00,520 INFO L225 Difference]: With dead ends: 7420 [2019-11-15 22:52:00,520 INFO L226 Difference]: Without dead ends: 4714 [2019-11-15 22:52:00,523 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:52:00,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4714 states. [2019-11-15 22:52:00,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4714 to 3019. [2019-11-15 22:52:00,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3019 states. [2019-11-15 22:52:00,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3019 states to 3019 states and 3790 transitions. [2019-11-15 22:52:00,977 INFO L78 Accepts]: Start accepts. Automaton has 3019 states and 3790 transitions. Word has length 144 [2019-11-15 22:52:00,977 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:52:00,977 INFO L462 AbstractCegarLoop]: Abstraction has 3019 states and 3790 transitions. [2019-11-15 22:52:00,978 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-15 22:52:00,978 INFO L276 IsEmpty]: Start isEmpty. Operand 3019 states and 3790 transitions. [2019-11-15 22:52:00,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2019-11-15 22:52:00,981 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:52:00,981 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:52:00,982 INFO L410 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:52:00,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:52:00,982 INFO L82 PathProgramCache]: Analyzing trace with hash -1504651889, now seen corresponding path program 1 times [2019-11-15 22:52:00,982 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:52:00,983 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [551576096] [2019-11-15 22:52:00,983 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:52:00,983 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:52:00,983 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:52:01,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:52:01,082 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 41 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:52:01,083 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [551576096] [2019-11-15 22:52:01,083 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1271743788] [2019-11-15 22:52:01,083 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:52:01,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:52:01,295 INFO L256 TraceCheckSpWp]: Trace formula consists of 794 conjuncts, 5 conjunts are in the unsatisfiable core [2019-11-15 22:52:01,297 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:52:01,351 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-11-15 22:52:01,351 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-15 22:52:01,352 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 10 [2019-11-15 22:52:01,352 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1040937457] [2019-11-15 22:52:01,353 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:52:01,354 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:52:01,354 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:52:01,354 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-11-15 22:52:01,354 INFO L87 Difference]: Start difference. First operand 3019 states and 3790 transitions. Second operand 5 states. [2019-11-15 22:52:02,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:52:02,103 INFO L93 Difference]: Finished difference Result 5566 states and 7031 transitions. [2019-11-15 22:52:02,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-15 22:52:02,104 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 144 [2019-11-15 22:52:02,104 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:52:02,107 INFO L225 Difference]: With dead ends: 5566 [2019-11-15 22:52:02,107 INFO L226 Difference]: Without dead ends: 2797 [2019-11-15 22:52:02,110 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 142 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-11-15 22:52:02,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2797 states. [2019-11-15 22:52:02,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2797 to 2797. [2019-11-15 22:52:02,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2797 states. [2019-11-15 22:52:02,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2797 states to 2797 states and 3527 transitions. [2019-11-15 22:52:02,548 INFO L78 Accepts]: Start accepts. Automaton has 2797 states and 3527 transitions. Word has length 144 [2019-11-15 22:52:02,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:52:02,548 INFO L462 AbstractCegarLoop]: Abstraction has 2797 states and 3527 transitions. [2019-11-15 22:52:02,548 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:52:02,548 INFO L276 IsEmpty]: Start isEmpty. Operand 2797 states and 3527 transitions. [2019-11-15 22:52:02,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2019-11-15 22:52:02,551 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:52:02,551 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:52:02,751 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:52:02,752 INFO L410 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:52:02,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:52:02,752 INFO L82 PathProgramCache]: Analyzing trace with hash -710176924, now seen corresponding path program 1 times [2019-11-15 22:52:02,752 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:52:02,752 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404041415] [2019-11-15 22:52:02,752 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:52:02,752 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:52:02,752 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:52:02,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:52:02,939 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 17 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:52:02,939 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404041415] [2019-11-15 22:52:02,939 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1199812442] [2019-11-15 22:52:02,939 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:52:03,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:52:03,111 INFO L256 TraceCheckSpWp]: Trace formula consists of 783 conjuncts, 14 conjunts are in the unsatisfiable core [2019-11-15 22:52:03,113 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 22:52:03,191 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 17 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:52:03,192 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-15 22:52:03,192 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2019-11-15 22:52:03,192 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1681871143] [2019-11-15 22:52:03,192 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-15 22:52:03,192 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:52:03,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-15 22:52:03,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-11-15 22:52:03,193 INFO L87 Difference]: Start difference. First operand 2797 states and 3527 transitions. Second operand 7 states. [2019-11-15 22:52:04,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:52:04,643 INFO L93 Difference]: Finished difference Result 8201 states and 10547 transitions. [2019-11-15 22:52:04,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-11-15 22:52:04,643 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 144 [2019-11-15 22:52:04,645 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:52:04,651 INFO L225 Difference]: With dead ends: 8201 [2019-11-15 22:52:04,651 INFO L226 Difference]: Without dead ends: 5611 [2019-11-15 22:52:04,655 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 149 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=138, Invalid=324, Unknown=0, NotChecked=0, Total=462 [2019-11-15 22:52:04,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5611 states. [2019-11-15 22:52:05,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5611 to 2797. [2019-11-15 22:52:05,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2797 states. [2019-11-15 22:52:05,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2797 states to 2797 states and 3502 transitions. [2019-11-15 22:52:05,066 INFO L78 Accepts]: Start accepts. Automaton has 2797 states and 3502 transitions. Word has length 144 [2019-11-15 22:52:05,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:52:05,066 INFO L462 AbstractCegarLoop]: Abstraction has 2797 states and 3502 transitions. [2019-11-15 22:52:05,066 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-15 22:52:05,067 INFO L276 IsEmpty]: Start isEmpty. Operand 2797 states and 3502 transitions. [2019-11-15 22:52:05,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2019-11-15 22:52:05,069 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:52:05,069 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:52:05,269 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-15 22:52:05,270 INFO L410 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:52:05,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:52:05,270 INFO L82 PathProgramCache]: Analyzing trace with hash -1523121785, now seen corresponding path program 1 times [2019-11-15 22:52:05,270 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:52:05,270 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046130552] [2019-11-15 22:52:05,271 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:52:05,271 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:52:05,271 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:52:05,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 22:52:05,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 22:52:05,514 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 22:52:05,514 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-11-15 22:52:05,773 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 15.11 10:52:05 BoogieIcfgContainer [2019-11-15 22:52:05,774 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-15 22:52:05,775 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-15 22:52:05,775 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-15 22:52:05,775 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-15 22:52:05,775 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 10:51:06" (3/4) ... [2019-11-15 22:52:05,778 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-15 22:52:06,073 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_876fd337-5bde-4b2b-9859-1528dc1ab5a5/bin/uautomizer/witness.graphml [2019-11-15 22:52:06,073 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-15 22:52:06,076 INFO L168 Benchmark]: Toolchain (without parser) took 61420.87 ms. Allocated memory was 1.0 GB in the beginning and 2.6 GB in the end (delta: 1.6 GB). Free memory was 946.1 MB in the beginning and 1.8 GB in the end (delta: -843.8 MB). Peak memory consumption was 741.1 MB. Max. memory is 11.5 GB. [2019-11-15 22:52:06,077 INFO L168 Benchmark]: CDTParser took 0.34 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-15 22:52:06,077 INFO L168 Benchmark]: CACSL2BoogieTranslator took 520.69 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 117.4 MB). Free memory was 940.7 MB in the beginning and 1.1 GB in the end (delta: -158.9 MB). Peak memory consumption was 17.9 MB. Max. memory is 11.5 GB. [2019-11-15 22:52:06,078 INFO L168 Benchmark]: Boogie Procedure Inliner took 102.03 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2019-11-15 22:52:06,078 INFO L168 Benchmark]: Boogie Preprocessor took 57.50 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2019-11-15 22:52:06,078 INFO L168 Benchmark]: RCFGBuilder took 1550.55 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 994.4 MB in the end (delta: 91.3 MB). Peak memory consumption was 91.3 MB. Max. memory is 11.5 GB. [2019-11-15 22:52:06,079 INFO L168 Benchmark]: TraceAbstraction took 58886.79 ms. Allocated memory was 1.1 GB in the beginning and 2.6 GB in the end (delta: 1.5 GB). Free memory was 994.4 MB in the beginning and 1.8 GB in the end (delta: -842.2 MB). Peak memory consumption was 625.3 MB. Max. memory is 11.5 GB. [2019-11-15 22:52:06,079 INFO L168 Benchmark]: Witness Printer took 298.94 ms. Allocated memory is still 2.6 GB. Free memory was 1.8 GB in the beginning and 1.8 GB in the end (delta: 46.7 MB). Peak memory consumption was 46.7 MB. Max. memory is 11.5 GB. [2019-11-15 22:52:06,082 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.34 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 520.69 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 117.4 MB). Free memory was 940.7 MB in the beginning and 1.1 GB in the end (delta: -158.9 MB). Peak memory consumption was 17.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 102.03 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 57.50 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1550.55 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 994.4 MB in the end (delta: 91.3 MB). Peak memory consumption was 91.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 58886.79 ms. Allocated memory was 1.1 GB in the beginning and 2.6 GB in the end (delta: 1.5 GB). Free memory was 994.4 MB in the beginning and 1.8 GB in the end (delta: -842.2 MB). Peak memory consumption was 625.3 MB. Max. memory is 11.5 GB. * Witness Printer took 298.94 ms. Allocated memory is still 2.6 GB. Free memory was 1.8 GB in the beginning and 1.8 GB in the end (delta: 46.7 MB). Peak memory consumption was 46.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 661]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L463] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L585] int c1 ; [L586] int i2 ; [L589] c1 = 0 [L590] side1Failed = __VERIFIER_nondet_bool() [L591] side2Failed = __VERIFIER_nondet_bool() [L592] side1_written = __VERIFIER_nondet_char() [L593] side2_written = __VERIFIER_nondet_char() [L594] side1Failed_History_0 = __VERIFIER_nondet_bool() [L595] side1Failed_History_1 = __VERIFIER_nondet_bool() [L596] side1Failed_History_2 = __VERIFIER_nondet_bool() [L597] side2Failed_History_0 = __VERIFIER_nondet_bool() [L598] side2Failed_History_1 = __VERIFIER_nondet_bool() [L599] side2Failed_History_2 = __VERIFIER_nondet_bool() [L600] active_side_History_0 = __VERIFIER_nondet_char() [L601] active_side_History_1 = __VERIFIER_nondet_char() [L602] active_side_History_2 = __VERIFIER_nondet_char() [L603] manual_selection_History_0 = __VERIFIER_nondet_char() [L604] manual_selection_History_1 = __VERIFIER_nondet_char() [L605] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L606] i2 = init() [L608] cs1_old = nomsg [L609] cs1_new = nomsg [L610] cs2_old = nomsg [L611] cs2_new = nomsg [L612] s1s2_old = nomsg [L613] s1s2_new = nomsg [L614] s1s1_old = nomsg [L615] s1s1_new = nomsg [L616] s2s1_old = nomsg [L617] s2s1_new = nomsg [L618] s2s2_old = nomsg [L619] s2s2_new = nomsg [L620] s1p_old = nomsg [L621] s1p_new = nomsg [L622] s2p_old = nomsg [L623] s2p_new = nomsg [L624] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE 1 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND FALSE !((int )side2 == 0) [L454] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L501] tmp___1 = read_side1_failed_history((unsigned char)1) [L502] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L503] tmp___2 = read_side1_failed_history((unsigned char)0) [L504] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L545] tmp___11 = read_side1_failed_history((unsigned char)1) [L546] COND TRUE ! tmp___11 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L547] tmp___12 = read_side2_failed_history((unsigned char)1) [L548] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L561] tmp___20 = read_active_side_history((unsigned char)2) [L562] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L580] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L659] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE 1 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L392] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L393] COND TRUE (int )side2 != (int )nomsg [L394] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND TRUE (int )side2 == 0 [L452] active_side = (int8_t )2 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND FALSE !(! tmp___0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND TRUE \read(tmp___7) [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L531] tmp___8 = read_side2_failed_history((unsigned char)1) [L532] COND TRUE ! tmp___8 [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L533] tmp___5 = read_active_side_history((unsigned char)0) [L534] COND FALSE !(! ((int )tmp___5 == 2)) [L160] COND TRUE (int )index == 0 [L161] return (side2Failed_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] tmp___6 = read_side2_failed_history((unsigned char)0) [L538] COND TRUE ! tmp___6 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L539] COND TRUE ! ((int )side2_written == 1) [L540] return (0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L659] COND TRUE ! arg VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L661] __VERIFIER_error() VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 292 locations, 23 error locations. Result: UNSAFE, OverallTime: 58.7s, OverallIterations: 46, TraceHistogramMax: 2, AutomataDifference: 36.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 20833 SDtfs, 43914 SDslu, 57800 SDs, 0 SdLazy, 11322 SolverSat, 632 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2332 GetRequests, 1687 SyntacticMatches, 25 SemanticMatches, 620 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14472 ImplicationChecksByTransitivity, 14.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3832occurred in iteration=40, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 7.5s AutomataMinimizationTime, 45 MinimizatonAttempts, 41649 StatesRemovedByMinimization, 40 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.7s SsaConstructionTime, 2.5s SatisfiabilityAnalysisTime, 6.7s InterpolantComputationTime, 6021 NumberOfCodeBlocks, 6021 NumberOfCodeBlocksAsserted, 58 NumberOfCheckSat, 5820 ConstructedInterpolants, 0 QuantifiedInterpolants, 2762353 SizeOfPredicates, 63 NumberOfNonLiveVariables, 9156 ConjunctsInSsa, 219 ConjunctsInUnsatCore, 57 InterpolantComputations, 39 PerfectInterpolantSequences, 918/1149 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...