./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5e27a879cb97b2b6600a7b4379c4e090f4fa709a ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-11-15 21:19:14,224 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-15 21:19:14,226 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-15 21:19:14,240 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-15 21:19:14,240 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-15 21:19:14,242 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-15 21:19:14,243 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-15 21:19:14,253 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-15 21:19:14,257 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-15 21:19:14,262 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-15 21:19:14,263 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-15 21:19:14,264 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-15 21:19:14,265 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-15 21:19:14,266 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-15 21:19:14,267 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-15 21:19:14,268 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-15 21:19:14,269 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-15 21:19:14,270 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-15 21:19:14,272 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-15 21:19:14,276 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-15 21:19:14,279 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-15 21:19:14,282 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-15 21:19:14,284 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-15 21:19:14,285 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-15 21:19:14,287 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-15 21:19:14,287 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-15 21:19:14,287 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-15 21:19:14,289 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-15 21:19:14,289 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-15 21:19:14,290 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-15 21:19:14,290 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-15 21:19:14,291 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-15 21:19:14,292 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-15 21:19:14,292 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-15 21:19:14,294 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-15 21:19:14,294 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-15 21:19:14,295 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-15 21:19:14,295 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-15 21:19:14,295 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-15 21:19:14,296 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-15 21:19:14,297 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-15 21:19:14,298 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-15 21:19:14,322 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-15 21:19:14,333 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-15 21:19:14,334 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-15 21:19:14,334 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-15 21:19:14,335 INFO L138 SettingsManager]: * Use SBE=true [2019-11-15 21:19:14,335 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-15 21:19:14,335 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-15 21:19:14,335 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-15 21:19:14,336 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-15 21:19:14,336 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-15 21:19:14,336 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-15 21:19:14,336 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-15 21:19:14,337 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-15 21:19:14,337 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-15 21:19:14,337 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-15 21:19:14,337 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-15 21:19:14,338 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-15 21:19:14,338 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-15 21:19:14,338 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-15 21:19:14,338 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-15 21:19:14,339 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-15 21:19:14,339 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 21:19:14,339 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-15 21:19:14,339 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-15 21:19:14,340 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-15 21:19:14,340 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-15 21:19:14,340 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-15 21:19:14,340 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-15 21:19:14,341 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5e27a879cb97b2b6600a7b4379c4e090f4fa709a [2019-11-15 21:19:14,366 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-15 21:19:14,376 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-15 21:19:14,379 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-15 21:19:14,381 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-15 21:19:14,381 INFO L275 PluginConnector]: CDTParser initialized [2019-11-15 21:19:14,382 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2019-11-15 21:19:14,434 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/data/f01e0c9ef/f204105e62844ebe95e5b38f9d1e1937/FLAG5d5e0e5be [2019-11-15 21:19:14,903 INFO L306 CDTParser]: Found 1 translation units. [2019-11-15 21:19:14,903 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2019-11-15 21:19:14,914 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/data/f01e0c9ef/f204105e62844ebe95e5b38f9d1e1937/FLAG5d5e0e5be [2019-11-15 21:19:14,927 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/data/f01e0c9ef/f204105e62844ebe95e5b38f9d1e1937 [2019-11-15 21:19:14,930 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-15 21:19:14,930 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-15 21:19:14,931 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-15 21:19:14,931 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-15 21:19:14,935 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-15 21:19:14,935 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 09:19:14" (1/1) ... [2019-11-15 21:19:14,937 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@55009174 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:14, skipping insertion in model container [2019-11-15 21:19:14,937 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 09:19:14" (1/1) ... [2019-11-15 21:19:14,944 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-15 21:19:14,983 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-15 21:19:15,259 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 21:19:15,269 INFO L188 MainTranslator]: Completed pre-run [2019-11-15 21:19:15,341 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 21:19:15,367 INFO L192 MainTranslator]: Completed translation [2019-11-15 21:19:15,368 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15 WrapperNode [2019-11-15 21:19:15,368 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-15 21:19:15,369 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-15 21:19:15,369 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-15 21:19:15,369 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-15 21:19:15,377 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15" (1/1) ... [2019-11-15 21:19:15,384 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15" (1/1) ... [2019-11-15 21:19:15,464 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-15 21:19:15,465 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-15 21:19:15,465 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-15 21:19:15,465 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-15 21:19:15,486 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15" (1/1) ... [2019-11-15 21:19:15,486 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15" (1/1) ... [2019-11-15 21:19:15,491 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15" (1/1) ... [2019-11-15 21:19:15,491 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15" (1/1) ... [2019-11-15 21:19:15,521 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15" (1/1) ... [2019-11-15 21:19:15,563 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15" (1/1) ... [2019-11-15 21:19:15,566 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15" (1/1) ... [2019-11-15 21:19:15,573 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-15 21:19:15,573 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-15 21:19:15,573 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-15 21:19:15,574 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-15 21:19:15,574 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 21:19:15,651 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-15 21:19:15,651 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-15 21:19:16,796 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-15 21:19:16,796 INFO L284 CfgBuilder]: Removed 163 assume(true) statements. [2019-11-15 21:19:16,798 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 09:19:16 BoogieIcfgContainer [2019-11-15 21:19:16,798 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-15 21:19:16,799 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-15 21:19:16,799 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-15 21:19:16,802 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-15 21:19:16,802 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 15.11 09:19:14" (1/3) ... [2019-11-15 21:19:16,803 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@16c98781 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 09:19:16, skipping insertion in model container [2019-11-15 21:19:16,803 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:19:15" (2/3) ... [2019-11-15 21:19:16,803 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@16c98781 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 09:19:16, skipping insertion in model container [2019-11-15 21:19:16,807 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 09:19:16" (3/3) ... [2019-11-15 21:19:16,809 INFO L109 eAbstractionObserver]: Analyzing ICFG token_ring.04.cil-2.c [2019-11-15 21:19:16,818 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-15 21:19:16,827 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-15 21:19:16,838 INFO L249 AbstractCegarLoop]: Starting to check reachability of 2 error locations. [2019-11-15 21:19:16,885 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-15 21:19:16,885 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-15 21:19:16,885 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-15 21:19:16,886 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-15 21:19:16,886 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-15 21:19:16,886 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-15 21:19:16,886 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-15 21:19:16,888 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-15 21:19:16,923 INFO L276 IsEmpty]: Start isEmpty. Operand 421 states. [2019-11-15 21:19:16,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:16,940 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:16,941 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:16,943 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:16,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:16,949 INFO L82 PathProgramCache]: Analyzing trace with hash 1090379614, now seen corresponding path program 1 times [2019-11-15 21:19:16,956 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:16,956 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098063593] [2019-11-15 21:19:16,957 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:16,957 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:16,957 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:17,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:17,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:17,170 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1098063593] [2019-11-15 21:19:17,171 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:17,171 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:17,172 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884362496] [2019-11-15 21:19:17,176 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:17,176 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:17,189 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:17,189 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:17,191 INFO L87 Difference]: Start difference. First operand 421 states. Second operand 3 states. [2019-11-15 21:19:17,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:17,289 INFO L93 Difference]: Finished difference Result 837 states and 1301 transitions. [2019-11-15 21:19:17,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:17,296 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:17,296 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:17,313 INFO L225 Difference]: With dead ends: 837 [2019-11-15 21:19:17,314 INFO L226 Difference]: Without dead ends: 417 [2019-11-15 21:19:17,323 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:17,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 417 states. [2019-11-15 21:19:17,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 417 to 417. [2019-11-15 21:19:17,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 417 states. [2019-11-15 21:19:17,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 417 states to 417 states and 633 transitions. [2019-11-15 21:19:17,402 INFO L78 Accepts]: Start accepts. Automaton has 417 states and 633 transitions. Word has length 72 [2019-11-15 21:19:17,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:17,402 INFO L462 AbstractCegarLoop]: Abstraction has 417 states and 633 transitions. [2019-11-15 21:19:17,402 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:17,403 INFO L276 IsEmpty]: Start isEmpty. Operand 417 states and 633 transitions. [2019-11-15 21:19:17,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:17,405 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:17,406 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:17,406 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:17,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:17,406 INFO L82 PathProgramCache]: Analyzing trace with hash 136439456, now seen corresponding path program 1 times [2019-11-15 21:19:17,407 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:17,407 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698371299] [2019-11-15 21:19:17,407 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:17,407 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:17,408 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:17,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:17,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:17,454 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698371299] [2019-11-15 21:19:17,454 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:17,454 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:17,455 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696494078] [2019-11-15 21:19:17,456 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:17,456 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:17,457 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:17,457 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:17,457 INFO L87 Difference]: Start difference. First operand 417 states and 633 transitions. Second operand 3 states. [2019-11-15 21:19:17,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:17,511 INFO L93 Difference]: Finished difference Result 1143 states and 1731 transitions. [2019-11-15 21:19:17,512 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:17,512 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:17,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:17,517 INFO L225 Difference]: With dead ends: 1143 [2019-11-15 21:19:17,517 INFO L226 Difference]: Without dead ends: 735 [2019-11-15 21:19:17,519 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:17,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 735 states. [2019-11-15 21:19:17,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 735 to 731. [2019-11-15 21:19:17,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 731 states. [2019-11-15 21:19:17,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 731 states to 731 states and 1106 transitions. [2019-11-15 21:19:17,555 INFO L78 Accepts]: Start accepts. Automaton has 731 states and 1106 transitions. Word has length 72 [2019-11-15 21:19:17,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:17,555 INFO L462 AbstractCegarLoop]: Abstraction has 731 states and 1106 transitions. [2019-11-15 21:19:17,556 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:17,556 INFO L276 IsEmpty]: Start isEmpty. Operand 731 states and 1106 transitions. [2019-11-15 21:19:17,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:17,558 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:17,558 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:17,559 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:17,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:17,559 INFO L82 PathProgramCache]: Analyzing trace with hash -51966948, now seen corresponding path program 1 times [2019-11-15 21:19:17,559 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:17,563 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303658489] [2019-11-15 21:19:17,564 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:17,565 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:17,565 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:17,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:17,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:17,616 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303658489] [2019-11-15 21:19:17,616 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:17,616 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:17,617 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1609855842] [2019-11-15 21:19:17,617 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:17,618 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:17,618 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:17,618 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:17,618 INFO L87 Difference]: Start difference. First operand 731 states and 1106 transitions. Second operand 3 states. [2019-11-15 21:19:17,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:17,668 INFO L93 Difference]: Finished difference Result 1452 states and 2197 transitions. [2019-11-15 21:19:17,668 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:17,669 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:17,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:17,674 INFO L225 Difference]: With dead ends: 1452 [2019-11-15 21:19:17,675 INFO L226 Difference]: Without dead ends: 731 [2019-11-15 21:19:17,676 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:17,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 731 states. [2019-11-15 21:19:17,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 731 to 731. [2019-11-15 21:19:17,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 731 states. [2019-11-15 21:19:17,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 731 states to 731 states and 1098 transitions. [2019-11-15 21:19:17,720 INFO L78 Accepts]: Start accepts. Automaton has 731 states and 1098 transitions. Word has length 72 [2019-11-15 21:19:17,720 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:17,720 INFO L462 AbstractCegarLoop]: Abstraction has 731 states and 1098 transitions. [2019-11-15 21:19:17,720 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:17,721 INFO L276 IsEmpty]: Start isEmpty. Operand 731 states and 1098 transitions. [2019-11-15 21:19:17,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:17,722 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:17,722 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:17,722 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:17,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:17,723 INFO L82 PathProgramCache]: Analyzing trace with hash -469363554, now seen corresponding path program 1 times [2019-11-15 21:19:17,723 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:17,723 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028449862] [2019-11-15 21:19:17,723 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:17,723 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:17,724 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:17,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:17,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:17,799 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028449862] [2019-11-15 21:19:17,800 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:17,800 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:17,800 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1825106133] [2019-11-15 21:19:17,800 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:17,801 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:17,801 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:17,801 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:17,801 INFO L87 Difference]: Start difference. First operand 731 states and 1098 transitions. Second operand 3 states. [2019-11-15 21:19:17,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:17,844 INFO L93 Difference]: Finished difference Result 1451 states and 2180 transitions. [2019-11-15 21:19:17,844 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:17,845 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:17,845 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:17,849 INFO L225 Difference]: With dead ends: 1451 [2019-11-15 21:19:17,849 INFO L226 Difference]: Without dead ends: 731 [2019-11-15 21:19:17,850 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:17,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 731 states. [2019-11-15 21:19:17,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 731 to 731. [2019-11-15 21:19:17,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 731 states. [2019-11-15 21:19:17,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 731 states to 731 states and 1090 transitions. [2019-11-15 21:19:17,881 INFO L78 Accepts]: Start accepts. Automaton has 731 states and 1090 transitions. Word has length 72 [2019-11-15 21:19:17,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:17,881 INFO L462 AbstractCegarLoop]: Abstraction has 731 states and 1090 transitions. [2019-11-15 21:19:17,881 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:17,882 INFO L276 IsEmpty]: Start isEmpty. Operand 731 states and 1090 transitions. [2019-11-15 21:19:17,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:17,883 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:17,883 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:17,883 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:17,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:17,884 INFO L82 PathProgramCache]: Analyzing trace with hash 428763418, now seen corresponding path program 1 times [2019-11-15 21:19:17,884 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:17,884 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955549373] [2019-11-15 21:19:17,885 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:17,885 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:17,885 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:17,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:17,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:17,919 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955549373] [2019-11-15 21:19:17,919 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:17,920 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:17,920 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199733726] [2019-11-15 21:19:17,920 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:17,921 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:17,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:17,921 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:17,921 INFO L87 Difference]: Start difference. First operand 731 states and 1090 transitions. Second operand 3 states. [2019-11-15 21:19:17,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:17,971 INFO L93 Difference]: Finished difference Result 1450 states and 2163 transitions. [2019-11-15 21:19:17,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:17,972 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:17,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:17,976 INFO L225 Difference]: With dead ends: 1450 [2019-11-15 21:19:17,976 INFO L226 Difference]: Without dead ends: 731 [2019-11-15 21:19:17,977 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:17,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 731 states. [2019-11-15 21:19:18,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 731 to 731. [2019-11-15 21:19:18,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 731 states. [2019-11-15 21:19:18,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 731 states to 731 states and 1082 transitions. [2019-11-15 21:19:18,007 INFO L78 Accepts]: Start accepts. Automaton has 731 states and 1082 transitions. Word has length 72 [2019-11-15 21:19:18,008 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:18,008 INFO L462 AbstractCegarLoop]: Abstraction has 731 states and 1082 transitions. [2019-11-15 21:19:18,008 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:18,008 INFO L276 IsEmpty]: Start isEmpty. Operand 731 states and 1082 transitions. [2019-11-15 21:19:18,009 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:18,009 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:18,011 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:18,012 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:18,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:18,012 INFO L82 PathProgramCache]: Analyzing trace with hash -1481927394, now seen corresponding path program 1 times [2019-11-15 21:19:18,012 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:18,013 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774544812] [2019-11-15 21:19:18,013 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,013 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,013 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:18,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:18,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:18,057 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774544812] [2019-11-15 21:19:18,057 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:18,058 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:18,058 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910496525] [2019-11-15 21:19:18,058 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:18,059 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:18,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:18,059 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,059 INFO L87 Difference]: Start difference. First operand 731 states and 1082 transitions. Second operand 3 states. [2019-11-15 21:19:18,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:18,129 INFO L93 Difference]: Finished difference Result 1448 states and 2144 transitions. [2019-11-15 21:19:18,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:18,129 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:18,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:18,133 INFO L225 Difference]: With dead ends: 1448 [2019-11-15 21:19:18,134 INFO L226 Difference]: Without dead ends: 731 [2019-11-15 21:19:18,135 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 731 states. [2019-11-15 21:19:18,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 731 to 731. [2019-11-15 21:19:18,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 731 states. [2019-11-15 21:19:18,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 731 states to 731 states and 1062 transitions. [2019-11-15 21:19:18,169 INFO L78 Accepts]: Start accepts. Automaton has 731 states and 1062 transitions. Word has length 72 [2019-11-15 21:19:18,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:18,170 INFO L462 AbstractCegarLoop]: Abstraction has 731 states and 1062 transitions. [2019-11-15 21:19:18,170 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:18,170 INFO L276 IsEmpty]: Start isEmpty. Operand 731 states and 1062 transitions. [2019-11-15 21:19:18,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:18,171 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:18,171 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:18,171 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:18,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:18,172 INFO L82 PathProgramCache]: Analyzing trace with hash 1411017443, now seen corresponding path program 1 times [2019-11-15 21:19:18,172 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:18,172 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113616586] [2019-11-15 21:19:18,173 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,173 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,173 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:18,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:18,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:18,237 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113616586] [2019-11-15 21:19:18,237 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:18,237 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:18,237 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [957339122] [2019-11-15 21:19:18,237 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:18,238 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:18,238 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:18,238 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,238 INFO L87 Difference]: Start difference. First operand 731 states and 1062 transitions. Second operand 3 states. [2019-11-15 21:19:18,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:18,314 INFO L93 Difference]: Finished difference Result 1447 states and 2103 transitions. [2019-11-15 21:19:18,315 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:18,315 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:18,315 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:18,319 INFO L225 Difference]: With dead ends: 1447 [2019-11-15 21:19:18,319 INFO L226 Difference]: Without dead ends: 731 [2019-11-15 21:19:18,320 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 731 states. [2019-11-15 21:19:18,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 731 to 731. [2019-11-15 21:19:18,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 731 states. [2019-11-15 21:19:18,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 731 states to 731 states and 1042 transitions. [2019-11-15 21:19:18,350 INFO L78 Accepts]: Start accepts. Automaton has 731 states and 1042 transitions. Word has length 72 [2019-11-15 21:19:18,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:18,351 INFO L462 AbstractCegarLoop]: Abstraction has 731 states and 1042 transitions. [2019-11-15 21:19:18,351 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:18,351 INFO L276 IsEmpty]: Start isEmpty. Operand 731 states and 1042 transitions. [2019-11-15 21:19:18,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:18,352 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:18,352 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:18,352 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:18,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:18,352 INFO L82 PathProgramCache]: Analyzing trace with hash -149398177, now seen corresponding path program 1 times [2019-11-15 21:19:18,352 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:18,353 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084049115] [2019-11-15 21:19:18,353 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,353 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,353 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:18,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:18,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:18,388 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1084049115] [2019-11-15 21:19:18,389 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:18,389 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:18,389 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [211379860] [2019-11-15 21:19:18,389 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:18,389 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:18,390 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:18,390 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,390 INFO L87 Difference]: Start difference. First operand 731 states and 1042 transitions. Second operand 3 states. [2019-11-15 21:19:18,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:18,456 INFO L93 Difference]: Finished difference Result 1446 states and 2062 transitions. [2019-11-15 21:19:18,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:18,457 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:18,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:18,461 INFO L225 Difference]: With dead ends: 1446 [2019-11-15 21:19:18,461 INFO L226 Difference]: Without dead ends: 731 [2019-11-15 21:19:18,463 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 731 states. [2019-11-15 21:19:18,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 731 to 731. [2019-11-15 21:19:18,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 731 states. [2019-11-15 21:19:18,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 731 states to 731 states and 1022 transitions. [2019-11-15 21:19:18,496 INFO L78 Accepts]: Start accepts. Automaton has 731 states and 1022 transitions. Word has length 72 [2019-11-15 21:19:18,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:18,496 INFO L462 AbstractCegarLoop]: Abstraction has 731 states and 1022 transitions. [2019-11-15 21:19:18,496 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:18,497 INFO L276 IsEmpty]: Start isEmpty. Operand 731 states and 1022 transitions. [2019-11-15 21:19:18,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:18,497 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:18,497 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:18,498 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:18,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:18,498 INFO L82 PathProgramCache]: Analyzing trace with hash -962003548, now seen corresponding path program 1 times [2019-11-15 21:19:18,498 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:18,498 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [314584800] [2019-11-15 21:19:18,498 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,499 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,499 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:18,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:18,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:18,545 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [314584800] [2019-11-15 21:19:18,545 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:18,545 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:18,546 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1342348296] [2019-11-15 21:19:18,546 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:18,546 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:18,546 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:18,547 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,547 INFO L87 Difference]: Start difference. First operand 731 states and 1022 transitions. Second operand 3 states. [2019-11-15 21:19:18,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:18,614 INFO L93 Difference]: Finished difference Result 1445 states and 2021 transitions. [2019-11-15 21:19:18,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:18,615 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:18,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:18,619 INFO L225 Difference]: With dead ends: 1445 [2019-11-15 21:19:18,619 INFO L226 Difference]: Without dead ends: 731 [2019-11-15 21:19:18,622 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 731 states. [2019-11-15 21:19:18,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 731 to 731. [2019-11-15 21:19:18,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 731 states. [2019-11-15 21:19:18,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 731 states to 731 states and 1002 transitions. [2019-11-15 21:19:18,653 INFO L78 Accepts]: Start accepts. Automaton has 731 states and 1002 transitions. Word has length 72 [2019-11-15 21:19:18,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:18,653 INFO L462 AbstractCegarLoop]: Abstraction has 731 states and 1002 transitions. [2019-11-15 21:19:18,653 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:18,654 INFO L276 IsEmpty]: Start isEmpty. Operand 731 states and 1002 transitions. [2019-11-15 21:19:18,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:18,654 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:18,654 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:18,655 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:18,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:18,659 INFO L82 PathProgramCache]: Analyzing trace with hash -1942397152, now seen corresponding path program 1 times [2019-11-15 21:19:18,659 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:18,659 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [887240095] [2019-11-15 21:19:18,659 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,660 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,660 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:18,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:18,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:18,687 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [887240095] [2019-11-15 21:19:18,688 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:18,688 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:18,689 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1137155677] [2019-11-15 21:19:18,689 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:18,690 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:18,690 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:18,690 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,690 INFO L87 Difference]: Start difference. First operand 731 states and 1002 transitions. Second operand 3 states. [2019-11-15 21:19:18,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:18,758 INFO L93 Difference]: Finished difference Result 1444 states and 1980 transitions. [2019-11-15 21:19:18,759 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:18,759 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:18,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:18,763 INFO L225 Difference]: With dead ends: 1444 [2019-11-15 21:19:18,763 INFO L226 Difference]: Without dead ends: 731 [2019-11-15 21:19:18,768 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 731 states. [2019-11-15 21:19:18,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 731 to 731. [2019-11-15 21:19:18,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 731 states. [2019-11-15 21:19:18,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 731 states to 731 states and 982 transitions. [2019-11-15 21:19:18,798 INFO L78 Accepts]: Start accepts. Automaton has 731 states and 982 transitions. Word has length 72 [2019-11-15 21:19:18,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:18,798 INFO L462 AbstractCegarLoop]: Abstraction has 731 states and 982 transitions. [2019-11-15 21:19:18,799 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:18,799 INFO L276 IsEmpty]: Start isEmpty. Operand 731 states and 982 transitions. [2019-11-15 21:19:18,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:18,799 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:18,799 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:18,800 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:18,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:18,800 INFO L82 PathProgramCache]: Analyzing trace with hash -1527286429, now seen corresponding path program 1 times [2019-11-15 21:19:18,800 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:18,800 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505712997] [2019-11-15 21:19:18,800 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,801 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,801 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:18,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:18,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:18,842 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1505712997] [2019-11-15 21:19:18,842 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:18,842 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:18,842 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720058372] [2019-11-15 21:19:18,843 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:18,843 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:18,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:18,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,843 INFO L87 Difference]: Start difference. First operand 731 states and 982 transitions. Second operand 3 states. [2019-11-15 21:19:18,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:18,885 INFO L93 Difference]: Finished difference Result 1449 states and 1946 transitions. [2019-11-15 21:19:18,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:18,886 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:18,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:18,890 INFO L225 Difference]: With dead ends: 1449 [2019-11-15 21:19:18,890 INFO L226 Difference]: Without dead ends: 731 [2019-11-15 21:19:18,892 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 731 states. [2019-11-15 21:19:18,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 731 to 731. [2019-11-15 21:19:18,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 731 states. [2019-11-15 21:19:18,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 731 states to 731 states and 974 transitions. [2019-11-15 21:19:18,927 INFO L78 Accepts]: Start accepts. Automaton has 731 states and 974 transitions. Word has length 72 [2019-11-15 21:19:18,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:18,928 INFO L462 AbstractCegarLoop]: Abstraction has 731 states and 974 transitions. [2019-11-15 21:19:18,928 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:18,928 INFO L276 IsEmpty]: Start isEmpty. Operand 731 states and 974 transitions. [2019-11-15 21:19:18,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-15 21:19:18,930 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:18,930 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:18,930 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:18,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:18,931 INFO L82 PathProgramCache]: Analyzing trace with hash 1950032417, now seen corresponding path program 1 times [2019-11-15 21:19:18,931 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:18,931 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [88190265] [2019-11-15 21:19:18,931 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,931 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:18,931 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:18,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:18,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:18,971 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [88190265] [2019-11-15 21:19:18,971 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:18,971 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:18,971 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636121264] [2019-11-15 21:19:18,972 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:18,972 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:18,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:18,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:18,972 INFO L87 Difference]: Start difference. First operand 731 states and 974 transitions. Second operand 3 states. [2019-11-15 21:19:19,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:19,081 INFO L93 Difference]: Finished difference Result 2078 states and 2774 transitions. [2019-11-15 21:19:19,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:19,081 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-15 21:19:19,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:19,089 INFO L225 Difference]: With dead ends: 2078 [2019-11-15 21:19:19,089 INFO L226 Difference]: Without dead ends: 1367 [2019-11-15 21:19:19,090 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:19,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1367 states. [2019-11-15 21:19:19,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1367 to 1301. [2019-11-15 21:19:19,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1301 states. [2019-11-15 21:19:19,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1301 states to 1301 states and 1723 transitions. [2019-11-15 21:19:19,154 INFO L78 Accepts]: Start accepts. Automaton has 1301 states and 1723 transitions. Word has length 72 [2019-11-15 21:19:19,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:19,154 INFO L462 AbstractCegarLoop]: Abstraction has 1301 states and 1723 transitions. [2019-11-15 21:19:19,154 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:19,155 INFO L276 IsEmpty]: Start isEmpty. Operand 1301 states and 1723 transitions. [2019-11-15 21:19:19,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2019-11-15 21:19:19,158 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:19,158 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:19,159 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:19,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:19,159 INFO L82 PathProgramCache]: Analyzing trace with hash -1262693056, now seen corresponding path program 1 times [2019-11-15 21:19:19,159 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:19,159 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879535743] [2019-11-15 21:19:19,159 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:19,160 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:19,160 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:19,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:19,228 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:19,228 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879535743] [2019-11-15 21:19:19,228 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:19,228 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 21:19:19,229 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [592086483] [2019-11-15 21:19:19,229 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 21:19:19,229 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:19,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 21:19:19,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 21:19:19,230 INFO L87 Difference]: Start difference. First operand 1301 states and 1723 transitions. Second operand 5 states. [2019-11-15 21:19:19,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:19,426 INFO L93 Difference]: Finished difference Result 2968 states and 3967 transitions. [2019-11-15 21:19:19,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 21:19:19,427 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 117 [2019-11-15 21:19:19,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:19,436 INFO L225 Difference]: With dead ends: 2968 [2019-11-15 21:19:19,436 INFO L226 Difference]: Without dead ends: 1691 [2019-11-15 21:19:19,438 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 21:19:19,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1691 states. [2019-11-15 21:19:19,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1691 to 1307. [2019-11-15 21:19:19,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1307 states. [2019-11-15 21:19:19,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1307 states to 1307 states and 1706 transitions. [2019-11-15 21:19:19,520 INFO L78 Accepts]: Start accepts. Automaton has 1307 states and 1706 transitions. Word has length 117 [2019-11-15 21:19:19,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:19,520 INFO L462 AbstractCegarLoop]: Abstraction has 1307 states and 1706 transitions. [2019-11-15 21:19:19,520 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 21:19:19,520 INFO L276 IsEmpty]: Start isEmpty. Operand 1307 states and 1706 transitions. [2019-11-15 21:19:19,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2019-11-15 21:19:19,522 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:19,523 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:19,523 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:19,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:19,523 INFO L82 PathProgramCache]: Analyzing trace with hash 1661445820, now seen corresponding path program 1 times [2019-11-15 21:19:19,523 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:19,524 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [638249481] [2019-11-15 21:19:19,524 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:19,524 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:19,524 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:19,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:19,606 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:19,607 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [638249481] [2019-11-15 21:19:19,607 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:19,607 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:19,607 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335504505] [2019-11-15 21:19:19,608 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:19,608 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:19,608 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:19,608 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:19,608 INFO L87 Difference]: Start difference. First operand 1307 states and 1706 transitions. Second operand 3 states. [2019-11-15 21:19:19,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:19,754 INFO L93 Difference]: Finished difference Result 3774 states and 4946 transitions. [2019-11-15 21:19:19,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:19,754 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 117 [2019-11-15 21:19:19,755 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:19,767 INFO L225 Difference]: With dead ends: 3774 [2019-11-15 21:19:19,767 INFO L226 Difference]: Without dead ends: 2493 [2019-11-15 21:19:19,769 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:19,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2493 states. [2019-11-15 21:19:19,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2493 to 2377. [2019-11-15 21:19:19,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2377 states. [2019-11-15 21:19:19,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2377 states to 2377 states and 3100 transitions. [2019-11-15 21:19:19,880 INFO L78 Accepts]: Start accepts. Automaton has 2377 states and 3100 transitions. Word has length 117 [2019-11-15 21:19:19,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:19,880 INFO L462 AbstractCegarLoop]: Abstraction has 2377 states and 3100 transitions. [2019-11-15 21:19:19,880 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:19,880 INFO L276 IsEmpty]: Start isEmpty. Operand 2377 states and 3100 transitions. [2019-11-15 21:19:19,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2019-11-15 21:19:19,882 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:19,882 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:19,883 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:19,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:19,883 INFO L82 PathProgramCache]: Analyzing trace with hash 2061437019, now seen corresponding path program 1 times [2019-11-15 21:19:19,883 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:19,883 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [576364127] [2019-11-15 21:19:19,884 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:19,884 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:19,884 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:19,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:19,940 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:19,940 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [576364127] [2019-11-15 21:19:19,941 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:19,941 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 21:19:19,941 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012587245] [2019-11-15 21:19:19,941 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 21:19:19,941 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:19,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 21:19:19,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 21:19:19,942 INFO L87 Difference]: Start difference. First operand 2377 states and 3100 transitions. Second operand 5 states. [2019-11-15 21:19:20,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:20,195 INFO L93 Difference]: Finished difference Result 5178 states and 6787 transitions. [2019-11-15 21:19:20,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 21:19:20,195 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 117 [2019-11-15 21:19:20,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:20,209 INFO L225 Difference]: With dead ends: 5178 [2019-11-15 21:19:20,210 INFO L226 Difference]: Without dead ends: 2831 [2019-11-15 21:19:20,213 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 21:19:20,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2831 states. [2019-11-15 21:19:20,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2831 to 2383. [2019-11-15 21:19:20,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2383 states. [2019-11-15 21:19:20,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2383 states to 2383 states and 3063 transitions. [2019-11-15 21:19:20,354 INFO L78 Accepts]: Start accepts. Automaton has 2383 states and 3063 transitions. Word has length 117 [2019-11-15 21:19:20,354 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:20,355 INFO L462 AbstractCegarLoop]: Abstraction has 2383 states and 3063 transitions. [2019-11-15 21:19:20,355 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 21:19:20,355 INFO L276 IsEmpty]: Start isEmpty. Operand 2383 states and 3063 transitions. [2019-11-15 21:19:20,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2019-11-15 21:19:20,357 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:20,357 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:20,358 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:20,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:20,358 INFO L82 PathProgramCache]: Analyzing trace with hash 672376535, now seen corresponding path program 1 times [2019-11-15 21:19:20,358 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:20,358 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338387858] [2019-11-15 21:19:20,359 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:20,359 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:20,359 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:20,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:20,410 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:20,414 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338387858] [2019-11-15 21:19:20,416 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:20,417 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 21:19:20,417 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048658286] [2019-11-15 21:19:20,417 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 21:19:20,417 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:20,418 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 21:19:20,418 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 21:19:20,418 INFO L87 Difference]: Start difference. First operand 2383 states and 3063 transitions. Second operand 5 states. [2019-11-15 21:19:20,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:20,691 INFO L93 Difference]: Finished difference Result 5747 states and 7403 transitions. [2019-11-15 21:19:20,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 21:19:20,692 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 117 [2019-11-15 21:19:20,692 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:20,709 INFO L225 Difference]: With dead ends: 5747 [2019-11-15 21:19:20,709 INFO L226 Difference]: Without dead ends: 3401 [2019-11-15 21:19:20,713 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 21:19:20,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3401 states. [2019-11-15 21:19:20,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3401 to 2395. [2019-11-15 21:19:20,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2395 states. [2019-11-15 21:19:20,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2395 states to 2395 states and 3034 transitions. [2019-11-15 21:19:20,912 INFO L78 Accepts]: Start accepts. Automaton has 2395 states and 3034 transitions. Word has length 117 [2019-11-15 21:19:20,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:20,912 INFO L462 AbstractCegarLoop]: Abstraction has 2395 states and 3034 transitions. [2019-11-15 21:19:20,912 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 21:19:20,912 INFO L276 IsEmpty]: Start isEmpty. Operand 2395 states and 3034 transitions. [2019-11-15 21:19:20,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2019-11-15 21:19:20,915 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:20,915 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:20,915 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:20,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:20,916 INFO L82 PathProgramCache]: Analyzing trace with hash -2033200557, now seen corresponding path program 1 times [2019-11-15 21:19:20,916 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:20,916 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078013766] [2019-11-15 21:19:20,916 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:20,916 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:20,916 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:20,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:20,960 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:20,960 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2078013766] [2019-11-15 21:19:20,960 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:20,960 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 21:19:20,961 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395749146] [2019-11-15 21:19:20,961 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 21:19:20,961 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:20,961 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 21:19:20,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 21:19:20,962 INFO L87 Difference]: Start difference. First operand 2395 states and 3034 transitions. Second operand 5 states. [2019-11-15 21:19:21,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:21,269 INFO L93 Difference]: Finished difference Result 6833 states and 8746 transitions. [2019-11-15 21:19:21,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 21:19:21,269 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 117 [2019-11-15 21:19:21,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:21,290 INFO L225 Difference]: With dead ends: 6833 [2019-11-15 21:19:21,291 INFO L226 Difference]: Without dead ends: 4489 [2019-11-15 21:19:21,295 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 21:19:21,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4489 states. [2019-11-15 21:19:21,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4489 to 2419. [2019-11-15 21:19:21,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2419 states. [2019-11-15 21:19:21,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2419 states to 2419 states and 3021 transitions. [2019-11-15 21:19:21,449 INFO L78 Accepts]: Start accepts. Automaton has 2419 states and 3021 transitions. Word has length 117 [2019-11-15 21:19:21,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:21,449 INFO L462 AbstractCegarLoop]: Abstraction has 2419 states and 3021 transitions. [2019-11-15 21:19:21,449 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 21:19:21,450 INFO L276 IsEmpty]: Start isEmpty. Operand 2419 states and 3021 transitions. [2019-11-15 21:19:21,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2019-11-15 21:19:21,452 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:21,452 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:21,452 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:21,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:21,453 INFO L82 PathProgramCache]: Analyzing trace with hash -2118887473, now seen corresponding path program 1 times [2019-11-15 21:19:21,453 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:21,453 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834188873] [2019-11-15 21:19:21,453 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:21,453 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:21,453 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:21,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:21,495 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:21,495 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834188873] [2019-11-15 21:19:21,496 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:21,496 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:21,496 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420572857] [2019-11-15 21:19:21,496 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:21,496 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:21,497 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:21,497 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:21,497 INFO L87 Difference]: Start difference. First operand 2419 states and 3021 transitions. Second operand 3 states. [2019-11-15 21:19:21,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:21,728 INFO L93 Difference]: Finished difference Result 6877 states and 8545 transitions. [2019-11-15 21:19:21,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:21,729 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 117 [2019-11-15 21:19:21,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:21,748 INFO L225 Difference]: With dead ends: 6877 [2019-11-15 21:19:21,749 INFO L226 Difference]: Without dead ends: 4519 [2019-11-15 21:19:21,752 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:21,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4519 states. [2019-11-15 21:19:22,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4519 to 4515. [2019-11-15 21:19:22,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4515 states. [2019-11-15 21:19:22,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4515 states to 4515 states and 5559 transitions. [2019-11-15 21:19:22,056 INFO L78 Accepts]: Start accepts. Automaton has 4515 states and 5559 transitions. Word has length 117 [2019-11-15 21:19:22,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:22,057 INFO L462 AbstractCegarLoop]: Abstraction has 4515 states and 5559 transitions. [2019-11-15 21:19:22,057 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:22,057 INFO L276 IsEmpty]: Start isEmpty. Operand 4515 states and 5559 transitions. [2019-11-15 21:19:22,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-11-15 21:19:22,060 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:22,060 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:22,061 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:22,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:22,061 INFO L82 PathProgramCache]: Analyzing trace with hash 1555831778, now seen corresponding path program 1 times [2019-11-15 21:19:22,061 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:22,061 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68307507] [2019-11-15 21:19:22,062 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:22,062 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:22,062 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:22,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:22,107 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:22,108 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [68307507] [2019-11-15 21:19:22,108 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:22,108 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:22,108 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [995066362] [2019-11-15 21:19:22,109 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:22,110 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:22,110 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:22,110 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:22,110 INFO L87 Difference]: Start difference. First operand 4515 states and 5559 transitions. Second operand 3 states. [2019-11-15 21:19:22,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:22,511 INFO L93 Difference]: Finished difference Result 12790 states and 15720 transitions. [2019-11-15 21:19:22,511 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:22,512 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 118 [2019-11-15 21:19:22,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:22,527 INFO L225 Difference]: With dead ends: 12790 [2019-11-15 21:19:22,527 INFO L226 Difference]: Without dead ends: 8336 [2019-11-15 21:19:22,534 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:22,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8336 states. [2019-11-15 21:19:23,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8336 to 8332. [2019-11-15 21:19:23,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8332 states. [2019-11-15 21:19:23,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8332 states to 8332 states and 10188 transitions. [2019-11-15 21:19:23,130 INFO L78 Accepts]: Start accepts. Automaton has 8332 states and 10188 transitions. Word has length 118 [2019-11-15 21:19:23,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:23,130 INFO L462 AbstractCegarLoop]: Abstraction has 8332 states and 10188 transitions. [2019-11-15 21:19:23,131 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:23,131 INFO L276 IsEmpty]: Start isEmpty. Operand 8332 states and 10188 transitions. [2019-11-15 21:19:23,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-11-15 21:19:23,137 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:23,137 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:23,138 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:23,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:23,138 INFO L82 PathProgramCache]: Analyzing trace with hash -1011990556, now seen corresponding path program 1 times [2019-11-15 21:19:23,138 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:23,138 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358248515] [2019-11-15 21:19:23,139 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:23,139 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:23,139 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:23,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:23,164 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-11-15 21:19:23,164 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [358248515] [2019-11-15 21:19:23,165 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:23,165 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:23,165 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1610364466] [2019-11-15 21:19:23,166 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:23,166 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:23,166 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:23,166 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:23,166 INFO L87 Difference]: Start difference. First operand 8332 states and 10188 transitions. Second operand 3 states. [2019-11-15 21:19:23,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:23,569 INFO L93 Difference]: Finished difference Result 16548 states and 20246 transitions. [2019-11-15 21:19:23,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:23,569 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 118 [2019-11-15 21:19:23,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:23,584 INFO L225 Difference]: With dead ends: 16548 [2019-11-15 21:19:23,585 INFO L226 Difference]: Without dead ends: 8277 [2019-11-15 21:19:23,594 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:23,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8277 states. [2019-11-15 21:19:24,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8277 to 8277. [2019-11-15 21:19:24,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8277 states. [2019-11-15 21:19:24,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8277 states to 8277 states and 10126 transitions. [2019-11-15 21:19:24,130 INFO L78 Accepts]: Start accepts. Automaton has 8277 states and 10126 transitions. Word has length 118 [2019-11-15 21:19:24,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:24,130 INFO L462 AbstractCegarLoop]: Abstraction has 8277 states and 10126 transitions. [2019-11-15 21:19:24,130 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:24,130 INFO L276 IsEmpty]: Start isEmpty. Operand 8277 states and 10126 transitions. [2019-11-15 21:19:24,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2019-11-15 21:19:24,135 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:24,135 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:24,136 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:24,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:24,136 INFO L82 PathProgramCache]: Analyzing trace with hash -453804771, now seen corresponding path program 1 times [2019-11-15 21:19:24,136 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:24,136 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1888500770] [2019-11-15 21:19:24,137 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:24,137 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:24,137 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:24,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:24,175 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:24,176 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1888500770] [2019-11-15 21:19:24,176 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:24,176 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:24,176 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58774595] [2019-11-15 21:19:24,177 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:24,177 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:24,177 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:24,177 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:24,177 INFO L87 Difference]: Start difference. First operand 8277 states and 10126 transitions. Second operand 3 states. [2019-11-15 21:19:24,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:24,819 INFO L93 Difference]: Finished difference Result 23779 states and 29069 transitions. [2019-11-15 21:19:24,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:24,819 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 119 [2019-11-15 21:19:24,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:24,854 INFO L225 Difference]: With dead ends: 23779 [2019-11-15 21:19:24,854 INFO L226 Difference]: Without dead ends: 15563 [2019-11-15 21:19:24,866 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:24,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15563 states. [2019-11-15 21:19:25,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15563 to 15143. [2019-11-15 21:19:25,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15143 states. [2019-11-15 21:19:25,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15143 states to 15143 states and 18441 transitions. [2019-11-15 21:19:25,724 INFO L78 Accepts]: Start accepts. Automaton has 15143 states and 18441 transitions. Word has length 119 [2019-11-15 21:19:25,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:25,724 INFO L462 AbstractCegarLoop]: Abstraction has 15143 states and 18441 transitions. [2019-11-15 21:19:25,724 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:25,724 INFO L276 IsEmpty]: Start isEmpty. Operand 15143 states and 18441 transitions. [2019-11-15 21:19:25,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2019-11-15 21:19:25,730 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:25,730 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:25,731 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:25,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:25,731 INFO L82 PathProgramCache]: Analyzing trace with hash 2112373853, now seen corresponding path program 1 times [2019-11-15 21:19:25,731 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:25,732 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928212332] [2019-11-15 21:19:25,732 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:25,732 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:25,732 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:25,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:25,757 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-11-15 21:19:25,757 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928212332] [2019-11-15 21:19:25,757 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:25,758 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:25,758 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992941363] [2019-11-15 21:19:25,758 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:25,758 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:25,759 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:25,759 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:25,759 INFO L87 Difference]: Start difference. First operand 15143 states and 18441 transitions. Second operand 3 states. [2019-11-15 21:19:26,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:26,335 INFO L93 Difference]: Finished difference Result 30188 states and 36773 transitions. [2019-11-15 21:19:26,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:26,335 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 119 [2019-11-15 21:19:26,335 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:26,356 INFO L225 Difference]: With dead ends: 30188 [2019-11-15 21:19:26,357 INFO L226 Difference]: Without dead ends: 15089 [2019-11-15 21:19:26,374 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:26,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15089 states. [2019-11-15 21:19:27,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15089 to 15089. [2019-11-15 21:19:27,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15089 states. [2019-11-15 21:19:27,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15089 states to 15089 states and 18381 transitions. [2019-11-15 21:19:27,216 INFO L78 Accepts]: Start accepts. Automaton has 15089 states and 18381 transitions. Word has length 119 [2019-11-15 21:19:27,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:27,216 INFO L462 AbstractCegarLoop]: Abstraction has 15089 states and 18381 transitions. [2019-11-15 21:19:27,216 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:27,216 INFO L276 IsEmpty]: Start isEmpty. Operand 15089 states and 18381 transitions. [2019-11-15 21:19:27,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2019-11-15 21:19:27,222 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:27,222 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:27,222 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:27,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:27,223 INFO L82 PathProgramCache]: Analyzing trace with hash 564824724, now seen corresponding path program 1 times [2019-11-15 21:19:27,223 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:27,223 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515407994] [2019-11-15 21:19:27,223 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:27,224 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:27,224 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:27,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:27,276 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:27,277 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1515407994] [2019-11-15 21:19:27,277 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:27,277 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:27,277 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1718861728] [2019-11-15 21:19:27,278 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:27,279 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:27,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:27,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:27,279 INFO L87 Difference]: Start difference. First operand 15089 states and 18381 transitions. Second operand 3 states. [2019-11-15 21:19:28,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:28,835 INFO L93 Difference]: Finished difference Result 42542 states and 51834 transitions. [2019-11-15 21:19:28,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:28,836 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 120 [2019-11-15 21:19:28,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:28,865 INFO L225 Difference]: With dead ends: 42542 [2019-11-15 21:19:28,866 INFO L226 Difference]: Without dead ends: 27514 [2019-11-15 21:19:28,880 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:28,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27514 states. [2019-11-15 21:19:29,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27514 to 27510. [2019-11-15 21:19:29,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27510 states. [2019-11-15 21:19:29,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27510 states to 27510 states and 33430 transitions. [2019-11-15 21:19:29,911 INFO L78 Accepts]: Start accepts. Automaton has 27510 states and 33430 transitions. Word has length 120 [2019-11-15 21:19:29,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:29,912 INFO L462 AbstractCegarLoop]: Abstraction has 27510 states and 33430 transitions. [2019-11-15 21:19:29,912 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:29,912 INFO L276 IsEmpty]: Start isEmpty. Operand 27510 states and 33430 transitions. [2019-11-15 21:19:29,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2019-11-15 21:19:29,918 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:29,918 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:29,919 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:29,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:29,919 INFO L82 PathProgramCache]: Analyzing trace with hash -2002997610, now seen corresponding path program 1 times [2019-11-15 21:19:29,919 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:29,919 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748194144] [2019-11-15 21:19:29,919 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:29,920 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:29,920 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:29,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:29,948 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-11-15 21:19:29,949 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748194144] [2019-11-15 21:19:29,949 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:29,949 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:29,949 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680091587] [2019-11-15 21:19:29,950 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:29,950 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:29,950 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:29,951 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:29,951 INFO L87 Difference]: Start difference. First operand 27510 states and 33430 transitions. Second operand 3 states. [2019-11-15 21:19:31,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:31,632 INFO L93 Difference]: Finished difference Result 54906 states and 66736 transitions. [2019-11-15 21:19:31,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:31,633 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 120 [2019-11-15 21:19:31,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:31,664 INFO L225 Difference]: With dead ends: 54906 [2019-11-15 21:19:31,664 INFO L226 Difference]: Without dead ends: 27457 [2019-11-15 21:19:31,688 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:31,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27457 states. [2019-11-15 21:19:33,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27457 to 27457. [2019-11-15 21:19:33,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27457 states. [2019-11-15 21:19:33,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27457 states to 27457 states and 33372 transitions. [2019-11-15 21:19:33,178 INFO L78 Accepts]: Start accepts. Automaton has 27457 states and 33372 transitions. Word has length 120 [2019-11-15 21:19:33,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:33,178 INFO L462 AbstractCegarLoop]: Abstraction has 27457 states and 33372 transitions. [2019-11-15 21:19:33,178 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:33,178 INFO L276 IsEmpty]: Start isEmpty. Operand 27457 states and 33372 transitions. [2019-11-15 21:19:33,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2019-11-15 21:19:33,184 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:33,184 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:33,185 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:33,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:33,185 INFO L82 PathProgramCache]: Analyzing trace with hash 933474923, now seen corresponding path program 1 times [2019-11-15 21:19:33,185 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:33,185 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610028416] [2019-11-15 21:19:33,185 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:33,186 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:33,186 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:33,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:33,221 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:33,222 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610028416] [2019-11-15 21:19:33,222 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:33,222 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:33,222 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660640231] [2019-11-15 21:19:33,223 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:33,223 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:33,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:33,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:33,224 INFO L87 Difference]: Start difference. First operand 27457 states and 33372 transitions. Second operand 3 states. [2019-11-15 21:19:35,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:35,560 INFO L93 Difference]: Finished difference Result 78974 states and 95659 transitions. [2019-11-15 21:19:35,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:35,561 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 121 [2019-11-15 21:19:35,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:35,589 INFO L225 Difference]: With dead ends: 78974 [2019-11-15 21:19:35,589 INFO L226 Difference]: Without dead ends: 39641 [2019-11-15 21:19:35,607 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:35,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39641 states. [2019-11-15 21:19:36,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39641 to 39641. [2019-11-15 21:19:36,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39641 states. [2019-11-15 21:19:37,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39641 states to 39641 states and 47863 transitions. [2019-11-15 21:19:37,036 INFO L78 Accepts]: Start accepts. Automaton has 39641 states and 47863 transitions. Word has length 121 [2019-11-15 21:19:37,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:37,036 INFO L462 AbstractCegarLoop]: Abstraction has 39641 states and 47863 transitions. [2019-11-15 21:19:37,036 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:37,036 INFO L276 IsEmpty]: Start isEmpty. Operand 39641 states and 47863 transitions. [2019-11-15 21:19:37,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2019-11-15 21:19:37,048 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:37,049 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:37,049 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:37,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:37,049 INFO L82 PathProgramCache]: Analyzing trace with hash 334867575, now seen corresponding path program 1 times [2019-11-15 21:19:37,050 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:37,050 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297912400] [2019-11-15 21:19:37,050 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:37,050 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:37,050 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:37,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:37,112 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:37,112 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297912400] [2019-11-15 21:19:37,112 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:37,112 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:37,113 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920744666] [2019-11-15 21:19:37,113 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:37,113 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:37,113 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:37,114 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:37,114 INFO L87 Difference]: Start difference. First operand 39641 states and 47863 transitions. Second operand 3 states. [2019-11-15 21:19:39,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:39,562 INFO L93 Difference]: Finished difference Result 91203 states and 109883 transitions. [2019-11-15 21:19:39,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:39,563 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 156 [2019-11-15 21:19:39,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:39,612 INFO L225 Difference]: With dead ends: 91203 [2019-11-15 21:19:39,612 INFO L226 Difference]: Without dead ends: 51608 [2019-11-15 21:19:39,633 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:39,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51608 states. [2019-11-15 21:19:41,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51608 to 51416. [2019-11-15 21:19:41,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51416 states. [2019-11-15 21:19:41,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51416 states to 51416 states and 61605 transitions. [2019-11-15 21:19:41,837 INFO L78 Accepts]: Start accepts. Automaton has 51416 states and 61605 transitions. Word has length 156 [2019-11-15 21:19:41,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:41,837 INFO L462 AbstractCegarLoop]: Abstraction has 51416 states and 61605 transitions. [2019-11-15 21:19:41,837 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:41,837 INFO L276 IsEmpty]: Start isEmpty. Operand 51416 states and 61605 transitions. [2019-11-15 21:19:41,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2019-11-15 21:19:41,865 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:41,865 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:41,865 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:41,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:41,866 INFO L82 PathProgramCache]: Analyzing trace with hash -67611790, now seen corresponding path program 1 times [2019-11-15 21:19:41,866 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:41,866 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011133233] [2019-11-15 21:19:41,866 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:41,866 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:41,867 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:41,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:41,916 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-11-15 21:19:41,916 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1011133233] [2019-11-15 21:19:41,917 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:41,917 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:41,917 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202894606] [2019-11-15 21:19:41,917 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:41,918 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:41,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:41,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:41,918 INFO L87 Difference]: Start difference. First operand 51416 states and 61605 transitions. Second operand 3 states. [2019-11-15 21:19:43,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:43,827 INFO L93 Difference]: Finished difference Result 101872 states and 121803 transitions. [2019-11-15 21:19:43,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:43,827 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 174 [2019-11-15 21:19:43,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:43,876 INFO L225 Difference]: With dead ends: 101872 [2019-11-15 21:19:43,876 INFO L226 Difference]: Without dead ends: 50516 [2019-11-15 21:19:43,904 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:43,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50516 states. [2019-11-15 21:19:46,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50516 to 50516. [2019-11-15 21:19:46,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50516 states. [2019-11-15 21:19:46,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50516 states to 50516 states and 59621 transitions. [2019-11-15 21:19:46,588 INFO L78 Accepts]: Start accepts. Automaton has 50516 states and 59621 transitions. Word has length 174 [2019-11-15 21:19:46,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:46,589 INFO L462 AbstractCegarLoop]: Abstraction has 50516 states and 59621 transitions. [2019-11-15 21:19:46,589 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:46,589 INFO L276 IsEmpty]: Start isEmpty. Operand 50516 states and 59621 transitions. [2019-11-15 21:19:46,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 176 [2019-11-15 21:19:46,607 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:46,607 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:46,607 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:46,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:46,607 INFO L82 PathProgramCache]: Analyzing trace with hash -1145557634, now seen corresponding path program 1 times [2019-11-15 21:19:46,608 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:46,608 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301574547] [2019-11-15 21:19:46,608 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:46,608 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:46,608 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:46,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:46,660 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:46,661 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301574547] [2019-11-15 21:19:46,661 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:46,661 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:46,661 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1650304042] [2019-11-15 21:19:46,662 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:46,662 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:46,662 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:46,662 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:46,663 INFO L87 Difference]: Start difference. First operand 50516 states and 59621 transitions. Second operand 3 states. [2019-11-15 21:19:48,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:48,583 INFO L93 Difference]: Finished difference Result 89380 states and 105829 transitions. [2019-11-15 21:19:48,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:48,584 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 175 [2019-11-15 21:19:48,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:48,630 INFO L225 Difference]: With dead ends: 89380 [2019-11-15 21:19:48,630 INFO L226 Difference]: Without dead ends: 50520 [2019-11-15 21:19:48,653 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:48,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50520 states. [2019-11-15 21:19:50,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50520 to 50516. [2019-11-15 21:19:50,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50516 states. [2019-11-15 21:19:50,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50516 states to 50516 states and 59513 transitions. [2019-11-15 21:19:50,909 INFO L78 Accepts]: Start accepts. Automaton has 50516 states and 59513 transitions. Word has length 175 [2019-11-15 21:19:50,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:50,910 INFO L462 AbstractCegarLoop]: Abstraction has 50516 states and 59513 transitions. [2019-11-15 21:19:50,910 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:50,910 INFO L276 IsEmpty]: Start isEmpty. Operand 50516 states and 59513 transitions. [2019-11-15 21:19:50,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 211 [2019-11-15 21:19:50,926 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:50,926 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:50,926 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:50,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:50,927 INFO L82 PathProgramCache]: Analyzing trace with hash 2011308056, now seen corresponding path program 1 times [2019-11-15 21:19:50,927 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:50,927 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023562144] [2019-11-15 21:19:50,927 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:50,927 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:50,927 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:50,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:50,997 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2019-11-15 21:19:50,998 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023562144] [2019-11-15 21:19:50,998 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:50,998 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:19:50,998 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077338034] [2019-11-15 21:19:50,999 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:50,999 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:50,999 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:51,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:51,000 INFO L87 Difference]: Start difference. First operand 50516 states and 59513 transitions. Second operand 3 states. [2019-11-15 21:19:55,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:19:55,621 INFO L93 Difference]: Finished difference Result 111624 states and 131256 transitions. [2019-11-15 21:19:55,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:19:55,621 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 210 [2019-11-15 21:19:55,621 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:19:55,671 INFO L225 Difference]: With dead ends: 111624 [2019-11-15 21:19:55,672 INFO L226 Difference]: Without dead ends: 61147 [2019-11-15 21:19:55,693 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:55,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61147 states. [2019-11-15 21:19:57,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61147 to 60891. [2019-11-15 21:19:57,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60891 states. [2019-11-15 21:19:58,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60891 states to 60891 states and 71287 transitions. [2019-11-15 21:19:58,026 INFO L78 Accepts]: Start accepts. Automaton has 60891 states and 71287 transitions. Word has length 210 [2019-11-15 21:19:58,026 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:19:58,026 INFO L462 AbstractCegarLoop]: Abstraction has 60891 states and 71287 transitions. [2019-11-15 21:19:58,026 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:19:58,026 INFO L276 IsEmpty]: Start isEmpty. Operand 60891 states and 71287 transitions. [2019-11-15 21:19:58,056 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 214 [2019-11-15 21:19:58,056 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:19:58,056 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:19:58,057 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:19:58,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:19:58,057 INFO L82 PathProgramCache]: Analyzing trace with hash -1782699020, now seen corresponding path program 1 times [2019-11-15 21:19:58,057 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:19:58,057 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696849455] [2019-11-15 21:19:58,057 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:58,057 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:19:58,057 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:19:58,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:19:58,120 INFO L134 CoverageAnalysis]: Checked inductivity of 37 backedges. 37 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:19:58,121 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696849455] [2019-11-15 21:19:58,121 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:19:58,121 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:19:58,121 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729170294] [2019-11-15 21:19:58,122 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:19:58,122 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:19:58,122 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:19:58,122 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:19:58,123 INFO L87 Difference]: Start difference. First operand 60891 states and 71287 transitions. Second operand 3 states. [2019-11-15 21:20:00,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:00,833 INFO L93 Difference]: Finished difference Result 111351 states and 130739 transitions. [2019-11-15 21:20:00,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:20:00,833 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 213 [2019-11-15 21:20:00,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:00,892 INFO L225 Difference]: With dead ends: 111351 [2019-11-15 21:20:00,892 INFO L226 Difference]: Without dead ends: 60895 [2019-11-15 21:20:00,922 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:00,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60895 states. [2019-11-15 21:20:03,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60895 to 60891. [2019-11-15 21:20:03,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60891 states. [2019-11-15 21:20:03,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60891 states to 60891 states and 71123 transitions. [2019-11-15 21:20:03,694 INFO L78 Accepts]: Start accepts. Automaton has 60891 states and 71123 transitions. Word has length 213 [2019-11-15 21:20:03,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:03,694 INFO L462 AbstractCegarLoop]: Abstraction has 60891 states and 71123 transitions. [2019-11-15 21:20:03,694 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:20:03,694 INFO L276 IsEmpty]: Start isEmpty. Operand 60891 states and 71123 transitions. [2019-11-15 21:20:03,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 214 [2019-11-15 21:20:03,717 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:03,717 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:03,717 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:03,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:03,718 INFO L82 PathProgramCache]: Analyzing trace with hash -1923880001, now seen corresponding path program 1 times [2019-11-15 21:20:03,718 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:03,718 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1042406688] [2019-11-15 21:20:03,718 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:03,719 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:03,719 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:03,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:20:03,778 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 39 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:20:03,778 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1042406688] [2019-11-15 21:20:03,778 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:20:03,778 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:20:03,779 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [211693606] [2019-11-15 21:20:03,779 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:20:03,779 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:20:03,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:20:03,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:03,780 INFO L87 Difference]: Start difference. First operand 60891 states and 71123 transitions. Second operand 3 states. [2019-11-15 21:20:06,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:06,213 INFO L93 Difference]: Finished difference Result 111475 states and 130537 transitions. [2019-11-15 21:20:06,213 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:20:06,213 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 213 [2019-11-15 21:20:06,213 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:06,269 INFO L225 Difference]: With dead ends: 111475 [2019-11-15 21:20:06,269 INFO L226 Difference]: Without dead ends: 61019 [2019-11-15 21:20:06,300 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:06,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61019 states. [2019-11-15 21:20:09,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61019 to 60891. [2019-11-15 21:20:09,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60891 states. [2019-11-15 21:20:09,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60891 states to 60891 states and 69971 transitions. [2019-11-15 21:20:09,283 INFO L78 Accepts]: Start accepts. Automaton has 60891 states and 69971 transitions. Word has length 213 [2019-11-15 21:20:09,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:09,284 INFO L462 AbstractCegarLoop]: Abstraction has 60891 states and 69971 transitions. [2019-11-15 21:20:09,284 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:20:09,284 INFO L276 IsEmpty]: Start isEmpty. Operand 60891 states and 69971 transitions. [2019-11-15 21:20:09,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 217 [2019-11-15 21:20:09,303 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:09,304 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:09,304 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:09,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:09,304 INFO L82 PathProgramCache]: Analyzing trace with hash -1073074581, now seen corresponding path program 1 times [2019-11-15 21:20:09,305 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:09,305 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984323667] [2019-11-15 21:20:09,305 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:09,305 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:09,305 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:09,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:20:09,375 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-15 21:20:09,375 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984323667] [2019-11-15 21:20:09,375 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:20:09,376 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 21:20:09,376 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613348156] [2019-11-15 21:20:09,376 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 21:20:09,376 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:20:09,377 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 21:20:09,377 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 21:20:09,377 INFO L87 Difference]: Start difference. First operand 60891 states and 69971 transitions. Second operand 5 states. [2019-11-15 21:20:13,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:13,495 INFO L93 Difference]: Finished difference Result 154915 states and 179281 transitions. [2019-11-15 21:20:13,495 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 21:20:13,495 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 216 [2019-11-15 21:20:13,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:13,578 INFO L225 Difference]: With dead ends: 154915 [2019-11-15 21:20:13,578 INFO L226 Difference]: Without dead ends: 94067 [2019-11-15 21:20:13,610 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 21:20:13,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94067 states. [2019-11-15 21:20:16,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94067 to 61275. [2019-11-15 21:20:16,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61275 states. [2019-11-15 21:20:16,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61275 states to 61275 states and 69410 transitions. [2019-11-15 21:20:16,694 INFO L78 Accepts]: Start accepts. Automaton has 61275 states and 69410 transitions. Word has length 216 [2019-11-15 21:20:16,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:16,694 INFO L462 AbstractCegarLoop]: Abstraction has 61275 states and 69410 transitions. [2019-11-15 21:20:16,695 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 21:20:16,695 INFO L276 IsEmpty]: Start isEmpty. Operand 61275 states and 69410 transitions. [2019-11-15 21:20:16,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 251 [2019-11-15 21:20:16,724 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:16,725 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:16,725 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:16,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:16,725 INFO L82 PathProgramCache]: Analyzing trace with hash -1497272560, now seen corresponding path program 1 times [2019-11-15 21:20:16,725 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:16,726 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980715495] [2019-11-15 21:20:16,726 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:16,726 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:16,726 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:16,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:20:16,820 INFO L134 CoverageAnalysis]: Checked inductivity of 37 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-15 21:20:16,820 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [980715495] [2019-11-15 21:20:16,821 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:20:16,821 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:20:16,821 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [775113230] [2019-11-15 21:20:16,822 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:20:16,822 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:20:16,822 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:20:16,822 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:16,822 INFO L87 Difference]: Start difference. First operand 61275 states and 69410 transitions. Second operand 3 states. [2019-11-15 21:20:20,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:20,272 INFO L93 Difference]: Finished difference Result 131965 states and 149290 transitions. [2019-11-15 21:20:20,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:20:20,273 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 250 [2019-11-15 21:20:20,273 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:20,335 INFO L225 Difference]: With dead ends: 131965 [2019-11-15 21:20:20,335 INFO L226 Difference]: Without dead ends: 70722 [2019-11-15 21:20:20,364 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:20,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70722 states. [2019-11-15 21:20:23,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70722 to 70402. [2019-11-15 21:20:23,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70402 states. [2019-11-15 21:20:23,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70402 states to 70402 states and 79384 transitions. [2019-11-15 21:20:23,847 INFO L78 Accepts]: Start accepts. Automaton has 70402 states and 79384 transitions. Word has length 250 [2019-11-15 21:20:23,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:23,848 INFO L462 AbstractCegarLoop]: Abstraction has 70402 states and 79384 transitions. [2019-11-15 21:20:23,848 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:20:23,848 INFO L276 IsEmpty]: Start isEmpty. Operand 70402 states and 79384 transitions. [2019-11-15 21:20:23,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 254 [2019-11-15 21:20:23,878 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:23,878 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:23,878 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:23,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:23,879 INFO L82 PathProgramCache]: Analyzing trace with hash 1211305274, now seen corresponding path program 1 times [2019-11-15 21:20:23,879 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:23,879 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189262629] [2019-11-15 21:20:23,880 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:23,880 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:23,880 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:23,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:20:23,957 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 40 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:20:23,957 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189262629] [2019-11-15 21:20:23,958 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:20:23,958 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:20:23,958 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538698709] [2019-11-15 21:20:23,959 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:20:23,959 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:20:23,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:20:23,959 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:23,959 INFO L87 Difference]: Start difference. First operand 70402 states and 79384 transitions. Second operand 3 states. [2019-11-15 21:20:27,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:27,724 INFO L93 Difference]: Finished difference Result 131622 states and 148736 transitions. [2019-11-15 21:20:27,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:20:27,724 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 253 [2019-11-15 21:20:27,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:27,785 INFO L225 Difference]: With dead ends: 131622 [2019-11-15 21:20:27,786 INFO L226 Difference]: Without dead ends: 70406 [2019-11-15 21:20:27,811 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:27,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70406 states. [2019-11-15 21:20:30,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70406 to 70402. [2019-11-15 21:20:30,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70402 states. [2019-11-15 21:20:30,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70402 states to 70402 states and 79128 transitions. [2019-11-15 21:20:30,884 INFO L78 Accepts]: Start accepts. Automaton has 70402 states and 79128 transitions. Word has length 253 [2019-11-15 21:20:30,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:30,885 INFO L462 AbstractCegarLoop]: Abstraction has 70402 states and 79128 transitions. [2019-11-15 21:20:30,885 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:20:30,885 INFO L276 IsEmpty]: Start isEmpty. Operand 70402 states and 79128 transitions. [2019-11-15 21:20:30,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 293 [2019-11-15 21:20:30,911 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:30,911 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:30,911 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:30,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:30,912 INFO L82 PathProgramCache]: Analyzing trace with hash 78021096, now seen corresponding path program 1 times [2019-11-15 21:20:30,912 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:30,912 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227943268] [2019-11-15 21:20:30,912 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:30,912 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:30,912 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:30,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:20:30,995 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 39 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2019-11-15 21:20:30,995 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227943268] [2019-11-15 21:20:30,995 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:20:30,996 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:20:30,996 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [146716474] [2019-11-15 21:20:30,996 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:20:30,996 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:20:30,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:20:30,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:30,997 INFO L87 Difference]: Start difference. First operand 70402 states and 79128 transitions. Second operand 3 states. [2019-11-15 21:20:33,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:33,346 INFO L93 Difference]: Finished difference Result 91476 states and 102378 transitions. [2019-11-15 21:20:33,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:20:33,347 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 292 [2019-11-15 21:20:33,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:33,355 INFO L225 Difference]: With dead ends: 91476 [2019-11-15 21:20:33,355 INFO L226 Difference]: Without dead ends: 10928 [2019-11-15 21:20:33,389 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:33,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10928 states. [2019-11-15 21:20:33,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10928 to 10920. [2019-11-15 21:20:33,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10920 states. [2019-11-15 21:20:33,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10920 states to 10920 states and 11793 transitions. [2019-11-15 21:20:33,858 INFO L78 Accepts]: Start accepts. Automaton has 10920 states and 11793 transitions. Word has length 292 [2019-11-15 21:20:33,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:33,858 INFO L462 AbstractCegarLoop]: Abstraction has 10920 states and 11793 transitions. [2019-11-15 21:20:33,858 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:20:33,859 INFO L276 IsEmpty]: Start isEmpty. Operand 10920 states and 11793 transitions. [2019-11-15 21:20:33,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 294 [2019-11-15 21:20:33,864 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:33,864 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:33,864 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:33,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:33,865 INFO L82 PathProgramCache]: Analyzing trace with hash -394404878, now seen corresponding path program 1 times [2019-11-15 21:20:33,865 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:33,865 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136284819] [2019-11-15 21:20:33,865 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:33,866 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:33,866 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:33,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:20:33,943 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:20:33,943 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136284819] [2019-11-15 21:20:33,944 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:20:33,944 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:20:33,944 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1035040721] [2019-11-15 21:20:33,944 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:20:33,944 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:20:33,944 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:20:33,944 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:33,945 INFO L87 Difference]: Start difference. First operand 10920 states and 11793 transitions. Second operand 3 states. [2019-11-15 21:20:34,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:34,431 INFO L93 Difference]: Finished difference Result 18698 states and 20230 transitions. [2019-11-15 21:20:34,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:20:34,431 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 293 [2019-11-15 21:20:34,432 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:34,439 INFO L225 Difference]: With dead ends: 18698 [2019-11-15 21:20:34,439 INFO L226 Difference]: Without dead ends: 10920 [2019-11-15 21:20:34,444 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:34,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10920 states. [2019-11-15 21:20:34,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10920 to 10920. [2019-11-15 21:20:34,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10920 states. [2019-11-15 21:20:34,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10920 states to 10920 states and 11685 transitions. [2019-11-15 21:20:34,918 INFO L78 Accepts]: Start accepts. Automaton has 10920 states and 11685 transitions. Word has length 293 [2019-11-15 21:20:34,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:34,918 INFO L462 AbstractCegarLoop]: Abstraction has 10920 states and 11685 transitions. [2019-11-15 21:20:34,918 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:20:34,918 INFO L276 IsEmpty]: Start isEmpty. Operand 10920 states and 11685 transitions. [2019-11-15 21:20:34,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 298 [2019-11-15 21:20:34,924 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:34,924 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:34,924 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:34,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:34,924 INFO L82 PathProgramCache]: Analyzing trace with hash 526279388, now seen corresponding path program 1 times [2019-11-15 21:20:34,924 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:34,924 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464837738] [2019-11-15 21:20:34,925 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:34,925 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:34,925 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:34,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:20:35,007 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:20:35,007 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464837738] [2019-11-15 21:20:35,008 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:20:35,008 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:20:35,008 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101080377] [2019-11-15 21:20:35,009 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:20:35,009 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:20:35,009 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:20:35,009 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:35,009 INFO L87 Difference]: Start difference. First operand 10920 states and 11685 transitions. Second operand 3 states. [2019-11-15 21:20:35,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:35,518 INFO L93 Difference]: Finished difference Result 16951 states and 18170 transitions. [2019-11-15 21:20:35,519 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:20:35,519 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 297 [2019-11-15 21:20:35,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:35,527 INFO L225 Difference]: With dead ends: 16951 [2019-11-15 21:20:35,527 INFO L226 Difference]: Without dead ends: 10920 [2019-11-15 21:20:35,531 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:35,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10920 states. [2019-11-15 21:20:36,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10920 to 10920. [2019-11-15 21:20:36,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10920 states. [2019-11-15 21:20:36,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10920 states to 10920 states and 11599 transitions. [2019-11-15 21:20:36,221 INFO L78 Accepts]: Start accepts. Automaton has 10920 states and 11599 transitions. Word has length 297 [2019-11-15 21:20:36,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:36,221 INFO L462 AbstractCegarLoop]: Abstraction has 10920 states and 11599 transitions. [2019-11-15 21:20:36,221 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:20:36,221 INFO L276 IsEmpty]: Start isEmpty. Operand 10920 states and 11599 transitions. [2019-11-15 21:20:36,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 302 [2019-11-15 21:20:36,227 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:36,227 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:36,227 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:36,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:36,228 INFO L82 PathProgramCache]: Analyzing trace with hash 1535852850, now seen corresponding path program 1 times [2019-11-15 21:20:36,228 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:36,228 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106734725] [2019-11-15 21:20:36,228 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:36,228 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:36,228 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:36,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:20:36,322 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 37 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-15 21:20:36,322 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106734725] [2019-11-15 21:20:36,323 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:20:36,323 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:20:36,323 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1737459658] [2019-11-15 21:20:36,324 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:20:36,324 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:20:36,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:20:36,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:36,325 INFO L87 Difference]: Start difference. First operand 10920 states and 11599 transitions. Second operand 3 states. [2019-11-15 21:20:36,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:36,839 INFO L93 Difference]: Finished difference Result 17684 states and 18802 transitions. [2019-11-15 21:20:36,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:20:36,839 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 301 [2019-11-15 21:20:36,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:36,847 INFO L225 Difference]: With dead ends: 17684 [2019-11-15 21:20:36,848 INFO L226 Difference]: Without dead ends: 10984 [2019-11-15 21:20:36,852 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:36,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10984 states. [2019-11-15 21:20:37,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10984 to 10920. [2019-11-15 21:20:37,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10920 states. [2019-11-15 21:20:37,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10920 states to 10920 states and 11501 transitions. [2019-11-15 21:20:37,360 INFO L78 Accepts]: Start accepts. Automaton has 10920 states and 11501 transitions. Word has length 301 [2019-11-15 21:20:37,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:37,360 INFO L462 AbstractCegarLoop]: Abstraction has 10920 states and 11501 transitions. [2019-11-15 21:20:37,360 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:20:37,360 INFO L276 IsEmpty]: Start isEmpty. Operand 10920 states and 11501 transitions. [2019-11-15 21:20:37,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 305 [2019-11-15 21:20:37,366 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:37,367 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:37,367 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:37,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:37,367 INFO L82 PathProgramCache]: Analyzing trace with hash 185562899, now seen corresponding path program 1 times [2019-11-15 21:20:37,367 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:37,368 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683161267] [2019-11-15 21:20:37,368 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:37,368 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:37,368 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:37,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:20:37,461 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:20:37,461 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683161267] [2019-11-15 21:20:37,461 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:20:37,462 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:20:37,462 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1633656665] [2019-11-15 21:20:37,462 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:20:37,462 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:20:37,462 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:20:37,463 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:37,463 INFO L87 Difference]: Start difference. First operand 10920 states and 11501 transitions. Second operand 3 states. [2019-11-15 21:20:37,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:37,890 INFO L93 Difference]: Finished difference Result 13691 states and 14419 transitions. [2019-11-15 21:20:37,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:20:37,891 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 304 [2019-11-15 21:20:37,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:37,897 INFO L225 Difference]: With dead ends: 13691 [2019-11-15 21:20:37,897 INFO L226 Difference]: Without dead ends: 8725 [2019-11-15 21:20:37,900 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:37,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8725 states. [2019-11-15 21:20:38,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8725 to 8725. [2019-11-15 21:20:38,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8725 states. [2019-11-15 21:20:38,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8725 states to 8725 states and 9171 transitions. [2019-11-15 21:20:38,300 INFO L78 Accepts]: Start accepts. Automaton has 8725 states and 9171 transitions. Word has length 304 [2019-11-15 21:20:38,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:38,300 INFO L462 AbstractCegarLoop]: Abstraction has 8725 states and 9171 transitions. [2019-11-15 21:20:38,300 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:20:38,300 INFO L276 IsEmpty]: Start isEmpty. Operand 8725 states and 9171 transitions. [2019-11-15 21:20:38,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 309 [2019-11-15 21:20:38,305 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:38,306 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:38,306 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:38,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:38,306 INFO L82 PathProgramCache]: Analyzing trace with hash 1149032847, now seen corresponding path program 1 times [2019-11-15 21:20:38,306 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:38,306 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035994587] [2019-11-15 21:20:38,307 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:38,307 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:38,307 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:38,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:20:38,598 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 37 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-15 21:20:38,599 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1035994587] [2019-11-15 21:20:38,599 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:20:38,599 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-11-15 21:20:38,599 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123519200] [2019-11-15 21:20:38,600 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-15 21:20:38,600 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:20:38,600 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-15 21:20:38,600 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-11-15 21:20:38,600 INFO L87 Difference]: Start difference. First operand 8725 states and 9171 transitions. Second operand 7 states. [2019-11-15 21:20:39,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:39,152 INFO L93 Difference]: Finished difference Result 8725 states and 9171 transitions. [2019-11-15 21:20:39,153 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-15 21:20:39,153 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 308 [2019-11-15 21:20:39,153 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:39,159 INFO L225 Difference]: With dead ends: 8725 [2019-11-15 21:20:39,160 INFO L226 Difference]: Without dead ends: 8723 [2019-11-15 21:20:39,162 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-11-15 21:20:39,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8723 states. [2019-11-15 21:20:39,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8723 to 8723. [2019-11-15 21:20:39,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8723 states. [2019-11-15 21:20:39,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8723 states to 8723 states and 9168 transitions. [2019-11-15 21:20:39,573 INFO L78 Accepts]: Start accepts. Automaton has 8723 states and 9168 transitions. Word has length 308 [2019-11-15 21:20:39,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:39,574 INFO L462 AbstractCegarLoop]: Abstraction has 8723 states and 9168 transitions. [2019-11-15 21:20:39,574 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-15 21:20:39,574 INFO L276 IsEmpty]: Start isEmpty. Operand 8723 states and 9168 transitions. [2019-11-15 21:20:39,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 313 [2019-11-15 21:20:39,579 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:39,579 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:39,579 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:39,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:39,580 INFO L82 PathProgramCache]: Analyzing trace with hash -1404905635, now seen corresponding path program 1 times [2019-11-15 21:20:39,580 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:39,580 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2062668139] [2019-11-15 21:20:39,580 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:39,580 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:39,580 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:39,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:20:39,681 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2019-11-15 21:20:39,681 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2062668139] [2019-11-15 21:20:39,681 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:20:39,682 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:20:39,682 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1095622497] [2019-11-15 21:20:39,682 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 21:20:39,683 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:20:39,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:20:39,683 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:39,683 INFO L87 Difference]: Start difference. First operand 8723 states and 9168 transitions. Second operand 3 states. [2019-11-15 21:20:40,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:20:40,301 INFO L93 Difference]: Finished difference Result 11851 states and 12417 transitions. [2019-11-15 21:20:40,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:20:40,302 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 312 [2019-11-15 21:20:40,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 21:20:40,311 INFO L225 Difference]: With dead ends: 11851 [2019-11-15 21:20:40,311 INFO L226 Difference]: Without dead ends: 10279 [2019-11-15 21:20:40,314 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:20:40,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10279 states. [2019-11-15 21:20:40,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10279 to 8725. [2019-11-15 21:20:40,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8725 states. [2019-11-15 21:20:40,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8725 states to 8725 states and 9170 transitions. [2019-11-15 21:20:40,739 INFO L78 Accepts]: Start accepts. Automaton has 8725 states and 9170 transitions. Word has length 312 [2019-11-15 21:20:40,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 21:20:40,739 INFO L462 AbstractCegarLoop]: Abstraction has 8725 states and 9170 transitions. [2019-11-15 21:20:40,739 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 21:20:40,739 INFO L276 IsEmpty]: Start isEmpty. Operand 8725 states and 9170 transitions. [2019-11-15 21:20:40,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 314 [2019-11-15 21:20:40,744 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 21:20:40,745 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:20:40,745 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 21:20:40,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:20:40,745 INFO L82 PathProgramCache]: Analyzing trace with hash -839838432, now seen corresponding path program 1 times [2019-11-15 21:20:40,745 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:20:40,745 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882965191] [2019-11-15 21:20:40,746 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:40,746 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:20:40,746 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:20:40,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:20:40,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:20:40,941 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:20:40,941 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-11-15 21:20:41,139 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 15.11 09:20:41 BoogieIcfgContainer [2019-11-15 21:20:41,139 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-15 21:20:41,139 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-15 21:20:41,139 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-15 21:20:41,140 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-15 21:20:41,140 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 09:19:16" (3/4) ... [2019-11-15 21:20:41,142 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-15 21:20:41,364 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_a13ea3dc-3977-4a54-b3f4-70ea0b97b63a/bin/uautomizer/witness.graphml [2019-11-15 21:20:41,365 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-15 21:20:41,367 INFO L168 Benchmark]: Toolchain (without parser) took 86435.47 ms. Allocated memory was 1.0 GB in the beginning and 5.6 GB in the end (delta: 4.6 GB). Free memory was 950.0 MB in the beginning and 4.3 GB in the end (delta: -3.3 GB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2019-11-15 21:20:41,367 INFO L168 Benchmark]: CDTParser took 0.24 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-15 21:20:41,367 INFO L168 Benchmark]: CACSL2BoogieTranslator took 437.07 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 165.7 MB). Free memory was 950.0 MB in the beginning and 1.2 GB in the end (delta: -200.1 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. [2019-11-15 21:20:41,368 INFO L168 Benchmark]: Boogie Procedure Inliner took 95.65 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 11.5 GB. [2019-11-15 21:20:41,368 INFO L168 Benchmark]: Boogie Preprocessor took 108.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. [2019-11-15 21:20:41,368 INFO L168 Benchmark]: RCFGBuilder took 1224.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 96.2 MB). Peak memory consumption was 96.2 MB. Max. memory is 11.5 GB. [2019-11-15 21:20:41,369 INFO L168 Benchmark]: TraceAbstraction took 84340.05 ms. Allocated memory was 1.2 GB in the beginning and 5.6 GB in the end (delta: 4.4 GB). Free memory was 1.0 GB in the beginning and 4.3 GB in the end (delta: -3.3 GB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. [2019-11-15 21:20:41,369 INFO L168 Benchmark]: Witness Printer took 225.43 ms. Allocated memory is still 5.6 GB. Free memory was 4.3 GB in the beginning and 4.3 GB in the end (delta: 24.9 MB). Peak memory consumption was 24.9 MB. Max. memory is 11.5 GB. [2019-11-15 21:20:41,371 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 437.07 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 165.7 MB). Free memory was 950.0 MB in the beginning and 1.2 GB in the end (delta: -200.1 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 95.65 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 108.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1224.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 96.2 MB). Peak memory consumption was 96.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 84340.05 ms. Allocated memory was 1.2 GB in the beginning and 5.6 GB in the end (delta: 4.4 GB). Free memory was 1.0 GB in the beginning and 4.3 GB in the end (delta: -3.3 GB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. * Witness Printer took 225.43 ms. Allocated memory is still 5.6 GB. Free memory was 4.3 GB in the beginning and 4.3 GB in the end (delta: 24.9 MB). Peak memory consumption was 24.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 10]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int t4_st ; [L24] int m_i ; [L25] int t1_i ; [L26] int t2_i ; [L27] int t3_i ; [L28] int t4_i ; [L29] int M_E = 2; [L30] int T1_E = 2; [L31] int T2_E = 2; [L32] int T3_E = 2; [L33] int T4_E = 2; [L34] int E_M = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L45] int token ; [L47] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, token=0] [L850] int __retres1 ; [L762] m_i = 1 [L763] t1_i = 1 [L764] t2_i = 1 [L765] t3_i = 1 [L766] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L791] int kernel_st ; [L792] int tmp ; [L793] int tmp___0 ; [L797] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L355] COND TRUE m_i == 1 [L356] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L360] COND TRUE t1_i == 1 [L361] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L365] COND TRUE t2_i == 1 [L366] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t3_i == 1 [L371] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t4_i == 1 [L376] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L516] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L521] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L526] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] int tmp ; [L630] int tmp___0 ; [L631] int tmp___1 ; [L632] int tmp___2 ; [L633] int tmp___3 ; [L249] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L252] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L264] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L637] tmp = is_master_triggered() [L639] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L268] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L271] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L283] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L645] tmp___0 = is_transmit1_triggered() [L647] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L287] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L290] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L302] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L653] tmp___1 = is_transmit2_triggered() [L655] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L306] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L309] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L321] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L661] tmp___2 = is_transmit3_triggered() [L663] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L325] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L328] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L340] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L669] tmp___3 = is_transmit4_triggered() [L671] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L574] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L579] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L584] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L805] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L808] kernel_st = 1 [L421] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L425] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L388] COND TRUE m_st == 0 [L389] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L416] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L428] tmp = exists_runnable_thread() [L430] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L435] COND TRUE m_st == 0 [L436] int tmp_ndt_1; [L437] tmp_ndt_1 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L449] COND TRUE t1_st == 0 [L450] int tmp_ndt_2; [L451] tmp_ndt_2 = __VERIFIER_nondet_int() [L452] COND TRUE \read(tmp_ndt_2) [L454] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L108] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L119] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L121] t1_pc = 1 [L122] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L463] COND TRUE t2_st == 0 [L464] int tmp_ndt_3; [L465] tmp_ndt_3 = __VERIFIER_nondet_int() [L466] COND TRUE \read(tmp_ndt_3) [L468] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L144] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L155] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L157] t2_pc = 1 [L158] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L477] COND TRUE t3_st == 0 [L478] int tmp_ndt_4; [L479] tmp_ndt_4 = __VERIFIER_nondet_int() [L480] COND TRUE \read(tmp_ndt_4) [L482] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L180] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L191] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L193] t3_pc = 1 [L194] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L491] COND TRUE t4_st == 0 [L492] int tmp_ndt_5; [L493] tmp_ndt_5 = __VERIFIER_nondet_int() [L494] COND TRUE \read(tmp_ndt_5) [L496] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, token=0] [L216] COND TRUE t4_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, token=0] [L227] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, token=0] [L229] t4_pc = 1 [L230] t4_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L425] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L385] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L388] COND TRUE m_st == 0 [L389] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L416] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L428] tmp = exists_runnable_thread() [L430] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L435] COND TRUE m_st == 0 [L436] int tmp_ndt_1; [L437] tmp_ndt_1 = __VERIFIER_nondet_int() [L438] COND TRUE \read(tmp_ndt_1) [L440] m_st = 1 [L50] int tmp_var = __VERIFIER_nondet_int(); [L52] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L63] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L66] token = __VERIFIER_nondet_int() [L67] local = token [L68] E_1 = 1 [L629] int tmp ; [L630] int tmp___0 ; [L631] int tmp___1 ; [L632] int tmp___2 ; [L633] int tmp___3 ; [L249] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L252] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L262] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L264] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L637] tmp = is_master_triggered() [L639] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L268] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L271] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L272] COND TRUE E_1 == 1 [L273] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L283] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L645] tmp___0 = is_transmit1_triggered() [L647] COND TRUE \read(tmp___0) [L648] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L287] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L290] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L291] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L300] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L302] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L653] tmp___1 = is_transmit2_triggered() [L655] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L306] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L309] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L310] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L319] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L321] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L661] tmp___2 = is_transmit3_triggered() [L663] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L325] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L328] COND TRUE t4_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L329] COND FALSE !(E_4 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L338] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L340] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L669] tmp___3 = is_transmit4_triggered() [L671] COND FALSE !(\read(tmp___3)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L70] E_1 = 2 [L71] m_pc = 1 [L72] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L449] COND TRUE t1_st == 0 [L450] int tmp_ndt_2; [L451] tmp_ndt_2 = __VERIFIER_nondet_int() [L452] COND TRUE \read(tmp_ndt_2) [L454] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L108] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L111] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-4] [L127] token += 1 [L128] E_2 = 1 [L629] int tmp ; [L630] int tmp___0 ; [L631] int tmp___1 ; [L632] int tmp___2 ; [L633] int tmp___3 ; [L249] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L252] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L253] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L262] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L264] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L637] tmp = is_master_triggered() [L639] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L268] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L271] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L272] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L281] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L283] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L645] tmp___0 = is_transmit1_triggered() [L647] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L287] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L290] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L291] COND TRUE E_2 == 1 [L292] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L302] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L653] tmp___1 = is_transmit2_triggered() [L655] COND TRUE \read(tmp___1) [L656] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L306] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L309] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L310] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L319] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L321] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L661] tmp___2 = is_transmit3_triggered() [L663] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L325] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L328] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L329] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L338] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L340] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L669] tmp___3 = is_transmit4_triggered() [L671] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L130] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L119] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L121] t1_pc = 1 [L122] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L463] COND TRUE t2_st == 0 [L464] int tmp_ndt_3; [L465] tmp_ndt_3 = __VERIFIER_nondet_int() [L466] COND TRUE \read(tmp_ndt_3) [L468] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L144] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L147] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-3] [L163] token += 1 [L164] E_3 = 1 [L629] int tmp ; [L630] int tmp___0 ; [L631] int tmp___1 ; [L632] int tmp___2 ; [L633] int tmp___3 ; [L249] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L252] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L253] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L262] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L264] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L637] tmp = is_master_triggered() [L639] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L268] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L271] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L272] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L281] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L283] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L645] tmp___0 = is_transmit1_triggered() [L647] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L287] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L290] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L291] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L300] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L302] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L653] tmp___1 = is_transmit2_triggered() [L655] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L306] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L309] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L310] COND TRUE E_3 == 1 [L311] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L321] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L661] tmp___2 = is_transmit3_triggered() [L663] COND TRUE \read(tmp___2) [L664] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L325] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L328] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L329] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L338] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L340] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L669] tmp___3 = is_transmit4_triggered() [L671] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L166] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L155] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L157] t2_pc = 1 [L158] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L477] COND TRUE t3_st == 0 [L478] int tmp_ndt_4; [L479] tmp_ndt_4 = __VERIFIER_nondet_int() [L480] COND TRUE \read(tmp_ndt_4) [L482] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L180] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L183] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-2] [L199] token += 1 [L200] E_4 = 1 [L629] int tmp ; [L630] int tmp___0 ; [L631] int tmp___1 ; [L632] int tmp___2 ; [L633] int tmp___3 ; [L249] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L252] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L253] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L262] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L264] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L637] tmp = is_master_triggered() [L639] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L268] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L271] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L272] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L281] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L283] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L645] tmp___0 = is_transmit1_triggered() [L647] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L287] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L290] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L291] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L300] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L302] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L653] tmp___1 = is_transmit2_triggered() [L655] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L306] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L309] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L310] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L319] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L321] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L661] tmp___2 = is_transmit3_triggered() [L663] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L325] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L328] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L329] COND TRUE E_4 == 1 [L330] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L340] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=-1] [L669] tmp___3 = is_transmit4_triggered() [L671] COND TRUE \read(tmp___3) [L672] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, token=-1] [L202] E_4 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, token=-1] [L191] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, token=-1] [L193] t3_pc = 1 [L194] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, token=-1] [L491] COND TRUE t4_st == 0 [L492] int tmp_ndt_5; [L493] tmp_ndt_5 = __VERIFIER_nondet_int() [L494] COND TRUE \read(tmp_ndt_5) [L496] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=-1] [L216] COND FALSE !(t4_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=-1] [L219] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=-1] [L235] token += 1 [L236] E_M = 1 [L629] int tmp ; [L630] int tmp___0 ; [L631] int tmp___1 ; [L632] int tmp___2 ; [L633] int tmp___3 ; [L249] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L252] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L253] COND TRUE E_M == 1 [L254] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L264] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L637] tmp = is_master_triggered() [L639] COND TRUE \read(tmp) [L640] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L268] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L271] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L272] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L281] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L283] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L645] tmp___0 = is_transmit1_triggered() [L647] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L287] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L290] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L291] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L300] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L302] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L653] tmp___1 = is_transmit2_triggered() [L655] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L306] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L309] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L310] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L319] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L321] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L661] tmp___2 = is_transmit3_triggered() [L663] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L325] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L328] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L329] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L338] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L340] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L669] tmp___3 = is_transmit4_triggered() [L671] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=1, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L238] E_M = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L227] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, token=0] [L229] t4_pc = 1 [L230] t4_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L425] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L385] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L388] COND TRUE m_st == 0 [L389] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L416] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L428] tmp = exists_runnable_thread() [L430] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L435] COND TRUE m_st == 0 [L436] int tmp_ndt_1; [L437] tmp_ndt_1 = __VERIFIER_nondet_int() [L438] COND TRUE \read(tmp_ndt_1) [L440] m_st = 1 [L50] int tmp_var = __VERIFIER_nondet_int(); [L52] COND FALSE !(m_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L55] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L77] COND FALSE !(token != local + 4) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L82] COND TRUE tmp_var <= 5 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L83] COND TRUE tmp_var >= 5 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L88] COND TRUE tmp_var <= 5 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L89] COND TRUE tmp_var >= 5 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L90] COND TRUE tmp_var == 5 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] [L10] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=-4, M_E=2, m_i=1, m_pc=1, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, token=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 421 locations, 2 error locations. Result: UNSAFE, OverallTime: 84.2s, OverallIterations: 42, TraceHistogramMax: 3, AutomataDifference: 44.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 25645 SDtfs, 22698 SDslu, 18605 SDs, 0 SdLazy, 805 SolverSat, 374 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 143 GetRequests, 78 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=70402occurred in iteration=33, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 36.4s AutomataMinimizationTime, 41 MinimizatonAttempts, 39852 StatesRemovedByMinimization, 22 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.2s InterpolantComputationTime, 6681 NumberOfCodeBlocks, 6681 NumberOfCodeBlocksAsserted, 42 NumberOfCheckSat, 6327 ConstructedInterpolants, 0 QuantifiedInterpolants, 2308189 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 41 InterpolantComputations, 41 PerfectInterpolantSequences, 733/733 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...