./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-11-15 22:47:00,417 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-15 22:47:00,418 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-15 22:47:00,432 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-15 22:47:00,433 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-15 22:47:00,434 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-15 22:47:00,435 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-15 22:47:00,444 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-15 22:47:00,448 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-15 22:47:00,451 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-15 22:47:00,452 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-15 22:47:00,454 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-15 22:47:00,455 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-15 22:47:00,457 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-15 22:47:00,457 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-15 22:47:00,458 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-15 22:47:00,459 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-15 22:47:00,460 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-15 22:47:00,462 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-15 22:47:00,465 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-15 22:47:00,468 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-15 22:47:00,470 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-15 22:47:00,472 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-15 22:47:00,473 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-15 22:47:00,476 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-15 22:47:00,477 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-15 22:47:00,477 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-15 22:47:00,478 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-15 22:47:00,479 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-15 22:47:00,480 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-15 22:47:00,480 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-15 22:47:00,480 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-15 22:47:00,481 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-15 22:47:00,482 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-15 22:47:00,483 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-15 22:47:00,483 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-15 22:47:00,484 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-15 22:47:00,484 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-15 22:47:00,485 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-15 22:47:00,486 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-15 22:47:00,486 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-15 22:47:00,487 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-15 22:47:00,512 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-15 22:47:00,514 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-15 22:47:00,515 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-15 22:47:00,515 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-15 22:47:00,515 INFO L138 SettingsManager]: * Use SBE=true [2019-11-15 22:47:00,516 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-15 22:47:00,516 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-15 22:47:00,516 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-15 22:47:00,516 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-15 22:47:00,517 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-15 22:47:00,518 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-15 22:47:00,518 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-15 22:47:00,518 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-15 22:47:00,518 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-15 22:47:00,519 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-15 22:47:00,519 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-15 22:47:00,519 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-15 22:47:00,519 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-15 22:47:00,520 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-15 22:47:00,520 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-15 22:47:00,520 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-15 22:47:00,520 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 22:47:00,521 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-15 22:47:00,521 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-15 22:47:00,521 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-15 22:47:00,521 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-15 22:47:00,522 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-15 22:47:00,522 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-15 22:47:00,522 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2019-11-15 22:47:00,561 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-15 22:47:00,572 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-15 22:47:00,575 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-15 22:47:00,577 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-15 22:47:00,577 INFO L275 PluginConnector]: CDTParser initialized [2019-11-15 22:47:00,578 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.04.cil.c [2019-11-15 22:47:00,631 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/data/b4bef2c0a/04aeb92e07da4de7869dc5b77ad3857f/FLAG863ca2540 [2019-11-15 22:47:01,067 INFO L306 CDTParser]: Found 1 translation units. [2019-11-15 22:47:01,068 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/sv-benchmarks/c/systemc/transmitter.04.cil.c [2019-11-15 22:47:01,077 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/data/b4bef2c0a/04aeb92e07da4de7869dc5b77ad3857f/FLAG863ca2540 [2019-11-15 22:47:01,090 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/data/b4bef2c0a/04aeb92e07da4de7869dc5b77ad3857f [2019-11-15 22:47:01,092 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-15 22:47:01,094 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-15 22:47:01,094 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-15 22:47:01,095 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-15 22:47:01,098 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-15 22:47:01,099 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 10:47:01" (1/1) ... [2019-11-15 22:47:01,102 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c34b6b8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01, skipping insertion in model container [2019-11-15 22:47:01,102 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 10:47:01" (1/1) ... [2019-11-15 22:47:01,109 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-15 22:47:01,160 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-15 22:47:01,462 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 22:47:01,468 INFO L188 MainTranslator]: Completed pre-run [2019-11-15 22:47:01,519 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 22:47:01,539 INFO L192 MainTranslator]: Completed translation [2019-11-15 22:47:01,539 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01 WrapperNode [2019-11-15 22:47:01,540 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-15 22:47:01,540 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-15 22:47:01,540 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-15 22:47:01,541 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-15 22:47:01,549 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01" (1/1) ... [2019-11-15 22:47:01,556 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01" (1/1) ... [2019-11-15 22:47:01,601 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-15 22:47:01,602 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-15 22:47:01,602 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-15 22:47:01,602 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-15 22:47:01,611 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01" (1/1) ... [2019-11-15 22:47:01,611 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01" (1/1) ... [2019-11-15 22:47:01,619 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01" (1/1) ... [2019-11-15 22:47:01,619 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01" (1/1) ... [2019-11-15 22:47:01,640 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01" (1/1) ... [2019-11-15 22:47:01,667 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01" (1/1) ... [2019-11-15 22:47:01,672 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01" (1/1) ... [2019-11-15 22:47:01,679 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-15 22:47:01,679 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-15 22:47:01,679 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-15 22:47:01,679 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-15 22:47:01,680 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-15 22:47:01,740 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-15 22:47:01,740 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-15 22:47:02,934 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-15 22:47:02,934 INFO L284 CfgBuilder]: Removed 148 assume(true) statements. [2019-11-15 22:47:02,936 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 10:47:02 BoogieIcfgContainer [2019-11-15 22:47:02,936 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-15 22:47:02,937 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-15 22:47:02,937 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-15 22:47:02,939 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-15 22:47:02,940 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 15.11 10:47:01" (1/3) ... [2019-11-15 22:47:02,940 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1eeb235d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 10:47:02, skipping insertion in model container [2019-11-15 22:47:02,941 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 10:47:01" (2/3) ... [2019-11-15 22:47:02,941 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1eeb235d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.11 10:47:02, skipping insertion in model container [2019-11-15 22:47:02,941 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 10:47:02" (3/3) ... [2019-11-15 22:47:02,943 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.04.cil.c [2019-11-15 22:47:02,949 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-15 22:47:02,955 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-15 22:47:02,962 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-15 22:47:02,987 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-15 22:47:02,988 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-15 22:47:02,988 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-15 22:47:02,988 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-15 22:47:02,988 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-15 22:47:02,988 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-15 22:47:02,988 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-15 22:47:02,988 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-15 22:47:03,015 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states. [2019-11-15 22:47:03,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:47:03,025 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:03,025 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:03,027 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:03,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:03,033 INFO L82 PathProgramCache]: Analyzing trace with hash -1653942868, now seen corresponding path program 1 times [2019-11-15 22:47:03,039 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:03,039 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713164537] [2019-11-15 22:47:03,039 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:03,039 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:03,040 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:03,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:03,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:03,185 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713164537] [2019-11-15 22:47:03,186 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:03,186 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:47:03,186 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997470964] [2019-11-15 22:47:03,190 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:03,191 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:03,203 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:03,203 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:03,205 INFO L87 Difference]: Start difference. First operand 374 states. Second operand 3 states. [2019-11-15 22:47:03,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:03,279 INFO L93 Difference]: Finished difference Result 743 states and 1159 transitions. [2019-11-15 22:47:03,279 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:03,281 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 22:47:03,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:03,295 INFO L225 Difference]: With dead ends: 743 [2019-11-15 22:47:03,295 INFO L226 Difference]: Without dead ends: 370 [2019-11-15 22:47:03,299 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:03,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370 states. [2019-11-15 22:47:03,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370 to 370. [2019-11-15 22:47:03,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 370 states. [2019-11-15 22:47:03,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370 states to 370 states and 561 transitions. [2019-11-15 22:47:03,364 INFO L78 Accepts]: Start accepts. Automaton has 370 states and 561 transitions. Word has length 73 [2019-11-15 22:47:03,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:03,365 INFO L462 AbstractCegarLoop]: Abstraction has 370 states and 561 transitions. [2019-11-15 22:47:03,365 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:03,365 INFO L276 IsEmpty]: Start isEmpty. Operand 370 states and 561 transitions. [2019-11-15 22:47:03,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:47:03,368 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:03,369 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:03,369 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:03,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:03,369 INFO L82 PathProgramCache]: Analyzing trace with hash -1161316694, now seen corresponding path program 1 times [2019-11-15 22:47:03,370 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:03,370 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [505968392] [2019-11-15 22:47:03,370 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:03,370 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:03,371 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:03,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:03,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:03,457 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [505968392] [2019-11-15 22:47:03,457 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:03,457 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:03,457 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918674753] [2019-11-15 22:47:03,459 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:03,459 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:03,459 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:03,459 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:03,460 INFO L87 Difference]: Start difference. First operand 370 states and 561 transitions. Second operand 3 states. [2019-11-15 22:47:03,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:03,599 INFO L93 Difference]: Finished difference Result 1004 states and 1519 transitions. [2019-11-15 22:47:03,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:03,600 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 22:47:03,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:03,604 INFO L225 Difference]: With dead ends: 1004 [2019-11-15 22:47:03,604 INFO L226 Difference]: Without dead ends: 643 [2019-11-15 22:47:03,607 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:03,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 643 states. [2019-11-15 22:47:03,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 643 to 641. [2019-11-15 22:47:03,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-15 22:47:03,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 961 transitions. [2019-11-15 22:47:03,662 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 961 transitions. Word has length 73 [2019-11-15 22:47:03,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:03,662 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 961 transitions. [2019-11-15 22:47:03,663 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:03,663 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 961 transitions. [2019-11-15 22:47:03,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:47:03,672 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:03,672 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:03,673 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:03,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:03,673 INFO L82 PathProgramCache]: Analyzing trace with hash 1509510378, now seen corresponding path program 1 times [2019-11-15 22:47:03,673 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:03,675 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [915037026] [2019-11-15 22:47:03,675 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:03,676 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:03,676 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:03,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:03,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:03,739 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [915037026] [2019-11-15 22:47:03,739 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:03,740 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:03,740 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461678986] [2019-11-15 22:47:03,740 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:03,741 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:03,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:03,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:03,742 INFO L87 Difference]: Start difference. First operand 641 states and 961 transitions. Second operand 3 states. [2019-11-15 22:47:03,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:03,785 INFO L93 Difference]: Finished difference Result 1272 states and 1907 transitions. [2019-11-15 22:47:03,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:03,786 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 22:47:03,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:03,790 INFO L225 Difference]: With dead ends: 1272 [2019-11-15 22:47:03,791 INFO L226 Difference]: Without dead ends: 641 [2019-11-15 22:47:03,792 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:03,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-15 22:47:03,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-15 22:47:03,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-15 22:47:03,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 953 transitions. [2019-11-15 22:47:03,836 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 953 transitions. Word has length 73 [2019-11-15 22:47:03,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:03,837 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 953 transitions. [2019-11-15 22:47:03,837 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:03,837 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 953 transitions. [2019-11-15 22:47:03,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:47:03,838 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:03,839 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:03,839 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:03,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:03,839 INFO L82 PathProgramCache]: Analyzing trace with hash 1595666090, now seen corresponding path program 1 times [2019-11-15 22:47:03,839 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:03,840 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151193670] [2019-11-15 22:47:03,840 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:03,840 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:03,840 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:03,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:03,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:03,898 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151193670] [2019-11-15 22:47:03,899 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:03,899 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:03,899 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [640960770] [2019-11-15 22:47:03,900 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:03,900 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:03,900 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:03,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:03,900 INFO L87 Difference]: Start difference. First operand 641 states and 953 transitions. Second operand 3 states. [2019-11-15 22:47:03,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:03,951 INFO L93 Difference]: Finished difference Result 1271 states and 1890 transitions. [2019-11-15 22:47:03,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:03,951 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 22:47:03,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:03,955 INFO L225 Difference]: With dead ends: 1271 [2019-11-15 22:47:03,956 INFO L226 Difference]: Without dead ends: 641 [2019-11-15 22:47:03,957 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:03,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-15 22:47:03,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-15 22:47:03,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-15 22:47:03,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 945 transitions. [2019-11-15 22:47:03,988 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 945 transitions. Word has length 73 [2019-11-15 22:47:03,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:03,990 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 945 transitions. [2019-11-15 22:47:03,990 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:03,990 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 945 transitions. [2019-11-15 22:47:03,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:47:03,992 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:03,992 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:03,992 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:03,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:03,993 INFO L82 PathProgramCache]: Analyzing trace with hash 1178269484, now seen corresponding path program 1 times [2019-11-15 22:47:03,993 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:03,993 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609410276] [2019-11-15 22:47:03,993 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:03,993 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:03,994 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:04,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:04,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:04,061 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1609410276] [2019-11-15 22:47:04,061 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:04,062 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:04,062 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790236703] [2019-11-15 22:47:04,062 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:04,062 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:04,063 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:04,063 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,063 INFO L87 Difference]: Start difference. First operand 641 states and 945 transitions. Second operand 3 states. [2019-11-15 22:47:04,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:04,108 INFO L93 Difference]: Finished difference Result 1270 states and 1873 transitions. [2019-11-15 22:47:04,109 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:04,109 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 22:47:04,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:04,113 INFO L225 Difference]: With dead ends: 1270 [2019-11-15 22:47:04,114 INFO L226 Difference]: Without dead ends: 641 [2019-11-15 22:47:04,115 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-15 22:47:04,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-15 22:47:04,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-15 22:47:04,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 937 transitions. [2019-11-15 22:47:04,164 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 937 transitions. Word has length 73 [2019-11-15 22:47:04,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:04,164 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 937 transitions. [2019-11-15 22:47:04,164 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:04,165 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 937 transitions. [2019-11-15 22:47:04,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:47:04,166 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:04,166 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:04,166 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:04,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:04,167 INFO L82 PathProgramCache]: Analyzing trace with hash 52103404, now seen corresponding path program 1 times [2019-11-15 22:47:04,167 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:04,167 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362397978] [2019-11-15 22:47:04,167 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,168 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,168 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:04,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:04,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:04,197 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362397978] [2019-11-15 22:47:04,197 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:04,197 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:04,198 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945053380] [2019-11-15 22:47:04,198 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:04,198 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:04,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:04,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,199 INFO L87 Difference]: Start difference. First operand 641 states and 937 transitions. Second operand 3 states. [2019-11-15 22:47:04,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:04,262 INFO L93 Difference]: Finished difference Result 1268 states and 1854 transitions. [2019-11-15 22:47:04,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:04,263 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 22:47:04,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:04,267 INFO L225 Difference]: With dead ends: 1268 [2019-11-15 22:47:04,267 INFO L226 Difference]: Without dead ends: 641 [2019-11-15 22:47:04,268 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-15 22:47:04,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-15 22:47:04,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-15 22:47:04,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 919 transitions. [2019-11-15 22:47:04,299 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 919 transitions. Word has length 73 [2019-11-15 22:47:04,299 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:04,300 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 919 transitions. [2019-11-15 22:47:04,300 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:04,300 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 919 transitions. [2019-11-15 22:47:04,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:47:04,301 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:04,302 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:04,302 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:04,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:04,304 INFO L82 PathProgramCache]: Analyzing trace with hash 2144832493, now seen corresponding path program 1 times [2019-11-15 22:47:04,305 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:04,305 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106354069] [2019-11-15 22:47:04,305 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,305 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,306 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:04,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:04,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:04,338 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106354069] [2019-11-15 22:47:04,338 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:04,338 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:04,339 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1230338188] [2019-11-15 22:47:04,339 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:04,339 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:04,339 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:04,339 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,340 INFO L87 Difference]: Start difference. First operand 641 states and 919 transitions. Second operand 3 states. [2019-11-15 22:47:04,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:04,404 INFO L93 Difference]: Finished difference Result 1267 states and 1817 transitions. [2019-11-15 22:47:04,404 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:04,404 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 22:47:04,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:04,408 INFO L225 Difference]: With dead ends: 1267 [2019-11-15 22:47:04,408 INFO L226 Difference]: Without dead ends: 641 [2019-11-15 22:47:04,410 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-15 22:47:04,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-15 22:47:04,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-15 22:47:04,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 901 transitions. [2019-11-15 22:47:04,439 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 901 transitions. Word has length 73 [2019-11-15 22:47:04,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:04,440 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 901 transitions. [2019-11-15 22:47:04,440 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:04,440 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 901 transitions. [2019-11-15 22:47:04,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:47:04,441 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:04,441 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:04,441 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:04,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:04,442 INFO L82 PathProgramCache]: Analyzing trace with hash 1887883821, now seen corresponding path program 1 times [2019-11-15 22:47:04,442 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:04,442 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1216186936] [2019-11-15 22:47:04,442 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,442 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,442 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:04,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:04,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:04,469 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1216186936] [2019-11-15 22:47:04,469 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:04,469 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:04,470 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [321726659] [2019-11-15 22:47:04,470 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:04,470 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:04,470 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:04,471 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,471 INFO L87 Difference]: Start difference. First operand 641 states and 901 transitions. Second operand 3 states. [2019-11-15 22:47:04,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:04,530 INFO L93 Difference]: Finished difference Result 1266 states and 1780 transitions. [2019-11-15 22:47:04,531 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:04,531 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 22:47:04,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:04,535 INFO L225 Difference]: With dead ends: 1266 [2019-11-15 22:47:04,535 INFO L226 Difference]: Without dead ends: 641 [2019-11-15 22:47:04,536 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-15 22:47:04,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-15 22:47:04,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-15 22:47:04,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 883 transitions. [2019-11-15 22:47:04,565 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 883 transitions. Word has length 73 [2019-11-15 22:47:04,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:04,566 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 883 transitions. [2019-11-15 22:47:04,566 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:04,566 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 883 transitions. [2019-11-15 22:47:04,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:47:04,567 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:04,567 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:04,567 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:04,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:04,568 INFO L82 PathProgramCache]: Analyzing trace with hash 1757929134, now seen corresponding path program 1 times [2019-11-15 22:47:04,568 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:04,568 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836159817] [2019-11-15 22:47:04,568 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,568 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,568 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:04,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:04,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:04,593 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1836159817] [2019-11-15 22:47:04,593 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:04,594 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:04,594 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433886207] [2019-11-15 22:47:04,594 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:04,594 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:04,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:04,595 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,595 INFO L87 Difference]: Start difference. First operand 641 states and 883 transitions. Second operand 3 states. [2019-11-15 22:47:04,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:04,665 INFO L93 Difference]: Finished difference Result 1265 states and 1743 transitions. [2019-11-15 22:47:04,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:04,666 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 22:47:04,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:04,669 INFO L225 Difference]: With dead ends: 1265 [2019-11-15 22:47:04,670 INFO L226 Difference]: Without dead ends: 641 [2019-11-15 22:47:04,671 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-15 22:47:04,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-15 22:47:04,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-15 22:47:04,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 865 transitions. [2019-11-15 22:47:04,701 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 865 transitions. Word has length 73 [2019-11-15 22:47:04,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:04,702 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 865 transitions. [2019-11-15 22:47:04,702 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:04,702 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 865 transitions. [2019-11-15 22:47:04,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:47:04,703 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:04,704 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:04,707 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:04,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:04,707 INFO L82 PathProgramCache]: Analyzing trace with hash 1024701678, now seen corresponding path program 1 times [2019-11-15 22:47:04,707 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:04,708 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558311646] [2019-11-15 22:47:04,708 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,708 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,708 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:04,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:04,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:04,749 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558311646] [2019-11-15 22:47:04,750 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:04,751 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:04,751 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615813798] [2019-11-15 22:47:04,751 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:04,752 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:04,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:04,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,752 INFO L87 Difference]: Start difference. First operand 641 states and 865 transitions. Second operand 3 states. [2019-11-15 22:47:04,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:04,795 INFO L93 Difference]: Finished difference Result 1269 states and 1712 transitions. [2019-11-15 22:47:04,795 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:04,795 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 22:47:04,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:04,800 INFO L225 Difference]: With dead ends: 1269 [2019-11-15 22:47:04,800 INFO L226 Difference]: Without dead ends: 641 [2019-11-15 22:47:04,805 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-15 22:47:04,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-15 22:47:04,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-15 22:47:04,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 857 transitions. [2019-11-15 22:47:04,838 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 857 transitions. Word has length 73 [2019-11-15 22:47:04,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:04,839 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 857 transitions. [2019-11-15 22:47:04,839 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:04,840 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 857 transitions. [2019-11-15 22:47:04,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-15 22:47:04,840 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:04,841 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:04,841 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:04,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:04,841 INFO L82 PathProgramCache]: Analyzing trace with hash 1243556396, now seen corresponding path program 1 times [2019-11-15 22:47:04,841 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:04,842 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454275345] [2019-11-15 22:47:04,842 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,842 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:04,842 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:04,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:04,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:04,882 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454275345] [2019-11-15 22:47:04,883 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:04,883 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:47:04,883 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1865580739] [2019-11-15 22:47:04,883 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:04,884 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:04,884 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:04,884 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,884 INFO L87 Difference]: Start difference. First operand 641 states and 857 transitions. Second operand 3 states. [2019-11-15 22:47:04,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:04,976 INFO L93 Difference]: Finished difference Result 1812 states and 2410 transitions. [2019-11-15 22:47:04,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:04,976 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-15 22:47:04,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:04,983 INFO L225 Difference]: With dead ends: 1812 [2019-11-15 22:47:04,983 INFO L226 Difference]: Without dead ends: 1232 [2019-11-15 22:47:04,985 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:04,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1232 states. [2019-11-15 22:47:05,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1232 to 1168. [2019-11-15 22:47:05,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1168 states. [2019-11-15 22:47:05,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1168 states to 1168 states and 1539 transitions. [2019-11-15 22:47:05,041 INFO L78 Accepts]: Start accepts. Automaton has 1168 states and 1539 transitions. Word has length 73 [2019-11-15 22:47:05,041 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:05,041 INFO L462 AbstractCegarLoop]: Abstraction has 1168 states and 1539 transitions. [2019-11-15 22:47:05,042 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:05,042 INFO L276 IsEmpty]: Start isEmpty. Operand 1168 states and 1539 transitions. [2019-11-15 22:47:05,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-15 22:47:05,043 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:05,043 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:05,060 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:05,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:05,061 INFO L82 PathProgramCache]: Analyzing trace with hash -546581241, now seen corresponding path program 1 times [2019-11-15 22:47:05,061 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:05,061 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481583005] [2019-11-15 22:47:05,061 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:05,061 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:05,062 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:05,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:05,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:05,092 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481583005] [2019-11-15 22:47:05,092 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:05,092 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:47:05,092 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1367027066] [2019-11-15 22:47:05,093 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:05,093 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:05,093 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:05,093 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:05,094 INFO L87 Difference]: Start difference. First operand 1168 states and 1539 transitions. Second operand 3 states. [2019-11-15 22:47:05,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:05,224 INFO L93 Difference]: Finished difference Result 3182 states and 4193 transitions. [2019-11-15 22:47:05,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:05,224 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-11-15 22:47:05,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:05,236 INFO L225 Difference]: With dead ends: 3182 [2019-11-15 22:47:05,236 INFO L226 Difference]: Without dead ends: 2132 [2019-11-15 22:47:05,238 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:05,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2132 states. [2019-11-15 22:47:05,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2132 to 2034. [2019-11-15 22:47:05,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2034 states. [2019-11-15 22:47:05,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2034 states to 2034 states and 2664 transitions. [2019-11-15 22:47:05,330 INFO L78 Accepts]: Start accepts. Automaton has 2034 states and 2664 transitions. Word has length 74 [2019-11-15 22:47:05,331 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:05,331 INFO L462 AbstractCegarLoop]: Abstraction has 2034 states and 2664 transitions. [2019-11-15 22:47:05,331 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:05,331 INFO L276 IsEmpty]: Start isEmpty. Operand 2034 states and 2664 transitions. [2019-11-15 22:47:05,332 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-15 22:47:05,332 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:05,332 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:05,333 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:05,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:05,333 INFO L82 PathProgramCache]: Analyzing trace with hash 1027993841, now seen corresponding path program 1 times [2019-11-15 22:47:05,333 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:05,333 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623293225] [2019-11-15 22:47:05,334 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:05,334 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:05,334 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:05,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:05,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:05,360 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623293225] [2019-11-15 22:47:05,360 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:05,360 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:47:05,360 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1750242939] [2019-11-15 22:47:05,361 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:05,361 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:05,361 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:05,361 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:05,362 INFO L87 Difference]: Start difference. First operand 2034 states and 2664 transitions. Second operand 3 states. [2019-11-15 22:47:05,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:05,550 INFO L93 Difference]: Finished difference Result 5772 states and 7544 transitions. [2019-11-15 22:47:05,551 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:05,551 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2019-11-15 22:47:05,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:05,571 INFO L225 Difference]: With dead ends: 5772 [2019-11-15 22:47:05,571 INFO L226 Difference]: Without dead ends: 3856 [2019-11-15 22:47:05,575 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:05,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3856 states. [2019-11-15 22:47:05,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3856 to 3718. [2019-11-15 22:47:05,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3718 states. [2019-11-15 22:47:05,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3718 states to 3718 states and 4834 transitions. [2019-11-15 22:47:05,743 INFO L78 Accepts]: Start accepts. Automaton has 3718 states and 4834 transitions. Word has length 75 [2019-11-15 22:47:05,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:05,744 INFO L462 AbstractCegarLoop]: Abstraction has 3718 states and 4834 transitions. [2019-11-15 22:47:05,744 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:05,744 INFO L276 IsEmpty]: Start isEmpty. Operand 3718 states and 4834 transitions. [2019-11-15 22:47:05,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-15 22:47:05,746 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:05,746 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:05,747 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:05,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:05,747 INFO L82 PathProgramCache]: Analyzing trace with hash -934868943, now seen corresponding path program 1 times [2019-11-15 22:47:05,747 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:05,747 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242072553] [2019-11-15 22:47:05,748 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:05,748 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:05,748 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:05,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:05,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:05,765 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242072553] [2019-11-15 22:47:05,765 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:05,765 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:47:05,766 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [995744253] [2019-11-15 22:47:05,766 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:05,766 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:05,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:05,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:05,766 INFO L87 Difference]: Start difference. First operand 3718 states and 4834 transitions. Second operand 3 states. [2019-11-15 22:47:05,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:05,974 INFO L93 Difference]: Finished difference Result 7254 states and 9443 transitions. [2019-11-15 22:47:05,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:05,975 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2019-11-15 22:47:05,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:05,994 INFO L225 Difference]: With dead ends: 7254 [2019-11-15 22:47:05,995 INFO L226 Difference]: Without dead ends: 3608 [2019-11-15 22:47:05,999 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:06,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3608 states. [2019-11-15 22:47:06,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3608 to 3608. [2019-11-15 22:47:06,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3608 states. [2019-11-15 22:47:06,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3608 states to 3608 states and 4698 transitions. [2019-11-15 22:47:06,167 INFO L78 Accepts]: Start accepts. Automaton has 3608 states and 4698 transitions. Word has length 75 [2019-11-15 22:47:06,167 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:06,167 INFO L462 AbstractCegarLoop]: Abstraction has 3608 states and 4698 transitions. [2019-11-15 22:47:06,167 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:06,167 INFO L276 IsEmpty]: Start isEmpty. Operand 3608 states and 4698 transitions. [2019-11-15 22:47:06,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-11-15 22:47:06,169 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:06,169 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:06,169 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:06,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:06,169 INFO L82 PathProgramCache]: Analyzing trace with hash -607730891, now seen corresponding path program 1 times [2019-11-15 22:47:06,170 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:06,170 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615078886] [2019-11-15 22:47:06,170 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:06,170 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:06,170 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:06,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:06,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:06,211 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1615078886] [2019-11-15 22:47:06,212 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:06,212 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:47:06,212 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129752032] [2019-11-15 22:47:06,212 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:06,213 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:06,213 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:06,213 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:06,213 INFO L87 Difference]: Start difference. First operand 3608 states and 4698 transitions. Second operand 3 states. [2019-11-15 22:47:06,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:06,523 INFO L93 Difference]: Finished difference Result 10194 states and 13246 transitions. [2019-11-15 22:47:06,524 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:06,524 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2019-11-15 22:47:06,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:06,561 INFO L225 Difference]: With dead ends: 10194 [2019-11-15 22:47:06,561 INFO L226 Difference]: Without dead ends: 6704 [2019-11-15 22:47:06,568 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:06,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6704 states. [2019-11-15 22:47:06,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6704 to 6542. [2019-11-15 22:47:06,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6542 states. [2019-11-15 22:47:06,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6542 states to 6542 states and 8460 transitions. [2019-11-15 22:47:06,954 INFO L78 Accepts]: Start accepts. Automaton has 6542 states and 8460 transitions. Word has length 76 [2019-11-15 22:47:06,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:06,954 INFO L462 AbstractCegarLoop]: Abstraction has 6542 states and 8460 transitions. [2019-11-15 22:47:06,955 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:06,955 INFO L276 IsEmpty]: Start isEmpty. Operand 6542 states and 8460 transitions. [2019-11-15 22:47:06,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-11-15 22:47:06,957 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:06,957 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:06,957 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:06,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:06,957 INFO L82 PathProgramCache]: Analyzing trace with hash 906360113, now seen corresponding path program 1 times [2019-11-15 22:47:06,957 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:06,958 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950724670] [2019-11-15 22:47:06,958 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:06,958 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:06,958 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:06,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:06,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:06,974 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950724670] [2019-11-15 22:47:06,975 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:06,975 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:47:06,975 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1429183584] [2019-11-15 22:47:06,975 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:06,975 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:06,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:06,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:06,976 INFO L87 Difference]: Start difference. First operand 6542 states and 8460 transitions. Second operand 3 states. [2019-11-15 22:47:07,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:07,258 INFO L93 Difference]: Finished difference Result 12890 states and 16683 transitions. [2019-11-15 22:47:07,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:07,258 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2019-11-15 22:47:07,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:07,298 INFO L225 Difference]: With dead ends: 12890 [2019-11-15 22:47:07,298 INFO L226 Difference]: Without dead ends: 6434 [2019-11-15 22:47:07,307 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:07,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6434 states. [2019-11-15 22:47:07,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6434 to 6434. [2019-11-15 22:47:07,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6434 states. [2019-11-15 22:47:07,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6434 states to 6434 states and 8328 transitions. [2019-11-15 22:47:07,605 INFO L78 Accepts]: Start accepts. Automaton has 6434 states and 8328 transitions. Word has length 76 [2019-11-15 22:47:07,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:07,606 INFO L462 AbstractCegarLoop]: Abstraction has 6434 states and 8328 transitions. [2019-11-15 22:47:07,606 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:07,606 INFO L276 IsEmpty]: Start isEmpty. Operand 6434 states and 8328 transitions. [2019-11-15 22:47:07,607 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2019-11-15 22:47:07,607 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:07,608 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:07,608 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:07,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:07,608 INFO L82 PathProgramCache]: Analyzing trace with hash 675279555, now seen corresponding path program 1 times [2019-11-15 22:47:07,609 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:07,609 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929037137] [2019-11-15 22:47:07,609 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:07,609 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:07,609 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:07,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:07,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:07,653 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929037137] [2019-11-15 22:47:07,654 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:07,654 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:07,654 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2104081327] [2019-11-15 22:47:07,655 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:07,655 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:07,655 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:07,655 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:07,655 INFO L87 Difference]: Start difference. First operand 6434 states and 8328 transitions. Second operand 3 states. [2019-11-15 22:47:08,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:08,171 INFO L93 Difference]: Finished difference Result 18946 states and 24537 transitions. [2019-11-15 22:47:08,172 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:08,172 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 77 [2019-11-15 22:47:08,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:08,195 INFO L225 Difference]: With dead ends: 18946 [2019-11-15 22:47:08,195 INFO L226 Difference]: Without dead ends: 12602 [2019-11-15 22:47:08,206 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:08,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12602 states. [2019-11-15 22:47:08,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12602 to 12538. [2019-11-15 22:47:08,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12538 states. [2019-11-15 22:47:08,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12538 states to 12538 states and 16110 transitions. [2019-11-15 22:47:08,769 INFO L78 Accepts]: Start accepts. Automaton has 12538 states and 16110 transitions. Word has length 77 [2019-11-15 22:47:08,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:08,769 INFO L462 AbstractCegarLoop]: Abstraction has 12538 states and 16110 transitions. [2019-11-15 22:47:08,769 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:08,770 INFO L276 IsEmpty]: Start isEmpty. Operand 12538 states and 16110 transitions. [2019-11-15 22:47:08,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-11-15 22:47:08,774 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:08,774 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:08,775 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:08,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:08,775 INFO L82 PathProgramCache]: Analyzing trace with hash -1687722621, now seen corresponding path program 1 times [2019-11-15 22:47:08,775 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:08,775 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574937468] [2019-11-15 22:47:08,775 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:08,776 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:08,776 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:08,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:08,816 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:08,816 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574937468] [2019-11-15 22:47:08,816 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:08,816 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:47:08,817 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1440159574] [2019-11-15 22:47:08,817 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:08,817 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:08,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:08,817 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:08,818 INFO L87 Difference]: Start difference. First operand 12538 states and 16110 transitions. Second operand 3 states. [2019-11-15 22:47:09,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:09,839 INFO L93 Difference]: Finished difference Result 37260 states and 47825 transitions. [2019-11-15 22:47:09,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:09,839 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 96 [2019-11-15 22:47:09,839 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:09,882 INFO L225 Difference]: With dead ends: 37260 [2019-11-15 22:47:09,882 INFO L226 Difference]: Without dead ends: 24838 [2019-11-15 22:47:09,897 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:09,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24838 states. [2019-11-15 22:47:10,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24838 to 24838. [2019-11-15 22:47:10,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24838 states. [2019-11-15 22:47:10,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24838 states to 24838 states and 31776 transitions. [2019-11-15 22:47:10,804 INFO L78 Accepts]: Start accepts. Automaton has 24838 states and 31776 transitions. Word has length 96 [2019-11-15 22:47:10,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:10,805 INFO L462 AbstractCegarLoop]: Abstraction has 24838 states and 31776 transitions. [2019-11-15 22:47:10,805 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:10,805 INFO L276 IsEmpty]: Start isEmpty. Operand 24838 states and 31776 transitions. [2019-11-15 22:47:10,829 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-11-15 22:47:10,830 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:10,830 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:10,830 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:10,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:10,831 INFO L82 PathProgramCache]: Analyzing trace with hash 393922111, now seen corresponding path program 1 times [2019-11-15 22:47:10,831 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:10,831 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475268062] [2019-11-15 22:47:10,831 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:10,831 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:10,832 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:10,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:11,031 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-15 22:47:11,032 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475268062] [2019-11-15 22:47:11,032 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:11,032 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:11,032 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458446357] [2019-11-15 22:47:11,034 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:11,034 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:11,034 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:11,034 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:11,035 INFO L87 Difference]: Start difference. First operand 24838 states and 31776 transitions. Second operand 3 states. [2019-11-15 22:47:12,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:12,248 INFO L93 Difference]: Finished difference Result 60602 states and 77478 transitions. [2019-11-15 22:47:12,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:12,248 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-11-15 22:47:12,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:12,318 INFO L225 Difference]: With dead ends: 60602 [2019-11-15 22:47:12,318 INFO L226 Difference]: Without dead ends: 35876 [2019-11-15 22:47:12,357 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:12,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35876 states. [2019-11-15 22:47:13,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35876 to 35746. [2019-11-15 22:47:13,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35746 states. [2019-11-15 22:47:13,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35746 states to 35746 states and 45448 transitions. [2019-11-15 22:47:13,729 INFO L78 Accepts]: Start accepts. Automaton has 35746 states and 45448 transitions. Word has length 131 [2019-11-15 22:47:13,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:13,729 INFO L462 AbstractCegarLoop]: Abstraction has 35746 states and 45448 transitions. [2019-11-15 22:47:13,729 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:13,730 INFO L276 IsEmpty]: Start isEmpty. Operand 35746 states and 45448 transitions. [2019-11-15 22:47:13,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-11-15 22:47:13,754 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:13,754 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:13,755 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:13,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:13,755 INFO L82 PathProgramCache]: Analyzing trace with hash 760471151, now seen corresponding path program 1 times [2019-11-15 22:47:13,755 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:13,756 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451720264] [2019-11-15 22:47:13,756 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:13,756 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:13,756 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:13,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:13,807 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-15 22:47:13,808 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451720264] [2019-11-15 22:47:13,808 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:13,808 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:13,808 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [665071148] [2019-11-15 22:47:13,809 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:13,809 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:13,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:13,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:13,810 INFO L87 Difference]: Start difference. First operand 35746 states and 45448 transitions. Second operand 3 states. [2019-11-15 22:47:15,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:15,292 INFO L93 Difference]: Finished difference Result 87290 states and 110962 transitions. [2019-11-15 22:47:15,292 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:15,293 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-11-15 22:47:15,293 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:15,398 INFO L225 Difference]: With dead ends: 87290 [2019-11-15 22:47:15,398 INFO L226 Difference]: Without dead ends: 51680 [2019-11-15 22:47:15,436 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:15,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51680 states. [2019-11-15 22:47:16,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51680 to 51486. [2019-11-15 22:47:16,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51486 states. [2019-11-15 22:47:16,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51486 states to 51486 states and 65112 transitions. [2019-11-15 22:47:16,995 INFO L78 Accepts]: Start accepts. Automaton has 51486 states and 65112 transitions. Word has length 131 [2019-11-15 22:47:16,995 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:16,995 INFO L462 AbstractCegarLoop]: Abstraction has 51486 states and 65112 transitions. [2019-11-15 22:47:16,995 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:16,995 INFO L276 IsEmpty]: Start isEmpty. Operand 51486 states and 65112 transitions. [2019-11-15 22:47:17,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-11-15 22:47:17,018 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:17,019 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:17,019 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:17,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:17,019 INFO L82 PathProgramCache]: Analyzing trace with hash -776225517, now seen corresponding path program 1 times [2019-11-15 22:47:17,020 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:17,020 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868798277] [2019-11-15 22:47:17,020 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:17,020 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:17,020 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:17,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:17,072 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-11-15 22:47:17,073 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868798277] [2019-11-15 22:47:17,073 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:17,073 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 22:47:17,073 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048658286] [2019-11-15 22:47:17,074 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:17,074 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:17,074 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:17,074 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:17,074 INFO L87 Difference]: Start difference. First operand 51486 states and 65112 transitions. Second operand 3 states. [2019-11-15 22:47:18,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:18,938 INFO L93 Difference]: Finished difference Result 125690 states and 158770 transitions. [2019-11-15 22:47:18,939 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:18,939 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-11-15 22:47:18,939 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:19,087 INFO L225 Difference]: With dead ends: 125690 [2019-11-15 22:47:19,087 INFO L226 Difference]: Without dead ends: 74288 [2019-11-15 22:47:19,134 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:19,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74288 states. [2019-11-15 22:47:21,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74288 to 73998. [2019-11-15 22:47:21,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73998 states. [2019-11-15 22:47:21,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73998 states to 73998 states and 92936 transitions. [2019-11-15 22:47:21,169 INFO L78 Accepts]: Start accepts. Automaton has 73998 states and 92936 transitions. Word has length 131 [2019-11-15 22:47:21,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:21,169 INFO L462 AbstractCegarLoop]: Abstraction has 73998 states and 92936 transitions. [2019-11-15 22:47:21,169 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:21,169 INFO L276 IsEmpty]: Start isEmpty. Operand 73998 states and 92936 transitions. [2019-11-15 22:47:21,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-11-15 22:47:21,195 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:21,195 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:21,195 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:21,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:21,196 INFO L82 PathProgramCache]: Analyzing trace with hash 216677618, now seen corresponding path program 1 times [2019-11-15 22:47:21,196 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:21,196 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1196041274] [2019-11-15 22:47:21,196 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:21,196 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:21,196 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:21,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:21,257 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-15 22:47:21,257 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1196041274] [2019-11-15 22:47:21,258 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:21,258 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 22:47:21,258 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888635276] [2019-11-15 22:47:21,259 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:47:21,259 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:21,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:47:21,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:47:21,259 INFO L87 Difference]: Start difference. First operand 73998 states and 92936 transitions. Second operand 5 states. [2019-11-15 22:47:24,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:24,540 INFO L93 Difference]: Finished difference Result 179776 states and 227199 transitions. [2019-11-15 22:47:24,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 22:47:24,542 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 131 [2019-11-15 22:47:24,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:24,684 INFO L225 Difference]: With dead ends: 179776 [2019-11-15 22:47:24,684 INFO L226 Difference]: Without dead ends: 105878 [2019-11-15 22:47:24,749 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 22:47:24,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105878 states. [2019-11-15 22:47:27,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105878 to 74430. [2019-11-15 22:47:27,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74430 states. [2019-11-15 22:47:27,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74430 states to 74430 states and 92212 transitions. [2019-11-15 22:47:27,249 INFO L78 Accepts]: Start accepts. Automaton has 74430 states and 92212 transitions. Word has length 131 [2019-11-15 22:47:27,249 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:27,249 INFO L462 AbstractCegarLoop]: Abstraction has 74430 states and 92212 transitions. [2019-11-15 22:47:27,250 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:47:27,250 INFO L276 IsEmpty]: Start isEmpty. Operand 74430 states and 92212 transitions. [2019-11-15 22:47:27,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-11-15 22:47:27,269 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:27,270 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:27,270 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:27,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:27,270 INFO L82 PathProgramCache]: Analyzing trace with hash -1889102986, now seen corresponding path program 1 times [2019-11-15 22:47:27,270 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:27,270 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885280173] [2019-11-15 22:47:27,270 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:27,271 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:27,271 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:27,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:27,317 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:27,318 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885280173] [2019-11-15 22:47:27,318 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:27,318 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:47:27,318 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1578573037] [2019-11-15 22:47:27,319 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:27,319 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:27,319 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:27,319 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:27,319 INFO L87 Difference]: Start difference. First operand 74430 states and 92212 transitions. Second operand 3 states. [2019-11-15 22:47:30,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:30,936 INFO L93 Difference]: Finished difference Result 112028 states and 139157 transitions. [2019-11-15 22:47:30,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:30,936 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-11-15 22:47:30,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:31,001 INFO L225 Difference]: With dead ends: 112028 [2019-11-15 22:47:31,001 INFO L226 Difference]: Without dead ends: 74430 [2019-11-15 22:47:31,026 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:31,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74430 states. [2019-11-15 22:47:33,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74430 to 74216. [2019-11-15 22:47:33,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74216 states. [2019-11-15 22:47:33,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74216 states to 74216 states and 91134 transitions. [2019-11-15 22:47:33,202 INFO L78 Accepts]: Start accepts. Automaton has 74216 states and 91134 transitions. Word has length 131 [2019-11-15 22:47:33,203 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:33,203 INFO L462 AbstractCegarLoop]: Abstraction has 74216 states and 91134 transitions. [2019-11-15 22:47:33,203 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:47:33,203 INFO L276 IsEmpty]: Start isEmpty. Operand 74216 states and 91134 transitions. [2019-11-15 22:47:33,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-11-15 22:47:33,225 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:33,225 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:33,225 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:33,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:33,226 INFO L82 PathProgramCache]: Analyzing trace with hash 1177275041, now seen corresponding path program 1 times [2019-11-15 22:47:33,226 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:33,226 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021696070] [2019-11-15 22:47:33,226 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:33,227 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:33,227 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:33,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:33,617 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2019-11-15 22:47:33,617 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2021696070] [2019-11-15 22:47:33,618 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:33,618 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 22:47:33,618 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1457447913] [2019-11-15 22:47:33,618 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:47:33,619 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:33,619 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:47:33,620 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:47:33,620 INFO L87 Difference]: Start difference. First operand 74216 states and 91134 transitions. Second operand 5 states. [2019-11-15 22:47:37,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:37,102 INFO L93 Difference]: Finished difference Result 172884 states and 213543 transitions. [2019-11-15 22:47:37,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 22:47:37,103 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-11-15 22:47:37,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:37,202 INFO L225 Difference]: With dead ends: 172884 [2019-11-15 22:47:37,203 INFO L226 Difference]: Without dead ends: 98792 [2019-11-15 22:47:37,251 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 22:47:37,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98792 states. [2019-11-15 22:47:40,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98792 to 74504. [2019-11-15 22:47:40,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74504 states. [2019-11-15 22:47:40,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74504 states to 74504 states and 90218 transitions. [2019-11-15 22:47:40,218 INFO L78 Accepts]: Start accepts. Automaton has 74504 states and 90218 transitions. Word has length 132 [2019-11-15 22:47:40,218 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:40,218 INFO L462 AbstractCegarLoop]: Abstraction has 74504 states and 90218 transitions. [2019-11-15 22:47:40,218 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:47:40,218 INFO L276 IsEmpty]: Start isEmpty. Operand 74504 states and 90218 transitions. [2019-11-15 22:47:40,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-11-15 22:47:40,239 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:40,240 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:40,240 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:40,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:40,240 INFO L82 PathProgramCache]: Analyzing trace with hash -1238601315, now seen corresponding path program 1 times [2019-11-15 22:47:40,241 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:40,241 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255007208] [2019-11-15 22:47:40,241 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:40,241 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:40,241 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:40,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:40,311 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2019-11-15 22:47:40,312 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1255007208] [2019-11-15 22:47:40,312 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:40,312 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 22:47:40,312 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540780038] [2019-11-15 22:47:40,313 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:47:40,313 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:40,313 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:47:40,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:47:40,314 INFO L87 Difference]: Start difference. First operand 74504 states and 90218 transitions. Second operand 5 states. [2019-11-15 22:47:44,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:44,331 INFO L93 Difference]: Finished difference Result 176172 states and 214583 transitions. [2019-11-15 22:47:44,331 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 22:47:44,332 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-11-15 22:47:44,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:44,430 INFO L225 Difference]: With dead ends: 176172 [2019-11-15 22:47:44,430 INFO L226 Difference]: Without dead ends: 101816 [2019-11-15 22:47:44,468 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 22:47:44,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101816 states. [2019-11-15 22:47:47,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101816 to 74792. [2019-11-15 22:47:47,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74792 states. [2019-11-15 22:47:47,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74792 states to 74792 states and 89302 transitions. [2019-11-15 22:47:47,865 INFO L78 Accepts]: Start accepts. Automaton has 74792 states and 89302 transitions. Word has length 132 [2019-11-15 22:47:47,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:47,866 INFO L462 AbstractCegarLoop]: Abstraction has 74792 states and 89302 transitions. [2019-11-15 22:47:47,866 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:47:47,866 INFO L276 IsEmpty]: Start isEmpty. Operand 74792 states and 89302 transitions. [2019-11-15 22:47:47,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-11-15 22:47:47,887 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:47,887 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:47,887 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:47,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:47,888 INFO L82 PathProgramCache]: Analyzing trace with hash -1048246887, now seen corresponding path program 1 times [2019-11-15 22:47:47,888 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:47,888 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999752870] [2019-11-15 22:47:47,888 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:47,889 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:47,889 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:47,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:47,958 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2019-11-15 22:47:47,959 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [999752870] [2019-11-15 22:47:47,959 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:47,959 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 22:47:47,959 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1441579866] [2019-11-15 22:47:47,960 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:47:47,960 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:47,961 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:47:47,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:47:47,961 INFO L87 Difference]: Start difference. First operand 74792 states and 89302 transitions. Second operand 5 states. [2019-11-15 22:47:53,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:53,207 INFO L93 Difference]: Finished difference Result 144386 states and 173411 transitions. [2019-11-15 22:47:53,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 22:47:53,208 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-11-15 22:47:53,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:53,288 INFO L225 Difference]: With dead ends: 144386 [2019-11-15 22:47:53,289 INFO L226 Difference]: Without dead ends: 69686 [2019-11-15 22:47:53,331 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 22:47:53,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69686 states. [2019-11-15 22:47:56,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69686 to 50828. [2019-11-15 22:47:56,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50828 states. [2019-11-15 22:47:56,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50828 states to 50828 states and 59968 transitions. [2019-11-15 22:47:56,311 INFO L78 Accepts]: Start accepts. Automaton has 50828 states and 59968 transitions. Word has length 132 [2019-11-15 22:47:56,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:47:56,311 INFO L462 AbstractCegarLoop]: Abstraction has 50828 states and 59968 transitions. [2019-11-15 22:47:56,311 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:47:56,311 INFO L276 IsEmpty]: Start isEmpty. Operand 50828 states and 59968 transitions. [2019-11-15 22:47:56,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-15 22:47:56,322 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:47:56,322 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:47:56,322 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:47:56,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:47:56,322 INFO L82 PathProgramCache]: Analyzing trace with hash -307341713, now seen corresponding path program 1 times [2019-11-15 22:47:56,322 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:47:56,323 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361298149] [2019-11-15 22:47:56,323 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:56,323 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:47:56,323 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:47:56,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:47:56,361 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:47:56,361 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361298149] [2019-11-15 22:47:56,361 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:47:56,362 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:47:56,362 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384570959] [2019-11-15 22:47:56,362 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:47:56,362 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:47:56,363 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:47:56,363 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:56,363 INFO L87 Difference]: Start difference. First operand 50828 states and 59968 transitions. Second operand 3 states. [2019-11-15 22:47:58,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:47:58,463 INFO L93 Difference]: Finished difference Result 81694 states and 96668 transitions. [2019-11-15 22:47:58,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:47:58,463 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2019-11-15 22:47:58,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:47:58,500 INFO L225 Difference]: With dead ends: 81694 [2019-11-15 22:47:58,500 INFO L226 Difference]: Without dead ends: 42420 [2019-11-15 22:47:58,522 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:47:58,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42420 states. [2019-11-15 22:48:00,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42420 to 42416. [2019-11-15 22:48:00,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42416 states. [2019-11-15 22:48:00,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42416 states to 42416 states and 50000 transitions. [2019-11-15 22:48:00,725 INFO L78 Accepts]: Start accepts. Automaton has 42416 states and 50000 transitions. Word has length 134 [2019-11-15 22:48:00,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:48:00,725 INFO L462 AbstractCegarLoop]: Abstraction has 42416 states and 50000 transitions. [2019-11-15 22:48:00,726 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:48:00,726 INFO L276 IsEmpty]: Start isEmpty. Operand 42416 states and 50000 transitions. [2019-11-15 22:48:00,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2019-11-15 22:48:00,740 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:48:00,740 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:48:00,740 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:48:00,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:48:00,741 INFO L82 PathProgramCache]: Analyzing trace with hash -451521753, now seen corresponding path program 1 times [2019-11-15 22:48:00,741 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:48:00,741 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984010169] [2019-11-15 22:48:00,741 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:00,742 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:00,742 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:48:00,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:48:00,791 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:48:00,791 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984010169] [2019-11-15 22:48:00,791 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:48:00,791 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:48:00,792 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713518973] [2019-11-15 22:48:00,792 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:48:00,792 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:48:00,792 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:48:00,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:00,793 INFO L87 Difference]: Start difference. First operand 42416 states and 50000 transitions. Second operand 3 states. [2019-11-15 22:48:02,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:48:02,457 INFO L93 Difference]: Finished difference Result 69170 states and 81824 transitions. [2019-11-15 22:48:02,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:48:02,458 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 173 [2019-11-15 22:48:02,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:48:02,494 INFO L225 Difference]: With dead ends: 69170 [2019-11-15 22:48:02,494 INFO L226 Difference]: Without dead ends: 33872 [2019-11-15 22:48:02,519 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:02,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33872 states. [2019-11-15 22:48:04,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33872 to 33868. [2019-11-15 22:48:04,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33868 states. [2019-11-15 22:48:04,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33868 states to 33868 states and 39884 transitions. [2019-11-15 22:48:04,280 INFO L78 Accepts]: Start accepts. Automaton has 33868 states and 39884 transitions. Word has length 173 [2019-11-15 22:48:04,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:48:04,280 INFO L462 AbstractCegarLoop]: Abstraction has 33868 states and 39884 transitions. [2019-11-15 22:48:04,280 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:48:04,281 INFO L276 IsEmpty]: Start isEmpty. Operand 33868 states and 39884 transitions. [2019-11-15 22:48:04,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2019-11-15 22:48:04,292 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:48:04,292 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:48:04,292 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:48:04,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:48:04,292 INFO L82 PathProgramCache]: Analyzing trace with hash -1942944609, now seen corresponding path program 1 times [2019-11-15 22:48:04,293 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:48:04,293 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193942221] [2019-11-15 22:48:04,293 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:04,293 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:04,293 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:48:04,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:48:04,349 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:48:04,349 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193942221] [2019-11-15 22:48:04,350 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:48:04,350 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:48:04,350 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1085316135] [2019-11-15 22:48:04,350 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:48:04,351 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:48:04,351 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:48:04,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:04,351 INFO L87 Difference]: Start difference. First operand 33868 states and 39884 transitions. Second operand 3 states. [2019-11-15 22:48:05,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:48:05,901 INFO L93 Difference]: Finished difference Result 63390 states and 74832 transitions. [2019-11-15 22:48:05,902 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:48:05,902 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 212 [2019-11-15 22:48:05,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:48:05,930 INFO L225 Difference]: With dead ends: 63390 [2019-11-15 22:48:05,930 INFO L226 Difference]: Without dead ends: 33872 [2019-11-15 22:48:05,946 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:05,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33872 states. [2019-11-15 22:48:08,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33872 to 33868. [2019-11-15 22:48:08,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33868 states. [2019-11-15 22:48:09,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33868 states to 33868 states and 39684 transitions. [2019-11-15 22:48:09,013 INFO L78 Accepts]: Start accepts. Automaton has 33868 states and 39684 transitions. Word has length 212 [2019-11-15 22:48:09,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:48:09,014 INFO L462 AbstractCegarLoop]: Abstraction has 33868 states and 39684 transitions. [2019-11-15 22:48:09,014 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:48:09,014 INFO L276 IsEmpty]: Start isEmpty. Operand 33868 states and 39684 transitions. [2019-11-15 22:48:09,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 249 [2019-11-15 22:48:09,025 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:48:09,026 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:48:09,026 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:48:09,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:48:09,026 INFO L82 PathProgramCache]: Analyzing trace with hash -980083650, now seen corresponding path program 1 times [2019-11-15 22:48:09,026 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:48:09,027 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81338679] [2019-11-15 22:48:09,027 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:09,027 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:09,027 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:48:09,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:48:09,101 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-15 22:48:09,101 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [81338679] [2019-11-15 22:48:09,101 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:48:09,101 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 22:48:09,102 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920744666] [2019-11-15 22:48:09,102 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-15 22:48:09,102 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:48:09,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 22:48:09,103 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 22:48:09,103 INFO L87 Difference]: Start difference. First operand 33868 states and 39684 transitions. Second operand 5 states. [2019-11-15 22:48:12,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:48:12,754 INFO L93 Difference]: Finished difference Result 107663 states and 125750 transitions. [2019-11-15 22:48:12,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 22:48:12,754 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 248 [2019-11-15 22:48:12,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:48:12,808 INFO L225 Difference]: With dead ends: 107663 [2019-11-15 22:48:12,808 INFO L226 Difference]: Without dead ends: 73872 [2019-11-15 22:48:12,824 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-15 22:48:12,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73872 states. [2019-11-15 22:48:14,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73872 to 34876. [2019-11-15 22:48:14,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34876 states. [2019-11-15 22:48:14,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34876 states to 34876 states and 40450 transitions. [2019-11-15 22:48:14,755 INFO L78 Accepts]: Start accepts. Automaton has 34876 states and 40450 transitions. Word has length 248 [2019-11-15 22:48:14,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:48:14,756 INFO L462 AbstractCegarLoop]: Abstraction has 34876 states and 40450 transitions. [2019-11-15 22:48:14,756 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-15 22:48:14,756 INFO L276 IsEmpty]: Start isEmpty. Operand 34876 states and 40450 transitions. [2019-11-15 22:48:14,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 249 [2019-11-15 22:48:14,767 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:48:14,768 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:48:14,768 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:48:14,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:48:14,768 INFO L82 PathProgramCache]: Analyzing trace with hash -1127279802, now seen corresponding path program 1 times [2019-11-15 22:48:14,768 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:48:14,769 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673394280] [2019-11-15 22:48:14,769 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:14,769 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:14,769 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:48:14,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:48:14,835 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:48:14,836 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673394280] [2019-11-15 22:48:14,836 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:48:14,836 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:48:14,836 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [584936692] [2019-11-15 22:48:14,837 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:48:14,837 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:48:14,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:48:14,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:14,837 INFO L87 Difference]: Start difference. First operand 34876 states and 40450 transitions. Second operand 3 states. [2019-11-15 22:48:16,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:48:16,860 INFO L93 Difference]: Finished difference Result 62462 states and 72623 transitions. [2019-11-15 22:48:16,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:48:16,861 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 248 [2019-11-15 22:48:16,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:48:16,886 INFO L225 Difference]: With dead ends: 62462 [2019-11-15 22:48:16,886 INFO L226 Difference]: Without dead ends: 34940 [2019-11-15 22:48:16,898 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:16,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34940 states. [2019-11-15 22:48:18,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34940 to 34876. [2019-11-15 22:48:18,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34876 states. [2019-11-15 22:48:18,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34876 states to 34876 states and 39858 transitions. [2019-11-15 22:48:18,762 INFO L78 Accepts]: Start accepts. Automaton has 34876 states and 39858 transitions. Word has length 248 [2019-11-15 22:48:18,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:48:18,762 INFO L462 AbstractCegarLoop]: Abstraction has 34876 states and 39858 transitions. [2019-11-15 22:48:18,762 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:48:18,762 INFO L276 IsEmpty]: Start isEmpty. Operand 34876 states and 39858 transitions. [2019-11-15 22:48:18,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 252 [2019-11-15 22:48:18,774 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:48:18,774 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:48:18,775 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:48:18,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:48:18,775 INFO L82 PathProgramCache]: Analyzing trace with hash -301505065, now seen corresponding path program 1 times [2019-11-15 22:48:18,775 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:48:18,777 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960689927] [2019-11-15 22:48:18,777 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:18,777 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:18,778 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:48:18,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:48:18,850 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:48:18,854 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1960689927] [2019-11-15 22:48:18,855 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:48:18,856 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:48:18,856 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306075946] [2019-11-15 22:48:18,856 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:48:18,857 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:48:18,857 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:48:18,857 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:18,858 INFO L87 Difference]: Start difference. First operand 34876 states and 39858 transitions. Second operand 3 states. [2019-11-15 22:48:20,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:48:20,911 INFO L93 Difference]: Finished difference Result 59234 states and 67843 transitions. [2019-11-15 22:48:20,912 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:48:20,912 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 251 [2019-11-15 22:48:20,912 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:48:20,937 INFO L225 Difference]: With dead ends: 59234 [2019-11-15 22:48:20,937 INFO L226 Difference]: Without dead ends: 34940 [2019-11-15 22:48:20,949 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:20,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34940 states. [2019-11-15 22:48:22,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34940 to 34876. [2019-11-15 22:48:22,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34876 states. [2019-11-15 22:48:22,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34876 states to 34876 states and 39354 transitions. [2019-11-15 22:48:22,817 INFO L78 Accepts]: Start accepts. Automaton has 34876 states and 39354 transitions. Word has length 251 [2019-11-15 22:48:22,817 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:48:22,817 INFO L462 AbstractCegarLoop]: Abstraction has 34876 states and 39354 transitions. [2019-11-15 22:48:22,817 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:48:22,817 INFO L276 IsEmpty]: Start isEmpty. Operand 34876 states and 39354 transitions. [2019-11-15 22:48:22,829 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2019-11-15 22:48:22,830 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:48:22,830 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:48:22,830 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:48:22,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:48:22,830 INFO L82 PathProgramCache]: Analyzing trace with hash 391416485, now seen corresponding path program 1 times [2019-11-15 22:48:22,830 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:48:22,830 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916497472] [2019-11-15 22:48:22,831 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:22,831 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:22,831 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:48:22,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:48:22,898 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-15 22:48:22,898 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916497472] [2019-11-15 22:48:22,898 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:48:22,899 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:48:22,899 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [197729630] [2019-11-15 22:48:22,899 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:48:22,899 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:48:22,899 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:48:22,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:22,900 INFO L87 Difference]: Start difference. First operand 34876 states and 39354 transitions. Second operand 3 states. [2019-11-15 22:48:24,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:48:24,561 INFO L93 Difference]: Finished difference Result 62718 states and 70361 transitions. [2019-11-15 22:48:24,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:48:24,561 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 254 [2019-11-15 22:48:24,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:48:24,574 INFO L225 Difference]: With dead ends: 62718 [2019-11-15 22:48:24,574 INFO L226 Difference]: Without dead ends: 16774 [2019-11-15 22:48:24,591 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:24,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16774 states. [2019-11-15 22:48:25,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16774 to 16254. [2019-11-15 22:48:25,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16254 states. [2019-11-15 22:48:25,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16254 states to 16254 states and 17772 transitions. [2019-11-15 22:48:25,480 INFO L78 Accepts]: Start accepts. Automaton has 16254 states and 17772 transitions. Word has length 254 [2019-11-15 22:48:25,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:48:25,481 INFO L462 AbstractCegarLoop]: Abstraction has 16254 states and 17772 transitions. [2019-11-15 22:48:25,481 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:48:25,481 INFO L276 IsEmpty]: Start isEmpty. Operand 16254 states and 17772 transitions. [2019-11-15 22:48:25,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 258 [2019-11-15 22:48:25,491 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:48:25,492 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:48:25,492 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:48:25,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:48:25,492 INFO L82 PathProgramCache]: Analyzing trace with hash -1392087481, now seen corresponding path program 1 times [2019-11-15 22:48:25,492 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:48:25,492 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864722251] [2019-11-15 22:48:25,492 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:25,492 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:25,493 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:48:25,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 22:48:25,571 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 22:48:25,572 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864722251] [2019-11-15 22:48:25,572 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 22:48:25,572 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 22:48:25,572 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997499310] [2019-11-15 22:48:25,572 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-15 22:48:25,572 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 22:48:25,573 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 22:48:25,573 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:25,573 INFO L87 Difference]: Start difference. First operand 16254 states and 17772 transitions. Second operand 3 states. [2019-11-15 22:48:26,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 22:48:26,478 INFO L93 Difference]: Finished difference Result 28760 states and 31491 transitions. [2019-11-15 22:48:26,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 22:48:26,479 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 257 [2019-11-15 22:48:26,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-15 22:48:26,492 INFO L225 Difference]: With dead ends: 28760 [2019-11-15 22:48:26,492 INFO L226 Difference]: Without dead ends: 16254 [2019-11-15 22:48:26,500 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 22:48:26,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16254 states. [2019-11-15 22:48:27,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16254 to 16254. [2019-11-15 22:48:27,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16254 states. [2019-11-15 22:48:27,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16254 states to 16254 states and 17606 transitions. [2019-11-15 22:48:27,416 INFO L78 Accepts]: Start accepts. Automaton has 16254 states and 17606 transitions. Word has length 257 [2019-11-15 22:48:27,417 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-15 22:48:27,417 INFO L462 AbstractCegarLoop]: Abstraction has 16254 states and 17606 transitions. [2019-11-15 22:48:27,417 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-15 22:48:27,417 INFO L276 IsEmpty]: Start isEmpty. Operand 16254 states and 17606 transitions. [2019-11-15 22:48:27,426 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 261 [2019-11-15 22:48:27,426 INFO L372 BasicCegarLoop]: Found error trace [2019-11-15 22:48:27,427 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 22:48:27,427 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-15 22:48:27,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 22:48:27,427 INFO L82 PathProgramCache]: Analyzing trace with hash 1978087514, now seen corresponding path program 1 times [2019-11-15 22:48:27,427 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 22:48:27,427 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318905271] [2019-11-15 22:48:27,427 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:27,427 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 22:48:27,427 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 22:48:27,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 22:48:27,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 22:48:27,570 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 22:48:27,570 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-11-15 22:48:27,762 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 15.11 10:48:27 BoogieIcfgContainer [2019-11-15 22:48:27,762 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-15 22:48:27,763 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-15 22:48:27,763 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-15 22:48:27,763 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-15 22:48:27,764 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 10:47:02" (3/4) ... [2019-11-15 22:48:27,766 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-15 22:48:27,942 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_a4df28ae-285b-43a8-b52d-54a49eb04773/bin/uautomizer/witness.graphml [2019-11-15 22:48:27,942 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-15 22:48:27,944 INFO L168 Benchmark]: Toolchain (without parser) took 86850.34 ms. Allocated memory was 1.0 GB in the beginning and 5.6 GB in the end (delta: 4.6 GB). Free memory was 943.5 MB in the beginning and 1.5 GB in the end (delta: -526.9 MB). Peak memory consumption was 4.1 GB. Max. memory is 11.5 GB. [2019-11-15 22:48:27,945 INFO L168 Benchmark]: CDTParser took 0.23 ms. Allocated memory is still 1.0 GB. Free memory is still 966.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-15 22:48:27,945 INFO L168 Benchmark]: CACSL2BoogieTranslator took 445.64 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.6 MB). Free memory was 943.5 MB in the beginning and 1.1 GB in the end (delta: -187.6 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. [2019-11-15 22:48:27,946 INFO L168 Benchmark]: Boogie Procedure Inliner took 61.40 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-11-15 22:48:27,946 INFO L168 Benchmark]: Boogie Preprocessor took 76.85 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 11.5 GB. [2019-11-15 22:48:27,946 INFO L168 Benchmark]: RCFGBuilder took 1256.94 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 92.2 MB). Peak memory consumption was 92.2 MB. Max. memory is 11.5 GB. [2019-11-15 22:48:27,947 INFO L168 Benchmark]: TraceAbstraction took 84825.75 ms. Allocated memory was 1.2 GB in the beginning and 5.6 GB in the end (delta: 4.5 GB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -463.3 MB). Peak memory consumption was 4.0 GB. Max. memory is 11.5 GB. [2019-11-15 22:48:27,947 INFO L168 Benchmark]: Witness Printer took 179.73 ms. Allocated memory is still 5.6 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 25.0 MB). Peak memory consumption was 25.0 MB. Max. memory is 11.5 GB. [2019-11-15 22:48:27,949 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23 ms. Allocated memory is still 1.0 GB. Free memory is still 966.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 445.64 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.6 MB). Free memory was 943.5 MB in the beginning and 1.1 GB in the end (delta: -187.6 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 61.40 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 76.85 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1256.94 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 92.2 MB). Peak memory consumption was 92.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 84825.75 ms. Allocated memory was 1.2 GB in the beginning and 5.6 GB in the end (delta: 4.5 GB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -463.3 MB). Peak memory consumption was 4.0 GB. Max. memory is 11.5 GB. * Witness Printer took 179.73 ms. Allocated memory is still 5.6 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 25.0 MB). Peak memory consumption was 25.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L811] int __retres1 ; [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L331] COND TRUE m_i == 1 [L332] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L492] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L497] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L502] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L228] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L247] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L266] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L285] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L304] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L545] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L550] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L555] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L766] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L769] kernel_st = 1 [L397] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L401] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L90] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L101] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L125] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L136] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L160] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L171] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L195] COND TRUE t4_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L206] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L208] t4_pc = 1 [L209] t4_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L401] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND TRUE \read(tmp_ndt_1) [L416] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L49] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L60] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L63] E_1 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND TRUE E_1 == 1 [L249] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND TRUE \read(tmp___0) [L614] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L65] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L68] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L70] m_pc = 1 [L71] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L90] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L93] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L109] E_2 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND TRUE E_2 == 1 [L268] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND TRUE \read(tmp___1) [L622] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L111] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L101] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L125] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L128] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L144] E_3 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND TRUE E_3 == 1 [L287] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND TRUE \read(tmp___2) [L630] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L146] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L136] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L163] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L179] E_4 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND TRUE E_4 == 1 [L306] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND TRUE \read(tmp___3) [L638] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L181] E_4 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L171] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L195] COND FALSE !(t4_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L198] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 374 locations, 1 error locations. Result: UNSAFE, OverallTime: 84.7s, OverallIterations: 35, TraceHistogramMax: 2, AutomataDifference: 45.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 19229 SDtfs, 17991 SDslu, 12915 SDs, 0 SdLazy, 695 SolverSat, 359 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 113 GetRequests, 59 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=74792occurred in iteration=25, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 36.5s AutomataMinimizationTime, 34 MinimizatonAttempts, 142630 StatesRemovedByMinimization, 21 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 1.1s InterpolantComputationTime, 4440 NumberOfCodeBlocks, 4440 NumberOfCodeBlocksAsserted, 35 NumberOfCheckSat, 4146 ConstructedInterpolants, 0 QuantifiedInterpolants, 888600 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 34 InterpolantComputations, 34 PerfectInterpolantSequences, 352/352 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...