./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0e3598d1a4e9129bf22e72269576449e67f0febd ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-11-16 00:34:01,485 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-16 00:34:01,487 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-16 00:34:01,501 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-16 00:34:01,501 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-16 00:34:01,503 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-16 00:34:01,505 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-16 00:34:01,515 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-16 00:34:01,520 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-16 00:34:01,521 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-16 00:34:01,522 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-16 00:34:01,523 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-16 00:34:01,523 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-16 00:34:01,524 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-16 00:34:01,525 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-16 00:34:01,526 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-16 00:34:01,526 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-16 00:34:01,527 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-16 00:34:01,529 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-16 00:34:01,530 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-16 00:34:01,532 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-16 00:34:01,533 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-16 00:34:01,534 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-16 00:34:01,534 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-16 00:34:01,537 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-16 00:34:01,537 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-16 00:34:01,537 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-16 00:34:01,538 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-16 00:34:01,538 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-16 00:34:01,539 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-16 00:34:01,539 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-16 00:34:01,540 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-16 00:34:01,540 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-16 00:34:01,541 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-16 00:34:01,542 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-16 00:34:01,542 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-16 00:34:01,543 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-16 00:34:01,543 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-16 00:34:01,543 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-16 00:34:01,544 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-16 00:34:01,544 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-16 00:34:01,545 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-16 00:34:01,557 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-16 00:34:01,558 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-16 00:34:01,559 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-16 00:34:01,559 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-16 00:34:01,559 INFO L138 SettingsManager]: * Use SBE=true [2019-11-16 00:34:01,560 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-16 00:34:01,560 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-16 00:34:01,560 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-16 00:34:01,560 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-16 00:34:01,560 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-16 00:34:01,561 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-16 00:34:01,561 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-16 00:34:01,561 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-16 00:34:01,561 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-16 00:34:01,561 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-16 00:34:01,562 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-16 00:34:01,562 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-16 00:34:01,562 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-16 00:34:01,562 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-16 00:34:01,563 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-16 00:34:01,563 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-16 00:34:01,563 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-16 00:34:01,563 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-16 00:34:01,563 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-16 00:34:01,564 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-16 00:34:01,564 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-16 00:34:01,564 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-16 00:34:01,564 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-16 00:34:01,564 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0e3598d1a4e9129bf22e72269576449e67f0febd [2019-11-16 00:34:01,600 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-16 00:34:01,612 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-16 00:34:01,616 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-16 00:34:01,618 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-16 00:34:01,618 INFO L275 PluginConnector]: CDTParser initialized [2019-11-16 00:34:01,620 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2019-11-16 00:34:01,690 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/data/9bc9813d5/03f9702370964668be40157c33da1b1b/FLAGb01dd2097 [2019-11-16 00:34:02,203 INFO L306 CDTParser]: Found 1 translation units. [2019-11-16 00:34:02,204 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/sv-benchmarks/c/systemc/transmitter.15.cil.c [2019-11-16 00:34:02,228 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/data/9bc9813d5/03f9702370964668be40157c33da1b1b/FLAGb01dd2097 [2019-11-16 00:34:02,554 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/data/9bc9813d5/03f9702370964668be40157c33da1b1b [2019-11-16 00:34:02,557 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-16 00:34:02,564 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-16 00:34:02,565 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-16 00:34:02,565 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-16 00:34:02,570 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-16 00:34:02,571 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:34:02" (1/1) ... [2019-11-16 00:34:02,573 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4e6d2bfc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:02, skipping insertion in model container [2019-11-16 00:34:02,573 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:34:02" (1/1) ... [2019-11-16 00:34:02,580 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-16 00:34:02,637 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-16 00:34:03,010 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-16 00:34:03,032 INFO L188 MainTranslator]: Completed pre-run [2019-11-16 00:34:03,155 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-16 00:34:03,187 INFO L192 MainTranslator]: Completed translation [2019-11-16 00:34:03,194 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03 WrapperNode [2019-11-16 00:34:03,194 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-16 00:34:03,195 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-16 00:34:03,195 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-16 00:34:03,195 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-16 00:34:03,201 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03" (1/1) ... [2019-11-16 00:34:03,213 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03" (1/1) ... [2019-11-16 00:34:03,341 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-16 00:34:03,342 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-16 00:34:03,342 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-16 00:34:03,342 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-16 00:34:03,352 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03" (1/1) ... [2019-11-16 00:34:03,353 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03" (1/1) ... [2019-11-16 00:34:03,365 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03" (1/1) ... [2019-11-16 00:34:03,365 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03" (1/1) ... [2019-11-16 00:34:03,413 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03" (1/1) ... [2019-11-16 00:34:03,474 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03" (1/1) ... [2019-11-16 00:34:03,489 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03" (1/1) ... [2019-11-16 00:34:03,511 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-16 00:34:03,512 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-16 00:34:03,512 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-16 00:34:03,513 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-16 00:34:03,514 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-16 00:34:03,573 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-16 00:34:03,573 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-16 00:34:07,035 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-16 00:34:07,035 INFO L284 CfgBuilder]: Removed 589 assume(true) statements. [2019-11-16 00:34:07,038 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:34:07 BoogieIcfgContainer [2019-11-16 00:34:07,038 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-16 00:34:07,042 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-16 00:34:07,043 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-16 00:34:07,047 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-16 00:34:07,047 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 16.11 12:34:02" (1/3) ... [2019-11-16 00:34:07,051 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1bbccc45 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 12:34:07, skipping insertion in model container [2019-11-16 00:34:07,051 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:03" (2/3) ... [2019-11-16 00:34:07,051 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1bbccc45 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 12:34:07, skipping insertion in model container [2019-11-16 00:34:07,051 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:34:07" (3/3) ... [2019-11-16 00:34:07,053 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.15.cil.c [2019-11-16 00:34:07,069 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-16 00:34:07,080 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-16 00:34:07,093 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-16 00:34:07,144 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-16 00:34:07,145 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-16 00:34:07,145 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-16 00:34:07,145 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-16 00:34:07,145 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-16 00:34:07,145 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-16 00:34:07,145 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-16 00:34:07,146 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-16 00:34:07,191 INFO L276 IsEmpty]: Start isEmpty. Operand 1886 states. [2019-11-16 00:34:07,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:07,211 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:07,212 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:07,213 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:07,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:07,219 INFO L82 PathProgramCache]: Analyzing trace with hash 735925127, now seen corresponding path program 1 times [2019-11-16 00:34:07,226 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:07,227 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568495400] [2019-11-16 00:34:07,227 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:07,227 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:07,228 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:07,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:07,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:07,552 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568495400] [2019-11-16 00:34:07,553 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:07,553 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:34:07,554 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1482498601] [2019-11-16 00:34:07,559 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:07,560 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:07,572 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:07,573 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:07,575 INFO L87 Difference]: Start difference. First operand 1886 states. Second operand 3 states. [2019-11-16 00:34:07,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:07,709 INFO L93 Difference]: Finished difference Result 3767 states and 5677 transitions. [2019-11-16 00:34:07,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:07,711 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:07,712 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:07,741 INFO L225 Difference]: With dead ends: 3767 [2019-11-16 00:34:07,741 INFO L226 Difference]: Without dead ends: 1882 [2019-11-16 00:34:07,748 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:07,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1882 states. [2019-11-16 00:34:07,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1882 to 1882. [2019-11-16 00:34:07,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1882 states. [2019-11-16 00:34:07,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1882 states to 1882 states and 2802 transitions. [2019-11-16 00:34:07,944 INFO L78 Accepts]: Start accepts. Automaton has 1882 states and 2802 transitions. Word has length 167 [2019-11-16 00:34:07,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:07,944 INFO L462 AbstractCegarLoop]: Abstraction has 1882 states and 2802 transitions. [2019-11-16 00:34:07,944 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:07,944 INFO L276 IsEmpty]: Start isEmpty. Operand 1882 states and 2802 transitions. [2019-11-16 00:34:07,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:07,947 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:07,948 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:07,948 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:07,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:07,949 INFO L82 PathProgramCache]: Analyzing trace with hash 237368325, now seen corresponding path program 1 times [2019-11-16 00:34:07,949 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:07,949 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215446384] [2019-11-16 00:34:07,949 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:07,949 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:07,950 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:07,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:08,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:08,121 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215446384] [2019-11-16 00:34:08,122 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:08,122 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:34:08,122 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416398148] [2019-11-16 00:34:08,132 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:08,134 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:08,134 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:08,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:08,135 INFO L87 Difference]: Start difference. First operand 1882 states and 2802 transitions. Second operand 3 states. [2019-11-16 00:34:08,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:08,219 INFO L93 Difference]: Finished difference Result 3751 states and 5582 transitions. [2019-11-16 00:34:08,220 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:08,220 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:08,220 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:08,232 INFO L225 Difference]: With dead ends: 3751 [2019-11-16 00:34:08,232 INFO L226 Difference]: Without dead ends: 1882 [2019-11-16 00:34:08,237 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:08,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1882 states. [2019-11-16 00:34:08,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1882 to 1882. [2019-11-16 00:34:08,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1882 states. [2019-11-16 00:34:08,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1882 states to 1882 states and 2801 transitions. [2019-11-16 00:34:08,304 INFO L78 Accepts]: Start accepts. Automaton has 1882 states and 2801 transitions. Word has length 167 [2019-11-16 00:34:08,306 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:08,306 INFO L462 AbstractCegarLoop]: Abstraction has 1882 states and 2801 transitions. [2019-11-16 00:34:08,306 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:08,306 INFO L276 IsEmpty]: Start isEmpty. Operand 1882 states and 2801 transitions. [2019-11-16 00:34:08,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:08,316 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:08,316 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:08,316 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:08,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:08,317 INFO L82 PathProgramCache]: Analyzing trace with hash 2006839939, now seen corresponding path program 1 times [2019-11-16 00:34:08,317 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:08,318 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291668509] [2019-11-16 00:34:08,318 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:08,319 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:08,319 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:08,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:08,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:08,454 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291668509] [2019-11-16 00:34:08,455 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:08,455 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:08,455 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [956020348] [2019-11-16 00:34:08,456 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:08,456 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:08,456 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:08,456 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:08,457 INFO L87 Difference]: Start difference. First operand 1882 states and 2801 transitions. Second operand 3 states. [2019-11-16 00:34:08,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:08,691 INFO L93 Difference]: Finished difference Result 5360 states and 7953 transitions. [2019-11-16 00:34:08,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:08,692 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:08,692 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:08,713 INFO L225 Difference]: With dead ends: 5360 [2019-11-16 00:34:08,714 INFO L226 Difference]: Without dead ends: 3496 [2019-11-16 00:34:08,718 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:08,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3496 states. [2019-11-16 00:34:08,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3496 to 3494. [2019-11-16 00:34:08,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:08,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5163 transitions. [2019-11-16 00:34:08,859 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5163 transitions. Word has length 167 [2019-11-16 00:34:08,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:08,859 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5163 transitions. [2019-11-16 00:34:08,859 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:08,859 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5163 transitions. [2019-11-16 00:34:08,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:08,861 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:08,862 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:08,862 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:08,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:08,862 INFO L82 PathProgramCache]: Analyzing trace with hash -31533534, now seen corresponding path program 1 times [2019-11-16 00:34:08,863 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:08,863 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697442747] [2019-11-16 00:34:08,863 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:08,863 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:08,863 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:08,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:08,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:08,955 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697442747] [2019-11-16 00:34:08,955 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:08,955 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:08,956 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1232596844] [2019-11-16 00:34:08,956 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:08,957 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:08,957 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:08,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:08,957 INFO L87 Difference]: Start difference. First operand 3494 states and 5163 transitions. Second operand 3 states. [2019-11-16 00:34:09,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:09,097 INFO L93 Difference]: Finished difference Result 6969 states and 10294 transitions. [2019-11-16 00:34:09,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:09,097 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:09,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:09,117 INFO L225 Difference]: With dead ends: 6969 [2019-11-16 00:34:09,118 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:09,124 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:09,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:09,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:09,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:09,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5155 transitions. [2019-11-16 00:34:09,386 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5155 transitions. Word has length 167 [2019-11-16 00:34:09,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:09,386 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5155 transitions. [2019-11-16 00:34:09,386 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:09,387 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5155 transitions. [2019-11-16 00:34:09,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:09,388 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:09,389 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:09,389 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:09,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:09,389 INFO L82 PathProgramCache]: Analyzing trace with hash -675030430, now seen corresponding path program 1 times [2019-11-16 00:34:09,389 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:09,390 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446512964] [2019-11-16 00:34:09,390 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:09,390 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:09,390 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:09,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:09,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:09,468 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446512964] [2019-11-16 00:34:09,468 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:09,468 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:09,469 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286281267] [2019-11-16 00:34:09,469 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:09,469 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:09,470 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:09,470 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:09,470 INFO L87 Difference]: Start difference. First operand 3494 states and 5155 transitions. Second operand 3 states. [2019-11-16 00:34:09,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:09,585 INFO L93 Difference]: Finished difference Result 6968 states and 10277 transitions. [2019-11-16 00:34:09,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:09,586 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:09,586 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:09,605 INFO L225 Difference]: With dead ends: 6968 [2019-11-16 00:34:09,605 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:09,611 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:09,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:09,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:09,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:09,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5147 transitions. [2019-11-16 00:34:09,734 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5147 transitions. Word has length 167 [2019-11-16 00:34:09,734 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:09,734 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5147 transitions. [2019-11-16 00:34:09,734 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:09,734 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5147 transitions. [2019-11-16 00:34:09,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:09,736 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:09,737 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:09,737 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:09,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:09,737 INFO L82 PathProgramCache]: Analyzing trace with hash -939677920, now seen corresponding path program 1 times [2019-11-16 00:34:09,738 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:09,738 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932417459] [2019-11-16 00:34:09,738 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:09,738 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:09,738 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:09,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:09,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:09,792 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932417459] [2019-11-16 00:34:09,792 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:09,792 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:09,793 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461506247] [2019-11-16 00:34:09,793 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:09,793 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:09,794 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:09,794 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:09,794 INFO L87 Difference]: Start difference. First operand 3494 states and 5147 transitions. Second operand 3 states. [2019-11-16 00:34:09,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:09,910 INFO L93 Difference]: Finished difference Result 6966 states and 10258 transitions. [2019-11-16 00:34:09,910 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:09,911 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:09,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:09,930 INFO L225 Difference]: With dead ends: 6966 [2019-11-16 00:34:09,931 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:09,936 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:09,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:10,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:10,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:10,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5139 transitions. [2019-11-16 00:34:10,060 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5139 transitions. Word has length 167 [2019-11-16 00:34:10,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:10,060 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5139 transitions. [2019-11-16 00:34:10,061 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:10,061 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5139 transitions. [2019-11-16 00:34:10,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:10,063 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:10,063 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:10,063 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:10,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:10,064 INFO L82 PathProgramCache]: Analyzing trace with hash 1188104928, now seen corresponding path program 1 times [2019-11-16 00:34:10,064 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:10,064 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003994968] [2019-11-16 00:34:10,065 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:10,065 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:10,065 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:10,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:10,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:10,206 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1003994968] [2019-11-16 00:34:10,206 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:10,206 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:10,206 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [344687343] [2019-11-16 00:34:10,207 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:10,207 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:10,207 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:10,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:10,208 INFO L87 Difference]: Start difference. First operand 3494 states and 5139 transitions. Second operand 3 states. [2019-11-16 00:34:10,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:10,324 INFO L93 Difference]: Finished difference Result 6965 states and 10241 transitions. [2019-11-16 00:34:10,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:10,324 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:10,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:10,343 INFO L225 Difference]: With dead ends: 6965 [2019-11-16 00:34:10,344 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:10,349 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:10,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:10,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:10,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:10,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5131 transitions. [2019-11-16 00:34:10,474 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5131 transitions. Word has length 167 [2019-11-16 00:34:10,475 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:10,475 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5131 transitions. [2019-11-16 00:34:10,475 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:10,475 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5131 transitions. [2019-11-16 00:34:10,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:10,477 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:10,477 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:10,478 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:10,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:10,478 INFO L82 PathProgramCache]: Analyzing trace with hash 841101088, now seen corresponding path program 1 times [2019-11-16 00:34:10,478 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:10,479 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314136883] [2019-11-16 00:34:10,479 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:10,479 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:10,479 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:10,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:10,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:10,539 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1314136883] [2019-11-16 00:34:10,539 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:10,540 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:10,540 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120203897] [2019-11-16 00:34:10,540 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:10,541 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:10,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:10,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:10,541 INFO L87 Difference]: Start difference. First operand 3494 states and 5131 transitions. Second operand 3 states. [2019-11-16 00:34:10,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:10,644 INFO L93 Difference]: Finished difference Result 6964 states and 10224 transitions. [2019-11-16 00:34:10,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:10,645 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:10,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:10,684 INFO L225 Difference]: With dead ends: 6964 [2019-11-16 00:34:10,684 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:10,691 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:10,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:10,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:10,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:10,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5123 transitions. [2019-11-16 00:34:10,807 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5123 transitions. Word has length 167 [2019-11-16 00:34:10,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:10,808 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5123 transitions. [2019-11-16 00:34:10,808 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:10,808 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5123 transitions. [2019-11-16 00:34:10,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:10,810 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:10,810 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:10,810 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:10,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:10,811 INFO L82 PathProgramCache]: Analyzing trace with hash 1107002080, now seen corresponding path program 1 times [2019-11-16 00:34:10,811 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:10,811 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731487876] [2019-11-16 00:34:10,812 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:10,812 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:10,812 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:10,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:10,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:10,864 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1731487876] [2019-11-16 00:34:10,865 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:10,865 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:10,865 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488401397] [2019-11-16 00:34:10,866 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:10,866 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:10,866 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:10,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:10,867 INFO L87 Difference]: Start difference. First operand 3494 states and 5123 transitions. Second operand 3 states. [2019-11-16 00:34:10,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:10,973 INFO L93 Difference]: Finished difference Result 6963 states and 10207 transitions. [2019-11-16 00:34:10,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:10,973 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:10,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:10,982 INFO L225 Difference]: With dead ends: 6963 [2019-11-16 00:34:10,982 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:10,988 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:10,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:11,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:11,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:11,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5115 transitions. [2019-11-16 00:34:11,124 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5115 transitions. Word has length 167 [2019-11-16 00:34:11,124 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:11,124 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5115 transitions. [2019-11-16 00:34:11,125 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:11,125 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5115 transitions. [2019-11-16 00:34:11,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:11,127 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:11,128 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:11,128 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:11,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:11,131 INFO L82 PathProgramCache]: Analyzing trace with hash 1808316192, now seen corresponding path program 1 times [2019-11-16 00:34:11,131 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:11,131 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410999557] [2019-11-16 00:34:11,132 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:11,132 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:11,132 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:11,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:11,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:11,212 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [410999557] [2019-11-16 00:34:11,212 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:11,212 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:11,213 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1135472235] [2019-11-16 00:34:11,213 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:11,214 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:11,214 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:11,214 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:11,215 INFO L87 Difference]: Start difference. First operand 3494 states and 5115 transitions. Second operand 3 states. [2019-11-16 00:34:11,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:11,407 INFO L93 Difference]: Finished difference Result 6962 states and 10190 transitions. [2019-11-16 00:34:11,407 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:11,407 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:11,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:11,414 INFO L225 Difference]: With dead ends: 6962 [2019-11-16 00:34:11,414 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:11,420 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:11,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:11,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:11,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:11,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5107 transitions. [2019-11-16 00:34:11,526 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5107 transitions. Word has length 167 [2019-11-16 00:34:11,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:11,526 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5107 transitions. [2019-11-16 00:34:11,526 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:11,527 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5107 transitions. [2019-11-16 00:34:11,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:11,528 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:11,528 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:11,529 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:11,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:11,529 INFO L82 PathProgramCache]: Analyzing trace with hash 1969486560, now seen corresponding path program 1 times [2019-11-16 00:34:11,529 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:11,530 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296166412] [2019-11-16 00:34:11,530 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:11,530 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:11,530 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:11,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:11,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:11,577 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296166412] [2019-11-16 00:34:11,578 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:11,578 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:11,578 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1313826732] [2019-11-16 00:34:11,578 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:11,579 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:11,579 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:11,579 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:11,579 INFO L87 Difference]: Start difference. First operand 3494 states and 5107 transitions. Second operand 3 states. [2019-11-16 00:34:11,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:11,700 INFO L93 Difference]: Finished difference Result 6961 states and 10173 transitions. [2019-11-16 00:34:11,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:11,700 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:11,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:11,706 INFO L225 Difference]: With dead ends: 6961 [2019-11-16 00:34:11,707 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:11,712 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:11,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:11,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:11,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:11,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5099 transitions. [2019-11-16 00:34:11,828 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5099 transitions. Word has length 167 [2019-11-16 00:34:11,828 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:11,828 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5099 transitions. [2019-11-16 00:34:11,828 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:11,828 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5099 transitions. [2019-11-16 00:34:11,830 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:11,830 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:11,830 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:11,830 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:11,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:11,831 INFO L82 PathProgramCache]: Analyzing trace with hash 1836138272, now seen corresponding path program 1 times [2019-11-16 00:34:11,831 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:11,831 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029767167] [2019-11-16 00:34:11,831 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:11,832 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:11,832 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:11,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:11,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:11,879 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029767167] [2019-11-16 00:34:11,879 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:11,880 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:11,880 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [706597625] [2019-11-16 00:34:11,880 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:11,880 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:11,881 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:11,881 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:11,881 INFO L87 Difference]: Start difference. First operand 3494 states and 5099 transitions. Second operand 3 states. [2019-11-16 00:34:12,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:12,010 INFO L93 Difference]: Finished difference Result 6960 states and 10156 transitions. [2019-11-16 00:34:12,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:12,011 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:12,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:12,017 INFO L225 Difference]: With dead ends: 6960 [2019-11-16 00:34:12,017 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:12,023 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:12,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:12,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:12,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:12,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5091 transitions. [2019-11-16 00:34:12,144 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5091 transitions. Word has length 167 [2019-11-16 00:34:12,144 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:12,144 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5091 transitions. [2019-11-16 00:34:12,144 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:12,144 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5091 transitions. [2019-11-16 00:34:12,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:12,146 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:12,146 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:12,147 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:12,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:12,147 INFO L82 PathProgramCache]: Analyzing trace with hash -2048218658, now seen corresponding path program 1 times [2019-11-16 00:34:12,147 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:12,147 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112407630] [2019-11-16 00:34:12,148 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:12,148 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:12,148 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:12,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:12,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:12,308 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112407630] [2019-11-16 00:34:12,309 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:12,309 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:12,309 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [294966349] [2019-11-16 00:34:12,310 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:12,310 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:12,310 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:12,310 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:12,310 INFO L87 Difference]: Start difference. First operand 3494 states and 5091 transitions. Second operand 3 states. [2019-11-16 00:34:12,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:12,443 INFO L93 Difference]: Finished difference Result 6958 states and 10137 transitions. [2019-11-16 00:34:12,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:12,444 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:12,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:12,451 INFO L225 Difference]: With dead ends: 6958 [2019-11-16 00:34:12,451 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:12,457 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:12,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:12,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:12,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:12,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5083 transitions. [2019-11-16 00:34:12,582 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5083 transitions. Word has length 167 [2019-11-16 00:34:12,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:12,584 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5083 transitions. [2019-11-16 00:34:12,584 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:12,584 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5083 transitions. [2019-11-16 00:34:12,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:12,586 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:12,586 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:12,586 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:12,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:12,587 INFO L82 PathProgramCache]: Analyzing trace with hash 2034093470, now seen corresponding path program 1 times [2019-11-16 00:34:12,587 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:12,587 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239281904] [2019-11-16 00:34:12,587 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:12,588 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:12,588 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:12,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:12,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:12,660 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239281904] [2019-11-16 00:34:12,661 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:12,661 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:12,661 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1282546826] [2019-11-16 00:34:12,661 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:12,662 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:12,662 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:12,662 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:12,662 INFO L87 Difference]: Start difference. First operand 3494 states and 5083 transitions. Second operand 3 states. [2019-11-16 00:34:12,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:12,808 INFO L93 Difference]: Finished difference Result 6957 states and 10120 transitions. [2019-11-16 00:34:12,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:12,808 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:12,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:12,814 INFO L225 Difference]: With dead ends: 6957 [2019-11-16 00:34:12,815 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:12,821 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:12,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:12,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:12,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:12,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5075 transitions. [2019-11-16 00:34:12,945 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5075 transitions. Word has length 167 [2019-11-16 00:34:12,945 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:12,945 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5075 transitions. [2019-11-16 00:34:12,945 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:12,945 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5075 transitions. [2019-11-16 00:34:12,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:12,947 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:12,947 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:12,947 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:12,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:12,948 INFO L82 PathProgramCache]: Analyzing trace with hash -2129186338, now seen corresponding path program 1 times [2019-11-16 00:34:12,948 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:12,948 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812741498] [2019-11-16 00:34:12,948 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:12,949 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:12,949 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:12,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:13,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:13,003 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1812741498] [2019-11-16 00:34:13,003 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:13,003 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:13,003 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1626774825] [2019-11-16 00:34:13,004 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:13,004 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:13,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:13,005 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:13,005 INFO L87 Difference]: Start difference. First operand 3494 states and 5075 transitions. Second operand 3 states. [2019-11-16 00:34:13,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:13,193 INFO L93 Difference]: Finished difference Result 6956 states and 10103 transitions. [2019-11-16 00:34:13,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:13,194 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:13,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:13,200 INFO L225 Difference]: With dead ends: 6956 [2019-11-16 00:34:13,200 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:13,207 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:13,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:13,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:13,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:13,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5039 transitions. [2019-11-16 00:34:13,360 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5039 transitions. Word has length 167 [2019-11-16 00:34:13,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:13,360 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5039 transitions. [2019-11-16 00:34:13,360 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:13,360 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5039 transitions. [2019-11-16 00:34:13,362 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:13,362 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:13,363 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:13,363 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:13,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:13,363 INFO L82 PathProgramCache]: Analyzing trace with hash 904313021, now seen corresponding path program 1 times [2019-11-16 00:34:13,364 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:13,364 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770681563] [2019-11-16 00:34:13,364 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:13,364 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:13,365 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:13,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:13,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:13,441 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770681563] [2019-11-16 00:34:13,443 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:13,443 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:13,443 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1658071003] [2019-11-16 00:34:13,444 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:13,444 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:13,445 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:13,445 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:13,445 INFO L87 Difference]: Start difference. First operand 3494 states and 5039 transitions. Second operand 3 states. [2019-11-16 00:34:13,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:13,703 INFO L93 Difference]: Finished difference Result 6955 states and 10030 transitions. [2019-11-16 00:34:13,703 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:13,703 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:13,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:13,711 INFO L225 Difference]: With dead ends: 6955 [2019-11-16 00:34:13,711 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:13,718 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:13,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:13,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:13,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:13,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5003 transitions. [2019-11-16 00:34:13,986 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5003 transitions. Word has length 167 [2019-11-16 00:34:13,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:13,986 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5003 transitions. [2019-11-16 00:34:13,987 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:13,987 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5003 transitions. [2019-11-16 00:34:13,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:13,989 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:13,989 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:13,990 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:13,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:13,990 INFO L82 PathProgramCache]: Analyzing trace with hash -2125714179, now seen corresponding path program 1 times [2019-11-16 00:34:13,990 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:13,991 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768549406] [2019-11-16 00:34:13,991 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:13,991 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:13,991 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:14,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:14,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:14,056 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768549406] [2019-11-16 00:34:14,057 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:14,057 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:14,057 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2028465044] [2019-11-16 00:34:14,058 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:14,058 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:14,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:14,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:14,058 INFO L87 Difference]: Start difference. First operand 3494 states and 5003 transitions. Second operand 3 states. [2019-11-16 00:34:14,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:14,255 INFO L93 Difference]: Finished difference Result 6954 states and 9957 transitions. [2019-11-16 00:34:14,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:14,255 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:14,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:14,261 INFO L225 Difference]: With dead ends: 6954 [2019-11-16 00:34:14,262 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:14,269 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:14,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:14,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:14,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:14,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4967 transitions. [2019-11-16 00:34:14,401 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4967 transitions. Word has length 167 [2019-11-16 00:34:14,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:14,402 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4967 transitions. [2019-11-16 00:34:14,402 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:14,402 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4967 transitions. [2019-11-16 00:34:14,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:14,404 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:14,404 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:14,404 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:14,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:14,405 INFO L82 PathProgramCache]: Analyzing trace with hash 1803688540, now seen corresponding path program 1 times [2019-11-16 00:34:14,405 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:14,405 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848533490] [2019-11-16 00:34:14,406 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:14,406 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:14,406 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:14,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:14,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:14,457 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848533490] [2019-11-16 00:34:14,458 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:14,458 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:14,458 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [693700376] [2019-11-16 00:34:14,459 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:14,459 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:14,459 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:14,459 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:14,459 INFO L87 Difference]: Start difference. First operand 3494 states and 4967 transitions. Second operand 3 states. [2019-11-16 00:34:14,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:14,645 INFO L93 Difference]: Finished difference Result 6953 states and 9884 transitions. [2019-11-16 00:34:14,646 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:14,646 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:14,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:14,652 INFO L225 Difference]: With dead ends: 6953 [2019-11-16 00:34:14,653 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:14,658 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:14,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:14,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:14,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:14,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4931 transitions. [2019-11-16 00:34:14,803 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4931 transitions. Word has length 167 [2019-11-16 00:34:14,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:14,803 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4931 transitions. [2019-11-16 00:34:14,804 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:14,804 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4931 transitions. [2019-11-16 00:34:14,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:14,806 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:14,806 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:14,806 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:14,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:14,807 INFO L82 PathProgramCache]: Analyzing trace with hash -1908957540, now seen corresponding path program 1 times [2019-11-16 00:34:14,807 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:14,807 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990143100] [2019-11-16 00:34:14,808 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:14,808 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:14,808 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:14,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:14,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:14,864 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990143100] [2019-11-16 00:34:14,864 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:14,865 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:14,865 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829504336] [2019-11-16 00:34:14,866 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:14,866 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:14,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:14,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:14,867 INFO L87 Difference]: Start difference. First operand 3494 states and 4931 transitions. Second operand 3 states. [2019-11-16 00:34:15,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:15,092 INFO L93 Difference]: Finished difference Result 6952 states and 9811 transitions. [2019-11-16 00:34:15,092 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:15,093 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:15,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:15,099 INFO L225 Difference]: With dead ends: 6952 [2019-11-16 00:34:15,100 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:15,109 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:15,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:15,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:15,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:15,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4895 transitions. [2019-11-16 00:34:15,270 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4895 transitions. Word has length 167 [2019-11-16 00:34:15,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:15,270 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4895 transitions. [2019-11-16 00:34:15,271 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:15,271 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4895 transitions. [2019-11-16 00:34:15,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:15,273 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:15,273 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:15,273 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:15,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:15,274 INFO L82 PathProgramCache]: Analyzing trace with hash 1048299385, now seen corresponding path program 1 times [2019-11-16 00:34:15,274 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:15,274 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791509123] [2019-11-16 00:34:15,275 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:15,275 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:15,275 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:15,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:15,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:15,334 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [791509123] [2019-11-16 00:34:15,334 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:15,334 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:15,334 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547278790] [2019-11-16 00:34:15,335 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:15,335 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:15,335 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:15,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:15,336 INFO L87 Difference]: Start difference. First operand 3494 states and 4895 transitions. Second operand 3 states. [2019-11-16 00:34:15,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:15,575 INFO L93 Difference]: Finished difference Result 6950 states and 9736 transitions. [2019-11-16 00:34:15,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:15,575 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:15,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:15,582 INFO L225 Difference]: With dead ends: 6950 [2019-11-16 00:34:15,582 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:15,587 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:15,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:15,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:15,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:15,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4859 transitions. [2019-11-16 00:34:15,732 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4859 transitions. Word has length 167 [2019-11-16 00:34:15,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:15,732 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4859 transitions. [2019-11-16 00:34:15,732 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:15,732 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4859 transitions. [2019-11-16 00:34:15,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:15,734 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:15,734 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:15,735 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:15,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:15,735 INFO L82 PathProgramCache]: Analyzing trace with hash 1051443672, now seen corresponding path program 1 times [2019-11-16 00:34:15,735 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:15,735 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37007287] [2019-11-16 00:34:15,736 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:15,736 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:15,736 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:15,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:15,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:15,808 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37007287] [2019-11-16 00:34:15,809 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:15,809 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:15,809 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690508240] [2019-11-16 00:34:15,810 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:15,814 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:15,815 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:15,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:15,815 INFO L87 Difference]: Start difference. First operand 3494 states and 4859 transitions. Second operand 3 states. [2019-11-16 00:34:16,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:16,040 INFO L93 Difference]: Finished difference Result 6949 states and 9663 transitions. [2019-11-16 00:34:16,040 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:16,041 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:16,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:16,047 INFO L225 Difference]: With dead ends: 6949 [2019-11-16 00:34:16,048 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:16,051 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:16,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:16,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:16,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:16,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4823 transitions. [2019-11-16 00:34:16,187 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4823 transitions. Word has length 167 [2019-11-16 00:34:16,188 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:16,188 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4823 transitions. [2019-11-16 00:34:16,188 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:16,188 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4823 transitions. [2019-11-16 00:34:16,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:16,189 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:16,190 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:16,190 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:16,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:16,190 INFO L82 PathProgramCache]: Analyzing trace with hash -1890753000, now seen corresponding path program 1 times [2019-11-16 00:34:16,191 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:16,191 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793285086] [2019-11-16 00:34:16,191 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:16,191 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:16,191 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:16,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:16,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:16,237 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793285086] [2019-11-16 00:34:16,237 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:16,237 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:16,237 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [243949400] [2019-11-16 00:34:16,238 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:16,238 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:16,238 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:16,239 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:16,239 INFO L87 Difference]: Start difference. First operand 3494 states and 4823 transitions. Second operand 3 states. [2019-11-16 00:34:16,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:16,435 INFO L93 Difference]: Finished difference Result 6948 states and 9590 transitions. [2019-11-16 00:34:16,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:16,436 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:16,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:16,444 INFO L225 Difference]: With dead ends: 6948 [2019-11-16 00:34:16,444 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:16,448 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:16,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:16,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:16,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:16,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4787 transitions. [2019-11-16 00:34:16,599 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4787 transitions. Word has length 167 [2019-11-16 00:34:16,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:16,599 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4787 transitions. [2019-11-16 00:34:16,599 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:16,600 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4787 transitions. [2019-11-16 00:34:16,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:16,602 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:16,602 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:16,602 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:16,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:16,603 INFO L82 PathProgramCache]: Analyzing trace with hash 2068907767, now seen corresponding path program 1 times [2019-11-16 00:34:16,603 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:16,603 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819735431] [2019-11-16 00:34:16,603 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:16,603 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:16,604 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:16,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:16,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:16,662 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1819735431] [2019-11-16 00:34:16,662 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:16,663 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:16,663 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1850054619] [2019-11-16 00:34:16,664 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:16,665 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:16,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:16,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:16,665 INFO L87 Difference]: Start difference. First operand 3494 states and 4787 transitions. Second operand 3 states. [2019-11-16 00:34:16,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:16,910 INFO L93 Difference]: Finished difference Result 6947 states and 9517 transitions. [2019-11-16 00:34:16,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:16,911 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:16,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:16,924 INFO L225 Difference]: With dead ends: 6947 [2019-11-16 00:34:16,924 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:16,928 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:16,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:17,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:17,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:17,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4751 transitions. [2019-11-16 00:34:17,139 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4751 transitions. Word has length 167 [2019-11-16 00:34:17,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:17,139 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4751 transitions. [2019-11-16 00:34:17,140 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:17,140 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4751 transitions. [2019-11-16 00:34:17,142 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:17,142 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:17,142 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:17,143 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:17,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:17,143 INFO L82 PathProgramCache]: Analyzing trace with hash -1861907562, now seen corresponding path program 1 times [2019-11-16 00:34:17,144 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:17,144 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1602913915] [2019-11-16 00:34:17,144 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:17,144 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:17,145 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:17,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:17,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:17,237 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1602913915] [2019-11-16 00:34:17,237 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:17,238 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:17,238 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1060673353] [2019-11-16 00:34:17,238 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:17,239 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:17,239 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:17,240 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:17,240 INFO L87 Difference]: Start difference. First operand 3494 states and 4751 transitions. Second operand 3 states. [2019-11-16 00:34:17,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:17,554 INFO L93 Difference]: Finished difference Result 6946 states and 9444 transitions. [2019-11-16 00:34:17,554 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:17,554 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:17,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:17,561 INFO L225 Difference]: With dead ends: 6946 [2019-11-16 00:34:17,561 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:17,566 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:17,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:17,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:17,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:17,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4715 transitions. [2019-11-16 00:34:17,719 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4715 transitions. Word has length 167 [2019-11-16 00:34:17,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:17,719 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4715 transitions. [2019-11-16 00:34:17,719 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:17,719 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4715 transitions. [2019-11-16 00:34:17,721 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:17,722 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:17,722 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:17,722 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:17,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:17,723 INFO L82 PathProgramCache]: Analyzing trace with hash 723537750, now seen corresponding path program 1 times [2019-11-16 00:34:17,723 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:17,723 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578114161] [2019-11-16 00:34:17,723 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:17,724 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:17,724 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:17,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:17,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:17,773 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578114161] [2019-11-16 00:34:17,773 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:17,773 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:17,774 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1938902698] [2019-11-16 00:34:17,774 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:17,774 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:17,775 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:17,775 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:17,775 INFO L87 Difference]: Start difference. First operand 3494 states and 4715 transitions. Second operand 3 states. [2019-11-16 00:34:18,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:18,015 INFO L93 Difference]: Finished difference Result 6945 states and 9371 transitions. [2019-11-16 00:34:18,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:18,015 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:18,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:18,022 INFO L225 Difference]: With dead ends: 6945 [2019-11-16 00:34:18,023 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:18,027 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:18,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:18,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:18,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:18,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4679 transitions. [2019-11-16 00:34:18,210 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4679 transitions. Word has length 167 [2019-11-16 00:34:18,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:18,211 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4679 transitions. [2019-11-16 00:34:18,211 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:18,211 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4679 transitions. [2019-11-16 00:34:18,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:18,212 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:18,213 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:18,213 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:18,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:18,214 INFO L82 PathProgramCache]: Analyzing trace with hash 1570454133, now seen corresponding path program 1 times [2019-11-16 00:34:18,214 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:18,214 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265499139] [2019-11-16 00:34:18,215 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:18,215 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:18,215 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:18,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:18,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:18,279 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265499139] [2019-11-16 00:34:18,280 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:18,280 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:18,280 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812533743] [2019-11-16 00:34:18,281 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:18,281 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:18,282 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:18,282 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:18,282 INFO L87 Difference]: Start difference. First operand 3494 states and 4679 transitions. Second operand 3 states. [2019-11-16 00:34:18,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:18,531 INFO L93 Difference]: Finished difference Result 6944 states and 9298 transitions. [2019-11-16 00:34:18,531 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:18,532 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:18,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:18,540 INFO L225 Difference]: With dead ends: 6944 [2019-11-16 00:34:18,540 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:18,545 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:18,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:18,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:18,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:18,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4643 transitions. [2019-11-16 00:34:18,730 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4643 transitions. Word has length 167 [2019-11-16 00:34:18,730 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:18,730 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4643 transitions. [2019-11-16 00:34:18,730 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:18,730 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4643 transitions. [2019-11-16 00:34:18,731 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:18,732 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:18,732 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:18,732 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:18,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:18,733 INFO L82 PathProgramCache]: Analyzing trace with hash -1777475277, now seen corresponding path program 1 times [2019-11-16 00:34:18,733 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:18,733 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966064106] [2019-11-16 00:34:18,733 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:18,734 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:18,734 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:18,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:18,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:18,821 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [966064106] [2019-11-16 00:34:18,821 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:18,822 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:18,822 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772253841] [2019-11-16 00:34:18,822 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:18,823 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:18,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:18,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:18,823 INFO L87 Difference]: Start difference. First operand 3494 states and 4643 transitions. Second operand 3 states. [2019-11-16 00:34:19,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:19,044 INFO L93 Difference]: Finished difference Result 6967 states and 9252 transitions. [2019-11-16 00:34:19,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:19,045 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:19,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:19,052 INFO L225 Difference]: With dead ends: 6967 [2019-11-16 00:34:19,052 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:19,056 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:19,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:19,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:19,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:19,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4635 transitions. [2019-11-16 00:34:19,231 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4635 transitions. Word has length 167 [2019-11-16 00:34:19,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:19,232 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4635 transitions. [2019-11-16 00:34:19,232 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:19,232 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4635 transitions. [2019-11-16 00:34:19,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:19,233 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:19,233 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:19,233 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:19,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:19,234 INFO L82 PathProgramCache]: Analyzing trace with hash 2123125233, now seen corresponding path program 1 times [2019-11-16 00:34:19,234 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:19,234 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820510710] [2019-11-16 00:34:19,235 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:19,235 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:19,235 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:19,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:19,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:19,314 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820510710] [2019-11-16 00:34:19,314 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:19,314 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:19,315 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067561005] [2019-11-16 00:34:19,315 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:19,315 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:19,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:19,316 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:19,316 INFO L87 Difference]: Start difference. First operand 3494 states and 4635 transitions. Second operand 3 states. [2019-11-16 00:34:19,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:19,524 INFO L93 Difference]: Finished difference Result 6959 states and 9228 transitions. [2019-11-16 00:34:19,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:19,525 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:19,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:19,530 INFO L225 Difference]: With dead ends: 6959 [2019-11-16 00:34:19,530 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:19,534 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:19,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:19,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:19,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:19,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4627 transitions. [2019-11-16 00:34:19,709 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4627 transitions. Word has length 167 [2019-11-16 00:34:19,709 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:19,709 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4627 transitions. [2019-11-16 00:34:19,710 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:19,710 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4627 transitions. [2019-11-16 00:34:19,711 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:19,711 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:19,711 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:19,712 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:19,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:19,712 INFO L82 PathProgramCache]: Analyzing trace with hash 1613652143, now seen corresponding path program 1 times [2019-11-16 00:34:19,712 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:19,713 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319251288] [2019-11-16 00:34:19,713 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:19,713 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:19,713 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:19,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:19,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:19,784 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319251288] [2019-11-16 00:34:19,784 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:19,784 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:34:19,784 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1761129434] [2019-11-16 00:34:19,785 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:19,785 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:19,785 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:19,785 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:19,785 INFO L87 Difference]: Start difference. First operand 3494 states and 4627 transitions. Second operand 3 states. [2019-11-16 00:34:19,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:19,999 INFO L93 Difference]: Finished difference Result 6951 states and 9204 transitions. [2019-11-16 00:34:20,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:20,000 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:20,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:20,005 INFO L225 Difference]: With dead ends: 6951 [2019-11-16 00:34:20,005 INFO L226 Difference]: Without dead ends: 3494 [2019-11-16 00:34:20,009 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:20,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-16 00:34:20,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-16 00:34:20,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-16 00:34:20,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4591 transitions. [2019-11-16 00:34:20,179 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4591 transitions. Word has length 167 [2019-11-16 00:34:20,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:20,180 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4591 transitions. [2019-11-16 00:34:20,180 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:20,180 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4591 transitions. [2019-11-16 00:34:20,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-16 00:34:20,181 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:20,181 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:20,181 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:20,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:20,182 INFO L82 PathProgramCache]: Analyzing trace with hash 796003693, now seen corresponding path program 1 times [2019-11-16 00:34:20,182 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:20,182 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516017503] [2019-11-16 00:34:20,182 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:20,182 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:20,183 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:20,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:20,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:20,246 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [516017503] [2019-11-16 00:34:20,246 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:20,247 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:34:20,247 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19422641] [2019-11-16 00:34:20,247 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:34:20,247 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:20,248 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:34:20,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:20,248 INFO L87 Difference]: Start difference. First operand 3494 states and 4591 transitions. Second operand 3 states. [2019-11-16 00:34:20,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:20,630 INFO L93 Difference]: Finished difference Result 10209 states and 13370 transitions. [2019-11-16 00:34:20,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:34:20,631 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-16 00:34:20,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:20,640 INFO L225 Difference]: With dead ends: 10209 [2019-11-16 00:34:20,640 INFO L226 Difference]: Without dead ends: 6884 [2019-11-16 00:34:20,645 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:34:20,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6884 states. [2019-11-16 00:34:21,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6884 to 6694. [2019-11-16 00:34:21,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6694 states. [2019-11-16 00:34:21,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6694 states to 6694 states and 8737 transitions. [2019-11-16 00:34:21,015 INFO L78 Accepts]: Start accepts. Automaton has 6694 states and 8737 transitions. Word has length 167 [2019-11-16 00:34:21,015 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:21,015 INFO L462 AbstractCegarLoop]: Abstraction has 6694 states and 8737 transitions. [2019-11-16 00:34:21,016 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:34:21,016 INFO L276 IsEmpty]: Start isEmpty. Operand 6694 states and 8737 transitions. [2019-11-16 00:34:21,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:21,017 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:21,018 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:21,018 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:21,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:21,018 INFO L82 PathProgramCache]: Analyzing trace with hash -1437788242, now seen corresponding path program 1 times [2019-11-16 00:34:21,019 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:21,019 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093296265] [2019-11-16 00:34:21,019 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:21,019 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:21,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:21,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:21,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:21,134 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093296265] [2019-11-16 00:34:21,134 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:21,134 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:21,134 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949838130] [2019-11-16 00:34:21,135 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:21,135 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:21,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:21,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:21,136 INFO L87 Difference]: Start difference. First operand 6694 states and 8737 transitions. Second operand 5 states. [2019-11-16 00:34:22,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:22,319 INFO L93 Difference]: Finished difference Result 18864 states and 24680 transitions. [2019-11-16 00:34:22,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:22,320 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:22,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:22,329 INFO L225 Difference]: With dead ends: 18864 [2019-11-16 00:34:22,329 INFO L226 Difference]: Without dead ends: 12386 [2019-11-16 00:34:22,335 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:22,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12386 states. [2019-11-16 00:34:22,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12386 to 6781. [2019-11-16 00:34:22,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6781 states. [2019-11-16 00:34:22,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6781 states to 6781 states and 8795 transitions. [2019-11-16 00:34:22,724 INFO L78 Accepts]: Start accepts. Automaton has 6781 states and 8795 transitions. Word has length 168 [2019-11-16 00:34:22,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:22,724 INFO L462 AbstractCegarLoop]: Abstraction has 6781 states and 8795 transitions. [2019-11-16 00:34:22,724 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:22,724 INFO L276 IsEmpty]: Start isEmpty. Operand 6781 states and 8795 transitions. [2019-11-16 00:34:22,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:22,726 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:22,726 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:22,726 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:22,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:22,727 INFO L82 PathProgramCache]: Analyzing trace with hash 1575006768, now seen corresponding path program 1 times [2019-11-16 00:34:22,727 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:22,727 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563056244] [2019-11-16 00:34:22,728 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:22,728 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:22,728 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:22,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:22,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:22,806 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563056244] [2019-11-16 00:34:22,806 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:22,807 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:22,807 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [421646560] [2019-11-16 00:34:22,807 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:22,807 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:22,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:22,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:22,808 INFO L87 Difference]: Start difference. First operand 6781 states and 8795 transitions. Second operand 5 states. [2019-11-16 00:34:23,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:23,623 INFO L93 Difference]: Finished difference Result 15355 states and 20058 transitions. [2019-11-16 00:34:23,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:23,624 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:23,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:23,632 INFO L225 Difference]: With dead ends: 15355 [2019-11-16 00:34:23,632 INFO L226 Difference]: Without dead ends: 8686 [2019-11-16 00:34:23,640 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:23,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8686 states. [2019-11-16 00:34:24,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8686 to 6787. [2019-11-16 00:34:24,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6787 states. [2019-11-16 00:34:24,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6787 states to 6787 states and 8745 transitions. [2019-11-16 00:34:24,153 INFO L78 Accepts]: Start accepts. Automaton has 6787 states and 8745 transitions. Word has length 168 [2019-11-16 00:34:24,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:24,153 INFO L462 AbstractCegarLoop]: Abstraction has 6787 states and 8745 transitions. [2019-11-16 00:34:24,153 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:24,153 INFO L276 IsEmpty]: Start isEmpty. Operand 6787 states and 8745 transitions. [2019-11-16 00:34:24,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:24,155 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:24,155 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:24,155 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:24,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:24,156 INFO L82 PathProgramCache]: Analyzing trace with hash -992815566, now seen corresponding path program 1 times [2019-11-16 00:34:24,156 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:24,156 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205056689] [2019-11-16 00:34:24,156 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:24,156 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:24,157 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:24,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:24,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:24,238 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205056689] [2019-11-16 00:34:24,238 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:24,239 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:24,239 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320742521] [2019-11-16 00:34:24,239 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:24,239 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:24,240 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:24,240 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:24,240 INFO L87 Difference]: Start difference. First operand 6787 states and 8745 transitions. Second operand 5 states. [2019-11-16 00:34:25,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:25,075 INFO L93 Difference]: Finished difference Result 16335 states and 21156 transitions. [2019-11-16 00:34:25,076 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:25,076 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:25,076 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:25,083 INFO L225 Difference]: With dead ends: 16335 [2019-11-16 00:34:25,083 INFO L226 Difference]: Without dead ends: 9688 [2019-11-16 00:34:25,089 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:25,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9688 states. [2019-11-16 00:34:25,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9688 to 6799. [2019-11-16 00:34:25,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6799 states. [2019-11-16 00:34:25,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6799 states to 6799 states and 8703 transitions. [2019-11-16 00:34:25,480 INFO L78 Accepts]: Start accepts. Automaton has 6799 states and 8703 transitions. Word has length 168 [2019-11-16 00:34:25,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:25,480 INFO L462 AbstractCegarLoop]: Abstraction has 6799 states and 8703 transitions. [2019-11-16 00:34:25,481 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:25,481 INFO L276 IsEmpty]: Start isEmpty. Operand 6799 states and 8703 transitions. [2019-11-16 00:34:25,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:25,482 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:25,482 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:25,483 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:25,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:25,483 INFO L82 PathProgramCache]: Analyzing trace with hash 1995009332, now seen corresponding path program 1 times [2019-11-16 00:34:25,483 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:25,483 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39862895] [2019-11-16 00:34:25,484 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:25,484 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:25,484 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:25,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:25,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:25,559 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39862895] [2019-11-16 00:34:25,559 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:25,559 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:25,559 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1726497184] [2019-11-16 00:34:25,560 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:25,560 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:25,560 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:25,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:25,560 INFO L87 Difference]: Start difference. First operand 6799 states and 8703 transitions. Second operand 5 states. [2019-11-16 00:34:26,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:26,726 INFO L93 Difference]: Finished difference Result 16679 states and 21436 transitions. [2019-11-16 00:34:26,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:26,727 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:26,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:26,736 INFO L225 Difference]: With dead ends: 16679 [2019-11-16 00:34:26,736 INFO L226 Difference]: Without dead ends: 10034 [2019-11-16 00:34:26,745 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:26,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10034 states. [2019-11-16 00:34:27,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10034 to 6811. [2019-11-16 00:34:27,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6811 states. [2019-11-16 00:34:27,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6811 states to 6811 states and 8661 transitions. [2019-11-16 00:34:27,297 INFO L78 Accepts]: Start accepts. Automaton has 6811 states and 8661 transitions. Word has length 168 [2019-11-16 00:34:27,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:27,297 INFO L462 AbstractCegarLoop]: Abstraction has 6811 states and 8661 transitions. [2019-11-16 00:34:27,297 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:27,298 INFO L276 IsEmpty]: Start isEmpty. Operand 6811 states and 8661 transitions. [2019-11-16 00:34:27,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:27,298 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:27,299 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:27,299 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:27,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:27,299 INFO L82 PathProgramCache]: Analyzing trace with hash -948572746, now seen corresponding path program 1 times [2019-11-16 00:34:27,299 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:27,299 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173076290] [2019-11-16 00:34:27,300 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:27,300 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:27,300 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:27,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:27,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:27,390 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [173076290] [2019-11-16 00:34:27,390 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:27,391 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:27,391 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933614474] [2019-11-16 00:34:27,391 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:27,392 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:27,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:27,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:27,392 INFO L87 Difference]: Start difference. First operand 6811 states and 8661 transitions. Second operand 5 states. [2019-11-16 00:34:28,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:28,293 INFO L93 Difference]: Finished difference Result 17023 states and 21716 transitions. [2019-11-16 00:34:28,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:28,294 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:28,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:28,302 INFO L225 Difference]: With dead ends: 17023 [2019-11-16 00:34:28,302 INFO L226 Difference]: Without dead ends: 10380 [2019-11-16 00:34:28,307 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:28,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10380 states. [2019-11-16 00:34:28,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10380 to 6823. [2019-11-16 00:34:28,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6823 states. [2019-11-16 00:34:28,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6823 states to 6823 states and 8619 transitions. [2019-11-16 00:34:28,788 INFO L78 Accepts]: Start accepts. Automaton has 6823 states and 8619 transitions. Word has length 168 [2019-11-16 00:34:28,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:28,788 INFO L462 AbstractCegarLoop]: Abstraction has 6823 states and 8619 transitions. [2019-11-16 00:34:28,788 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:28,788 INFO L276 IsEmpty]: Start isEmpty. Operand 6823 states and 8619 transitions. [2019-11-16 00:34:28,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:28,790 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:28,792 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:28,792 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:28,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:28,792 INFO L82 PathProgramCache]: Analyzing trace with hash -1719306312, now seen corresponding path program 1 times [2019-11-16 00:34:28,793 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:28,793 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686140481] [2019-11-16 00:34:28,793 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:28,793 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:28,794 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:28,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:28,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:28,876 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686140481] [2019-11-16 00:34:28,877 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:28,877 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:28,877 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [660565833] [2019-11-16 00:34:28,878 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:28,878 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:28,878 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:28,878 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:28,878 INFO L87 Difference]: Start difference. First operand 6823 states and 8619 transitions. Second operand 5 states. [2019-11-16 00:34:30,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:30,040 INFO L93 Difference]: Finished difference Result 17367 states and 21996 transitions. [2019-11-16 00:34:30,040 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:30,040 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:30,040 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:30,048 INFO L225 Difference]: With dead ends: 17367 [2019-11-16 00:34:30,049 INFO L226 Difference]: Without dead ends: 10726 [2019-11-16 00:34:30,054 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:30,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10726 states. [2019-11-16 00:34:30,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10726 to 6835. [2019-11-16 00:34:30,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6835 states. [2019-11-16 00:34:30,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6835 states to 6835 states and 8577 transitions. [2019-11-16 00:34:30,587 INFO L78 Accepts]: Start accepts. Automaton has 6835 states and 8577 transitions. Word has length 168 [2019-11-16 00:34:30,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:30,587 INFO L462 AbstractCegarLoop]: Abstraction has 6835 states and 8577 transitions. [2019-11-16 00:34:30,587 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:30,587 INFO L276 IsEmpty]: Start isEmpty. Operand 6835 states and 8577 transitions. [2019-11-16 00:34:30,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:30,589 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:30,589 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:30,589 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:30,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:30,590 INFO L82 PathProgramCache]: Analyzing trace with hash -394450118, now seen corresponding path program 1 times [2019-11-16 00:34:30,590 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:30,590 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984183372] [2019-11-16 00:34:30,590 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:30,591 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:30,591 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:30,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:30,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:30,685 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984183372] [2019-11-16 00:34:30,686 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:30,686 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:30,686 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [497639102] [2019-11-16 00:34:30,687 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:30,687 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:30,687 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:30,687 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:30,688 INFO L87 Difference]: Start difference. First operand 6835 states and 8577 transitions. Second operand 5 states. [2019-11-16 00:34:32,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:32,110 INFO L93 Difference]: Finished difference Result 17711 states and 22276 transitions. [2019-11-16 00:34:32,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:32,110 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:32,110 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:32,120 INFO L225 Difference]: With dead ends: 17711 [2019-11-16 00:34:32,120 INFO L226 Difference]: Without dead ends: 11072 [2019-11-16 00:34:32,126 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:32,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11072 states. [2019-11-16 00:34:32,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11072 to 6847. [2019-11-16 00:34:32,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6847 states. [2019-11-16 00:34:32,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6847 states to 6847 states and 8535 transitions. [2019-11-16 00:34:32,859 INFO L78 Accepts]: Start accepts. Automaton has 6847 states and 8535 transitions. Word has length 168 [2019-11-16 00:34:32,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:32,860 INFO L462 AbstractCegarLoop]: Abstraction has 6847 states and 8535 transitions. [2019-11-16 00:34:32,860 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:32,860 INFO L276 IsEmpty]: Start isEmpty. Operand 6847 states and 8535 transitions. [2019-11-16 00:34:32,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:32,861 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:32,861 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:32,861 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:32,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:32,862 INFO L82 PathProgramCache]: Analyzing trace with hash -367384516, now seen corresponding path program 1 times [2019-11-16 00:34:32,862 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:32,862 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554563132] [2019-11-16 00:34:32,862 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:32,862 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:32,863 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:32,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:32,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:32,949 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554563132] [2019-11-16 00:34:32,949 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:32,950 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:32,950 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1060146836] [2019-11-16 00:34:32,950 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:32,951 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:32,951 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:32,951 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:32,951 INFO L87 Difference]: Start difference. First operand 6847 states and 8535 transitions. Second operand 5 states. [2019-11-16 00:34:34,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:34,244 INFO L93 Difference]: Finished difference Result 18055 states and 22556 transitions. [2019-11-16 00:34:34,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:34,245 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:34,245 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:34,255 INFO L225 Difference]: With dead ends: 18055 [2019-11-16 00:34:34,255 INFO L226 Difference]: Without dead ends: 11418 [2019-11-16 00:34:34,261 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:34,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11418 states. [2019-11-16 00:34:34,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11418 to 6859. [2019-11-16 00:34:34,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6859 states. [2019-11-16 00:34:34,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6859 states to 6859 states and 8493 transitions. [2019-11-16 00:34:34,849 INFO L78 Accepts]: Start accepts. Automaton has 6859 states and 8493 transitions. Word has length 168 [2019-11-16 00:34:34,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:34,850 INFO L462 AbstractCegarLoop]: Abstraction has 6859 states and 8493 transitions. [2019-11-16 00:34:34,850 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:34,850 INFO L276 IsEmpty]: Start isEmpty. Operand 6859 states and 8493 transitions. [2019-11-16 00:34:34,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:34,851 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:34,851 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:34,851 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:34,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:34,851 INFO L82 PathProgramCache]: Analyzing trace with hash -1334735170, now seen corresponding path program 1 times [2019-11-16 00:34:34,851 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:34,851 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350459729] [2019-11-16 00:34:34,851 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:34,852 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:34,852 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:34,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:34,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:34,941 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1350459729] [2019-11-16 00:34:34,942 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:34,942 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:34,942 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940648930] [2019-11-16 00:34:34,942 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:34,943 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:34,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:34,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:34,943 INFO L87 Difference]: Start difference. First operand 6859 states and 8493 transitions. Second operand 5 states. [2019-11-16 00:34:36,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:36,394 INFO L93 Difference]: Finished difference Result 18399 states and 22836 transitions. [2019-11-16 00:34:36,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:36,394 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:36,394 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:36,403 INFO L225 Difference]: With dead ends: 18399 [2019-11-16 00:34:36,403 INFO L226 Difference]: Without dead ends: 11764 [2019-11-16 00:34:36,408 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:36,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11764 states. [2019-11-16 00:34:37,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11764 to 6871. [2019-11-16 00:34:37,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6871 states. [2019-11-16 00:34:37,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6871 states to 6871 states and 8451 transitions. [2019-11-16 00:34:37,028 INFO L78 Accepts]: Start accepts. Automaton has 6871 states and 8451 transitions. Word has length 168 [2019-11-16 00:34:37,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:37,029 INFO L462 AbstractCegarLoop]: Abstraction has 6871 states and 8451 transitions. [2019-11-16 00:34:37,029 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:37,029 INFO L276 IsEmpty]: Start isEmpty. Operand 6871 states and 8451 transitions. [2019-11-16 00:34:37,030 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:37,030 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:37,031 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:37,031 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:37,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:37,031 INFO L82 PathProgramCache]: Analyzing trace with hash 1274052288, now seen corresponding path program 1 times [2019-11-16 00:34:37,032 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:37,032 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875251643] [2019-11-16 00:34:37,032 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:37,032 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:37,032 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:37,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:37,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:37,114 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1875251643] [2019-11-16 00:34:37,115 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:37,115 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:37,115 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135240196] [2019-11-16 00:34:37,115 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:37,116 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:37,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:37,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:37,116 INFO L87 Difference]: Start difference. First operand 6871 states and 8451 transitions. Second operand 5 states. [2019-11-16 00:34:38,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:38,642 INFO L93 Difference]: Finished difference Result 18743 states and 23116 transitions. [2019-11-16 00:34:38,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:38,642 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:38,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:38,650 INFO L225 Difference]: With dead ends: 18743 [2019-11-16 00:34:38,650 INFO L226 Difference]: Without dead ends: 12110 [2019-11-16 00:34:38,656 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:38,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12110 states. [2019-11-16 00:34:39,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12110 to 6883. [2019-11-16 00:34:39,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6883 states. [2019-11-16 00:34:39,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6883 states to 6883 states and 8409 transitions. [2019-11-16 00:34:39,337 INFO L78 Accepts]: Start accepts. Automaton has 6883 states and 8409 transitions. Word has length 168 [2019-11-16 00:34:39,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:39,338 INFO L462 AbstractCegarLoop]: Abstraction has 6883 states and 8409 transitions. [2019-11-16 00:34:39,338 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:39,338 INFO L276 IsEmpty]: Start isEmpty. Operand 6883 states and 8409 transitions. [2019-11-16 00:34:39,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:39,339 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:39,339 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:39,339 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:39,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:39,339 INFO L82 PathProgramCache]: Analyzing trace with hash 1834752066, now seen corresponding path program 1 times [2019-11-16 00:34:39,339 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:39,339 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039733121] [2019-11-16 00:34:39,340 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:39,340 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:39,340 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:39,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:39,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:39,417 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039733121] [2019-11-16 00:34:39,417 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:39,417 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:39,417 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090868512] [2019-11-16 00:34:39,418 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:39,418 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:39,418 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:39,418 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:39,419 INFO L87 Difference]: Start difference. First operand 6883 states and 8409 transitions. Second operand 5 states. [2019-11-16 00:34:40,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:40,883 INFO L93 Difference]: Finished difference Result 19395 states and 23796 transitions. [2019-11-16 00:34:40,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:40,883 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:40,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:40,893 INFO L225 Difference]: With dead ends: 19395 [2019-11-16 00:34:40,893 INFO L226 Difference]: Without dead ends: 12778 [2019-11-16 00:34:40,899 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:40,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12778 states. [2019-11-16 00:34:41,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12778 to 6895. [2019-11-16 00:34:41,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6895 states. [2019-11-16 00:34:41,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6895 states to 6895 states and 8367 transitions. [2019-11-16 00:34:41,706 INFO L78 Accepts]: Start accepts. Automaton has 6895 states and 8367 transitions. Word has length 168 [2019-11-16 00:34:41,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:41,706 INFO L462 AbstractCegarLoop]: Abstraction has 6895 states and 8367 transitions. [2019-11-16 00:34:41,706 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:41,706 INFO L276 IsEmpty]: Start isEmpty. Operand 6895 states and 8367 transitions. [2019-11-16 00:34:41,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:41,707 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:41,707 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:41,707 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:41,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:41,707 INFO L82 PathProgramCache]: Analyzing trace with hash 1481663684, now seen corresponding path program 1 times [2019-11-16 00:34:41,708 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:41,708 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905293316] [2019-11-16 00:34:41,708 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:41,708 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:41,708 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:41,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:34:41,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:34:41,779 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1905293316] [2019-11-16 00:34:41,779 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:34:41,779 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:34:41,779 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [430512281] [2019-11-16 00:34:41,780 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:34:41,780 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:34:41,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:34:41,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:34:41,780 INFO L87 Difference]: Start difference. First operand 6895 states and 8367 transitions. Second operand 5 states. [2019-11-16 00:34:43,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:34:43,466 INFO L93 Difference]: Finished difference Result 19739 states and 24076 transitions. [2019-11-16 00:34:43,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:34:43,467 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-16 00:34:43,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:34:43,480 INFO L225 Difference]: With dead ends: 19739 [2019-11-16 00:34:43,481 INFO L226 Difference]: Without dead ends: 13124 [2019-11-16 00:34:43,489 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:34:43,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13124 states. [2019-11-16 00:34:44,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13124 to 6907. [2019-11-16 00:34:44,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6907 states. [2019-11-16 00:34:44,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6907 states to 6907 states and 8325 transitions. [2019-11-16 00:34:44,248 INFO L78 Accepts]: Start accepts. Automaton has 6907 states and 8325 transitions. Word has length 168 [2019-11-16 00:34:44,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:34:44,248 INFO L462 AbstractCegarLoop]: Abstraction has 6907 states and 8325 transitions. [2019-11-16 00:34:44,248 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:34:44,249 INFO L276 IsEmpty]: Start isEmpty. Operand 6907 states and 8325 transitions. [2019-11-16 00:34:44,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-16 00:34:44,249 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:34:44,250 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:34:44,250 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:34:44,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:34:44,250 INFO L82 PathProgramCache]: Analyzing trace with hash 1905310406, now seen corresponding path program 1 times [2019-11-16 00:34:44,250 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:34:44,250 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791779806] [2019-11-16 00:34:44,250 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:44,250 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:34:44,251 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:34:44,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-16 00:34:44,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-16 00:34:44,400 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-16 00:34:44,400 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-11-16 00:34:44,600 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 16.11 12:34:44 BoogieIcfgContainer [2019-11-16 00:34:44,601 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-16 00:34:44,601 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-16 00:34:44,601 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-16 00:34:44,601 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-16 00:34:44,602 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:34:07" (3/4) ... [2019-11-16 00:34:44,604 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-16 00:34:44,828 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_249f564f-6e55-495b-ae4e-22264306e622/bin/uautomizer/witness.graphml [2019-11-16 00:34:44,828 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-16 00:34:44,830 INFO L168 Benchmark]: Toolchain (without parser) took 42271.41 ms. Allocated memory was 1.0 GB in the beginning and 4.0 GB in the end (delta: 3.0 GB). Free memory was 948.8 MB in the beginning and 1.4 GB in the end (delta: -493.6 MB). Peak memory consumption was 2.5 GB. Max. memory is 11.5 GB. [2019-11-16 00:34:44,831 INFO L168 Benchmark]: CDTParser took 0.26 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-16 00:34:44,831 INFO L168 Benchmark]: CACSL2BoogieTranslator took 629.65 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 185.1 MB). Free memory was 943.4 MB in the beginning and 1.2 GB in the end (delta: -224.3 MB). Peak memory consumption was 23.4 MB. Max. memory is 11.5 GB. [2019-11-16 00:34:44,831 INFO L168 Benchmark]: Boogie Procedure Inliner took 146.57 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2019-11-16 00:34:44,832 INFO L168 Benchmark]: Boogie Preprocessor took 170.00 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2019-11-16 00:34:44,832 INFO L168 Benchmark]: RCFGBuilder took 3526.26 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 135.1 MB). Peak memory consumption was 233.6 MB. Max. memory is 11.5 GB. [2019-11-16 00:34:44,832 INFO L168 Benchmark]: TraceAbstraction took 37558.19 ms. Allocated memory was 1.2 GB in the beginning and 4.0 GB in the end (delta: 2.8 GB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -523.3 MB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. [2019-11-16 00:34:44,833 INFO L168 Benchmark]: Witness Printer took 227.38 ms. Allocated memory is still 4.0 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 81.3 MB). Peak memory consumption was 81.3 MB. Max. memory is 11.5 GB. [2019-11-16 00:34:44,835 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.26 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 629.65 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 185.1 MB). Free memory was 943.4 MB in the beginning and 1.2 GB in the end (delta: -224.3 MB). Peak memory consumption was 23.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 146.57 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 170.00 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 3526.26 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 135.1 MB). Peak memory consumption was 233.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 37558.19 ms. Allocated memory was 1.2 GB in the beginning and 4.0 GB in the end (delta: 2.8 GB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -523.3 MB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. * Witness Printer took 227.38 ms. Allocated memory is still 4.0 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 81.3 MB). Peak memory consumption was 81.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int t9_pc = 0; [L25] int t10_pc = 0; [L26] int t11_pc = 0; [L27] int t12_pc = 0; [L28] int t13_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int t5_st ; [L35] int t6_st ; [L36] int t7_st ; [L37] int t8_st ; [L38] int t9_st ; [L39] int t10_st ; [L40] int t11_st ; [L41] int t12_st ; [L42] int t13_st ; [L43] int m_i ; [L44] int t1_i ; [L45] int t2_i ; [L46] int t3_i ; [L47] int t4_i ; [L48] int t5_i ; [L49] int t6_i ; [L50] int t7_i ; [L51] int t8_i ; [L52] int t9_i ; [L53] int t10_i ; [L54] int t11_i ; [L55] int t12_i ; [L56] int t13_i ; [L57] int M_E = 2; [L58] int T1_E = 2; [L59] int T2_E = 2; [L60] int T3_E = 2; [L61] int T4_E = 2; [L62] int T5_E = 2; [L63] int T6_E = 2; [L64] int T7_E = 2; [L65] int T8_E = 2; [L66] int T9_E = 2; [L67] int T10_E = 2; [L68] int T11_E = 2; [L69] int T12_E = 2; [L70] int T13_E = 2; [L71] int E_1 = 2; [L72] int E_2 = 2; [L73] int E_3 = 2; [L74] int E_4 = 2; [L75] int E_5 = 2; [L76] int E_6 = 2; [L77] int E_7 = 2; [L78] int E_8 = 2; [L79] int E_9 = 2; [L80] int E_10 = 2; [L81] int E_11 = 2; [L82] int E_12 = 2; [L83] int E_13 = 2; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=0, m_pc=0, m_st=0, T10_E=2, t10_i=0, t10_pc=0, t10_st=0, T11_E=2, t11_i=0, t11_pc=0, t11_st=0, T12_E=2, t12_i=0, t12_pc=0, t12_st=0, T13_E=2, t13_i=0, t13_pc=0, t13_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0, T7_E=2, t7_i=0, t7_pc=0, t7_st=0, T8_E=2, t8_i=0, t8_pc=0, t8_st=0, T9_E=2, t9_i=0, t9_pc=0, t9_st=0] [L1927] int __retres1 ; [L1830] m_i = 1 [L1831] t1_i = 1 [L1832] t2_i = 1 [L1833] t3_i = 1 [L1834] t4_i = 1 [L1835] t5_i = 1 [L1836] t6_i = 1 [L1837] t7_i = 1 [L1838] t8_i = 1 [L1839] t9_i = 1 [L1840] t10_i = 1 [L1841] t11_i = 1 [L1842] t12_i = 1 [L1843] t13_i = 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1868] int kernel_st ; [L1869] int tmp ; [L1870] int tmp___0 ; [L1874] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L871] COND TRUE m_i == 1 [L872] m_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L876] COND TRUE t1_i == 1 [L877] t1_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L881] COND TRUE t2_i == 1 [L882] t2_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L886] COND TRUE t3_i == 1 [L887] t3_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L891] COND TRUE t4_i == 1 [L892] t4_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L896] COND TRUE t5_i == 1 [L897] t5_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L901] COND TRUE t6_i == 1 [L902] t6_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L906] COND TRUE t7_i == 1 [L907] t7_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L911] COND TRUE t8_i == 1 [L912] t8_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L916] COND TRUE t9_i == 1 [L917] t9_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L921] COND TRUE t10_i == 1 [L922] t10_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L926] COND TRUE t11_i == 1 [L927] t11_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L931] COND TRUE t12_i == 1 [L932] t12_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L936] COND TRUE t13_i == 1 [L937] t13_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1248] COND FALSE !(M_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1253] COND FALSE !(T1_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1258] COND FALSE !(T2_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1263] COND FALSE !(T3_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1268] COND FALSE !(T4_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1273] COND FALSE !(T5_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1278] COND FALSE !(T6_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1283] COND FALSE !(T7_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1288] COND FALSE !(T8_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1293] COND FALSE !(T9_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1298] COND FALSE !(T10_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1303] COND FALSE !(T11_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1308] COND FALSE !(T12_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1313] COND FALSE !(T13_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1318] COND FALSE !(E_1 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1323] COND FALSE !(E_2 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1328] COND FALSE !(E_3 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1333] COND FALSE !(E_4 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1338] COND FALSE !(E_5 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1343] COND FALSE !(E_6 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1348] COND FALSE !(E_7 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1353] COND FALSE !(E_8 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1358] COND FALSE !(E_9 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1363] COND FALSE !(E_10 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1368] COND FALSE !(E_11 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1373] COND FALSE !(E_12 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1378] COND FALSE !(E_13 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1531] int tmp ; [L1532] int tmp___0 ; [L1533] int tmp___1 ; [L1534] int tmp___2 ; [L1535] int tmp___3 ; [L1536] int tmp___4 ; [L1537] int tmp___5 ; [L1538] int tmp___6 ; [L1539] int tmp___7 ; [L1540] int tmp___8 ; [L1541] int tmp___9 ; [L1542] int tmp___10 ; [L1543] int tmp___11 ; [L1544] int tmp___12 ; [L594] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L597] COND FALSE !(m_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L607] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L609] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1548] tmp = is_master_triggered() [L1550] COND FALSE !(\read(tmp)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L613] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L616] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L626] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L628] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1556] tmp___0 = is_transmit1_triggered() [L1558] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L632] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L635] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L645] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L647] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1564] tmp___1 = is_transmit2_triggered() [L1566] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L651] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L654] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L664] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L666] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1572] tmp___2 = is_transmit3_triggered() [L1574] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L670] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L673] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L683] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L685] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1580] tmp___3 = is_transmit4_triggered() [L1582] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L689] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L692] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L702] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L704] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1588] tmp___4 = is_transmit5_triggered() [L1590] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L708] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L711] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L721] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L723] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1596] tmp___5 = is_transmit6_triggered() [L1598] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L727] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L730] COND FALSE !(t7_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L740] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L742] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1604] tmp___6 = is_transmit7_triggered() [L1606] COND FALSE !(\read(tmp___6)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L746] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L749] COND FALSE !(t8_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L759] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L761] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1612] tmp___7 = is_transmit8_triggered() [L1614] COND FALSE !(\read(tmp___7)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L765] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L768] COND FALSE !(t9_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L778] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L780] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1620] tmp___8 = is_transmit9_triggered() [L1622] COND FALSE !(\read(tmp___8)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L784] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L787] COND FALSE !(t10_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L797] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L799] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1628] tmp___9 = is_transmit10_triggered() [L1630] COND FALSE !(\read(tmp___9)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L803] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L806] COND FALSE !(t11_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L816] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L818] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1636] tmp___10 = is_transmit11_triggered() [L1638] COND FALSE !(\read(tmp___10)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L822] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L825] COND FALSE !(t12_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L835] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L837] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1644] tmp___11 = is_transmit12_triggered() [L1646] COND FALSE !(\read(tmp___11)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L841] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L844] COND FALSE !(t13_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L854] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L856] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1652] tmp___12 = is_transmit13_triggered() [L1654] COND FALSE !(\read(tmp___12)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1391] COND FALSE !(M_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1396] COND FALSE !(T1_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1401] COND FALSE !(T2_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1406] COND FALSE !(T3_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1411] COND FALSE !(T4_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1416] COND FALSE !(T5_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1421] COND FALSE !(T6_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1426] COND FALSE !(T7_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1431] COND FALSE !(T8_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1436] COND FALSE !(T9_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1441] COND FALSE !(T10_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1446] COND FALSE !(T11_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1451] COND FALSE !(T12_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1456] COND FALSE !(T13_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1461] COND FALSE !(E_1 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1466] COND FALSE !(E_2 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1471] COND FALSE !(E_3 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1476] COND FALSE !(E_4 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1481] COND FALSE !(E_5 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1486] COND FALSE !(E_6 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1491] COND FALSE !(E_7 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1496] COND FALSE !(E_8 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1501] COND FALSE !(E_9 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1506] COND FALSE !(E_10 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1511] COND FALSE !(E_11 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1516] COND FALSE !(E_12 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1521] COND FALSE !(E_13 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1882] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1885] kernel_st = 1 [L1027] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1031] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L946] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L949] COND TRUE m_st == 0 [L950] __retres1 = 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1022] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1034] tmp = exists_runnable_thread() [L1036] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1041] COND TRUE m_st == 0 [L1042] int tmp_ndt_1; [L1043] tmp_ndt_1 = __VERIFIER_nondet_int() [L1044] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1055] COND TRUE t1_st == 0 [L1056] int tmp_ndt_2; [L1057] tmp_ndt_2 = __VERIFIER_nondet_int() [L1058] COND FALSE !(\read(tmp_ndt_2)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L11] __VERIFIER_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 1886 locations, 1 error locations. Result: UNSAFE, OverallTime: 37.4s, OverallIterations: 43, TraceHistogramMax: 1, AutomataDifference: 21.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 108702 SDtfs, 149913 SDslu, 65057 SDs, 0 SdLazy, 1934 SolverSat, 1116 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 147 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=6907occurred in iteration=42, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 11.8s AutomataMinimizationTime, 42 MinimizatonAttempts, 52260 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.2s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 1.7s InterpolantComputationTime, 7194 NumberOfCodeBlocks, 7194 NumberOfCodeBlocksAsserted, 43 NumberOfCheckSat, 6984 ConstructedInterpolants, 0 QuantifiedInterpolants, 1620728 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 42 InterpolantComputations, 42 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...