./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05a526ca9d0710db502cdfc74677e2807f071449 ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-11-16 00:01:50,036 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-16 00:01:50,038 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-16 00:01:50,053 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-16 00:01:50,054 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-16 00:01:50,055 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-16 00:01:50,057 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-16 00:01:50,066 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-16 00:01:50,070 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-16 00:01:50,075 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-16 00:01:50,077 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-16 00:01:50,078 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-16 00:01:50,079 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-16 00:01:50,081 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-16 00:01:50,083 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-16 00:01:50,084 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-16 00:01:50,084 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-16 00:01:50,085 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-16 00:01:50,088 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-16 00:01:50,092 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-16 00:01:50,095 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-16 00:01:50,097 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-16 00:01:50,099 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-16 00:01:50,100 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-16 00:01:50,103 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-16 00:01:50,104 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-16 00:01:50,104 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-16 00:01:50,106 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-16 00:01:50,106 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-16 00:01:50,107 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-16 00:01:50,107 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-16 00:01:50,108 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-16 00:01:50,108 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-16 00:01:50,109 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-16 00:01:50,110 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-16 00:01:50,111 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-16 00:01:50,111 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-16 00:01:50,112 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-16 00:01:50,112 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-16 00:01:50,113 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-16 00:01:50,113 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-16 00:01:50,114 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-16 00:01:50,140 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-16 00:01:50,140 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-16 00:01:50,141 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-16 00:01:50,141 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-16 00:01:50,142 INFO L138 SettingsManager]: * Use SBE=true [2019-11-16 00:01:50,142 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-16 00:01:50,142 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-16 00:01:50,142 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-16 00:01:50,143 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-16 00:01:50,143 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-16 00:01:50,143 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-16 00:01:50,143 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-16 00:01:50,143 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-16 00:01:50,144 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-16 00:01:50,144 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-16 00:01:50,144 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-16 00:01:50,144 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-16 00:01:50,145 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-16 00:01:50,145 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-16 00:01:50,145 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-16 00:01:50,145 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-16 00:01:50,145 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-16 00:01:50,146 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-16 00:01:50,146 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-16 00:01:50,146 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-16 00:01:50,146 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-16 00:01:50,147 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-16 00:01:50,147 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-16 00:01:50,147 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05a526ca9d0710db502cdfc74677e2807f071449 [2019-11-16 00:01:50,173 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-16 00:01:50,183 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-16 00:01:50,190 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-16 00:01:50,191 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-16 00:01:50,191 INFO L275 PluginConnector]: CDTParser initialized [2019-11-16 00:01:50,192 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.16.cil.c [2019-11-16 00:01:50,260 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/data/9fbbf1c85/9dba33e3f53942928f64da3af03cf6a2/FLAG132bae6a7 [2019-11-16 00:01:50,761 INFO L306 CDTParser]: Found 1 translation units. [2019-11-16 00:01:50,762 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/sv-benchmarks/c/systemc/transmitter.16.cil.c [2019-11-16 00:01:50,781 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/data/9fbbf1c85/9dba33e3f53942928f64da3af03cf6a2/FLAG132bae6a7 [2019-11-16 00:01:51,084 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/data/9fbbf1c85/9dba33e3f53942928f64da3af03cf6a2 [2019-11-16 00:01:51,087 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-16 00:01:51,089 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-16 00:01:51,096 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-16 00:01:51,096 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-16 00:01:51,099 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-16 00:01:51,100 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:01:51" (1/1) ... [2019-11-16 00:01:51,103 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4e6d2bfc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51, skipping insertion in model container [2019-11-16 00:01:51,103 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:01:51" (1/1) ... [2019-11-16 00:01:51,115 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-16 00:01:51,178 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-16 00:01:51,593 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-16 00:01:51,601 INFO L188 MainTranslator]: Completed pre-run [2019-11-16 00:01:51,703 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-16 00:01:51,736 INFO L192 MainTranslator]: Completed translation [2019-11-16 00:01:51,736 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51 WrapperNode [2019-11-16 00:01:51,736 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-16 00:01:51,737 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-16 00:01:51,737 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-16 00:01:51,737 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-16 00:01:51,746 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51" (1/1) ... [2019-11-16 00:01:51,759 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51" (1/1) ... [2019-11-16 00:01:51,910 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-16 00:01:51,910 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-16 00:01:51,910 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-16 00:01:51,910 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-16 00:01:51,920 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51" (1/1) ... [2019-11-16 00:01:51,920 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51" (1/1) ... [2019-11-16 00:01:51,932 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51" (1/1) ... [2019-11-16 00:01:51,933 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51" (1/1) ... [2019-11-16 00:01:51,979 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51" (1/1) ... [2019-11-16 00:01:52,019 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51" (1/1) ... [2019-11-16 00:01:52,027 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51" (1/1) ... [2019-11-16 00:01:52,046 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-16 00:01:52,046 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-16 00:01:52,046 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-16 00:01:52,046 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-16 00:01:52,047 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-16 00:01:52,117 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-16 00:01:52,118 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-16 00:01:55,662 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-16 00:01:55,663 INFO L284 CfgBuilder]: Removed 624 assume(true) statements. [2019-11-16 00:01:55,668 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:01:55 BoogieIcfgContainer [2019-11-16 00:01:55,668 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-16 00:01:55,670 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-16 00:01:55,670 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-16 00:01:55,673 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-16 00:01:55,674 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 16.11 12:01:51" (1/3) ... [2019-11-16 00:01:55,676 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4e0456cd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 12:01:55, skipping insertion in model container [2019-11-16 00:01:55,676 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:01:51" (2/3) ... [2019-11-16 00:01:55,676 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4e0456cd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 12:01:55, skipping insertion in model container [2019-11-16 00:01:55,676 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:01:55" (3/3) ... [2019-11-16 00:01:55,678 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.16.cil.c [2019-11-16 00:01:55,687 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-16 00:01:55,700 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-16 00:01:55,711 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-16 00:01:55,763 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-16 00:01:55,764 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-16 00:01:55,764 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-16 00:01:55,764 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-16 00:01:55,764 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-16 00:01:55,765 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-16 00:01:55,765 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-16 00:01:55,765 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-16 00:01:55,810 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states. [2019-11-16 00:01:55,830 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:01:55,831 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:01:55,832 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:01:55,834 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:01:55,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:01:55,839 INFO L82 PathProgramCache]: Analyzing trace with hash -1186634079, now seen corresponding path program 1 times [2019-11-16 00:01:55,847 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:01:55,847 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403874161] [2019-11-16 00:01:55,847 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:55,848 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:55,848 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:01:55,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:01:56,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:01:56,195 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403874161] [2019-11-16 00:01:56,195 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:01:56,196 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:01:56,196 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1130787005] [2019-11-16 00:01:56,201 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:01:56,202 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:01:56,214 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:01:56,215 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:56,217 INFO L87 Difference]: Start difference. First operand 2018 states. Second operand 3 states. [2019-11-16 00:01:56,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:01:56,389 INFO L93 Difference]: Finished difference Result 4031 states and 6077 transitions. [2019-11-16 00:01:56,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:01:56,391 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:01:56,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:01:56,423 INFO L225 Difference]: With dead ends: 4031 [2019-11-16 00:01:56,424 INFO L226 Difference]: Without dead ends: 2014 [2019-11-16 00:01:56,436 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:56,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2014 states. [2019-11-16 00:01:56,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2014 to 2014. [2019-11-16 00:01:56,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2014 states. [2019-11-16 00:01:56,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2014 states to 2014 states and 3000 transitions. [2019-11-16 00:01:56,579 INFO L78 Accepts]: Start accepts. Automaton has 2014 states and 3000 transitions. Word has length 178 [2019-11-16 00:01:56,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:01:56,580 INFO L462 AbstractCegarLoop]: Abstraction has 2014 states and 3000 transitions. [2019-11-16 00:01:56,580 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:01:56,581 INFO L276 IsEmpty]: Start isEmpty. Operand 2014 states and 3000 transitions. [2019-11-16 00:01:56,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:01:56,596 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:01:56,597 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:01:56,597 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:01:56,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:01:56,598 INFO L82 PathProgramCache]: Analyzing trace with hash -355980445, now seen corresponding path program 1 times [2019-11-16 00:01:56,598 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:01:56,599 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949305267] [2019-11-16 00:01:56,599 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:56,599 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:56,599 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:01:56,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:01:56,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:01:56,733 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949305267] [2019-11-16 00:01:56,733 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:01:56,734 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:01:56,734 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989741618] [2019-11-16 00:01:56,736 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:01:56,736 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:01:56,736 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:01:56,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:56,737 INFO L87 Difference]: Start difference. First operand 2014 states and 3000 transitions. Second operand 3 states. [2019-11-16 00:01:56,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:01:56,806 INFO L93 Difference]: Finished difference Result 4015 states and 5978 transitions. [2019-11-16 00:01:56,806 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:01:56,806 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:01:56,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:01:56,817 INFO L225 Difference]: With dead ends: 4015 [2019-11-16 00:01:56,818 INFO L226 Difference]: Without dead ends: 2014 [2019-11-16 00:01:56,822 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:56,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2014 states. [2019-11-16 00:01:56,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2014 to 2014. [2019-11-16 00:01:56,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2014 states. [2019-11-16 00:01:56,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2014 states to 2014 states and 2999 transitions. [2019-11-16 00:01:56,885 INFO L78 Accepts]: Start accepts. Automaton has 2014 states and 2999 transitions. Word has length 178 [2019-11-16 00:01:56,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:01:56,885 INFO L462 AbstractCegarLoop]: Abstraction has 2014 states and 2999 transitions. [2019-11-16 00:01:56,885 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:01:56,886 INFO L276 IsEmpty]: Start isEmpty. Operand 2014 states and 2999 transitions. [2019-11-16 00:01:56,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:01:56,888 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:01:56,888 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:01:56,889 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:01:56,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:01:56,889 INFO L82 PathProgramCache]: Analyzing trace with hash -864759259, now seen corresponding path program 1 times [2019-11-16 00:01:56,889 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:01:56,890 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742603042] [2019-11-16 00:01:56,890 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:56,890 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:56,890 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:01:56,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:01:56,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:01:57,000 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [742603042] [2019-11-16 00:01:57,001 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:01:57,001 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:01:57,002 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301027819] [2019-11-16 00:01:57,004 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:01:57,004 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:01:57,005 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:01:57,005 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:57,008 INFO L87 Difference]: Start difference. First operand 2014 states and 2999 transitions. Second operand 3 states. [2019-11-16 00:01:57,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:01:57,358 INFO L93 Difference]: Finished difference Result 5736 states and 8515 transitions. [2019-11-16 00:01:57,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:01:57,359 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:01:57,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:01:57,380 INFO L225 Difference]: With dead ends: 5736 [2019-11-16 00:01:57,380 INFO L226 Difference]: Without dead ends: 3741 [2019-11-16 00:01:57,383 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:57,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3741 states. [2019-11-16 00:01:57,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3741 to 3739. [2019-11-16 00:01:57,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:01:57,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5529 transitions. [2019-11-16 00:01:57,502 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5529 transitions. Word has length 178 [2019-11-16 00:01:57,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:01:57,503 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5529 transitions. [2019-11-16 00:01:57,503 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:01:57,503 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5529 transitions. [2019-11-16 00:01:57,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:01:57,505 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:01:57,506 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:01:57,506 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:01:57,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:01:57,506 INFO L82 PathProgramCache]: Analyzing trace with hash 439277764, now seen corresponding path program 1 times [2019-11-16 00:01:57,507 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:01:57,507 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807140324] [2019-11-16 00:01:57,507 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:57,507 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:57,507 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:01:57,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:01:57,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:01:57,609 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807140324] [2019-11-16 00:01:57,609 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:01:57,609 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:01:57,609 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077268823] [2019-11-16 00:01:57,611 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:01:57,611 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:01:57,611 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:01:57,612 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:57,612 INFO L87 Difference]: Start difference. First operand 3739 states and 5529 transitions. Second operand 3 states. [2019-11-16 00:01:57,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:01:57,745 INFO L93 Difference]: Finished difference Result 7458 states and 11024 transitions. [2019-11-16 00:01:57,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:01:57,745 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:01:57,746 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:01:57,766 INFO L225 Difference]: With dead ends: 7458 [2019-11-16 00:01:57,766 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:01:57,773 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:57,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:01:57,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:01:57,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:01:57,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5521 transitions. [2019-11-16 00:01:57,900 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5521 transitions. Word has length 178 [2019-11-16 00:01:57,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:01:57,900 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5521 transitions. [2019-11-16 00:01:57,901 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:01:57,901 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5521 transitions. [2019-11-16 00:01:57,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:01:57,902 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:01:57,903 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:01:57,903 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:01:57,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:01:57,904 INFO L82 PathProgramCache]: Analyzing trace with hash -265147644, now seen corresponding path program 1 times [2019-11-16 00:01:57,904 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:01:57,904 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699521202] [2019-11-16 00:01:57,904 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:57,904 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:57,905 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:01:57,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:01:57,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:01:57,998 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699521202] [2019-11-16 00:01:57,999 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:01:57,999 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:01:57,999 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527080155] [2019-11-16 00:01:58,000 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:01:58,000 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:01:58,000 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:01:58,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:58,001 INFO L87 Difference]: Start difference. First operand 3739 states and 5521 transitions. Second operand 3 states. [2019-11-16 00:01:58,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:01:58,129 INFO L93 Difference]: Finished difference Result 7456 states and 11005 transitions. [2019-11-16 00:01:58,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:01:58,130 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:01:58,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:01:58,150 INFO L225 Difference]: With dead ends: 7456 [2019-11-16 00:01:58,150 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:01:58,156 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:58,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:01:58,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:01:58,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:01:58,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5513 transitions. [2019-11-16 00:01:58,284 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5513 transitions. Word has length 178 [2019-11-16 00:01:58,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:01:58,285 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5513 transitions. [2019-11-16 00:01:58,285 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:01:58,285 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5513 transitions. [2019-11-16 00:01:58,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:01:58,287 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:01:58,288 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:01:58,288 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:01:58,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:01:58,288 INFO L82 PathProgramCache]: Analyzing trace with hash 79680518, now seen corresponding path program 1 times [2019-11-16 00:01:58,289 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:01:58,289 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751371088] [2019-11-16 00:01:58,289 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:58,289 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:58,289 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:01:58,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:01:58,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:01:58,363 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751371088] [2019-11-16 00:01:58,364 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:01:58,364 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:01:58,364 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1789355788] [2019-11-16 00:01:58,365 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:01:58,365 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:01:58,365 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:01:58,365 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:58,366 INFO L87 Difference]: Start difference. First operand 3739 states and 5513 transitions. Second operand 3 states. [2019-11-16 00:01:58,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:01:58,498 INFO L93 Difference]: Finished difference Result 7455 states and 10988 transitions. [2019-11-16 00:01:58,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:01:58,499 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:01:58,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:01:58,519 INFO L225 Difference]: With dead ends: 7455 [2019-11-16 00:01:58,520 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:01:58,526 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:58,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:01:58,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:01:58,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:01:58,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5505 transitions. [2019-11-16 00:01:58,684 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5505 transitions. Word has length 178 [2019-11-16 00:01:58,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:01:58,685 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5505 transitions. [2019-11-16 00:01:58,685 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:01:58,685 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5505 transitions. [2019-11-16 00:01:58,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:01:58,687 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:01:58,688 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:01:58,688 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:01:58,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:01:58,696 INFO L82 PathProgramCache]: Analyzing trace with hash 1720166854, now seen corresponding path program 1 times [2019-11-16 00:01:58,696 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:01:58,697 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350432088] [2019-11-16 00:01:58,697 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:58,697 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:58,697 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:01:58,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:01:58,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:01:58,823 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1350432088] [2019-11-16 00:01:58,823 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:01:58,824 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:01:58,824 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435736335] [2019-11-16 00:01:58,824 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:01:58,824 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:01:58,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:01:58,825 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:58,825 INFO L87 Difference]: Start difference. First operand 3739 states and 5505 transitions. Second operand 3 states. [2019-11-16 00:01:58,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:01:58,946 INFO L93 Difference]: Finished difference Result 7454 states and 10971 transitions. [2019-11-16 00:01:58,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:01:58,946 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:01:58,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:01:58,966 INFO L225 Difference]: With dead ends: 7454 [2019-11-16 00:01:58,966 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:01:58,972 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:58,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:01:59,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:01:59,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:01:59,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5497 transitions. [2019-11-16 00:01:59,096 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5497 transitions. Word has length 178 [2019-11-16 00:01:59,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:01:59,096 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5497 transitions. [2019-11-16 00:01:59,097 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:01:59,097 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5497 transitions. [2019-11-16 00:01:59,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:01:59,099 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:01:59,099 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:01:59,099 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:01:59,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:01:59,100 INFO L82 PathProgramCache]: Analyzing trace with hash -443671546, now seen corresponding path program 1 times [2019-11-16 00:01:59,100 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:01:59,100 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481485877] [2019-11-16 00:01:59,100 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:59,101 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:59,101 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:01:59,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:01:59,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:01:59,164 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481485877] [2019-11-16 00:01:59,165 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:01:59,165 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:01:59,165 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1146519801] [2019-11-16 00:01:59,166 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:01:59,166 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:01:59,166 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:01:59,166 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:59,166 INFO L87 Difference]: Start difference. First operand 3739 states and 5497 transitions. Second operand 3 states. [2019-11-16 00:01:59,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:01:59,276 INFO L93 Difference]: Finished difference Result 7453 states and 10954 transitions. [2019-11-16 00:01:59,277 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:01:59,277 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:01:59,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:01:59,310 INFO L225 Difference]: With dead ends: 7453 [2019-11-16 00:01:59,311 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:01:59,317 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:59,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:01:59,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:01:59,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:01:59,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5489 transitions. [2019-11-16 00:01:59,438 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5489 transitions. Word has length 178 [2019-11-16 00:01:59,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:01:59,440 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5489 transitions. [2019-11-16 00:01:59,441 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:01:59,441 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5489 transitions. [2019-11-16 00:01:59,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:01:59,443 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:01:59,443 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:01:59,443 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:01:59,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:01:59,444 INFO L82 PathProgramCache]: Analyzing trace with hash -1898946106, now seen corresponding path program 1 times [2019-11-16 00:01:59,444 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:01:59,444 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787204171] [2019-11-16 00:01:59,444 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:59,444 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:59,445 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:01:59,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:01:59,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:01:59,505 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [787204171] [2019-11-16 00:01:59,506 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:01:59,506 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:01:59,506 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73849010] [2019-11-16 00:01:59,507 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:01:59,507 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:01:59,507 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:01:59,507 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:59,507 INFO L87 Difference]: Start difference. First operand 3739 states and 5489 transitions. Second operand 3 states. [2019-11-16 00:01:59,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:01:59,622 INFO L93 Difference]: Finished difference Result 7452 states and 10937 transitions. [2019-11-16 00:01:59,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:01:59,623 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:01:59,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:01:59,631 INFO L225 Difference]: With dead ends: 7452 [2019-11-16 00:01:59,631 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:01:59,637 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:59,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:01:59,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:01:59,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:01:59,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5481 transitions. [2019-11-16 00:01:59,758 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5481 transitions. Word has length 178 [2019-11-16 00:01:59,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:01:59,758 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5481 transitions. [2019-11-16 00:01:59,758 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:01:59,758 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5481 transitions. [2019-11-16 00:01:59,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:01:59,760 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:01:59,760 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:01:59,761 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:01:59,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:01:59,761 INFO L82 PathProgramCache]: Analyzing trace with hash -1253153786, now seen corresponding path program 1 times [2019-11-16 00:01:59,761 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:01:59,762 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [465484646] [2019-11-16 00:01:59,762 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:59,762 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:01:59,762 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:01:59,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:01:59,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:01:59,885 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [465484646] [2019-11-16 00:01:59,886 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:01:59,886 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:01:59,886 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004122283] [2019-11-16 00:01:59,888 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:01:59,888 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:01:59,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:01:59,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:01:59,889 INFO L87 Difference]: Start difference. First operand 3739 states and 5481 transitions. Second operand 3 states. [2019-11-16 00:02:00,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:00,005 INFO L93 Difference]: Finished difference Result 7451 states and 10920 transitions. [2019-11-16 00:02:00,005 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:00,005 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:00,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:00,012 INFO L225 Difference]: With dead ends: 7451 [2019-11-16 00:02:00,012 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:00,022 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:00,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:00,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:00,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:00,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5473 transitions. [2019-11-16 00:02:00,132 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5473 transitions. Word has length 178 [2019-11-16 00:02:00,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:00,132 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5473 transitions. [2019-11-16 00:02:00,132 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:00,132 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5473 transitions. [2019-11-16 00:02:00,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:00,134 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:00,134 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:00,135 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:00,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:00,135 INFO L82 PathProgramCache]: Analyzing trace with hash 568793542, now seen corresponding path program 1 times [2019-11-16 00:02:00,135 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:00,135 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917420130] [2019-11-16 00:02:00,136 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:00,136 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:00,136 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:00,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:00,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:00,194 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917420130] [2019-11-16 00:02:00,194 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:00,194 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:00,194 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933444581] [2019-11-16 00:02:00,195 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:00,195 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:00,195 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:00,195 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:00,196 INFO L87 Difference]: Start difference. First operand 3739 states and 5473 transitions. Second operand 3 states. [2019-11-16 00:02:00,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:00,313 INFO L93 Difference]: Finished difference Result 7450 states and 10903 transitions. [2019-11-16 00:02:00,314 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:00,314 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:00,314 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:00,321 INFO L225 Difference]: With dead ends: 7450 [2019-11-16 00:02:00,321 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:00,327 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:00,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:00,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:00,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:00,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5465 transitions. [2019-11-16 00:02:00,442 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5465 transitions. Word has length 178 [2019-11-16 00:02:00,442 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:00,442 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5465 transitions. [2019-11-16 00:02:00,442 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:00,442 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5465 transitions. [2019-11-16 00:02:00,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:00,444 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:00,444 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:00,445 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:00,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:00,445 INFO L82 PathProgramCache]: Analyzing trace with hash -2004833274, now seen corresponding path program 1 times [2019-11-16 00:02:00,445 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:00,445 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298013259] [2019-11-16 00:02:00,446 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:00,446 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:00,446 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:00,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:00,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:00,507 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [298013259] [2019-11-16 00:02:00,507 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:00,510 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:00,510 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [276686578] [2019-11-16 00:02:00,511 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:00,511 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:00,511 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:00,511 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:00,512 INFO L87 Difference]: Start difference. First operand 3739 states and 5465 transitions. Second operand 3 states. [2019-11-16 00:02:00,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:00,646 INFO L93 Difference]: Finished difference Result 7448 states and 10884 transitions. [2019-11-16 00:02:00,646 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:00,647 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:00,648 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:00,654 INFO L225 Difference]: With dead ends: 7448 [2019-11-16 00:02:00,655 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:00,660 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:00,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:00,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:00,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:00,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5457 transitions. [2019-11-16 00:02:00,791 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5457 transitions. Word has length 178 [2019-11-16 00:02:00,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:00,792 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5457 transitions. [2019-11-16 00:02:00,792 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:00,793 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5457 transitions. [2019-11-16 00:02:00,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:00,794 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:00,795 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:00,795 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:00,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:00,795 INFO L82 PathProgramCache]: Analyzing trace with hash -1618970872, now seen corresponding path program 1 times [2019-11-16 00:02:00,796 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:00,796 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743349683] [2019-11-16 00:02:00,796 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:00,796 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:00,796 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:00,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:00,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:00,878 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743349683] [2019-11-16 00:02:00,878 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:00,879 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:00,879 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881274473] [2019-11-16 00:02:00,879 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:00,880 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:00,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:00,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:00,881 INFO L87 Difference]: Start difference. First operand 3739 states and 5457 transitions. Second operand 3 states. [2019-11-16 00:02:01,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:01,064 INFO L93 Difference]: Finished difference Result 7447 states and 10867 transitions. [2019-11-16 00:02:01,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:01,065 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:01,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:01,072 INFO L225 Difference]: With dead ends: 7447 [2019-11-16 00:02:01,073 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:01,079 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:01,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:01,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:01,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:01,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5449 transitions. [2019-11-16 00:02:01,296 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5449 transitions. Word has length 178 [2019-11-16 00:02:01,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:01,296 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5449 transitions. [2019-11-16 00:02:01,297 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:01,297 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5449 transitions. [2019-11-16 00:02:01,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:01,299 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:01,299 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:01,299 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:01,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:01,300 INFO L82 PathProgramCache]: Analyzing trace with hash -497414968, now seen corresponding path program 1 times [2019-11-16 00:02:01,300 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:01,300 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1818864802] [2019-11-16 00:02:01,300 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:01,300 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:01,300 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:01,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:01,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:01,369 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1818864802] [2019-11-16 00:02:01,369 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:01,369 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:01,370 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1057809205] [2019-11-16 00:02:01,370 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:01,370 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:01,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:01,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:01,371 INFO L87 Difference]: Start difference. First operand 3739 states and 5449 transitions. Second operand 3 states. [2019-11-16 00:02:01,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:01,504 INFO L93 Difference]: Finished difference Result 7446 states and 10850 transitions. [2019-11-16 00:02:01,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:01,505 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:01,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:01,512 INFO L225 Difference]: With dead ends: 7446 [2019-11-16 00:02:01,512 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:01,518 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:01,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:01,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:01,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:01,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5441 transitions. [2019-11-16 00:02:01,642 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5441 transitions. Word has length 178 [2019-11-16 00:02:01,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:01,642 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5441 transitions. [2019-11-16 00:02:01,642 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:01,642 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5441 transitions. [2019-11-16 00:02:01,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:01,644 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:01,644 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:01,644 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:01,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:01,645 INFO L82 PathProgramCache]: Analyzing trace with hash 924237576, now seen corresponding path program 1 times [2019-11-16 00:02:01,645 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:01,645 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253951696] [2019-11-16 00:02:01,645 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:01,645 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:01,646 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:01,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:01,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:01,701 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253951696] [2019-11-16 00:02:01,701 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:01,701 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:01,701 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053245601] [2019-11-16 00:02:01,702 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:01,702 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:01,702 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:01,702 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:01,702 INFO L87 Difference]: Start difference. First operand 3739 states and 5441 transitions. Second operand 3 states. [2019-11-16 00:02:01,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:01,842 INFO L93 Difference]: Finished difference Result 7445 states and 10833 transitions. [2019-11-16 00:02:01,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:01,843 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:01,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:01,849 INFO L225 Difference]: With dead ends: 7445 [2019-11-16 00:02:01,849 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:01,856 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:01,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:01,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:01,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:01,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5433 transitions. [2019-11-16 00:02:01,978 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5433 transitions. Word has length 178 [2019-11-16 00:02:01,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:01,978 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5433 transitions. [2019-11-16 00:02:01,978 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:01,978 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5433 transitions. [2019-11-16 00:02:01,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:01,980 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:01,980 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:01,980 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:01,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:01,981 INFO L82 PathProgramCache]: Analyzing trace with hash 1524286664, now seen corresponding path program 1 times [2019-11-16 00:02:01,981 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:01,981 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135135702] [2019-11-16 00:02:01,981 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:01,981 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:01,981 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:01,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:02,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:02,040 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135135702] [2019-11-16 00:02:02,042 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:02,042 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:02,042 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259933020] [2019-11-16 00:02:02,042 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:02,043 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:02,043 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:02,043 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:02,043 INFO L87 Difference]: Start difference. First operand 3739 states and 5433 transitions. Second operand 3 states. [2019-11-16 00:02:02,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:02,237 INFO L93 Difference]: Finished difference Result 7444 states and 10816 transitions. [2019-11-16 00:02:02,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:02,237 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:02,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:02,244 INFO L225 Difference]: With dead ends: 7444 [2019-11-16 00:02:02,244 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:02,250 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:02,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:02,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:02,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:02,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5397 transitions. [2019-11-16 00:02:02,466 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5397 transitions. Word has length 178 [2019-11-16 00:02:02,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:02,466 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5397 transitions. [2019-11-16 00:02:02,467 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:02,467 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5397 transitions. [2019-11-16 00:02:02,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:02,469 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:02,469 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:02,469 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:02,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:02,470 INFO L82 PathProgramCache]: Analyzing trace with hash -811661560, now seen corresponding path program 1 times [2019-11-16 00:02:02,470 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:02,470 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124968270] [2019-11-16 00:02:02,470 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:02,471 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:02,471 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:02,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:02,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:02,529 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [124968270] [2019-11-16 00:02:02,529 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:02,529 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:02,529 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262842217] [2019-11-16 00:02:02,530 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:02,530 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:02,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:02,530 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:02,531 INFO L87 Difference]: Start difference. First operand 3739 states and 5397 transitions. Second operand 3 states. [2019-11-16 00:02:02,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:02,731 INFO L93 Difference]: Finished difference Result 7443 states and 10743 transitions. [2019-11-16 00:02:02,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:02,732 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:02,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:02,739 INFO L225 Difference]: With dead ends: 7443 [2019-11-16 00:02:02,739 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:02,744 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:02,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:02,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:02,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:02,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5361 transitions. [2019-11-16 00:02:02,878 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5361 transitions. Word has length 178 [2019-11-16 00:02:02,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:02,878 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5361 transitions. [2019-11-16 00:02:02,878 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:02,879 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5361 transitions. [2019-11-16 00:02:02,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:02,880 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:02,881 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:02,881 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:02,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:02,881 INFO L82 PathProgramCache]: Analyzing trace with hash -1210080217, now seen corresponding path program 1 times [2019-11-16 00:02:02,882 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:02,882 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052609464] [2019-11-16 00:02:02,882 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:02,882 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:02,882 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:02,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:02,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:02,931 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052609464] [2019-11-16 00:02:02,931 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:02,932 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:02,932 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350645889] [2019-11-16 00:02:02,932 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:02,932 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:02,933 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:02,933 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:02,933 INFO L87 Difference]: Start difference. First operand 3739 states and 5361 transitions. Second operand 3 states. [2019-11-16 00:02:03,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:03,132 INFO L93 Difference]: Finished difference Result 7442 states and 10670 transitions. [2019-11-16 00:02:03,132 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:03,133 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:03,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:03,140 INFO L225 Difference]: With dead ends: 7442 [2019-11-16 00:02:03,140 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:03,150 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:03,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:03,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:03,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:03,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5325 transitions. [2019-11-16 00:02:03,287 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5325 transitions. Word has length 178 [2019-11-16 00:02:03,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:03,288 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5325 transitions. [2019-11-16 00:02:03,288 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:03,288 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5325 transitions. [2019-11-16 00:02:03,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:03,289 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:03,290 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:03,290 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:03,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:03,290 INFO L82 PathProgramCache]: Analyzing trace with hash 85086470, now seen corresponding path program 1 times [2019-11-16 00:02:03,290 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:03,290 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208021727] [2019-11-16 00:02:03,291 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:03,291 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:03,291 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:03,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:03,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:03,349 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1208021727] [2019-11-16 00:02:03,349 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:03,349 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:03,349 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494657173] [2019-11-16 00:02:03,350 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:03,350 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:03,351 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:03,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:03,351 INFO L87 Difference]: Start difference. First operand 3739 states and 5325 transitions. Second operand 3 states. [2019-11-16 00:02:03,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:03,534 INFO L93 Difference]: Finished difference Result 7440 states and 10595 transitions. [2019-11-16 00:02:03,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:03,535 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:03,535 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:03,541 INFO L225 Difference]: With dead ends: 7440 [2019-11-16 00:02:03,541 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:03,546 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:03,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:03,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:03,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:03,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5289 transitions. [2019-11-16 00:02:03,679 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5289 transitions. Word has length 178 [2019-11-16 00:02:03,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:03,680 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5289 transitions. [2019-11-16 00:02:03,680 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:03,680 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5289 transitions. [2019-11-16 00:02:03,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:03,681 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:03,682 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:03,682 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:03,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:03,682 INFO L82 PathProgramCache]: Analyzing trace with hash -1073950937, now seen corresponding path program 1 times [2019-11-16 00:02:03,682 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:03,682 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967189789] [2019-11-16 00:02:03,683 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:03,683 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:03,683 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:03,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:03,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:03,760 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967189789] [2019-11-16 00:02:03,760 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:03,760 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:03,760 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [157766283] [2019-11-16 00:02:03,761 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:03,761 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:03,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:03,762 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:03,762 INFO L87 Difference]: Start difference. First operand 3739 states and 5289 transitions. Second operand 3 states. [2019-11-16 00:02:04,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:04,017 INFO L93 Difference]: Finished difference Result 7439 states and 10522 transitions. [2019-11-16 00:02:04,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:04,018 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:04,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:04,031 INFO L225 Difference]: With dead ends: 7439 [2019-11-16 00:02:04,031 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:04,036 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:04,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:04,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:04,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:04,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5253 transitions. [2019-11-16 00:02:04,224 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5253 transitions. Word has length 178 [2019-11-16 00:02:04,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:04,224 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5253 transitions. [2019-11-16 00:02:04,225 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:04,225 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5253 transitions. [2019-11-16 00:02:04,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:04,227 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:04,227 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:04,228 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:04,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:04,228 INFO L82 PathProgramCache]: Analyzing trace with hash -240638745, now seen corresponding path program 1 times [2019-11-16 00:02:04,229 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:04,229 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153552878] [2019-11-16 00:02:04,229 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:04,229 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:04,230 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:04,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:04,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:04,301 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [153552878] [2019-11-16 00:02:04,301 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:04,302 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:04,302 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193250683] [2019-11-16 00:02:04,303 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:04,303 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:04,303 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:04,303 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:04,303 INFO L87 Difference]: Start difference. First operand 3739 states and 5253 transitions. Second operand 3 states. [2019-11-16 00:02:04,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:04,583 INFO L93 Difference]: Finished difference Result 7438 states and 10449 transitions. [2019-11-16 00:02:04,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:04,584 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:04,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:04,591 INFO L225 Difference]: With dead ends: 7438 [2019-11-16 00:02:04,591 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:04,595 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:04,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:04,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:04,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:04,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5217 transitions. [2019-11-16 00:02:04,730 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5217 transitions. Word has length 178 [2019-11-16 00:02:04,730 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:04,730 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5217 transitions. [2019-11-16 00:02:04,731 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:04,731 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5217 transitions. [2019-11-16 00:02:04,731 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:04,732 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:04,732 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:04,732 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:04,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:04,732 INFO L82 PathProgramCache]: Analyzing trace with hash -1643962682, now seen corresponding path program 1 times [2019-11-16 00:02:04,733 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:04,733 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084685614] [2019-11-16 00:02:04,733 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:04,733 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:04,733 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:04,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:04,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:04,782 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2084685614] [2019-11-16 00:02:04,782 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:04,782 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:04,782 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605483880] [2019-11-16 00:02:04,783 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:04,783 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:04,783 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:04,783 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:04,783 INFO L87 Difference]: Start difference. First operand 3739 states and 5217 transitions. Second operand 3 states. [2019-11-16 00:02:04,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:04,994 INFO L93 Difference]: Finished difference Result 7437 states and 10376 transitions. [2019-11-16 00:02:04,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:04,995 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:04,995 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:05,002 INFO L225 Difference]: With dead ends: 7437 [2019-11-16 00:02:05,002 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:05,006 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:05,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:05,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:05,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:05,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5181 transitions. [2019-11-16 00:02:05,144 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5181 transitions. Word has length 178 [2019-11-16 00:02:05,144 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:05,144 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5181 transitions. [2019-11-16 00:02:05,144 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:05,144 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5181 transitions. [2019-11-16 00:02:05,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:05,145 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:05,146 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:05,146 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:05,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:05,146 INFO L82 PathProgramCache]: Analyzing trace with hash -1173822330, now seen corresponding path program 1 times [2019-11-16 00:02:05,146 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:05,146 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937403142] [2019-11-16 00:02:05,147 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:05,147 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:05,147 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:05,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:05,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:05,195 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937403142] [2019-11-16 00:02:05,195 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:05,195 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:05,195 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645390691] [2019-11-16 00:02:05,196 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:05,196 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:05,196 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:05,196 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:05,196 INFO L87 Difference]: Start difference. First operand 3739 states and 5181 transitions. Second operand 3 states. [2019-11-16 00:02:05,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:05,407 INFO L93 Difference]: Finished difference Result 7436 states and 10303 transitions. [2019-11-16 00:02:05,407 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:05,407 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:05,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:05,414 INFO L225 Difference]: With dead ends: 7436 [2019-11-16 00:02:05,414 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:05,419 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:05,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:05,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:05,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:05,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5145 transitions. [2019-11-16 00:02:05,571 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5145 transitions. Word has length 178 [2019-11-16 00:02:05,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:05,571 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5145 transitions. [2019-11-16 00:02:05,571 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:05,571 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5145 transitions. [2019-11-16 00:02:05,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:05,572 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:05,572 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:05,573 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:05,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:05,573 INFO L82 PathProgramCache]: Analyzing trace with hash 1275765989, now seen corresponding path program 1 times [2019-11-16 00:02:05,573 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:05,573 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399875782] [2019-11-16 00:02:05,573 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:05,574 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:05,574 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:05,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:05,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:05,628 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399875782] [2019-11-16 00:02:05,628 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:05,628 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:05,628 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6031886] [2019-11-16 00:02:05,628 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:05,629 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:05,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:05,630 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:05,630 INFO L87 Difference]: Start difference. First operand 3739 states and 5145 transitions. Second operand 3 states. [2019-11-16 00:02:05,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:05,826 INFO L93 Difference]: Finished difference Result 7435 states and 10230 transitions. [2019-11-16 00:02:05,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:05,827 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:05,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:05,832 INFO L225 Difference]: With dead ends: 7435 [2019-11-16 00:02:05,832 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:05,838 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:05,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:05,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:05,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:05,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5109 transitions. [2019-11-16 00:02:05,985 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5109 transitions. Word has length 178 [2019-11-16 00:02:05,985 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:05,986 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5109 transitions. [2019-11-16 00:02:05,986 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:05,986 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5109 transitions. [2019-11-16 00:02:05,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:05,987 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:05,987 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:05,987 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:05,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:05,988 INFO L82 PathProgramCache]: Analyzing trace with hash 105306789, now seen corresponding path program 1 times [2019-11-16 00:02:05,988 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:05,988 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [823508963] [2019-11-16 00:02:05,988 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:05,989 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:05,989 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:05,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:06,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:06,040 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [823508963] [2019-11-16 00:02:06,041 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:06,041 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:06,041 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302289460] [2019-11-16 00:02:06,042 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:06,042 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:06,042 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:06,042 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:06,042 INFO L87 Difference]: Start difference. First operand 3739 states and 5109 transitions. Second operand 3 states. [2019-11-16 00:02:06,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:06,279 INFO L93 Difference]: Finished difference Result 7434 states and 10157 transitions. [2019-11-16 00:02:06,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:06,280 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:06,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:06,286 INFO L225 Difference]: With dead ends: 7434 [2019-11-16 00:02:06,286 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:06,291 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:06,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:06,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:06,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:06,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5073 transitions. [2019-11-16 00:02:06,447 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5073 transitions. Word has length 178 [2019-11-16 00:02:06,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:06,448 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5073 transitions. [2019-11-16 00:02:06,448 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:06,448 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5073 transitions. [2019-11-16 00:02:06,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:06,449 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:06,449 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:06,450 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:06,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:06,450 INFO L82 PathProgramCache]: Analyzing trace with hash 1188110724, now seen corresponding path program 1 times [2019-11-16 00:02:06,450 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:06,450 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228050763] [2019-11-16 00:02:06,451 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:06,451 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:06,451 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:06,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:06,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:06,510 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228050763] [2019-11-16 00:02:06,510 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:06,510 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:06,511 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720256747] [2019-11-16 00:02:06,512 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:06,512 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:06,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:06,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:06,514 INFO L87 Difference]: Start difference. First operand 3739 states and 5073 transitions. Second operand 3 states. [2019-11-16 00:02:06,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:06,726 INFO L93 Difference]: Finished difference Result 7432 states and 10082 transitions. [2019-11-16 00:02:06,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:06,727 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:06,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:06,732 INFO L225 Difference]: With dead ends: 7432 [2019-11-16 00:02:06,732 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:06,738 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:06,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:06,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:06,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:06,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5037 transitions. [2019-11-16 00:02:06,899 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5037 transitions. Word has length 178 [2019-11-16 00:02:06,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:06,900 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5037 transitions. [2019-11-16 00:02:06,900 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:06,900 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5037 transitions. [2019-11-16 00:02:06,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:06,901 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:06,901 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:06,902 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:06,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:06,903 INFO L82 PathProgramCache]: Analyzing trace with hash 1551577222, now seen corresponding path program 1 times [2019-11-16 00:02:06,903 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:06,903 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841441273] [2019-11-16 00:02:06,903 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:06,904 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:06,904 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:06,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:06,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:06,957 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841441273] [2019-11-16 00:02:06,958 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:06,958 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:06,958 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984183372] [2019-11-16 00:02:06,958 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:06,959 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:06,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:06,959 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:06,959 INFO L87 Difference]: Start difference. First operand 3739 states and 5037 transitions. Second operand 3 states. [2019-11-16 00:02:07,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:07,172 INFO L93 Difference]: Finished difference Result 7431 states and 10009 transitions. [2019-11-16 00:02:07,172 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:07,172 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:07,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:07,176 INFO L225 Difference]: With dead ends: 7431 [2019-11-16 00:02:07,176 INFO L226 Difference]: Without dead ends: 3739 [2019-11-16 00:02:07,181 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:07,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-11-16 00:02:07,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-11-16 00:02:07,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-11-16 00:02:07,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 4999 transitions. [2019-11-16 00:02:07,352 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 4999 transitions. Word has length 178 [2019-11-16 00:02:07,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:07,353 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 4999 transitions. [2019-11-16 00:02:07,353 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:07,353 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 4999 transitions. [2019-11-16 00:02:07,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:07,354 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:07,354 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:07,355 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:07,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:07,355 INFO L82 PathProgramCache]: Analyzing trace with hash -54414171, now seen corresponding path program 1 times [2019-11-16 00:02:07,355 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:07,356 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861329063] [2019-11-16 00:02:07,356 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:07,356 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:07,356 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:07,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:07,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:07,440 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1861329063] [2019-11-16 00:02:07,440 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:07,440 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:07,440 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137136797] [2019-11-16 00:02:07,441 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:07,441 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:07,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:07,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:07,442 INFO L87 Difference]: Start difference. First operand 3739 states and 4999 transitions. Second operand 3 states. [2019-11-16 00:02:07,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:07,818 INFO L93 Difference]: Finished difference Result 10663 states and 14252 transitions. [2019-11-16 00:02:07,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:07,819 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:07,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:07,825 INFO L225 Difference]: With dead ends: 10663 [2019-11-16 00:02:07,825 INFO L226 Difference]: Without dead ends: 7057 [2019-11-16 00:02:07,831 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:07,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7057 states. [2019-11-16 00:02:08,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7057 to 7051. [2019-11-16 00:02:08,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-11-16 00:02:08,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9394 transitions. [2019-11-16 00:02:08,257 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9394 transitions. Word has length 178 [2019-11-16 00:02:08,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:08,258 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9394 transitions. [2019-11-16 00:02:08,258 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:08,258 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9394 transitions. [2019-11-16 00:02:08,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:08,259 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:08,260 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:08,260 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:08,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:08,261 INFO L82 PathProgramCache]: Analyzing trace with hash -1196061564, now seen corresponding path program 1 times [2019-11-16 00:02:08,261 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:08,261 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726502617] [2019-11-16 00:02:08,261 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:08,261 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:08,262 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:08,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:08,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:08,407 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [726502617] [2019-11-16 00:02:08,407 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:08,407 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:08,407 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481866213] [2019-11-16 00:02:08,408 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:08,408 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:08,408 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:08,408 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:08,409 INFO L87 Difference]: Start difference. First operand 7051 states and 9394 transitions. Second operand 3 states. [2019-11-16 00:02:08,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:08,742 INFO L93 Difference]: Finished difference Result 14081 states and 18753 transitions. [2019-11-16 00:02:08,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:08,743 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:08,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:08,750 INFO L225 Difference]: With dead ends: 14081 [2019-11-16 00:02:08,750 INFO L226 Difference]: Without dead ends: 7051 [2019-11-16 00:02:08,758 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:08,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7051 states. [2019-11-16 00:02:09,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7051 to 7051. [2019-11-16 00:02:09,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-11-16 00:02:09,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9380 transitions. [2019-11-16 00:02:09,081 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9380 transitions. Word has length 178 [2019-11-16 00:02:09,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:09,082 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9380 transitions. [2019-11-16 00:02:09,082 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:09,082 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9380 transitions. [2019-11-16 00:02:09,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:09,083 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:09,084 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:09,084 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:09,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:09,084 INFO L82 PathProgramCache]: Analyzing trace with hash 1253538566, now seen corresponding path program 1 times [2019-11-16 00:02:09,085 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:09,085 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952216723] [2019-11-16 00:02:09,085 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:09,085 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:09,085 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:09,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:09,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:09,172 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952216723] [2019-11-16 00:02:09,172 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:09,172 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:09,173 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141278229] [2019-11-16 00:02:09,173 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:09,173 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:09,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:09,174 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:09,174 INFO L87 Difference]: Start difference. First operand 7051 states and 9380 transitions. Second operand 3 states. [2019-11-16 00:02:09,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:09,419 INFO L93 Difference]: Finished difference Result 14073 states and 18717 transitions. [2019-11-16 00:02:09,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:09,419 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:09,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:09,425 INFO L225 Difference]: With dead ends: 14073 [2019-11-16 00:02:09,425 INFO L226 Difference]: Without dead ends: 7051 [2019-11-16 00:02:09,432 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:09,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7051 states. [2019-11-16 00:02:09,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7051 to 7051. [2019-11-16 00:02:09,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-11-16 00:02:09,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9366 transitions. [2019-11-16 00:02:09,656 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9366 transitions. Word has length 178 [2019-11-16 00:02:09,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:09,657 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9366 transitions. [2019-11-16 00:02:09,657 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:09,657 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9366 transitions. [2019-11-16 00:02:09,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:09,657 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:09,658 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:09,658 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:09,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:09,658 INFO L82 PathProgramCache]: Analyzing trace with hash 1955138440, now seen corresponding path program 1 times [2019-11-16 00:02:09,658 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:09,658 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1626281208] [2019-11-16 00:02:09,658 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:09,659 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:09,659 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:09,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:09,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:09,737 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1626281208] [2019-11-16 00:02:09,737 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:09,737 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:09,737 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229924794] [2019-11-16 00:02:09,738 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:09,738 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:09,738 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:09,738 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:09,738 INFO L87 Difference]: Start difference. First operand 7051 states and 9366 transitions. Second operand 3 states. [2019-11-16 00:02:10,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:10,169 INFO L93 Difference]: Finished difference Result 14065 states and 18681 transitions. [2019-11-16 00:02:10,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:10,170 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:10,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:10,177 INFO L225 Difference]: With dead ends: 14065 [2019-11-16 00:02:10,177 INFO L226 Difference]: Without dead ends: 7051 [2019-11-16 00:02:10,183 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:10,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7051 states. [2019-11-16 00:02:10,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7051 to 7051. [2019-11-16 00:02:10,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-11-16 00:02:10,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9299 transitions. [2019-11-16 00:02:10,423 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9299 transitions. Word has length 178 [2019-11-16 00:02:10,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:10,423 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9299 transitions. [2019-11-16 00:02:10,423 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:10,423 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9299 transitions. [2019-11-16 00:02:10,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:10,424 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:10,424 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:10,425 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:10,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:10,425 INFO L82 PathProgramCache]: Analyzing trace with hash 149700106, now seen corresponding path program 1 times [2019-11-16 00:02:10,425 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:10,425 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121541811] [2019-11-16 00:02:10,425 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:10,425 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:10,426 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:10,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:10,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:10,530 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1121541811] [2019-11-16 00:02:10,530 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:10,530 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-16 00:02:10,530 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107216840] [2019-11-16 00:02:10,531 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:10,531 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:10,532 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:10,532 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:10,532 INFO L87 Difference]: Start difference. First operand 7051 states and 9299 transitions. Second operand 3 states. [2019-11-16 00:02:10,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:10,893 INFO L93 Difference]: Finished difference Result 14057 states and 18539 transitions. [2019-11-16 00:02:10,893 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:10,894 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:10,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:10,899 INFO L225 Difference]: With dead ends: 14057 [2019-11-16 00:02:10,899 INFO L226 Difference]: Without dead ends: 7051 [2019-11-16 00:02:10,904 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:10,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7051 states. [2019-11-16 00:02:11,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7051 to 7051. [2019-11-16 00:02:11,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-11-16 00:02:11,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9258 transitions. [2019-11-16 00:02:11,127 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9258 transitions. Word has length 178 [2019-11-16 00:02:11,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:11,128 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9258 transitions. [2019-11-16 00:02:11,128 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:11,128 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9258 transitions. [2019-11-16 00:02:11,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-16 00:02:11,129 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:11,129 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:11,129 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:11,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:11,129 INFO L82 PathProgramCache]: Analyzing trace with hash -1130163572, now seen corresponding path program 1 times [2019-11-16 00:02:11,129 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:11,129 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662568309] [2019-11-16 00:02:11,130 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:11,130 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:11,130 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:11,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:11,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:11,201 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [662568309] [2019-11-16 00:02:11,202 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:11,202 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-16 00:02:11,202 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906159728] [2019-11-16 00:02:11,202 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-16 00:02:11,203 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:11,203 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-16 00:02:11,203 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:11,203 INFO L87 Difference]: Start difference. First operand 7051 states and 9258 transitions. Second operand 3 states. [2019-11-16 00:02:11,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:11,791 INFO L93 Difference]: Finished difference Result 20757 states and 27145 transitions. [2019-11-16 00:02:11,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-16 00:02:11,792 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-16 00:02:11,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:11,803 INFO L225 Difference]: With dead ends: 20757 [2019-11-16 00:02:11,804 INFO L226 Difference]: Without dead ends: 13886 [2019-11-16 00:02:11,813 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-16 00:02:11,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13886 states. [2019-11-16 00:02:12,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13886 to 13482. [2019-11-16 00:02:12,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13482 states. [2019-11-16 00:02:12,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13482 states to 13482 states and 17576 transitions. [2019-11-16 00:02:12,478 INFO L78 Accepts]: Start accepts. Automaton has 13482 states and 17576 transitions. Word has length 178 [2019-11-16 00:02:12,478 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:12,478 INFO L462 AbstractCegarLoop]: Abstraction has 13482 states and 17576 transitions. [2019-11-16 00:02:12,479 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-16 00:02:12,479 INFO L276 IsEmpty]: Start isEmpty. Operand 13482 states and 17576 transitions. [2019-11-16 00:02:12,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:12,480 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:12,481 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:12,481 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:12,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:12,481 INFO L82 PathProgramCache]: Analyzing trace with hash -1040694295, now seen corresponding path program 1 times [2019-11-16 00:02:12,482 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:12,482 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494724265] [2019-11-16 00:02:12,482 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:12,482 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:12,482 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:12,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:12,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:12,572 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [494724265] [2019-11-16 00:02:12,572 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:12,572 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:12,573 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [270051710] [2019-11-16 00:02:12,573 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:12,573 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:12,574 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:12,574 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:12,574 INFO L87 Difference]: Start difference. First operand 13482 states and 17576 transitions. Second operand 5 states. [2019-11-16 00:02:14,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:14,370 INFO L93 Difference]: Finished difference Result 38554 states and 50369 transitions. [2019-11-16 00:02:14,370 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:14,370 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:14,370 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:14,391 INFO L225 Difference]: With dead ends: 38554 [2019-11-16 00:02:14,391 INFO L226 Difference]: Without dead ends: 25302 [2019-11-16 00:02:14,402 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:14,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25302 states. [2019-11-16 00:02:15,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25302 to 13650. [2019-11-16 00:02:15,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13650 states. [2019-11-16 00:02:15,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13650 states to 13650 states and 17690 transitions. [2019-11-16 00:02:15,261 INFO L78 Accepts]: Start accepts. Automaton has 13650 states and 17690 transitions. Word has length 179 [2019-11-16 00:02:15,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:15,261 INFO L462 AbstractCegarLoop]: Abstraction has 13650 states and 17690 transitions. [2019-11-16 00:02:15,261 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:15,261 INFO L276 IsEmpty]: Start isEmpty. Operand 13650 states and 17690 transitions. [2019-11-16 00:02:15,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:15,262 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:15,263 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:15,263 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:15,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:15,263 INFO L82 PathProgramCache]: Analyzing trace with hash -1475199893, now seen corresponding path program 1 times [2019-11-16 00:02:15,263 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:15,264 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509888494] [2019-11-16 00:02:15,264 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:15,264 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:15,264 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:15,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:15,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:15,339 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [509888494] [2019-11-16 00:02:15,339 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:15,340 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:15,340 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224553356] [2019-11-16 00:02:15,340 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:15,340 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:15,341 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:15,341 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:15,341 INFO L87 Difference]: Start difference. First operand 13650 states and 17690 transitions. Second operand 5 states. [2019-11-16 00:02:16,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:16,480 INFO L93 Difference]: Finished difference Result 31118 states and 40645 transitions. [2019-11-16 00:02:16,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:16,481 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:16,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:16,494 INFO L225 Difference]: With dead ends: 31118 [2019-11-16 00:02:16,494 INFO L226 Difference]: Without dead ends: 17586 [2019-11-16 00:02:16,503 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:16,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17586 states. [2019-11-16 00:02:17,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17586 to 13662. [2019-11-16 00:02:17,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13662 states. [2019-11-16 00:02:17,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13662 states to 13662 states and 17596 transitions. [2019-11-16 00:02:17,161 INFO L78 Accepts]: Start accepts. Automaton has 13662 states and 17596 transitions. Word has length 179 [2019-11-16 00:02:17,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:17,161 INFO L462 AbstractCegarLoop]: Abstraction has 13662 states and 17596 transitions. [2019-11-16 00:02:17,161 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:17,161 INFO L276 IsEmpty]: Start isEmpty. Operand 13662 states and 17596 transitions. [2019-11-16 00:02:17,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:17,163 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:17,163 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:17,163 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:17,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:17,163 INFO L82 PathProgramCache]: Analyzing trace with hash -987152787, now seen corresponding path program 1 times [2019-11-16 00:02:17,164 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:17,164 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720455298] [2019-11-16 00:02:17,164 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:17,164 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:17,164 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:17,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:17,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:17,262 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720455298] [2019-11-16 00:02:17,262 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:17,262 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:17,262 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2018761652] [2019-11-16 00:02:17,263 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:17,263 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:17,263 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:17,263 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:17,263 INFO L87 Difference]: Start difference. First operand 13662 states and 17596 transitions. Second operand 5 states. [2019-11-16 00:02:19,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:19,035 INFO L93 Difference]: Finished difference Result 32500 states and 42101 transitions. [2019-11-16 00:02:19,035 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:19,035 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:19,036 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:19,049 INFO L225 Difference]: With dead ends: 32500 [2019-11-16 00:02:19,049 INFO L226 Difference]: Without dead ends: 18970 [2019-11-16 00:02:19,060 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:19,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18970 states. [2019-11-16 00:02:19,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18970 to 13686. [2019-11-16 00:02:19,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13686 states. [2019-11-16 00:02:19,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13686 states to 13686 states and 17518 transitions. [2019-11-16 00:02:19,829 INFO L78 Accepts]: Start accepts. Automaton has 13686 states and 17518 transitions. Word has length 179 [2019-11-16 00:02:19,829 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:19,829 INFO L462 AbstractCegarLoop]: Abstraction has 13686 states and 17518 transitions. [2019-11-16 00:02:19,829 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:19,829 INFO L276 IsEmpty]: Start isEmpty. Operand 13686 states and 17518 transitions. [2019-11-16 00:02:19,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:19,831 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:19,831 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:19,832 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:19,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:19,832 INFO L82 PathProgramCache]: Analyzing trace with hash 941779439, now seen corresponding path program 1 times [2019-11-16 00:02:19,832 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:19,833 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742324664] [2019-11-16 00:02:19,833 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:19,833 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:19,833 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:19,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:19,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:19,916 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742324664] [2019-11-16 00:02:19,917 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:19,917 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:19,917 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576033827] [2019-11-16 00:02:19,917 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:19,918 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:19,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:19,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:19,918 INFO L87 Difference]: Start difference. First operand 13686 states and 17518 transitions. Second operand 5 states. [2019-11-16 00:02:21,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:21,525 INFO L93 Difference]: Finished difference Result 33174 states and 42657 transitions. [2019-11-16 00:02:21,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:21,526 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:21,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:21,540 INFO L225 Difference]: With dead ends: 33174 [2019-11-16 00:02:21,540 INFO L226 Difference]: Without dead ends: 19634 [2019-11-16 00:02:21,547 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:21,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19634 states. [2019-11-16 00:02:22,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19634 to 13710. [2019-11-16 00:02:22,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13710 states. [2019-11-16 00:02:22,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13710 states to 13710 states and 17440 transitions. [2019-11-16 00:02:22,383 INFO L78 Accepts]: Start accepts. Automaton has 13710 states and 17440 transitions. Word has length 179 [2019-11-16 00:02:22,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:22,383 INFO L462 AbstractCegarLoop]: Abstraction has 13710 states and 17440 transitions. [2019-11-16 00:02:22,383 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:22,383 INFO L276 IsEmpty]: Start isEmpty. Operand 13710 states and 17440 transitions. [2019-11-16 00:02:22,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:22,384 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:22,384 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:22,384 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:22,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:22,385 INFO L82 PathProgramCache]: Analyzing trace with hash -96805135, now seen corresponding path program 1 times [2019-11-16 00:02:22,385 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:22,385 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1754021154] [2019-11-16 00:02:22,385 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:22,385 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:22,385 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:22,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:22,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:22,479 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1754021154] [2019-11-16 00:02:22,479 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:22,479 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:22,480 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280462624] [2019-11-16 00:02:22,480 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:22,480 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:22,480 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:22,481 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:22,481 INFO L87 Difference]: Start difference. First operand 13710 states and 17440 transitions. Second operand 5 states. [2019-11-16 00:02:24,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:24,138 INFO L93 Difference]: Finished difference Result 34450 states and 43995 transitions. [2019-11-16 00:02:24,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:24,138 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:24,139 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:24,156 INFO L225 Difference]: With dead ends: 34450 [2019-11-16 00:02:24,157 INFO L226 Difference]: Without dead ends: 20914 [2019-11-16 00:02:24,168 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:24,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20914 states. [2019-11-16 00:02:25,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20914 to 13734. [2019-11-16 00:02:25,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13734 states. [2019-11-16 00:02:25,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13734 states to 13734 states and 17362 transitions. [2019-11-16 00:02:25,424 INFO L78 Accepts]: Start accepts. Automaton has 13734 states and 17362 transitions. Word has length 179 [2019-11-16 00:02:25,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:25,424 INFO L462 AbstractCegarLoop]: Abstraction has 13734 states and 17362 transitions. [2019-11-16 00:02:25,424 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:25,424 INFO L276 IsEmpty]: Start isEmpty. Operand 13734 states and 17362 transitions. [2019-11-16 00:02:25,426 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:25,426 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:25,426 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:25,426 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:25,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:25,426 INFO L82 PathProgramCache]: Analyzing trace with hash 1504265971, now seen corresponding path program 1 times [2019-11-16 00:02:25,426 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:25,426 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409767036] [2019-11-16 00:02:25,427 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:25,427 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:25,427 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:25,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:25,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:25,508 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409767036] [2019-11-16 00:02:25,508 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:25,508 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:25,508 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [962202809] [2019-11-16 00:02:25,509 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:25,509 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:25,509 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:25,509 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:25,509 INFO L87 Difference]: Start difference. First operand 13734 states and 17362 transitions. Second operand 5 states. [2019-11-16 00:02:27,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:27,282 INFO L93 Difference]: Finished difference Result 35124 states and 44551 transitions. [2019-11-16 00:02:27,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:27,283 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:27,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:27,299 INFO L225 Difference]: With dead ends: 35124 [2019-11-16 00:02:27,300 INFO L226 Difference]: Without dead ends: 21578 [2019-11-16 00:02:27,310 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:27,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21578 states. [2019-11-16 00:02:28,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21578 to 13758. [2019-11-16 00:02:28,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13758 states. [2019-11-16 00:02:28,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13758 states to 13758 states and 17284 transitions. [2019-11-16 00:02:28,478 INFO L78 Accepts]: Start accepts. Automaton has 13758 states and 17284 transitions. Word has length 179 [2019-11-16 00:02:28,478 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:28,478 INFO L462 AbstractCegarLoop]: Abstraction has 13758 states and 17284 transitions. [2019-11-16 00:02:28,478 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:28,478 INFO L276 IsEmpty]: Start isEmpty. Operand 13758 states and 17284 transitions. [2019-11-16 00:02:28,479 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:28,479 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:28,479 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:28,479 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:28,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:28,480 INFO L82 PathProgramCache]: Analyzing trace with hash -436316043, now seen corresponding path program 1 times [2019-11-16 00:02:28,480 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:28,480 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055192898] [2019-11-16 00:02:28,480 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:28,480 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:28,480 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:28,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:28,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:28,563 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055192898] [2019-11-16 00:02:28,563 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:28,563 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:28,564 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [903937792] [2019-11-16 00:02:28,564 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:28,564 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:28,564 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:28,565 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:28,565 INFO L87 Difference]: Start difference. First operand 13758 states and 17284 transitions. Second operand 5 states. [2019-11-16 00:02:30,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:30,433 INFO L93 Difference]: Finished difference Result 35798 states and 45107 transitions. [2019-11-16 00:02:30,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:30,433 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:30,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:30,450 INFO L225 Difference]: With dead ends: 35798 [2019-11-16 00:02:30,450 INFO L226 Difference]: Without dead ends: 22242 [2019-11-16 00:02:30,460 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:30,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22242 states. [2019-11-16 00:02:31,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22242 to 13782. [2019-11-16 00:02:31,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13782 states. [2019-11-16 00:02:31,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13782 states to 13782 states and 17206 transitions. [2019-11-16 00:02:31,588 INFO L78 Accepts]: Start accepts. Automaton has 13782 states and 17206 transitions. Word has length 179 [2019-11-16 00:02:31,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:31,588 INFO L462 AbstractCegarLoop]: Abstraction has 13782 states and 17206 transitions. [2019-11-16 00:02:31,589 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:31,589 INFO L276 IsEmpty]: Start isEmpty. Operand 13782 states and 17206 transitions. [2019-11-16 00:02:31,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:31,590 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:31,590 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:31,590 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:31,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:31,590 INFO L82 PathProgramCache]: Analyzing trace with hash 1440166775, now seen corresponding path program 1 times [2019-11-16 00:02:31,590 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:31,590 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936341749] [2019-11-16 00:02:31,591 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:31,591 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:31,591 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:31,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:31,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:31,674 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936341749] [2019-11-16 00:02:31,674 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:31,674 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:31,674 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [643915561] [2019-11-16 00:02:31,675 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:31,675 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:31,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:31,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:31,676 INFO L87 Difference]: Start difference. First operand 13782 states and 17206 transitions. Second operand 5 states. [2019-11-16 00:02:34,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:34,255 INFO L93 Difference]: Finished difference Result 36472 states and 45663 transitions. [2019-11-16 00:02:34,256 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:34,256 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:34,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:34,272 INFO L225 Difference]: With dead ends: 36472 [2019-11-16 00:02:34,272 INFO L226 Difference]: Without dead ends: 22906 [2019-11-16 00:02:34,281 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:34,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22906 states. [2019-11-16 00:02:35,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22906 to 13806. [2019-11-16 00:02:35,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13806 states. [2019-11-16 00:02:35,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13806 states to 13806 states and 17128 transitions. [2019-11-16 00:02:35,485 INFO L78 Accepts]: Start accepts. Automaton has 13806 states and 17128 transitions. Word has length 179 [2019-11-16 00:02:35,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:35,486 INFO L462 AbstractCegarLoop]: Abstraction has 13806 states and 17128 transitions. [2019-11-16 00:02:35,486 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:35,486 INFO L276 IsEmpty]: Start isEmpty. Operand 13806 states and 17128 transitions. [2019-11-16 00:02:35,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:35,487 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:35,487 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:35,487 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:35,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:35,487 INFO L82 PathProgramCache]: Analyzing trace with hash 1680406521, now seen corresponding path program 1 times [2019-11-16 00:02:35,488 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:35,488 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599051550] [2019-11-16 00:02:35,488 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:35,488 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:35,488 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:35,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:35,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:35,574 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599051550] [2019-11-16 00:02:35,574 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:35,575 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:35,575 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1126601201] [2019-11-16 00:02:35,575 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:35,575 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:35,576 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:35,576 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:35,576 INFO L87 Difference]: Start difference. First operand 13806 states and 17128 transitions. Second operand 5 states. [2019-11-16 00:02:37,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:37,962 INFO L93 Difference]: Finished difference Result 37146 states and 46219 transitions. [2019-11-16 00:02:37,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:37,962 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:37,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:37,978 INFO L225 Difference]: With dead ends: 37146 [2019-11-16 00:02:37,978 INFO L226 Difference]: Without dead ends: 23570 [2019-11-16 00:02:37,987 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:38,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23570 states. [2019-11-16 00:02:39,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23570 to 13830. [2019-11-16 00:02:39,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13830 states. [2019-11-16 00:02:39,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13830 states to 13830 states and 17050 transitions. [2019-11-16 00:02:39,283 INFO L78 Accepts]: Start accepts. Automaton has 13830 states and 17050 transitions. Word has length 179 [2019-11-16 00:02:39,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:39,284 INFO L462 AbstractCegarLoop]: Abstraction has 13830 states and 17050 transitions. [2019-11-16 00:02:39,284 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:39,284 INFO L276 IsEmpty]: Start isEmpty. Operand 13830 states and 17050 transitions. [2019-11-16 00:02:39,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:39,285 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:39,285 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:39,285 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:39,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:39,285 INFO L82 PathProgramCache]: Analyzing trace with hash -230636037, now seen corresponding path program 1 times [2019-11-16 00:02:39,285 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:39,286 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845879627] [2019-11-16 00:02:39,286 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:39,286 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:39,286 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:39,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:39,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:39,365 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1845879627] [2019-11-16 00:02:39,365 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:39,365 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:39,366 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [559254361] [2019-11-16 00:02:39,366 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:39,367 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:39,367 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:39,367 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:39,367 INFO L87 Difference]: Start difference. First operand 13830 states and 17050 transitions. Second operand 5 states. [2019-11-16 00:02:41,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:41,917 INFO L93 Difference]: Finished difference Result 37820 states and 46775 transitions. [2019-11-16 00:02:41,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:41,918 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:41,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:41,934 INFO L225 Difference]: With dead ends: 37820 [2019-11-16 00:02:41,934 INFO L226 Difference]: Without dead ends: 24234 [2019-11-16 00:02:41,941 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:41,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24234 states. [2019-11-16 00:02:43,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24234 to 13854. [2019-11-16 00:02:43,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13854 states. [2019-11-16 00:02:43,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13854 states to 13854 states and 16972 transitions. [2019-11-16 00:02:43,337 INFO L78 Accepts]: Start accepts. Automaton has 13854 states and 16972 transitions. Word has length 179 [2019-11-16 00:02:43,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:43,337 INFO L462 AbstractCegarLoop]: Abstraction has 13854 states and 16972 transitions. [2019-11-16 00:02:43,337 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:43,338 INFO L276 IsEmpty]: Start isEmpty. Operand 13854 states and 16972 transitions. [2019-11-16 00:02:43,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:43,339 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:43,339 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:43,339 INFO L410 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:43,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:43,340 INFO L82 PathProgramCache]: Analyzing trace with hash -1446789763, now seen corresponding path program 1 times [2019-11-16 00:02:43,340 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:43,340 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699325234] [2019-11-16 00:02:43,340 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:43,340 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:43,340 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:43,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:43,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:43,421 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699325234] [2019-11-16 00:02:43,421 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:43,421 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:43,421 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630155666] [2019-11-16 00:02:43,422 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:43,422 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:43,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:43,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:43,422 INFO L87 Difference]: Start difference. First operand 13854 states and 16972 transitions. Second operand 5 states. [2019-11-16 00:02:46,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:46,257 INFO L93 Difference]: Finished difference Result 38494 states and 47331 transitions. [2019-11-16 00:02:46,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:46,257 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:46,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:46,275 INFO L225 Difference]: With dead ends: 38494 [2019-11-16 00:02:46,275 INFO L226 Difference]: Without dead ends: 24898 [2019-11-16 00:02:46,282 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:46,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24898 states. [2019-11-16 00:02:47,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24898 to 13878. [2019-11-16 00:02:47,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13878 states. [2019-11-16 00:02:47,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13878 states to 13878 states and 16894 transitions. [2019-11-16 00:02:47,789 INFO L78 Accepts]: Start accepts. Automaton has 13878 states and 16894 transitions. Word has length 179 [2019-11-16 00:02:47,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:47,789 INFO L462 AbstractCegarLoop]: Abstraction has 13878 states and 16894 transitions. [2019-11-16 00:02:47,789 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:47,789 INFO L276 IsEmpty]: Start isEmpty. Operand 13878 states and 16894 transitions. [2019-11-16 00:02:47,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:47,791 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:47,791 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:47,791 INFO L410 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:47,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:47,791 INFO L82 PathProgramCache]: Analyzing trace with hash 514784895, now seen corresponding path program 1 times [2019-11-16 00:02:47,791 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:47,791 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137468696] [2019-11-16 00:02:47,791 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:47,792 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:47,792 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:47,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:47,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:47,868 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2137468696] [2019-11-16 00:02:47,868 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:47,868 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:47,869 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317178301] [2019-11-16 00:02:47,869 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:47,869 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:47,869 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:47,870 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:47,870 INFO L87 Difference]: Start difference. First operand 13878 states and 16894 transitions. Second operand 5 states. [2019-11-16 00:02:50,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:50,503 INFO L93 Difference]: Finished difference Result 33517 states and 40902 transitions. [2019-11-16 00:02:50,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-16 00:02:50,503 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:50,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:50,519 INFO L225 Difference]: With dead ends: 33517 [2019-11-16 00:02:50,519 INFO L226 Difference]: Without dead ends: 19909 [2019-11-16 00:02:50,529 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:50,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19909 states. [2019-11-16 00:02:52,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19909 to 13890. [2019-11-16 00:02:52,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13890 states. [2019-11-16 00:02:52,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13890 states to 13890 states and 16800 transitions. [2019-11-16 00:02:52,195 INFO L78 Accepts]: Start accepts. Automaton has 13890 states and 16800 transitions. Word has length 179 [2019-11-16 00:02:52,195 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:52,195 INFO L462 AbstractCegarLoop]: Abstraction has 13890 states and 16800 transitions. [2019-11-16 00:02:52,195 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:52,195 INFO L276 IsEmpty]: Start isEmpty. Operand 13890 states and 16800 transitions. [2019-11-16 00:02:52,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:52,196 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:52,196 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:52,196 INFO L410 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:52,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:52,197 INFO L82 PathProgramCache]: Analyzing trace with hash 1901570305, now seen corresponding path program 1 times [2019-11-16 00:02:52,197 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:52,197 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294814992] [2019-11-16 00:02:52,197 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:52,197 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:52,197 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:52,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-16 00:02:52,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-16 00:02:52,279 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294814992] [2019-11-16 00:02:52,280 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-16 00:02:52,280 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-16 00:02:52,280 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1956319580] [2019-11-16 00:02:52,280 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-16 00:02:52,281 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-16 00:02:52,281 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-16 00:02:52,281 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-16 00:02:52,281 INFO L87 Difference]: Start difference. First operand 13890 states and 16800 transitions. Second operand 5 states. [2019-11-16 00:02:54,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-16 00:02:54,081 INFO L93 Difference]: Finished difference Result 27482 states and 33243 transitions. [2019-11-16 00:02:54,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-16 00:02:54,081 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-11-16 00:02:54,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-16 00:02:54,092 INFO L225 Difference]: With dead ends: 27482 [2019-11-16 00:02:54,092 INFO L226 Difference]: Without dead ends: 13890 [2019-11-16 00:02:54,100 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-16 00:02:54,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13890 states. [2019-11-16 00:02:55,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13890 to 13890. [2019-11-16 00:02:55,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13890 states. [2019-11-16 00:02:55,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13890 states to 13890 states and 16690 transitions. [2019-11-16 00:02:55,783 INFO L78 Accepts]: Start accepts. Automaton has 13890 states and 16690 transitions. Word has length 179 [2019-11-16 00:02:55,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-16 00:02:55,784 INFO L462 AbstractCegarLoop]: Abstraction has 13890 states and 16690 transitions. [2019-11-16 00:02:55,784 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-16 00:02:55,784 INFO L276 IsEmpty]: Start isEmpty. Operand 13890 states and 16690 transitions. [2019-11-16 00:02:55,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-16 00:02:55,785 INFO L372 BasicCegarLoop]: Found error trace [2019-11-16 00:02:55,785 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-16 00:02:55,785 INFO L410 AbstractCegarLoop]: === Iteration 47 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-16 00:02:55,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-16 00:02:55,785 INFO L82 PathProgramCache]: Analyzing trace with hash 1004177027, now seen corresponding path program 1 times [2019-11-16 00:02:55,786 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-16 00:02:55,786 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265699832] [2019-11-16 00:02:55,786 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:55,786 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-16 00:02:55,786 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-16 00:02:55,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-16 00:02:55,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-16 00:02:55,954 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-16 00:02:55,954 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-11-16 00:02:56,176 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 16.11 12:02:56 BoogieIcfgContainer [2019-11-16 00:02:56,176 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-16 00:02:56,177 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-16 00:02:56,177 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-16 00:02:56,177 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-16 00:02:56,178 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:01:55" (3/4) ... [2019-11-16 00:02:56,180 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-16 00:02:56,404 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_78fe5354-baa5-488b-aa2a-2ac6ed3d06f3/bin/uautomizer/witness.graphml [2019-11-16 00:02:56,404 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-16 00:02:56,406 INFO L168 Benchmark]: Toolchain (without parser) took 65317.27 ms. Allocated memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: 4.0 GB). Free memory was 948.7 MB in the beginning and 3.7 GB in the end (delta: -2.8 GB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2019-11-16 00:02:56,406 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-16 00:02:56,407 INFO L168 Benchmark]: CACSL2BoogieTranslator took 641.01 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 943.3 MB in the beginning and 1.1 GB in the end (delta: -173.6 MB). Peak memory consumption was 23.6 MB. Max. memory is 11.5 GB. [2019-11-16 00:02:56,407 INFO L168 Benchmark]: Boogie Procedure Inliner took 172.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 15.0 MB). Peak memory consumption was 15.0 MB. Max. memory is 11.5 GB. [2019-11-16 00:02:56,408 INFO L168 Benchmark]: Boogie Preprocessor took 135.83 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 20.0 MB). Peak memory consumption was 20.0 MB. Max. memory is 11.5 GB. [2019-11-16 00:02:56,408 INFO L168 Benchmark]: RCFGBuilder took 3621.79 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 101.2 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -5.5 MB). Peak memory consumption was 293.4 MB. Max. memory is 11.5 GB. [2019-11-16 00:02:56,409 INFO L168 Benchmark]: TraceAbstraction took 60506.30 ms. Allocated memory was 1.3 GB in the beginning and 5.0 GB in the end (delta: 3.7 GB). Free memory was 1.1 GB in the beginning and 3.9 GB in the end (delta: -2.8 GB). Peak memory consumption was 959.4 MB. Max. memory is 11.5 GB. [2019-11-16 00:02:56,409 INFO L168 Benchmark]: Witness Printer took 227.61 ms. Allocated memory is still 5.0 GB. Free memory was 3.9 GB in the beginning and 3.7 GB in the end (delta: 107.6 MB). Peak memory consumption was 107.6 MB. Max. memory is 11.5 GB. [2019-11-16 00:02:56,411 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 641.01 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 943.3 MB in the beginning and 1.1 GB in the end (delta: -173.6 MB). Peak memory consumption was 23.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 172.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 15.0 MB). Peak memory consumption was 15.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 135.83 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 20.0 MB). Peak memory consumption was 20.0 MB. Max. memory is 11.5 GB. * RCFGBuilder took 3621.79 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 101.2 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -5.5 MB). Peak memory consumption was 293.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 60506.30 ms. Allocated memory was 1.3 GB in the beginning and 5.0 GB in the end (delta: 3.7 GB). Free memory was 1.1 GB in the beginning and 3.9 GB in the end (delta: -2.8 GB). Peak memory consumption was 959.4 MB. Max. memory is 11.5 GB. * Witness Printer took 227.61 ms. Allocated memory is still 5.0 GB. Free memory was 3.9 GB in the beginning and 3.7 GB in the end (delta: 107.6 MB). Peak memory consumption was 107.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int t9_pc = 0; [L25] int t10_pc = 0; [L26] int t11_pc = 0; [L27] int t12_pc = 0; [L28] int t13_pc = 0; [L29] int t14_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int t6_st ; [L37] int t7_st ; [L38] int t8_st ; [L39] int t9_st ; [L40] int t10_st ; [L41] int t11_st ; [L42] int t12_st ; [L43] int t13_st ; [L44] int t14_st ; [L45] int m_i ; [L46] int t1_i ; [L47] int t2_i ; [L48] int t3_i ; [L49] int t4_i ; [L50] int t5_i ; [L51] int t6_i ; [L52] int t7_i ; [L53] int t8_i ; [L54] int t9_i ; [L55] int t10_i ; [L56] int t11_i ; [L57] int t12_i ; [L58] int t13_i ; [L59] int t14_i ; [L60] int M_E = 2; [L61] int T1_E = 2; [L62] int T2_E = 2; [L63] int T3_E = 2; [L64] int T4_E = 2; [L65] int T5_E = 2; [L66] int T6_E = 2; [L67] int T7_E = 2; [L68] int T8_E = 2; [L69] int T9_E = 2; [L70] int T10_E = 2; [L71] int T11_E = 2; [L72] int T12_E = 2; [L73] int T13_E = 2; [L74] int T14_E = 2; [L75] int E_1 = 2; [L76] int E_2 = 2; [L77] int E_3 = 2; [L78] int E_4 = 2; [L79] int E_5 = 2; [L80] int E_6 = 2; [L81] int E_7 = 2; [L82] int E_8 = 2; [L83] int E_9 = 2; [L84] int E_10 = 2; [L85] int E_11 = 2; [L86] int E_12 = 2; [L87] int E_13 = 2; [L88] int E_14 = 2; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=0, m_pc=0, m_st=0, T10_E=2, t10_i=0, t10_pc=0, t10_st=0, T11_E=2, t11_i=0, t11_pc=0, t11_st=0, T12_E=2, t12_i=0, t12_pc=0, t12_st=0, T13_E=2, t13_i=0, t13_pc=0, t13_st=0, T14_E=2, t14_i=0, t14_pc=0, t14_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0, T7_E=2, t7_i=0, t7_pc=0, t7_st=0, T8_E=2, t8_i=0, t8_pc=0, t8_st=0, T9_E=2, t9_i=0, t9_pc=0, t9_st=0] [L2052] int __retres1 ; [L1954] m_i = 1 [L1955] t1_i = 1 [L1956] t2_i = 1 [L1957] t3_i = 1 [L1958] t4_i = 1 [L1959] t5_i = 1 [L1960] t6_i = 1 [L1961] t7_i = 1 [L1962] t8_i = 1 [L1963] t9_i = 1 [L1964] t10_i = 1 [L1965] t11_i = 1 [L1966] t12_i = 1 [L1967] t13_i = 1 [L1968] t14_i = 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1993] int kernel_st ; [L1994] int tmp ; [L1995] int tmp___0 ; [L1999] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L929] COND TRUE m_i == 1 [L930] m_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L934] COND TRUE t1_i == 1 [L935] t1_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L939] COND TRUE t2_i == 1 [L940] t2_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L944] COND TRUE t3_i == 1 [L945] t3_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L949] COND TRUE t4_i == 1 [L950] t4_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L954] COND TRUE t5_i == 1 [L955] t5_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L959] COND TRUE t6_i == 1 [L960] t6_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L964] COND TRUE t7_i == 1 [L965] t7_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L969] COND TRUE t8_i == 1 [L970] t8_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L974] COND TRUE t9_i == 1 [L975] t9_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L979] COND TRUE t10_i == 1 [L980] t10_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L984] COND TRUE t11_i == 1 [L985] t11_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L989] COND TRUE t12_i == 1 [L990] t12_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L994] COND TRUE t13_i == 1 [L995] t13_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L999] COND TRUE t14_i == 1 [L1000] t14_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1332] COND FALSE !(M_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1337] COND FALSE !(T1_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1342] COND FALSE !(T2_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1347] COND FALSE !(T3_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1352] COND FALSE !(T4_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1357] COND FALSE !(T5_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1362] COND FALSE !(T6_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1367] COND FALSE !(T7_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1372] COND FALSE !(T8_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1377] COND FALSE !(T9_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1382] COND FALSE !(T10_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1387] COND FALSE !(T11_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1392] COND FALSE !(T12_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1397] COND FALSE !(T13_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1402] COND FALSE !(T14_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1407] COND FALSE !(E_1 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1412] COND FALSE !(E_2 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1417] COND FALSE !(E_3 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1422] COND FALSE !(E_4 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1427] COND FALSE !(E_5 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1432] COND FALSE !(E_6 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1437] COND FALSE !(E_7 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1442] COND FALSE !(E_8 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1447] COND FALSE !(E_9 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1452] COND FALSE !(E_10 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1457] COND FALSE !(E_11 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1462] COND FALSE !(E_12 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1467] COND FALSE !(E_13 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1472] COND FALSE !(E_14 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1635] int tmp ; [L1636] int tmp___0 ; [L1637] int tmp___1 ; [L1638] int tmp___2 ; [L1639] int tmp___3 ; [L1640] int tmp___4 ; [L1641] int tmp___5 ; [L1642] int tmp___6 ; [L1643] int tmp___7 ; [L1644] int tmp___8 ; [L1645] int tmp___9 ; [L1646] int tmp___10 ; [L1647] int tmp___11 ; [L1648] int tmp___12 ; [L1649] int tmp___13 ; [L633] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L636] COND FALSE !(m_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L646] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L648] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1654] tmp = is_master_triggered() [L1656] COND FALSE !(\read(tmp)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L652] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L655] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L665] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L667] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1662] tmp___0 = is_transmit1_triggered() [L1664] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L671] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L674] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L684] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L686] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1670] tmp___1 = is_transmit2_triggered() [L1672] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L690] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L693] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L703] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L705] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1678] tmp___2 = is_transmit3_triggered() [L1680] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L709] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L712] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L722] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L724] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1686] tmp___3 = is_transmit4_triggered() [L1688] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L728] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L731] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L741] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L743] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1694] tmp___4 = is_transmit5_triggered() [L1696] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L747] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L750] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L760] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L762] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1702] tmp___5 = is_transmit6_triggered() [L1704] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L766] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L769] COND FALSE !(t7_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L779] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L781] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1710] tmp___6 = is_transmit7_triggered() [L1712] COND FALSE !(\read(tmp___6)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L785] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L788] COND FALSE !(t8_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L798] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L800] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1718] tmp___7 = is_transmit8_triggered() [L1720] COND FALSE !(\read(tmp___7)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L804] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L807] COND FALSE !(t9_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L817] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L819] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1726] tmp___8 = is_transmit9_triggered() [L1728] COND FALSE !(\read(tmp___8)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L823] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L826] COND FALSE !(t10_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L836] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L838] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1734] tmp___9 = is_transmit10_triggered() [L1736] COND FALSE !(\read(tmp___9)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L842] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L845] COND FALSE !(t11_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L855] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L857] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1742] tmp___10 = is_transmit11_triggered() [L1744] COND FALSE !(\read(tmp___10)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L861] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L864] COND FALSE !(t12_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L874] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L876] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1750] tmp___11 = is_transmit12_triggered() [L1752] COND FALSE !(\read(tmp___11)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L880] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L883] COND FALSE !(t13_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L893] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L895] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1758] tmp___12 = is_transmit13_triggered() [L1760] COND FALSE !(\read(tmp___12)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L899] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L902] COND FALSE !(t14_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L912] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L914] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1766] tmp___13 = is_transmit14_triggered() [L1768] COND FALSE !(\read(tmp___13)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1485] COND FALSE !(M_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1490] COND FALSE !(T1_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1495] COND FALSE !(T2_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1500] COND FALSE !(T3_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1505] COND FALSE !(T4_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1510] COND FALSE !(T5_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1515] COND FALSE !(T6_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1520] COND FALSE !(T7_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1525] COND FALSE !(T8_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1530] COND FALSE !(T9_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1535] COND FALSE !(T10_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1540] COND FALSE !(T11_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1545] COND FALSE !(T12_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1550] COND FALSE !(T13_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1555] COND FALSE !(T14_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1560] COND FALSE !(E_1 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1565] COND FALSE !(E_2 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1570] COND FALSE !(E_3 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1575] COND FALSE !(E_4 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1580] COND FALSE !(E_5 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1585] COND FALSE !(E_6 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1590] COND FALSE !(E_7 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1595] COND FALSE !(E_8 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1600] COND FALSE !(E_9 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1605] COND FALSE !(E_10 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1610] COND FALSE !(E_11 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1615] COND FALSE !(E_12 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1620] COND FALSE !(E_13 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1625] COND FALSE !(E_14 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2007] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2010] kernel_st = 1 [L1096] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1100] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1009] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1012] COND TRUE m_st == 0 [L1013] __retres1 = 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1091] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1103] tmp = exists_runnable_thread() [L1105] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1110] COND TRUE m_st == 0 [L1111] int tmp_ndt_1; [L1112] tmp_ndt_1 = __VERIFIER_nondet_int() [L1113] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1124] COND TRUE t1_st == 0 [L1125] int tmp_ndt_2; [L1126] tmp_ndt_2 = __VERIFIER_nondet_int() [L1127] COND FALSE !(\read(tmp_ndt_2)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L11] __VERIFIER_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 2018 locations, 1 error locations. Result: UNSAFE, OverallTime: 60.4s, OverallIterations: 47, TraceHistogramMax: 1, AutomataDifference: 34.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 127614 SDtfs, 174983 SDslu, 71134 SDs, 0 SdLazy, 2123 SolverSat, 1215 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 160 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=13890occurred in iteration=45, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 21.2s AutomataMinimizationTime, 46 MinimizatonAttempts, 96915 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 1.8s InterpolantComputationTime, 8380 NumberOfCodeBlocks, 8380 NumberOfCodeBlocksAsserted, 47 NumberOfCheckSat, 8155 ConstructedInterpolants, 0 QuantifiedInterpolants, 2077177 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 46 InterpolantComputations, 46 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...