./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cad46833 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0c244c639ec9718adcbacffa967b748c52a23cd0 ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.24-cad4683 [2019-11-15 21:00:34,583 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-15 21:00:34,585 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-15 21:00:34,600 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-15 21:00:34,600 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-15 21:00:34,601 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-15 21:00:34,603 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-15 21:00:34,613 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-15 21:00:34,617 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-15 21:00:34,622 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-15 21:00:34,623 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-15 21:00:34,624 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-15 21:00:34,624 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-15 21:00:34,625 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-15 21:00:34,625 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-15 21:00:34,626 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-15 21:00:34,627 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-15 21:00:34,628 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-15 21:00:34,629 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-15 21:00:34,633 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-15 21:00:34,637 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-15 21:00:34,639 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-15 21:00:34,642 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-15 21:00:34,642 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-15 21:00:34,647 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-15 21:00:34,647 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-15 21:00:34,647 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-15 21:00:34,650 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-15 21:00:34,650 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-15 21:00:34,652 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-15 21:00:34,652 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-15 21:00:34,653 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-15 21:00:34,653 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-15 21:00:34,654 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-15 21:00:34,656 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-15 21:00:34,656 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-15 21:00:34,657 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-15 21:00:34,657 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-15 21:00:34,657 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-15 21:00:34,658 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-15 21:00:34,659 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-15 21:00:34,660 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-11-15 21:00:34,689 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-15 21:00:34,689 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-15 21:00:34,690 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-15 21:00:34,690 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-15 21:00:34,691 INFO L138 SettingsManager]: * Use SBE=true [2019-11-15 21:00:34,691 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-11-15 21:00:34,691 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-11-15 21:00:34,691 INFO L138 SettingsManager]: * Use old map elimination=false [2019-11-15 21:00:34,692 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-11-15 21:00:34,692 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-11-15 21:00:34,692 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-11-15 21:00:34,692 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-15 21:00:34,692 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-15 21:00:34,693 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-11-15 21:00:34,693 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-15 21:00:34,693 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-15 21:00:34,693 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-15 21:00:34,694 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-11-15 21:00:34,694 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-11-15 21:00:34,694 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-11-15 21:00:34,694 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-15 21:00:34,694 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-15 21:00:34,695 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-11-15 21:00:34,695 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-15 21:00:34,695 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-11-15 21:00:34,695 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-15 21:00:34,696 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-15 21:00:34,696 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-11-15 21:00:34,696 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-15 21:00:34,696 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-15 21:00:34,696 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-11-15 21:00:34,697 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-11-15 21:00:34,698 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0c244c639ec9718adcbacffa967b748c52a23cd0 [2019-11-15 21:00:34,741 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-15 21:00:34,757 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-15 21:00:34,760 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-15 21:00:34,762 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-15 21:00:34,762 INFO L275 PluginConnector]: CDTParser initialized [2019-11-15 21:00:34,763 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.02.cil.c [2019-11-15 21:00:34,830 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/data/7fef4a3bf/bae47d4fcd6f47039178d7e51bac85ca/FLAG5a1d9e2d5 [2019-11-15 21:00:35,280 INFO L306 CDTParser]: Found 1 translation units. [2019-11-15 21:00:35,280 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/sv-benchmarks/c/systemc/transmitter.02.cil.c [2019-11-15 21:00:35,296 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/data/7fef4a3bf/bae47d4fcd6f47039178d7e51bac85ca/FLAG5a1d9e2d5 [2019-11-15 21:00:35,649 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/data/7fef4a3bf/bae47d4fcd6f47039178d7e51bac85ca [2019-11-15 21:00:35,652 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-15 21:00:35,653 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-15 21:00:35,656 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-15 21:00:35,656 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-15 21:00:35,660 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-15 21:00:35,660 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 09:00:35" (1/1) ... [2019-11-15 21:00:35,663 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@58d32988 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:35, skipping insertion in model container [2019-11-15 21:00:35,663 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.11 09:00:35" (1/1) ... [2019-11-15 21:00:35,670 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-15 21:00:35,698 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-15 21:00:35,967 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 21:00:35,973 INFO L188 MainTranslator]: Completed pre-run [2019-11-15 21:00:36,020 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-15 21:00:36,039 INFO L192 MainTranslator]: Completed translation [2019-11-15 21:00:36,039 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36 WrapperNode [2019-11-15 21:00:36,040 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-15 21:00:36,040 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-15 21:00:36,041 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-15 21:00:36,041 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-15 21:00:36,048 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36" (1/1) ... [2019-11-15 21:00:36,055 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36" (1/1) ... [2019-11-15 21:00:36,087 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-15 21:00:36,088 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-15 21:00:36,088 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-15 21:00:36,088 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-15 21:00:36,097 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36" (1/1) ... [2019-11-15 21:00:36,097 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36" (1/1) ... [2019-11-15 21:00:36,100 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36" (1/1) ... [2019-11-15 21:00:36,100 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36" (1/1) ... [2019-11-15 21:00:36,108 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36" (1/1) ... [2019-11-15 21:00:36,118 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36" (1/1) ... [2019-11-15 21:00:36,121 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36" (1/1) ... [2019-11-15 21:00:36,139 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-15 21:00:36,150 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-15 21:00:36,150 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-15 21:00:36,150 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-15 21:00:36,151 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:36,218 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-15 21:00:36,218 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-15 21:00:37,050 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-15 21:00:37,050 INFO L284 CfgBuilder]: Removed 94 assume(true) statements. [2019-11-15 21:00:37,051 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 09:00:37 BoogieIcfgContainer [2019-11-15 21:00:37,051 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-15 21:00:37,052 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-11-15 21:00:37,052 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-11-15 21:00:37,055 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-11-15 21:00:37,058 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-15 21:00:37,059 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.11 09:00:35" (1/3) ... [2019-11-15 21:00:37,060 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@74f2ecc3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.11 09:00:37, skipping insertion in model container [2019-11-15 21:00:37,060 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-15 21:00:37,060 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.11 09:00:36" (2/3) ... [2019-11-15 21:00:37,060 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@74f2ecc3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.11 09:00:37, skipping insertion in model container [2019-11-15 21:00:37,060 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-15 21:00:37,060 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 09:00:37" (3/3) ... [2019-11-15 21:00:37,062 INFO L371 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2019-11-15 21:00:37,101 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-11-15 21:00:37,101 INFO L357 BuchiCegarLoop]: Hoare is false [2019-11-15 21:00:37,102 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-11-15 21:00:37,102 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-15 21:00:37,102 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-15 21:00:37,102 INFO L361 BuchiCegarLoop]: Difference is false [2019-11-15 21:00:37,102 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-15 21:00:37,102 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-11-15 21:00:37,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states. [2019-11-15 21:00:37,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 150 [2019-11-15 21:00:37,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:37,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:37,162 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:37,162 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:37,162 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-11-15 21:00:37,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states. [2019-11-15 21:00:37,172 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 150 [2019-11-15 21:00:37,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:37,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:37,175 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:37,175 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:37,181 INFO L791 eck$LassoCheckResult]: Stem: 157#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 13#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 184#L481true havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 130#L204true assume !(1 == ~m_i~0);~m_st~0 := 2; 185#L211-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 54#L216-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 71#L221-1true assume !(0 == ~M_E~0); 180#L324-1true assume !(0 == ~T1_E~0); 18#L329-1true assume !(0 == ~T2_E~0); 68#L334-1true assume !(0 == ~E_1~0); 99#L339-1true assume !(0 == ~E_2~0); 146#L344-1true havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 122#L146true assume !(1 == ~m_pc~0); 116#L146-2true is_master_triggered_~__retres1~0 := 0; 123#L157true is_master_triggered_#res := is_master_triggered_~__retres1~0; 47#L158true activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 44#L395true assume !(0 != activate_threads_~tmp~1); 14#L395-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 141#L165true assume 1 == ~t1_pc~0; 69#L166true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 142#L176true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 70#L177true activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 50#L403true assume !(0 != activate_threads_~tmp___0~0); 55#L403-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 176#L184true assume !(1 == ~t2_pc~0); 172#L184-2true is_transmit2_triggered_~__retres1~2 := 0; 177#L195true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 110#L196true activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 80#L411true assume !(0 != activate_threads_~tmp___1~0); 63#L411-2true assume !(1 == ~M_E~0); 178#L357-1true assume !(1 == ~T1_E~0); 15#L362-1true assume !(1 == ~T2_E~0); 64#L367-1true assume !(1 == ~E_1~0); 95#L372-1true assume !(1 == ~E_2~0); 107#L518-1true [2019-11-15 21:00:37,182 INFO L793 eck$LassoCheckResult]: Loop: 107#L518-1true assume !false; 22#L519true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 19#L299true assume false; 136#L314true start_simulation_~kernel_st~0 := 2; 129#L204-1true start_simulation_~kernel_st~0 := 3; 181#L324-2true assume 0 == ~M_E~0;~M_E~0 := 1; 186#L324-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 25#L329-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 74#L334-3true assume 0 == ~E_1~0;~E_1~0 := 1; 105#L339-3true assume !(0 == ~E_2~0); 152#L344-3true havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 92#L146-9true assume 1 == ~m_pc~0; 34#L147-3true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 113#L157-3true is_master_triggered_#res := is_master_triggered_~__retres1~0; 35#L158-3true activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6#L395-9true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11#L395-11true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 121#L165-9true assume !(1 == ~t1_pc~0); 114#L165-11true is_transmit1_triggered_~__retres1~1 := 0; 162#L176-3true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 85#L177-3true activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 48#L403-9true assume !(0 != activate_threads_~tmp___0~0); 21#L403-11true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 140#L184-9true assume 1 == ~t2_pc~0; 98#L185-3true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 171#L195-3true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 100#L196-3true activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 52#L411-9true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 59#L411-11true assume 1 == ~M_E~0;~M_E~0 := 2; 182#L357-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 23#L362-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 72#L367-3true assume !(1 == ~E_1~0); 103#L372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 150#L377-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 127#L234-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 87#L251-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5#L252-1true start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 115#L537true assume !(0 == start_simulation_~tmp~3); 118#L537-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 125#L234-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 109#L251-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3#L252-2true stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 183#L492true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 76#L499true stop_simulation_#res := stop_simulation_~__retres2~0; 190#L500true start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 175#L550true assume !(0 != start_simulation_~tmp___0~1); 107#L518-1true [2019-11-15 21:00:37,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:37,186 INFO L82 PathProgramCache]: Analyzing trace with hash 1765217540, now seen corresponding path program 1 times [2019-11-15 21:00:37,192 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:37,193 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31591868] [2019-11-15 21:00:37,193 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,193 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,193 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:37,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:37,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:37,321 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31591868] [2019-11-15 21:00:37,322 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:37,322 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:37,323 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271457480] [2019-11-15 21:00:37,334 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-11-15 21:00:37,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:37,335 INFO L82 PathProgramCache]: Analyzing trace with hash 1231104429, now seen corresponding path program 1 times [2019-11-15 21:00:37,335 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:37,336 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889346390] [2019-11-15 21:00:37,336 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,336 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,336 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:37,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:37,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:37,360 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889346390] [2019-11-15 21:00:37,361 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:37,361 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:00:37,361 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686164588] [2019-11-15 21:00:37,363 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:37,364 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:37,378 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:37,379 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:37,381 INFO L87 Difference]: Start difference. First operand 191 states. Second operand 3 states. [2019-11-15 21:00:37,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:37,414 INFO L93 Difference]: Finished difference Result 191 states and 286 transitions. [2019-11-15 21:00:37,414 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:37,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191 states and 286 transitions. [2019-11-15 21:00:37,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2019-11-15 21:00:37,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191 states to 186 states and 281 transitions. [2019-11-15 21:00:37,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2019-11-15 21:00:37,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2019-11-15 21:00:37,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 281 transitions. [2019-11-15 21:00:37,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:37,438 INFO L688 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2019-11-15 21:00:37,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 281 transitions. [2019-11-15 21:00:37,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2019-11-15 21:00:37,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2019-11-15 21:00:37,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 281 transitions. [2019-11-15 21:00:37,479 INFO L711 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2019-11-15 21:00:37,479 INFO L591 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2019-11-15 21:00:37,479 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-11-15 21:00:37,480 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 281 transitions. [2019-11-15 21:00:37,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2019-11-15 21:00:37,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:37,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:37,484 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:37,484 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:37,484 INFO L791 eck$LassoCheckResult]: Stem: 573#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 413#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 414#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 569#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 570#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 481#L216-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 482#L221-1 assume !(0 == ~M_E~0); 508#L324-1 assume !(0 == ~T1_E~0); 427#L329-1 assume !(0 == ~T2_E~0); 428#L334-1 assume !(0 == ~E_1~0); 503#L339-1 assume !(0 == ~E_2~0); 543#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 563#L146 assume !(1 == ~m_pc~0); 469#L146-2 is_master_triggered_~__retres1~0 := 0; 470#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 471#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 467#L395 assume !(0 != activate_threads_~tmp~1); 415#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 416#L165 assume 1 == ~t1_pc~0; 504#L166 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 505#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 507#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 474#L403 assume !(0 != activate_threads_~tmp___0~0); 475#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 483#L184 assume !(1 == ~t2_pc~0); 556#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 555#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 557#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 521#L411 assume !(0 != activate_threads_~tmp___1~0); 494#L411-2 assume !(1 == ~M_E~0); 495#L357-1 assume !(1 == ~T1_E~0); 417#L362-1 assume !(1 == ~T2_E~0); 418#L367-1 assume !(1 == ~E_1~0); 499#L372-1 assume !(1 == ~E_2~0); 538#L518-1 [2019-11-15 21:00:37,485 INFO L793 eck$LassoCheckResult]: Loop: 538#L518-1 assume !false; 434#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 406#L299 assume !false; 429#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 530#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 490#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 399#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 400#L266 assume !(0 != eval_~tmp~0); 420#L314 start_simulation_~kernel_st~0 := 2; 566#L204-1 start_simulation_~kernel_st~0 := 3; 567#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 576#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 435#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 436#L334-3 assume 0 == ~E_1~0;~E_1~0 := 1; 510#L339-3 assume !(0 == ~E_2~0); 552#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 531#L146-9 assume !(1 == ~m_pc~0); 448#L146-11 is_master_triggered_~__retres1~0 := 0; 447#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 449#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 397#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 398#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 410#L165-9 assume 1 == ~t1_pc~0; 522#L166-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 523#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 525#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 472#L403-9 assume !(0 != activate_threads_~tmp___0~0); 425#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 426#L184-9 assume 1 == ~t2_pc~0; 539#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 540#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 542#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 476#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 477#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 488#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 430#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 431#L367-3 assume !(1 == ~E_1~0); 509#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 548#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 565#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 485#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 395#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 396#L537 assume !(0 == start_simulation_~tmp~3); 559#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 561#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 479#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 391#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 392#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 512#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 513#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 575#L550 assume !(0 != start_simulation_~tmp___0~1); 538#L518-1 [2019-11-15 21:00:37,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:37,485 INFO L82 PathProgramCache]: Analyzing trace with hash 1063617666, now seen corresponding path program 1 times [2019-11-15 21:00:37,485 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:37,486 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083281480] [2019-11-15 21:00:37,486 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,486 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,486 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:37,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:37,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:37,517 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083281480] [2019-11-15 21:00:37,518 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:37,518 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:37,518 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228214986] [2019-11-15 21:00:37,519 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-11-15 21:00:37,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:37,519 INFO L82 PathProgramCache]: Analyzing trace with hash -1036257152, now seen corresponding path program 1 times [2019-11-15 21:00:37,519 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:37,519 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213049958] [2019-11-15 21:00:37,520 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,520 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,520 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:37,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:37,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:37,575 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213049958] [2019-11-15 21:00:37,575 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:37,576 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:37,576 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6284972] [2019-11-15 21:00:37,576 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:37,576 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:37,577 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:37,577 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:37,577 INFO L87 Difference]: Start difference. First operand 186 states and 281 transitions. cyclomatic complexity: 96 Second operand 3 states. [2019-11-15 21:00:37,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:37,597 INFO L93 Difference]: Finished difference Result 186 states and 280 transitions. [2019-11-15 21:00:37,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:37,601 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 280 transitions. [2019-11-15 21:00:37,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2019-11-15 21:00:37,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 186 states and 280 transitions. [2019-11-15 21:00:37,608 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2019-11-15 21:00:37,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2019-11-15 21:00:37,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 280 transitions. [2019-11-15 21:00:37,609 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:37,609 INFO L688 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2019-11-15 21:00:37,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 280 transitions. [2019-11-15 21:00:37,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2019-11-15 21:00:37,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2019-11-15 21:00:37,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 280 transitions. [2019-11-15 21:00:37,620 INFO L711 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2019-11-15 21:00:37,621 INFO L591 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2019-11-15 21:00:37,621 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-11-15 21:00:37,621 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 280 transitions. [2019-11-15 21:00:37,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2019-11-15 21:00:37,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:37,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:37,624 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:37,624 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:37,625 INFO L791 eck$LassoCheckResult]: Stem: 952#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 792#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 793#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 947#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 948#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 860#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 861#L221-1 assume !(0 == ~M_E~0); 887#L324-1 assume !(0 == ~T1_E~0); 802#L329-1 assume !(0 == ~T2_E~0); 803#L334-1 assume !(0 == ~E_1~0); 882#L339-1 assume !(0 == ~E_2~0); 921#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 942#L146 assume !(1 == ~m_pc~0); 848#L146-2 is_master_triggered_~__retres1~0 := 0; 849#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 850#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 845#L395 assume !(0 != activate_threads_~tmp~1); 794#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 795#L165 assume 1 == ~t1_pc~0; 883#L166 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 884#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 886#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 852#L403 assume !(0 != activate_threads_~tmp___0~0); 853#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 862#L184 assume !(1 == ~t2_pc~0); 935#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 934#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 936#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 898#L411 assume !(0 != activate_threads_~tmp___1~0); 873#L411-2 assume !(1 == ~M_E~0); 874#L357-1 assume !(1 == ~T1_E~0); 796#L362-1 assume !(1 == ~T2_E~0); 797#L367-1 assume !(1 == ~E_1~0); 875#L372-1 assume !(1 == ~E_2~0); 915#L518-1 [2019-11-15 21:00:37,625 INFO L793 eck$LassoCheckResult]: Loop: 915#L518-1 assume !false; 809#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 785#L299 assume !false; 804#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 908#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 869#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 778#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 779#L266 assume !(0 != eval_~tmp~0); 799#L314 start_simulation_~kernel_st~0 := 2; 945#L204-1 start_simulation_~kernel_st~0 := 3; 946#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 955#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 814#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 815#L334-3 assume 0 == ~E_1~0;~E_1~0 := 1; 889#L339-3 assume !(0 == ~E_2~0); 931#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 910#L146-9 assume 1 == ~m_pc~0; 825#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 826#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 828#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 776#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 777#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 789#L165-9 assume 1 == ~t1_pc~0; 901#L166-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 902#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 904#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 851#L403-9 assume !(0 != activate_threads_~tmp___0~0); 807#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 808#L184-9 assume 1 == ~t2_pc~0; 918#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 919#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 922#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 855#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 856#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 867#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 810#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 811#L367-3 assume !(1 == ~E_1~0); 888#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 927#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 944#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 864#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 774#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 775#L537 assume !(0 == start_simulation_~tmp~3); 938#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 940#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 858#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 770#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 771#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 891#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 892#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 954#L550 assume !(0 != start_simulation_~tmp___0~1); 915#L518-1 [2019-11-15 21:00:37,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:37,625 INFO L82 PathProgramCache]: Analyzing trace with hash -322585728, now seen corresponding path program 1 times [2019-11-15 21:00:37,626 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:37,626 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609855251] [2019-11-15 21:00:37,626 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,626 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,626 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:37,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:37,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:37,667 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1609855251] [2019-11-15 21:00:37,667 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:37,667 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:00:37,667 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137688734] [2019-11-15 21:00:37,668 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-11-15 21:00:37,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:37,668 INFO L82 PathProgramCache]: Analyzing trace with hash -2087706241, now seen corresponding path program 1 times [2019-11-15 21:00:37,668 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:37,668 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973552646] [2019-11-15 21:00:37,668 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,669 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,669 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:37,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:37,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:37,751 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973552646] [2019-11-15 21:00:37,752 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:37,752 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:37,752 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82810907] [2019-11-15 21:00:37,752 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:37,753 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:37,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:37,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:37,753 INFO L87 Difference]: Start difference. First operand 186 states and 280 transitions. cyclomatic complexity: 95 Second operand 3 states. [2019-11-15 21:00:37,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:37,839 INFO L93 Difference]: Finished difference Result 309 states and 459 transitions. [2019-11-15 21:00:37,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:37,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 309 states and 459 transitions. [2019-11-15 21:00:37,844 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 271 [2019-11-15 21:00:37,847 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 309 states to 309 states and 459 transitions. [2019-11-15 21:00:37,848 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 309 [2019-11-15 21:00:37,848 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 309 [2019-11-15 21:00:37,849 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309 states and 459 transitions. [2019-11-15 21:00:37,859 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:37,860 INFO L688 BuchiCegarLoop]: Abstraction has 309 states and 459 transitions. [2019-11-15 21:00:37,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309 states and 459 transitions. [2019-11-15 21:00:37,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309 to 307. [2019-11-15 21:00:37,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 307 states. [2019-11-15 21:00:37,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 457 transitions. [2019-11-15 21:00:37,878 INFO L711 BuchiCegarLoop]: Abstraction has 307 states and 457 transitions. [2019-11-15 21:00:37,878 INFO L591 BuchiCegarLoop]: Abstraction has 307 states and 457 transitions. [2019-11-15 21:00:37,878 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-11-15 21:00:37,878 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307 states and 457 transitions. [2019-11-15 21:00:37,880 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 269 [2019-11-15 21:00:37,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:37,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:37,882 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:37,883 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:37,883 INFO L791 eck$LassoCheckResult]: Stem: 1460#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1294#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1295#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1451#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 1452#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1361#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1362#L221-1 assume !(0 == ~M_E~0); 1385#L324-1 assume !(0 == ~T1_E~0); 1309#L329-1 assume !(0 == ~T2_E~0); 1310#L334-1 assume !(0 == ~E_1~0); 1383#L339-1 assume !(0 == ~E_2~0); 1421#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1445#L146 assume !(1 == ~m_pc~0); 1349#L146-2 is_master_triggered_~__retres1~0 := 0; 1350#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1351#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1347#L395 assume !(0 != activate_threads_~tmp~1); 1298#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1299#L165 assume !(1 == ~t1_pc~0); 1456#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 1457#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1384#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1354#L403 assume !(0 != activate_threads_~tmp___0~0); 1355#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1363#L184 assume !(1 == ~t2_pc~0); 1436#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 1435#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1437#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1399#L411 assume !(0 != activate_threads_~tmp___1~0); 1374#L411-2 assume !(1 == ~M_E~0); 1375#L357-1 assume !(1 == ~T1_E~0); 1300#L362-1 assume !(1 == ~T2_E~0); 1301#L367-1 assume !(1 == ~E_1~0); 1379#L372-1 assume !(1 == ~E_2~0); 1416#L518-1 [2019-11-15 21:00:37,883 INFO L793 eck$LassoCheckResult]: Loop: 1416#L518-1 assume !false; 1315#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1287#L299 assume !false; 1304#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1407#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1370#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1280#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1281#L266 assume !(0 != eval_~tmp~0); 1297#L314 start_simulation_~kernel_st~0 := 2; 1448#L204-1 start_simulation_~kernel_st~0 := 3; 1449#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1465#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1316#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1317#L334-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1387#L339-3 assume !(0 == ~E_2~0); 1431#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1409#L146-9 assume !(1 == ~m_pc~0); 1329#L146-11 is_master_triggered_~__retres1~0 := 0; 1328#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1330#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1278#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1279#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1291#L165-9 assume !(1 == ~t1_pc~0); 1444#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 1578#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1577#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1576#L403-9 assume !(0 != activate_threads_~tmp___0~0); 1575#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1574#L184-9 assume 1 == ~t2_pc~0; 1571#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1569#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1567#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1565#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1563#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 1560#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1558#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1556#L367-3 assume !(1 == ~E_1~0); 1425#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1426#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1447#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1365#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1276#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 1277#L537 assume !(0 == start_simulation_~tmp~3); 1439#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1549#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1433#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1272#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 1273#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1389#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 1390#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 1463#L550 assume !(0 != start_simulation_~tmp___0~1); 1416#L518-1 [2019-11-15 21:00:37,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:37,884 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 1 times [2019-11-15 21:00:37,884 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:37,884 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604286542] [2019-11-15 21:00:37,884 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,884 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,884 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:37,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:37,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:37,948 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:37,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:37,949 INFO L82 PathProgramCache]: Analyzing trace with hash -2007931839, now seen corresponding path program 1 times [2019-11-15 21:00:37,949 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:37,949 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681177706] [2019-11-15 21:00:37,949 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,949 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:37,950 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:37,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:37,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:37,982 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1681177706] [2019-11-15 21:00:37,982 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:37,982 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:37,982 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48324580] [2019-11-15 21:00:37,983 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:37,983 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:37,983 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:37,984 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:37,984 INFO L87 Difference]: Start difference. First operand 307 states and 457 transitions. cyclomatic complexity: 152 Second operand 3 states. [2019-11-15 21:00:38,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:38,045 INFO L93 Difference]: Finished difference Result 453 states and 669 transitions. [2019-11-15 21:00:38,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:38,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 453 states and 669 transitions. [2019-11-15 21:00:38,050 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 390 [2019-11-15 21:00:38,054 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 453 states to 453 states and 669 transitions. [2019-11-15 21:00:38,055 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 453 [2019-11-15 21:00:38,055 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 453 [2019-11-15 21:00:38,056 INFO L73 IsDeterministic]: Start isDeterministic. Operand 453 states and 669 transitions. [2019-11-15 21:00:38,056 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:38,056 INFO L688 BuchiCegarLoop]: Abstraction has 453 states and 669 transitions. [2019-11-15 21:00:38,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 453 states and 669 transitions. [2019-11-15 21:00:38,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 453 to 451. [2019-11-15 21:00:38,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 451 states. [2019-11-15 21:00:38,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 451 states to 451 states and 667 transitions. [2019-11-15 21:00:38,072 INFO L711 BuchiCegarLoop]: Abstraction has 451 states and 667 transitions. [2019-11-15 21:00:38,072 INFO L591 BuchiCegarLoop]: Abstraction has 451 states and 667 transitions. [2019-11-15 21:00:38,072 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-11-15 21:00:38,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 451 states and 667 transitions. [2019-11-15 21:00:38,076 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 388 [2019-11-15 21:00:38,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:38,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:38,077 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:38,078 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:38,078 INFO L791 eck$LassoCheckResult]: Stem: 2231#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2060#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2061#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2220#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 2221#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2129#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2130#L221-1 assume !(0 == ~M_E~0); 2153#L324-1 assume !(0 == ~T1_E~0); 2070#L329-1 assume !(0 == ~T2_E~0); 2071#L334-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2150#L339-1 assume !(0 == ~E_2~0); 2189#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2213#L146 assume !(1 == ~m_pc~0); 2117#L146-2 is_master_triggered_~__retres1~0 := 0; 2118#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2119#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2114#L395 assume !(0 != activate_threads_~tmp~1); 2062#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2063#L165 assume !(1 == ~t1_pc~0); 2226#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 2227#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2152#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2121#L403 assume !(0 != activate_threads_~tmp___0~0); 2122#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2131#L184 assume !(1 == ~t2_pc~0); 2203#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 2202#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2204#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2166#L411 assume !(0 != activate_threads_~tmp___1~0); 2142#L411-2 assume !(1 == ~M_E~0); 2143#L357-1 assume !(1 == ~T1_E~0); 2064#L362-1 assume !(1 == ~T2_E~0); 2065#L367-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2144#L372-1 assume !(1 == ~E_2~0); 2183#L518-1 [2019-11-15 21:00:38,078 INFO L793 eck$LassoCheckResult]: Loop: 2183#L518-1 assume !false; 2077#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2053#L299 assume !false; 2072#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2176#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2175#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2046#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2047#L266 assume !(0 != eval_~tmp~0); 2067#L314 start_simulation_~kernel_st~0 := 2; 2218#L204-1 start_simulation_~kernel_st~0 := 3; 2219#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2241#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2082#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2083#L334-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2156#L339-3 assume !(0 == ~E_2~0); 2199#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2178#L146-9 assume !(1 == ~m_pc~0); 2096#L146-11 is_master_triggered_~__retres1~0 := 0; 2095#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2097#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2044#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2045#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2057#L165-9 assume !(1 == ~t1_pc~0); 2206#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 2207#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2172#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2120#L403-9 assume !(0 != activate_threads_~tmp___0~0); 2075#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2076#L184-9 assume 1 == ~t2_pc~0; 2186#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2187#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2190#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2124#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2125#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 2136#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2078#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2079#L367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2154#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2194#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2217#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2133#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2042#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 2043#L537 assume !(0 == start_simulation_~tmp~3); 2208#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2215#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2127#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2038#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 2039#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2159#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 2160#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 2238#L550 assume !(0 != start_simulation_~tmp___0~1); 2183#L518-1 [2019-11-15 21:00:38,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:38,079 INFO L82 PathProgramCache]: Analyzing trace with hash 713469919, now seen corresponding path program 1 times [2019-11-15 21:00:38,079 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:38,079 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799198879] [2019-11-15 21:00:38,079 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,079 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,080 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:38,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:38,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:38,117 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1799198879] [2019-11-15 21:00:38,117 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:38,118 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:00:38,118 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [291899701] [2019-11-15 21:00:38,118 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-11-15 21:00:38,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:38,119 INFO L82 PathProgramCache]: Analyzing trace with hash -728068161, now seen corresponding path program 1 times [2019-11-15 21:00:38,119 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:38,119 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738770096] [2019-11-15 21:00:38,119 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,120 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,120 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:38,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:38,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:38,278 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1738770096] [2019-11-15 21:00:38,278 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:38,278 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-15 21:00:38,278 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2056419478] [2019-11-15 21:00:38,279 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:38,279 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:38,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:38,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:38,280 INFO L87 Difference]: Start difference. First operand 451 states and 667 transitions. cyclomatic complexity: 218 Second operand 3 states. [2019-11-15 21:00:38,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:38,323 INFO L93 Difference]: Finished difference Result 307 states and 445 transitions. [2019-11-15 21:00:38,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:38,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 307 states and 445 transitions. [2019-11-15 21:00:38,327 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 269 [2019-11-15 21:00:38,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 307 states to 307 states and 445 transitions. [2019-11-15 21:00:38,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 307 [2019-11-15 21:00:38,331 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 307 [2019-11-15 21:00:38,331 INFO L73 IsDeterministic]: Start isDeterministic. Operand 307 states and 445 transitions. [2019-11-15 21:00:38,332 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:38,332 INFO L688 BuchiCegarLoop]: Abstraction has 307 states and 445 transitions. [2019-11-15 21:00:38,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307 states and 445 transitions. [2019-11-15 21:00:38,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307 to 307. [2019-11-15 21:00:38,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 307 states. [2019-11-15 21:00:38,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 445 transitions. [2019-11-15 21:00:38,341 INFO L711 BuchiCegarLoop]: Abstraction has 307 states and 445 transitions. [2019-11-15 21:00:38,341 INFO L591 BuchiCegarLoop]: Abstraction has 307 states and 445 transitions. [2019-11-15 21:00:38,341 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-11-15 21:00:38,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307 states and 445 transitions. [2019-11-15 21:00:38,344 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 269 [2019-11-15 21:00:38,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:38,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:38,345 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:38,345 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:38,346 INFO L791 eck$LassoCheckResult]: Stem: 3002#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2833#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2834#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2990#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 2991#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2902#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2903#L221-1 assume !(0 == ~M_E~0); 2926#L324-1 assume !(0 == ~T1_E~0); 2849#L329-1 assume !(0 == ~T2_E~0); 2850#L334-1 assume !(0 == ~E_1~0); 2924#L339-1 assume !(0 == ~E_2~0); 2960#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2983#L146 assume !(1 == ~m_pc~0); 2890#L146-2 is_master_triggered_~__retres1~0 := 0; 2891#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2892#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2888#L395 assume !(0 != activate_threads_~tmp~1); 2837#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2838#L165 assume !(1 == ~t1_pc~0); 2997#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 2998#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2925#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2895#L403 assume !(0 != activate_threads_~tmp___0~0); 2896#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2904#L184 assume !(1 == ~t2_pc~0); 2973#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 2972#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2974#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2938#L411 assume !(0 != activate_threads_~tmp___1~0); 2916#L411-2 assume !(1 == ~M_E~0); 2917#L357-1 assume !(1 == ~T1_E~0); 2839#L362-1 assume !(1 == ~T2_E~0); 2840#L367-1 assume !(1 == ~E_1~0); 2920#L372-1 assume !(1 == ~E_2~0); 2955#L518-1 [2019-11-15 21:00:38,346 INFO L793 eck$LassoCheckResult]: Loop: 2955#L518-1 assume !false; 2855#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2826#L299 assume !false; 2844#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2946#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2945#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2819#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2820#L266 assume !(0 != eval_~tmp~0); 2836#L314 start_simulation_~kernel_st~0 := 2; 2987#L204-1 start_simulation_~kernel_st~0 := 3; 2988#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3006#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2856#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2857#L334-3 assume !(0 == ~E_1~0); 2928#L339-3 assume !(0 == ~E_2~0); 2969#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2948#L146-9 assume 1 == ~m_pc~0; 2868#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2869#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2871#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2817#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2818#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2830#L165-9 assume !(1 == ~t1_pc~0); 2982#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 3057#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3056#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3055#L403-9 assume !(0 != activate_threads_~tmp___0~0); 3054#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2996#L184-9 assume 1 == ~t2_pc~0; 2956#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2957#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2959#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2897#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2898#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 3048#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3047#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3046#L367-3 assume !(1 == ~E_1~0); 3045#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3044#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3043#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3040#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3039#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 2977#L537 assume !(0 == start_simulation_~tmp~3); 2978#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2980#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2900#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2811#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 2812#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2930#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 2931#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 3005#L550 assume !(0 != start_simulation_~tmp___0~1); 2955#L518-1 [2019-11-15 21:00:38,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:38,347 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 2 times [2019-11-15 21:00:38,347 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:38,347 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733039542] [2019-11-15 21:00:38,347 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,347 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,348 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:38,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:38,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:38,367 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:38,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:38,368 INFO L82 PathProgramCache]: Analyzing trace with hash 206227070, now seen corresponding path program 1 times [2019-11-15 21:00:38,368 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:38,368 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445428273] [2019-11-15 21:00:38,368 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,369 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,369 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:38,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:38,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:38,479 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445428273] [2019-11-15 21:00:38,479 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:38,479 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-15 21:00:38,480 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [126790046] [2019-11-15 21:00:38,480 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:38,480 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:38,481 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-11-15 21:00:38,481 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-11-15 21:00:38,481 INFO L87 Difference]: Start difference. First operand 307 states and 445 transitions. cyclomatic complexity: 140 Second operand 11 states. [2019-11-15 21:00:38,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:38,675 INFO L93 Difference]: Finished difference Result 511 states and 726 transitions. [2019-11-15 21:00:38,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-15 21:00:38,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 511 states and 726 transitions. [2019-11-15 21:00:38,681 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 471 [2019-11-15 21:00:38,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 511 states to 511 states and 726 transitions. [2019-11-15 21:00:38,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 511 [2019-11-15 21:00:38,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 511 [2019-11-15 21:00:38,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 511 states and 726 transitions. [2019-11-15 21:00:38,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:38,688 INFO L688 BuchiCegarLoop]: Abstraction has 511 states and 726 transitions. [2019-11-15 21:00:38,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 511 states and 726 transitions. [2019-11-15 21:00:38,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 511 to 313. [2019-11-15 21:00:38,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 313 states. [2019-11-15 21:00:38,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 313 states to 313 states and 451 transitions. [2019-11-15 21:00:38,698 INFO L711 BuchiCegarLoop]: Abstraction has 313 states and 451 transitions. [2019-11-15 21:00:38,698 INFO L591 BuchiCegarLoop]: Abstraction has 313 states and 451 transitions. [2019-11-15 21:00:38,698 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-11-15 21:00:38,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 313 states and 451 transitions. [2019-11-15 21:00:38,701 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 275 [2019-11-15 21:00:38,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:38,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:38,702 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:38,702 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:38,703 INFO L791 eck$LassoCheckResult]: Stem: 3850#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3674#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3675#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3832#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 3833#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3742#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3743#L221-1 assume !(0 == ~M_E~0); 3766#L324-1 assume !(0 == ~T1_E~0); 3684#L329-1 assume !(0 == ~T2_E~0); 3685#L334-1 assume !(0 == ~E_1~0); 3764#L339-1 assume !(0 == ~E_2~0); 3799#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3825#L146 assume !(1 == ~m_pc~0); 3729#L146-2 is_master_triggered_~__retres1~0 := 0; 3730#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3731#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3726#L395 assume !(0 != activate_threads_~tmp~1); 3676#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3677#L165 assume !(1 == ~t1_pc~0); 3843#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 3844#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3765#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3734#L403 assume !(0 != activate_threads_~tmp___0~0); 3735#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3744#L184 assume !(1 == ~t2_pc~0); 3815#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 3814#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3816#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3777#L411 assume !(0 != activate_threads_~tmp___1~0); 3756#L411-2 assume !(1 == ~M_E~0); 3757#L357-1 assume !(1 == ~T1_E~0); 3678#L362-1 assume !(1 == ~T2_E~0); 3679#L367-1 assume !(1 == ~E_1~0); 3758#L372-1 assume !(1 == ~E_2~0); 3793#L518-1 [2019-11-15 21:00:38,703 INFO L793 eck$LassoCheckResult]: Loop: 3793#L518-1 assume !false; 3691#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 3666#L299 assume !false; 3686#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3786#L234 assume !(0 == ~m_st~0); 3849#L238 assume !(0 == ~t1_st~0); 3887#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 3886#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3884#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3873#L266 assume !(0 != eval_~tmp~0); 3874#L314 start_simulation_~kernel_st~0 := 2; 3881#L204-1 start_simulation_~kernel_st~0 := 3; 3880#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3879#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3878#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3877#L334-3 assume !(0 == ~E_1~0); 3876#L339-3 assume !(0 == ~E_2~0); 3875#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3872#L146-9 assume !(1 == ~m_pc~0); 3870#L146-11 is_master_triggered_~__retres1~0 := 0; 3869#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3868#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3867#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3670#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3671#L165-9 assume !(1 == ~t1_pc~0); 3824#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 3853#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3854#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3732#L403-9 assume !(0 != activate_threads_~tmp___0~0); 3733#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3840#L184-9 assume 1 == ~t2_pc~0; 3841#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3857#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3858#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3737#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3738#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 3863#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3864#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3767#L367-3 assume !(1 == ~E_1~0); 3768#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3846#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3829#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3746#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3655#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 3656#L537 assume !(0 == start_simulation_~tmp~3); 3819#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3827#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3740#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3651#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 3652#L492 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3771#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 3772#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 3860#L550 assume !(0 != start_simulation_~tmp___0~1); 3793#L518-1 [2019-11-15 21:00:38,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:38,704 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 3 times [2019-11-15 21:00:38,704 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:38,704 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764359979] [2019-11-15 21:00:38,705 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,705 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,705 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:38,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:38,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:38,722 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:38,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:38,722 INFO L82 PathProgramCache]: Analyzing trace with hash 805723206, now seen corresponding path program 1 times [2019-11-15 21:00:38,723 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:38,723 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084800615] [2019-11-15 21:00:38,723 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,723 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:38,724 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:38,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:38,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:38,794 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2084800615] [2019-11-15 21:00:38,794 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:38,794 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-11-15 21:00:38,795 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [347397952] [2019-11-15 21:00:38,795 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:38,795 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:38,795 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-15 21:00:38,795 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2019-11-15 21:00:38,796 INFO L87 Difference]: Start difference. First operand 313 states and 451 transitions. cyclomatic complexity: 140 Second operand 8 states. [2019-11-15 21:00:38,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:38,967 INFO L93 Difference]: Finished difference Result 912 states and 1302 transitions. [2019-11-15 21:00:38,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-15 21:00:38,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 912 states and 1302 transitions. [2019-11-15 21:00:38,977 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 868 [2019-11-15 21:00:38,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 912 states to 912 states and 1302 transitions. [2019-11-15 21:00:38,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 912 [2019-11-15 21:00:38,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 912 [2019-11-15 21:00:38,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 912 states and 1302 transitions. [2019-11-15 21:00:38,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:38,989 INFO L688 BuchiCegarLoop]: Abstraction has 912 states and 1302 transitions. [2019-11-15 21:00:38,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 912 states and 1302 transitions. [2019-11-15 21:00:39,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 912 to 319. [2019-11-15 21:00:39,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 319 states. [2019-11-15 21:00:39,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319 states to 319 states and 457 transitions. [2019-11-15 21:00:39,002 INFO L711 BuchiCegarLoop]: Abstraction has 319 states and 457 transitions. [2019-11-15 21:00:39,002 INFO L591 BuchiCegarLoop]: Abstraction has 319 states and 457 transitions. [2019-11-15 21:00:39,003 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-11-15 21:00:39,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 319 states and 457 transitions. [2019-11-15 21:00:39,005 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 281 [2019-11-15 21:00:39,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:39,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:39,007 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:39,007 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:39,007 INFO L791 eck$LassoCheckResult]: Stem: 5099#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4918#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4919#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5081#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 5082#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4986#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4987#L221-1 assume !(0 == ~M_E~0); 5011#L324-1 assume !(0 == ~T1_E~0); 4932#L329-1 assume !(0 == ~T2_E~0); 4933#L334-1 assume !(0 == ~E_1~0); 5009#L339-1 assume !(0 == ~E_2~0); 5047#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5073#L146 assume !(1 == ~m_pc~0); 4973#L146-2 is_master_triggered_~__retres1~0 := 0; 4974#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4975#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4971#L395 assume !(0 != activate_threads_~tmp~1); 4921#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4922#L165 assume !(1 == ~t1_pc~0); 5090#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 5091#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5010#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4979#L403 assume !(0 != activate_threads_~tmp___0~0); 4980#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4988#L184 assume !(1 == ~t2_pc~0); 5062#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 5061#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5063#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5025#L411 assume !(0 != activate_threads_~tmp___1~0); 5001#L411-2 assume !(1 == ~M_E~0); 5002#L357-1 assume !(1 == ~T1_E~0); 4923#L362-1 assume !(1 == ~T2_E~0); 4924#L367-1 assume !(1 == ~E_1~0); 5005#L372-1 assume !(1 == ~E_2~0); 5042#L518-1 [2019-11-15 21:00:39,008 INFO L793 eck$LassoCheckResult]: Loop: 5042#L518-1 assume !false; 4936#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4911#L299 assume !false; 4931#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5033#L234 assume !(0 == ~m_st~0); 5132#L238 assume !(0 == ~t1_st~0); 5092#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 5093#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5143#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5142#L266 assume !(0 != eval_~tmp~0); 5084#L314 start_simulation_~kernel_st~0 := 2; 5078#L204-1 start_simulation_~kernel_st~0 := 3; 5079#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5108#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4940#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4941#L334-3 assume !(0 == ~E_1~0); 5122#L339-3 assume !(0 == ~E_2~0); 5121#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5120#L146-9 assume !(1 == ~m_pc~0); 5118#L146-11 is_master_triggered_~__retres1~0 := 0; 5117#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4954#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4902#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4903#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4915#L165-9 assume !(1 == ~t1_pc~0); 5066#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 5067#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5028#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5029#L403-9 assume !(0 != activate_threads_~tmp___0~0); 4929#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4930#L184-9 assume 1 == ~t2_pc~0; 5043#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5044#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5046#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4981#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4982#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 5109#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5110#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5012#L367-3 assume !(1 == ~E_1~0); 5013#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5051#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5174#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5171#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5170#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 5068#L537 assume !(0 == start_simulation_~tmp~3); 5069#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5071#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5138#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5139#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 5157#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5017#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 5018#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 5106#L550 assume !(0 != start_simulation_~tmp___0~1); 5042#L518-1 [2019-11-15 21:00:39,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:39,008 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 4 times [2019-11-15 21:00:39,008 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:39,009 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789400351] [2019-11-15 21:00:39,009 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:39,009 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:39,009 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:39,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:39,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:39,043 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:39,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:39,044 INFO L82 PathProgramCache]: Analyzing trace with hash 805663624, now seen corresponding path program 1 times [2019-11-15 21:00:39,044 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:39,044 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138513427] [2019-11-15 21:00:39,045 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:39,045 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:39,045 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:39,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:39,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:39,134 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138513427] [2019-11-15 21:00:39,134 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:39,135 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 21:00:39,135 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792532106] [2019-11-15 21:00:39,137 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:39,137 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:39,138 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 21:00:39,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 21:00:39,139 INFO L87 Difference]: Start difference. First operand 319 states and 457 transitions. cyclomatic complexity: 140 Second operand 5 states. [2019-11-15 21:00:39,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:39,318 INFO L93 Difference]: Finished difference Result 861 states and 1217 transitions. [2019-11-15 21:00:39,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 21:00:39,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 861 states and 1217 transitions. [2019-11-15 21:00:39,328 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 780 [2019-11-15 21:00:39,336 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 861 states to 861 states and 1217 transitions. [2019-11-15 21:00:39,337 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 861 [2019-11-15 21:00:39,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 861 [2019-11-15 21:00:39,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 861 states and 1217 transitions. [2019-11-15 21:00:39,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:39,340 INFO L688 BuchiCegarLoop]: Abstraction has 861 states and 1217 transitions. [2019-11-15 21:00:39,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 861 states and 1217 transitions. [2019-11-15 21:00:39,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 861 to 343. [2019-11-15 21:00:39,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 343 states. [2019-11-15 21:00:39,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 343 states to 343 states and 481 transitions. [2019-11-15 21:00:39,353 INFO L711 BuchiCegarLoop]: Abstraction has 343 states and 481 transitions. [2019-11-15 21:00:39,353 INFO L591 BuchiCegarLoop]: Abstraction has 343 states and 481 transitions. [2019-11-15 21:00:39,353 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-11-15 21:00:39,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 343 states and 481 transitions. [2019-11-15 21:00:39,356 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 302 [2019-11-15 21:00:39,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:39,356 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:39,357 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:39,358 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:39,358 INFO L791 eck$LassoCheckResult]: Stem: 6297#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6111#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6112#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6283#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 6284#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6181#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6182#L221-1 assume !(0 == ~M_E~0); 6204#L324-1 assume !(0 == ~T1_E~0); 6120#L329-1 assume !(0 == ~T2_E~0); 6121#L334-1 assume !(0 == ~E_1~0); 6202#L339-1 assume !(0 == ~E_2~0); 6243#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6275#L146 assume !(1 == ~m_pc~0); 6168#L146-2 is_master_triggered_~__retres1~0 := 0; 6268#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6276#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6165#L395 assume !(0 != activate_threads_~tmp~1); 6113#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6114#L165 assume !(1 == ~t1_pc~0); 6291#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 6292#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6203#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6173#L403 assume !(0 != activate_threads_~tmp___0~0); 6174#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6183#L184 assume !(1 == ~t2_pc~0); 6257#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 6256#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6258#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6215#L411 assume !(0 != activate_threads_~tmp___1~0); 6194#L411-2 assume !(1 == ~M_E~0); 6195#L357-1 assume !(1 == ~T1_E~0); 6115#L362-1 assume !(1 == ~T2_E~0); 6116#L367-1 assume !(1 == ~E_1~0); 6196#L372-1 assume !(1 == ~E_2~0); 6235#L518-1 [2019-11-15 21:00:39,358 INFO L793 eck$LassoCheckResult]: Loop: 6235#L518-1 assume !false; 6127#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6104#L299 assume !false; 6122#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6223#L234 assume !(0 == ~m_st~0); 6189#L238 assume !(0 == ~t1_st~0); 6191#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 6294#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6418#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6417#L266 assume !(0 != eval_~tmp~0); 6288#L314 start_simulation_~kernel_st~0 := 2; 6281#L204-1 start_simulation_~kernel_st~0 := 3; 6282#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6306#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6307#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6206#L334-3 assume !(0 == ~E_1~0); 6207#L339-3 assume !(0 == ~E_2~0); 6253#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6295#L146-9 assume 1 == ~m_pc~0; 6144#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6145#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6263#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6348#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6096#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6108#L165-9 assume !(1 == ~t1_pc~0); 6264#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 6265#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6220#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6172#L403-9 assume !(0 != activate_threads_~tmp___0~0); 6125#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6126#L184-9 assume 1 == ~t2_pc~0; 6240#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6241#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6244#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6176#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6177#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 6188#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6128#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6129#L367-3 assume !(1 == ~E_1~0); 6205#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6248#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6280#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6185#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6093#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 6094#L537 assume !(0 == start_simulation_~tmp~3); 6266#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6271#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6179#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6089#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 6090#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6209#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 6210#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 6304#L550 assume !(0 != start_simulation_~tmp___0~1); 6235#L518-1 [2019-11-15 21:00:39,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:39,359 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 5 times [2019-11-15 21:00:39,359 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:39,359 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960691432] [2019-11-15 21:00:39,360 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:39,360 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:39,360 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:39,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:39,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:39,383 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:39,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:39,386 INFO L82 PathProgramCache]: Analyzing trace with hash -245785465, now seen corresponding path program 1 times [2019-11-15 21:00:39,386 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:39,386 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146208297] [2019-11-15 21:00:39,387 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:39,387 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:39,387 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:39,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:39,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:39,418 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:39,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:39,419 INFO L82 PathProgramCache]: Analyzing trace with hash 1118136617, now seen corresponding path program 1 times [2019-11-15 21:00:39,420 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:39,420 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691884162] [2019-11-15 21:00:39,420 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:39,420 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:39,421 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:39,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:39,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:39,488 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691884162] [2019-11-15 21:00:39,489 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:39,489 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:39,489 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922128363] [2019-11-15 21:00:39,906 WARN L191 SmtUtils]: Spent 410.00 ms on a formula simplification. DAG size of input: 113 DAG size of output: 100 [2019-11-15 21:00:40,023 WARN L191 SmtUtils]: Spent 108.00 ms on a formula simplification that was a NOOP. DAG size: 82 [2019-11-15 21:00:40,036 INFO L210 LassoAnalysis]: Preferences: [2019-11-15 21:00:40,036 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2019-11-15 21:00:40,038 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-11-15 21:00:40,038 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2019-11-15 21:00:40,038 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2019-11-15 21:00:40,038 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:40,038 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2019-11-15 21:00:40,039 INFO L130 ssoRankerPreferences]: Path of dumped script: [2019-11-15 21:00:40,039 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration9_Loop [2019-11-15 21:00:40,039 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2019-11-15 21:00:40,039 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-11-15 21:00:40,059 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,070 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,073 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,079 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,081 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,083 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,085 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,087 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,092 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,096 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,107 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,116 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,119 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,128 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,138 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,140 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,142 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,143 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,146 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,148 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,150 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,151 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,156 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,165 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,168 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,176 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,179 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,185 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,187 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,195 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,198 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,204 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,209 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:40,638 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-11-15 21:00:40,639 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-15 21:00:40,651 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-15 21:00:40,652 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:40,667 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-15 21:00:40,672 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_~__retres1~3=1, ULTIMATE.start_stop_simulation_~tmp~2=1, ULTIMATE.start_exists_runnable_thread_#res=1} Honda state: {ULTIMATE.start_exists_runnable_thread_~__retres1~3=1, ULTIMATE.start_stop_simulation_~tmp~2=1, ULTIMATE.start_exists_runnable_thread_#res=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:40,756 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-15 21:00:40,756 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-15 21:00:40,771 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-15 21:00:40,771 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-15 21:00:40,782 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-15 21:00:40,782 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:40,811 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-15 21:00:40,812 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0=1, ULTIMATE.start_is_transmit2_triggered_#res=1, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=1} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0=1, ULTIMATE.start_is_transmit2_triggered_#res=1, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-15 21:00:40,868 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-15 21:00:40,868 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:40,873 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-15 21:00:40,873 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:40,879 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-15 21:00:40,880 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-15 21:00:40,883 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-15 21:00:40,883 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret5=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret5=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:40,889 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-15 21:00:40,889 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-15 21:00:40,895 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-15 21:00:40,895 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=-8} Honda state: {~t1_pc~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:40,915 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-15 21:00:40,915 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-15 21:00:40,919 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-15 21:00:40,920 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret9=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret9=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:40,937 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-15 21:00:40,937 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-15 21:00:40,942 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-15 21:00:40,942 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_1~0=3} Honda state: {~E_1~0=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-15 21:00:40,958 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-15 21:00:40,958 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-15 21:00:40,985 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-11-15 21:00:40,985 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:41,002 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-11-15 21:00:41,005 INFO L210 LassoAnalysis]: Preferences: [2019-11-15 21:00:41,005 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2019-11-15 21:00:41,005 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-11-15 21:00:41,005 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2019-11-15 21:00:41,006 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2019-11-15 21:00:41,006 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-15 21:00:41,006 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2019-11-15 21:00:41,006 INFO L130 ssoRankerPreferences]: Path of dumped script: [2019-11-15 21:00:41,006 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.02.cil.c_Iteration9_Loop [2019-11-15 21:00:41,006 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2019-11-15 21:00:41,006 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-11-15 21:00:41,010 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,027 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,030 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,035 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,048 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,053 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,059 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,075 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,087 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,090 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,097 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,107 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,112 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,114 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,126 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,128 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,131 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,134 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,140 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,143 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,146 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,152 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,155 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,158 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,160 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,162 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,169 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,173 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,175 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,181 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,183 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,191 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,194 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-15 21:00:41,614 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-11-15 21:00:41,623 INFO L489 LassoAnalysis]: Using template 'affine'. [2019-11-15 21:00:41,624 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-15 21:00:41,627 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-11-15 21:00:41,627 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-15 21:00:41,628 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-15 21:00:41,628 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-15 21:00:41,628 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-15 21:00:41,631 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-15 21:00:41,631 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-15 21:00:41,635 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-11-15 21:00:41,636 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-15 21:00:41,637 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-11-15 21:00:41,637 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-15 21:00:41,637 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-15 21:00:41,637 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-15 21:00:41,638 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-15 21:00:41,639 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-15 21:00:41,639 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-15 21:00:41,645 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-11-15 21:00:41,646 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-15 21:00:41,647 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-11-15 21:00:41,647 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-15 21:00:41,647 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-15 21:00:41,647 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-15 21:00:41,647 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-15 21:00:41,653 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-15 21:00:41,653 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-15 21:00:41,655 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-11-15 21:00:41,655 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-15 21:00:41,657 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-11-15 21:00:41,657 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-15 21:00:41,658 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-15 21:00:41,658 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-15 21:00:41,658 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-15 21:00:41,662 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-15 21:00:41,662 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-15 21:00:41,669 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-11-15 21:00:41,669 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-15 21:00:41,670 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-11-15 21:00:41,670 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-15 21:00:41,670 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-15 21:00:41,670 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-15 21:00:41,671 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-15 21:00:41,671 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-15 21:00:41,671 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-15 21:00:41,673 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-11-15 21:00:41,674 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-15 21:00:41,675 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-11-15 21:00:41,675 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-15 21:00:41,676 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-15 21:00:41,676 INFO L203 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-15 21:00:41,676 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-15 21:00:41,677 INFO L400 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-15 21:00:41,677 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-15 21:00:41,680 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-11-15 21:00:41,681 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-15 21:00:41,682 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-11-15 21:00:41,682 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-15 21:00:41,683 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-15 21:00:41,683 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-15 21:00:41,683 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-15 21:00:41,684 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-15 21:00:41,684 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-15 21:00:41,685 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-11-15 21:00:41,686 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-15 21:00:41,686 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-11-15 21:00:41,687 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-15 21:00:41,687 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-15 21:00:41,687 INFO L203 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-15 21:00:41,688 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-15 21:00:41,694 INFO L400 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-15 21:00:41,694 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-15 21:00:41,695 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-11-15 21:00:41,695 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-15 21:00:41,696 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-11-15 21:00:41,696 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-15 21:00:41,696 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-15 21:00:41,697 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-15 21:00:41,697 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-15 21:00:41,697 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-15 21:00:41,697 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-15 21:00:41,698 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-11-15 21:00:41,699 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-15 21:00:41,700 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-11-15 21:00:41,700 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-15 21:00:41,700 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-15 21:00:41,700 INFO L203 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-15 21:00:41,700 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-15 21:00:41,702 INFO L400 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-15 21:00:41,702 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-15 21:00:41,707 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. [2019-11-15 21:00:41,708 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-15 21:00:41,709 INFO L337 nArgumentSynthesizer]: Template has degree 0. [2019-11-15 21:00:41,709 INFO L350 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-15 21:00:41,709 INFO L202 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-15 21:00:41,709 INFO L203 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-15 21:00:41,709 INFO L204 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-15 21:00:41,710 INFO L400 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-15 21:00:41,710 INFO L401 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-15 21:00:41,713 INFO L419 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-11-15 21:00:41,715 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-11-15 21:00:41,716 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2019-11-15 21:00:41,718 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-11-15 21:00:41,718 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-11-15 21:00:41,718 INFO L510 LassoAnalysis]: Proved termination. [2019-11-15 21:00:41,719 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2019-11-15 21:00:41,721 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-11-15 21:00:41,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:41,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:41,778 INFO L256 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 2 conjunts are in the unsatisfiable core [2019-11-15 21:00:41,785 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 21:00:41,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:41,828 INFO L256 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 4 conjunts are in the unsatisfiable core [2019-11-15 21:00:41,839 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-11-15 21:00:41,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:41,894 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2019-11-15 21:00:41,895 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 343 states and 481 transitions. cyclomatic complexity: 140 Second operand 5 states. [2019-11-15 21:00:42,044 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 343 states and 481 transitions. cyclomatic complexity: 140. Second operand 5 states. Result 1151 states and 1620 transitions. Complement of second has 5 states. [2019-11-15 21:00:42,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-11-15 21:00:42,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2019-11-15 21:00:42,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 450 transitions. [2019-11-15 21:00:42,049 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 450 transitions. Stem has 34 letters. Loop has 53 letters. [2019-11-15 21:00:42,052 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-15 21:00:42,052 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 450 transitions. Stem has 87 letters. Loop has 53 letters. [2019-11-15 21:00:42,054 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-15 21:00:42,054 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 450 transitions. Stem has 34 letters. Loop has 106 letters. [2019-11-15 21:00:42,059 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-15 21:00:42,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1151 states and 1620 transitions. [2019-11-15 21:00:42,076 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 849 [2019-11-15 21:00:42,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1151 states to 1151 states and 1620 transitions. [2019-11-15 21:00:42,089 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 895 [2019-11-15 21:00:42,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 900 [2019-11-15 21:00:42,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1151 states and 1620 transitions. [2019-11-15 21:00:42,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-15 21:00:42,091 INFO L688 BuchiCegarLoop]: Abstraction has 1151 states and 1620 transitions. [2019-11-15 21:00:42,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1151 states and 1620 transitions. [2019-11-15 21:00:42,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1151 to 842. [2019-11-15 21:00:42,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 842 states. [2019-11-15 21:00:42,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 842 states to 842 states and 1185 transitions. [2019-11-15 21:00:42,125 INFO L711 BuchiCegarLoop]: Abstraction has 842 states and 1185 transitions. [2019-11-15 21:00:42,125 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:42,126 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:42,126 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:42,126 INFO L87 Difference]: Start difference. First operand 842 states and 1185 transitions. Second operand 3 states. [2019-11-15 21:00:42,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:42,184 INFO L93 Difference]: Finished difference Result 1384 states and 1899 transitions. [2019-11-15 21:00:42,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:42,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1384 states and 1899 transitions. [2019-11-15 21:00:42,200 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 922 [2019-11-15 21:00:42,215 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1384 states to 1384 states and 1899 transitions. [2019-11-15 21:00:42,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 970 [2019-11-15 21:00:42,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 970 [2019-11-15 21:00:42,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1384 states and 1899 transitions. [2019-11-15 21:00:42,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-15 21:00:42,219 INFO L688 BuchiCegarLoop]: Abstraction has 1384 states and 1899 transitions. [2019-11-15 21:00:42,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1384 states and 1899 transitions. [2019-11-15 21:00:42,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1384 to 1285. [2019-11-15 21:00:42,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1285 states. [2019-11-15 21:00:42,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1285 states to 1285 states and 1773 transitions. [2019-11-15 21:00:42,256 INFO L711 BuchiCegarLoop]: Abstraction has 1285 states and 1773 transitions. [2019-11-15 21:00:42,256 INFO L591 BuchiCegarLoop]: Abstraction has 1285 states and 1773 transitions. [2019-11-15 21:00:42,256 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-11-15 21:00:42,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1285 states and 1773 transitions. [2019-11-15 21:00:42,265 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 856 [2019-11-15 21:00:42,265 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:42,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:42,267 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:42,267 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:42,267 INFO L791 eck$LassoCheckResult]: Stem: 10449#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 10137#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10138#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10422#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 10423#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10250#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10251#L221-1 assume !(0 == ~M_E~0); 10290#L324-1 assume !(0 == ~T1_E~0); 10149#L329-1 assume !(0 == ~T2_E~0); 10150#L334-1 assume !(0 == ~E_1~0); 10288#L339-1 assume !(0 == ~E_2~0); 10356#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10410#L146 assume !(1 == ~m_pc~0); 10230#L146-2 is_master_triggered_~__retres1~0 := 0; 10400#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10232#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 10226#L395 assume !(0 != activate_threads_~tmp~1); 10139#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10140#L165 assume !(1 == ~t1_pc~0); 10435#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 10436#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10289#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10236#L403 assume !(0 != activate_threads_~tmp___0~0); 10237#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10252#L184 assume !(1 == ~t2_pc~0); 10384#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 10383#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10387#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10309#L411 assume !(0 != activate_threads_~tmp___1~0); 10275#L411-2 assume !(1 == ~M_E~0); 10276#L357-1 assume !(1 == ~T1_E~0); 10141#L362-1 assume !(1 == ~T2_E~0); 10142#L367-1 assume !(1 == ~E_1~0); 10277#L372-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10344#L518-1 [2019-11-15 21:00:42,268 INFO L793 eck$LassoCheckResult]: Loop: 10344#L518-1 assume !false; 11007#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 11006#L299 assume !false; 11005#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11004#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10777#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11003#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 11002#L266 assume 0 != eval_~tmp~0; 11001#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 10818#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 10999#L37 assume !(0 == ~m_pc~0); 10996#L40 assume 1 == ~m_pc~0; 10924#L41 assume !false; 10819#L57 ~m_pc~0 := 1;~m_st~0 := 2; 10801#L271 assume !(0 == ~t1_st~0); 10787#L285 assume !(0 == ~t2_st~0); 10782#L299 assume !false; 10780#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10776#L234 assume !(0 == ~m_st~0); 10774#L238 assume !(0 == ~t1_st~0); 10770#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 10768#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10766#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 10762#L266 assume !(0 != eval_~tmp~0); 10760#L314 start_simulation_~kernel_st~0 := 2; 10758#L204-1 start_simulation_~kernel_st~0 := 3; 10755#L324-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10750#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10751#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10293#L334-3 assume !(0 == ~E_1~0); 10294#L339-3 assume !(0 == ~E_2~0); 10378#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10444#L146-9 assume 1 == ~m_pc~0; 10992#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 10991#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10990#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 10989#L395-9 assume !(0 != activate_threads_~tmp~1); 10106#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10911#L165-9 assume !(1 == ~t1_pc~0); 10908#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 10906#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10904#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10902#L403-9 assume !(0 != activate_threads_~tmp___0~0); 10900#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10898#L184-9 assume 1 == ~t2_pc~0; 10894#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10891#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10887#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10884#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10881#L411-11 assume 1 == ~M_E~0;~M_E~0 := 2; 10878#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10875#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10871#L367-3 assume !(1 == ~E_1~0); 10868#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10865#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10861#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10862#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10921#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 10914#L537 assume !(0 == start_simulation_~tmp~3); 10915#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11021#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10840#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11020#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 11019#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11018#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 11017#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 11015#L550 assume !(0 != start_simulation_~tmp___0~1); 10344#L518-1 [2019-11-15 21:00:42,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:42,269 INFO L82 PathProgramCache]: Analyzing trace with hash 854018589, now seen corresponding path program 1 times [2019-11-15 21:00:42,269 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:42,269 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827234827] [2019-11-15 21:00:42,269 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,269 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,270 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:42,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:42,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:42,319 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827234827] [2019-11-15 21:00:42,320 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:42,320 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-15 21:00:42,320 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461085238] [2019-11-15 21:00:42,320 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-11-15 21:00:42,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:42,321 INFO L82 PathProgramCache]: Analyzing trace with hash 1097849957, now seen corresponding path program 1 times [2019-11-15 21:00:42,321 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:42,321 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719294033] [2019-11-15 21:00:42,321 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,321 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,322 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:42,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:42,392 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-15 21:00:42,393 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1719294033] [2019-11-15 21:00:42,393 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:42,393 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-15 21:00:42,394 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1633947402] [2019-11-15 21:00:42,394 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:42,394 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:42,395 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:42,395 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:42,395 INFO L87 Difference]: Start difference. First operand 1285 states and 1773 transitions. cyclomatic complexity: 494 Second operand 3 states. [2019-11-15 21:00:42,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:42,443 INFO L93 Difference]: Finished difference Result 1285 states and 1726 transitions. [2019-11-15 21:00:42,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:42,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1285 states and 1726 transitions. [2019-11-15 21:00:42,456 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 856 [2019-11-15 21:00:42,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1285 states to 1285 states and 1726 transitions. [2019-11-15 21:00:42,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 904 [2019-11-15 21:00:42,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 904 [2019-11-15 21:00:42,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1285 states and 1726 transitions. [2019-11-15 21:00:42,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-15 21:00:42,499 INFO L688 BuchiCegarLoop]: Abstraction has 1285 states and 1726 transitions. [2019-11-15 21:00:42,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1285 states and 1726 transitions. [2019-11-15 21:00:42,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1285 to 1285. [2019-11-15 21:00:42,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1285 states. [2019-11-15 21:00:42,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1285 states to 1285 states and 1726 transitions. [2019-11-15 21:00:42,528 INFO L711 BuchiCegarLoop]: Abstraction has 1285 states and 1726 transitions. [2019-11-15 21:00:42,528 INFO L591 BuchiCegarLoop]: Abstraction has 1285 states and 1726 transitions. [2019-11-15 21:00:42,528 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-11-15 21:00:42,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1285 states and 1726 transitions. [2019-11-15 21:00:42,536 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 856 [2019-11-15 21:00:42,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:42,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:42,538 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:42,538 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:42,538 INFO L791 eck$LassoCheckResult]: Stem: 13025#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 12715#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12716#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12994#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 12995#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12833#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12834#L221-1 assume !(0 == ~M_E~0); 12871#L324-1 assume !(0 == ~T1_E~0); 12741#L329-1 assume !(0 == ~T2_E~0); 12742#L334-1 assume !(0 == ~E_1~0); 12869#L339-1 assume !(0 == ~E_2~0); 12930#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12981#L146 assume !(1 == ~m_pc~0); 12813#L146-2 is_master_triggered_~__retres1~0 := 0; 12972#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13054#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 12811#L395 assume !(0 != activate_threads_~tmp~1); 12721#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12722#L165 assume !(1 == ~t1_pc~0); 13006#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 13009#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12870#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 12821#L403 assume !(0 != activate_threads_~tmp___0~0); 12822#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12835#L184 assume !(1 == ~t2_pc~0); 12955#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 13036#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12956#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12892#L411 assume !(0 != activate_threads_~tmp___1~0); 12856#L411-2 assume !(1 == ~M_E~0); 12857#L357-1 assume !(1 == ~T1_E~0); 12723#L362-1 assume !(1 == ~T2_E~0); 12724#L367-1 assume !(1 == ~E_1~0); 12862#L372-1 assume !(1 == ~E_2~0); 12922#L518-1 assume !false; 12743#L519 [2019-11-15 21:00:42,538 INFO L793 eck$LassoCheckResult]: Loop: 12743#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 12701#L299 assume !false; 12730#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12905#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13748#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13746#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 13744#L266 assume 0 != eval_~tmp~0; 13672#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 12693#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 12694#L37 assume !(0 == ~m_pc~0); 12705#L40 assume 1 == ~m_pc~0; 12706#L41 assume !false; 13016#L57 ~m_pc~0 := 1;~m_st~0 := 2; 13052#L271 assume !(0 == ~t1_st~0); 13735#L285 assume !(0 == ~t2_st~0); 13822#L299 assume !false; 13820#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13819#L234 assume !(0 == ~m_st~0); 12847#L238 assume !(0 == ~t1_st~0); 12849#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 13010#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13957#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 13956#L266 assume !(0 != eval_~tmp~0); 12998#L314 start_simulation_~kernel_st~0 := 2; 12988#L204-1 start_simulation_~kernel_st~0 := 3; 12989#L324-2 assume !(0 == ~M_E~0); 13042#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13795#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13793#L334-3 assume !(0 == ~E_1~0); 13792#L339-3 assume !(0 == ~E_2~0); 13015#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12912#L146-9 assume 1 == ~m_pc~0; 12771#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 12772#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13930#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 13928#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13925#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13923#L165-9 assume !(1 == ~t1_pc~0); 13922#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 13921#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13920#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 13919#L403-9 assume !(0 != activate_threads_~tmp___0~0); 13918#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13917#L184-9 assume !(1 == ~t2_pc~0); 13915#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 13914#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13912#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 13911#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13910#L411-11 assume !(1 == ~M_E~0); 13909#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13908#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13907#L367-3 assume !(1 == ~E_1~0); 13904#L372-3 assume !(1 == ~E_2~0); 13902#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12985#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12903#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12681#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 12682#L537 assume !(0 == start_simulation_~tmp~3); 12969#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12973#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12952#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12673#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 12674#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12880#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 12881#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 13039#L550 assume !(0 != start_simulation_~tmp___0~1); 12950#L518-1 assume !false; 12743#L519 [2019-11-15 21:00:42,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:42,543 INFO L82 PathProgramCache]: Analyzing trace with hash 704772710, now seen corresponding path program 1 times [2019-11-15 21:00:42,544 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:42,544 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096977546] [2019-11-15 21:00:42,544 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,544 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,544 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:42,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:42,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:42,566 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:42,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:42,566 INFO L82 PathProgramCache]: Analyzing trace with hash -1284606298, now seen corresponding path program 1 times [2019-11-15 21:00:42,567 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:42,567 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354267653] [2019-11-15 21:00:42,567 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,567 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,567 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:42,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:42,626 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-15 21:00:42,626 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354267653] [2019-11-15 21:00:42,627 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:42,627 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-15 21:00:42,627 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1971834867] [2019-11-15 21:00:42,627 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:42,627 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:42,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-15 21:00:42,631 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-15 21:00:42,633 INFO L87 Difference]: Start difference. First operand 1285 states and 1726 transitions. cyclomatic complexity: 447 Second operand 5 states. [2019-11-15 21:00:42,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:42,731 INFO L93 Difference]: Finished difference Result 1905 states and 2543 transitions. [2019-11-15 21:00:42,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-15 21:00:42,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1905 states and 2543 transitions. [2019-11-15 21:00:42,746 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1268 [2019-11-15 21:00:42,761 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1905 states to 1905 states and 2543 transitions. [2019-11-15 21:00:42,761 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1316 [2019-11-15 21:00:42,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1316 [2019-11-15 21:00:42,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1905 states and 2543 transitions. [2019-11-15 21:00:42,764 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-15 21:00:42,765 INFO L688 BuchiCegarLoop]: Abstraction has 1905 states and 2543 transitions. [2019-11-15 21:00:42,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1905 states and 2543 transitions. [2019-11-15 21:00:42,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1905 to 1303. [2019-11-15 21:00:42,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1303 states. [2019-11-15 21:00:42,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1303 states to 1303 states and 1721 transitions. [2019-11-15 21:00:42,794 INFO L711 BuchiCegarLoop]: Abstraction has 1303 states and 1721 transitions. [2019-11-15 21:00:42,794 INFO L591 BuchiCegarLoop]: Abstraction has 1303 states and 1721 transitions. [2019-11-15 21:00:42,794 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-11-15 21:00:42,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1303 states and 1721 transitions. [2019-11-15 21:00:42,801 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 868 [2019-11-15 21:00:42,802 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:42,802 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:42,803 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:42,803 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:42,803 INFO L791 eck$LassoCheckResult]: Stem: 16248#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 15920#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 15921#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16209#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 16210#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16033#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16034#L221-1 assume !(0 == ~M_E~0); 16074#L324-1 assume !(0 == ~T1_E~0); 15932#L329-1 assume !(0 == ~T2_E~0); 15933#L334-1 assume !(0 == ~E_1~0); 16072#L339-1 assume !(0 == ~E_2~0); 16136#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16193#L146 assume !(1 == ~m_pc~0); 16013#L146-2 is_master_triggered_~__retres1~0 := 0; 16183#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16194#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 16008#L395 assume !(0 != activate_threads_~tmp~1); 15922#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15923#L165 assume !(1 == ~t1_pc~0); 16219#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 16220#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16073#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 16019#L403 assume !(0 != activate_threads_~tmp___0~0); 16020#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16035#L184 assume !(1 == ~t2_pc~0); 16165#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 16267#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16169#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 16093#L411 assume !(0 != activate_threads_~tmp___1~0); 16058#L411-2 assume !(1 == ~M_E~0); 16059#L357-1 assume !(1 == ~T1_E~0); 15924#L362-1 assume !(1 == ~T2_E~0); 15925#L367-1 assume !(1 == ~E_1~0); 16060#L372-1 assume !(1 == ~E_2~0); 16128#L518-1 assume !false; 16386#L519 [2019-11-15 21:00:42,804 INFO L793 eck$LassoCheckResult]: Loop: 16386#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 16737#L299 assume !false; 16735#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16733#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 16640#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16729#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 16727#L266 assume 0 != eval_~tmp~0; 16725#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 16671#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 16721#L37 assume !(0 == ~m_pc~0); 16694#L40 assume 1 == ~m_pc~0; 16692#L41 assume !false; 16672#L57 ~m_pc~0 := 1;~m_st~0 := 2; 16669#L271 assume !(0 == ~t1_st~0); 16653#L285 assume !(0 == ~t2_st~0); 16644#L299 assume !false; 16642#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16639#L234 assume !(0 == ~m_st~0); 16636#L238 assume !(0 == ~t1_st~0); 16633#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 16630#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16628#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 16625#L266 assume !(0 != eval_~tmp~0); 16622#L314 start_simulation_~kernel_st~0 := 2; 16620#L204-1 start_simulation_~kernel_st~0 := 3; 16618#L324-2 assume !(0 == ~M_E~0); 16616#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16614#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16612#L334-3 assume !(0 == ~E_1~0); 16610#L339-3 assume !(0 == ~E_2~0); 16608#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16606#L146-9 assume 1 == ~m_pc~0; 16603#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 16600#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16598#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 16595#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16592#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16590#L165-9 assume !(1 == ~t1_pc~0); 16588#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 16586#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16584#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 16582#L403-9 assume !(0 != activate_threads_~tmp___0~0); 16580#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16578#L184-9 assume !(1 == ~t2_pc~0); 16574#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 16572#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16570#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 16568#L411-9 assume !(0 != activate_threads_~tmp___1~0); 16566#L411-11 assume !(1 == ~M_E~0); 16557#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16558#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16814#L367-3 assume !(1 == ~E_1~0); 16812#L372-3 assume !(1 == ~E_2~0); 16541#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16538#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 16519#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16520#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 16795#L537 assume !(0 == start_simulation_~tmp~3); 16793#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16791#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 16745#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16782#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 16780#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16778#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 16761#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 16760#L550 assume !(0 != start_simulation_~tmp___0~1); 16759#L518-1 assume !false; 16386#L519 [2019-11-15 21:00:42,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:42,804 INFO L82 PathProgramCache]: Analyzing trace with hash 704772710, now seen corresponding path program 2 times [2019-11-15 21:00:42,805 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:42,805 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400851779] [2019-11-15 21:00:42,805 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,805 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,805 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:42,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:42,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:42,822 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:42,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:42,825 INFO L82 PathProgramCache]: Analyzing trace with hash -2102254748, now seen corresponding path program 1 times [2019-11-15 21:00:42,825 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:42,825 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267724685] [2019-11-15 21:00:42,825 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,826 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:42,826 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:42,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:42,857 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-15 21:00:42,857 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267724685] [2019-11-15 21:00:42,857 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:42,857 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:42,858 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272008688] [2019-11-15 21:00:42,860 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:42,861 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:42,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:42,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:42,861 INFO L87 Difference]: Start difference. First operand 1303 states and 1721 transitions. cyclomatic complexity: 424 Second operand 3 states. [2019-11-15 21:00:42,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:42,927 INFO L93 Difference]: Finished difference Result 2056 states and 2675 transitions. [2019-11-15 21:00:42,928 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:42,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2056 states and 2675 transitions. [2019-11-15 21:00:42,944 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1244 [2019-11-15 21:00:42,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2056 states to 1964 states and 2561 transitions. [2019-11-15 21:00:42,963 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1335 [2019-11-15 21:00:42,965 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1335 [2019-11-15 21:00:42,965 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1964 states and 2561 transitions. [2019-11-15 21:00:42,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-15 21:00:42,966 INFO L688 BuchiCegarLoop]: Abstraction has 1964 states and 2561 transitions. [2019-11-15 21:00:42,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1964 states and 2561 transitions. [2019-11-15 21:00:42,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1964 to 1956. [2019-11-15 21:00:42,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1956 states. [2019-11-15 21:00:43,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1956 states to 1956 states and 2551 transitions. [2019-11-15 21:00:43,005 INFO L711 BuchiCegarLoop]: Abstraction has 1956 states and 2551 transitions. [2019-11-15 21:00:43,006 INFO L591 BuchiCegarLoop]: Abstraction has 1956 states and 2551 transitions. [2019-11-15 21:00:43,006 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-11-15 21:00:43,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1956 states and 2551 transitions. [2019-11-15 21:00:43,017 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1238 [2019-11-15 21:00:43,017 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:43,017 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:43,018 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,019 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,019 INFO L791 eck$LassoCheckResult]: Stem: 19593#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 19284#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 19285#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19563#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 19564#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19392#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19393#L221-1 assume 0 == ~M_E~0;~M_E~0 := 1; 19430#L324-1 assume !(0 == ~T1_E~0); 19297#L329-1 assume !(0 == ~T2_E~0); 19298#L334-1 assume !(0 == ~E_1~0); 19428#L339-1 assume !(0 == ~E_2~0); 19648#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19645#L146 assume !(1 == ~m_pc~0); 19646#L146-2 is_master_triggered_~__retres1~0 := 0; 19647#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19644#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 19369#L395 assume !(0 != activate_threads_~tmp~1); 19286#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19287#L165 assume !(1 == ~t1_pc~0); 19575#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 19633#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19632#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 19631#L403 assume !(0 != activate_threads_~tmp___0~0); 19630#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19612#L184 assume !(1 == ~t2_pc~0); 19518#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 19613#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19520#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 19450#L411 assume !(0 != activate_threads_~tmp___1~0); 19415#L411-2 assume 1 == ~M_E~0;~M_E~0 := 2; 19416#L357-1 assume !(1 == ~T1_E~0); 19288#L362-1 assume !(1 == ~T2_E~0); 19289#L367-1 assume !(1 == ~E_1~0); 19417#L372-1 assume !(1 == ~E_2~0); 19484#L518-1 assume !false; 20095#L519 [2019-11-15 21:00:43,019 INFO L793 eck$LassoCheckResult]: Loop: 20095#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 20916#L299 assume !false; 20914#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 20912#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 20876#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 20909#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 20907#L266 assume 0 != eval_~tmp~0; 20905#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 20889#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 20900#L37 assume !(0 == ~m_pc~0); 20893#L40 assume 1 == ~m_pc~0; 20891#L41 assume !false; 20890#L57 ~m_pc~0 := 1;~m_st~0 := 2; 20887#L271 assume !(0 == ~t1_st~0); 20882#L285 assume !(0 == ~t2_st~0); 20878#L299 assume !false; 20877#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 20875#L234 assume !(0 == ~m_st~0); 20874#L238 assume !(0 == ~t1_st~0); 20872#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 20871#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 20870#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 20868#L266 assume !(0 != eval_~tmp~0); 20867#L314 start_simulation_~kernel_st~0 := 2; 20865#L204-1 start_simulation_~kernel_st~0 := 3; 20840#L324-2 assume !(0 == ~M_E~0); 20839#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20838#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20837#L334-3 assume !(0 == ~E_1~0); 20836#L339-3 assume !(0 == ~E_2~0); 20835#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20834#L146-9 assume !(1 == ~m_pc~0); 20831#L146-11 is_master_triggered_~__retres1~0 := 0; 20830#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20829#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 20828#L395-9 assume !(0 != activate_threads_~tmp~1); 20826#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19545#L165-9 assume !(1 == ~t1_pc~0); 19546#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 20866#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20864#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 20863#L403-9 assume !(0 != activate_threads_~tmp___0~0); 20862#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20861#L184-9 assume !(1 == ~t2_pc~0); 20859#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 20858#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20856#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 20853#L411-9 assume !(0 != activate_threads_~tmp___1~0); 19403#L411-11 assume !(1 == ~M_E~0); 19404#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19618#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19432#L367-3 assume !(1 == ~E_1~0); 19433#L372-3 assume !(1 == ~E_2~0); 19504#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 19582#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 19555#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 20857#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 20854#L537 assume !(0 == start_simulation_~tmp~3); 20855#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 20942#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 20940#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 20938#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 20937#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 20936#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 20935#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 20934#L550 assume !(0 != start_simulation_~tmp___0~1); 20933#L518-1 assume !false; 20095#L519 [2019-11-15 21:00:43,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,020 INFO L82 PathProgramCache]: Analyzing trace with hash -738688986, now seen corresponding path program 1 times [2019-11-15 21:00:43,020 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,020 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296909336] [2019-11-15 21:00:43,021 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,021 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,021 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:43,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:43,039 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296909336] [2019-11-15 21:00:43,039 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:43,040 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:00:43,040 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271217743] [2019-11-15 21:00:43,040 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-11-15 21:00:43,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,040 INFO L82 PathProgramCache]: Analyzing trace with hash 702655553, now seen corresponding path program 1 times [2019-11-15 21:00:43,041 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,041 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143094710] [2019-11-15 21:00:43,041 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,041 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,041 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:43,074 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:43,074 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143094710] [2019-11-15 21:00:43,074 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:43,075 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:43,075 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [470955238] [2019-11-15 21:00:43,076 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:43,076 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:43,077 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:43,078 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:43,078 INFO L87 Difference]: Start difference. First operand 1956 states and 2551 transitions. cyclomatic complexity: 603 Second operand 3 states. [2019-11-15 21:00:43,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:43,115 INFO L93 Difference]: Finished difference Result 1117 states and 1430 transitions. [2019-11-15 21:00:43,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:43,116 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1117 states and 1430 transitions. [2019-11-15 21:00:43,122 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 750 [2019-11-15 21:00:43,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1117 states to 795 states and 1017 transitions. [2019-11-15 21:00:43,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 795 [2019-11-15 21:00:43,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 795 [2019-11-15 21:00:43,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 795 states and 1017 transitions. [2019-11-15 21:00:43,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:43,132 INFO L688 BuchiCegarLoop]: Abstraction has 795 states and 1017 transitions. [2019-11-15 21:00:43,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 795 states and 1017 transitions. [2019-11-15 21:00:43,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 795 to 472. [2019-11-15 21:00:43,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2019-11-15 21:00:43,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 600 transitions. [2019-11-15 21:00:43,143 INFO L711 BuchiCegarLoop]: Abstraction has 472 states and 600 transitions. [2019-11-15 21:00:43,143 INFO L591 BuchiCegarLoop]: Abstraction has 472 states and 600 transitions. [2019-11-15 21:00:43,143 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-11-15 21:00:43,144 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 472 states and 600 transitions. [2019-11-15 21:00:43,145 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 432 [2019-11-15 21:00:43,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:43,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:43,147 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,147 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,147 INFO L791 eck$LassoCheckResult]: Stem: 22522#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 22345#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 22346#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 22502#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 22503#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22409#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22410#L221-1 assume !(0 == ~M_E~0); 22434#L324-1 assume !(0 == ~T1_E~0); 22354#L329-1 assume !(0 == ~T2_E~0); 22355#L334-1 assume !(0 == ~E_1~0); 22432#L339-1 assume !(0 == ~E_2~0); 22470#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22496#L146 assume !(1 == ~m_pc~0); 22398#L146-2 is_master_triggered_~__retres1~0 := 0; 22490#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22399#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 22395#L395 assume !(0 != activate_threads_~tmp~1); 22347#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22348#L165 assume !(1 == ~t1_pc~0); 22512#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 22513#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22433#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 22401#L403 assume !(0 != activate_threads_~tmp___0~0); 22402#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22411#L184 assume !(1 == ~t2_pc~0); 22482#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 22534#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22484#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 22446#L411 assume !(0 != activate_threads_~tmp___1~0); 22424#L411-2 assume !(1 == ~M_E~0); 22425#L357-1 assume !(1 == ~T1_E~0); 22349#L362-1 assume !(1 == ~T2_E~0); 22350#L367-1 assume !(1 == ~E_1~0); 22426#L372-1 assume !(1 == ~E_2~0); 22465#L518-1 [2019-11-15 21:00:43,147 INFO L793 eck$LassoCheckResult]: Loop: 22465#L518-1 assume !false; 22361#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 22337#L299 assume !false; 22356#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22457#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22676#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22672#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 22601#L266 assume 0 != eval_~tmp~0; 22600#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 22599#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 22596#L37 assume !(0 == ~m_pc~0); 22597#L40 assume 1 == ~m_pc~0; 22436#L41 assume !false; 22542#L57 ~m_pc~0 := 1;~m_st~0 := 2; 22543#L271 assume !(0 == ~t1_st~0); 22637#L285 assume !(0 == ~t2_st~0); 22777#L299 assume !false; 22776#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22775#L234 assume !(0 == ~m_st~0); 22418#L238 assume !(0 == ~t1_st~0); 22420#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 22516#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22609#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 22606#L266 assume !(0 != eval_~tmp~0); 22603#L314 start_simulation_~kernel_st~0 := 2; 22602#L204-1 start_simulation_~kernel_st~0 := 3; 22598#L324-2 assume !(0 == ~M_E~0); 22595#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22593#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22591#L334-3 assume !(0 == ~E_1~0); 22590#L339-3 assume !(0 == ~E_2~0); 22582#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22575#L146-9 assume !(1 == ~m_pc~0); 22569#L146-11 is_master_triggered_~__retres1~0 := 0; 22563#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22558#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 22552#L395-9 assume !(0 != activate_threads_~tmp~1); 22341#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22342#L165-9 assume !(1 == ~t1_pc~0); 22495#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 22729#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22728#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 22727#L403-9 assume !(0 != activate_threads_~tmp___0~0); 22726#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22725#L184-9 assume !(1 == ~t2_pc~0); 22723#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 22721#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22719#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 22718#L411-9 assume !(0 != activate_threads_~tmp___1~0); 22416#L411-11 assume !(1 == ~M_E~0); 22417#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22362#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22363#L367-3 assume !(1 == ~E_1~0); 22435#L372-3 assume !(1 == ~E_2~0); 22476#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22499#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22455#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22326#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 22327#L537 assume !(0 == start_simulation_~tmp~3); 22488#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22492#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22483#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22322#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 22323#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22439#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 22440#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 22535#L550 assume !(0 != start_simulation_~tmp___0~1); 22465#L518-1 [2019-11-15 21:00:43,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,149 INFO L82 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 6 times [2019-11-15 21:00:43,149 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,149 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589403511] [2019-11-15 21:00:43,149 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,149 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,150 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,173 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:43,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,174 INFO L82 PathProgramCache]: Analyzing trace with hash -1341279001, now seen corresponding path program 2 times [2019-11-15 21:00:43,174 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,174 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335749535] [2019-11-15 21:00:43,174 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,174 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,175 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:43,209 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:43,209 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335749535] [2019-11-15 21:00:43,209 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:43,209 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:43,209 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1091212680] [2019-11-15 21:00:43,210 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:43,210 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:43,210 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:43,210 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:43,210 INFO L87 Difference]: Start difference. First operand 472 states and 600 transitions. cyclomatic complexity: 130 Second operand 3 states. [2019-11-15 21:00:43,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:43,236 INFO L93 Difference]: Finished difference Result 587 states and 737 transitions. [2019-11-15 21:00:43,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:43,236 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 587 states and 737 transitions. [2019-11-15 21:00:43,239 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 431 [2019-11-15 21:00:43,243 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 587 states to 587 states and 737 transitions. [2019-11-15 21:00:43,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 587 [2019-11-15 21:00:43,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 587 [2019-11-15 21:00:43,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 587 states and 737 transitions. [2019-11-15 21:00:43,245 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:43,245 INFO L688 BuchiCegarLoop]: Abstraction has 587 states and 737 transitions. [2019-11-15 21:00:43,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 587 states and 737 transitions. [2019-11-15 21:00:43,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 587 to 546. [2019-11-15 21:00:43,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 546 states. [2019-11-15 21:00:43,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 691 transitions. [2019-11-15 21:00:43,255 INFO L711 BuchiCegarLoop]: Abstraction has 546 states and 691 transitions. [2019-11-15 21:00:43,255 INFO L591 BuchiCegarLoop]: Abstraction has 546 states and 691 transitions. [2019-11-15 21:00:43,255 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-11-15 21:00:43,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 691 transitions. [2019-11-15 21:00:43,257 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 431 [2019-11-15 21:00:43,257 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:43,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:43,258 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,258 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,258 INFO L791 eck$LassoCheckResult]: Stem: 23594#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 23409#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 23410#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 23572#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 23573#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23475#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23476#L221-1 assume !(0 == ~M_E~0); 23499#L324-1 assume !(0 == ~T1_E~0); 23419#L329-1 assume !(0 == ~T2_E~0); 23420#L334-1 assume !(0 == ~E_1~0); 23497#L339-1 assume !(0 == ~E_2~0); 23535#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23564#L146 assume 1 == ~m_pc~0; 23462#L147 assume !(1 == ~M_E~0); 23463#L146-2 is_master_triggered_~__retres1~0 := 0; 23557#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23464#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 23460#L395 assume !(0 != activate_threads_~tmp~1); 23411#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23412#L165 assume !(1 == ~t1_pc~0); 23583#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 23584#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23498#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 23467#L403 assume !(0 != activate_threads_~tmp___0~0); 23468#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23844#L184 assume !(1 == ~t2_pc~0); 23843#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 23842#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23841#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 23840#L411 assume !(0 != activate_threads_~tmp___1~0); 23839#L411-2 assume !(1 == ~M_E~0); 23837#L357-1 assume !(1 == ~T1_E~0); 23836#L362-1 assume !(1 == ~T2_E~0); 23835#L367-1 assume !(1 == ~E_1~0); 23827#L372-1 assume !(1 == ~E_2~0); 23826#L518-1 [2019-11-15 21:00:43,259 INFO L793 eck$LassoCheckResult]: Loop: 23826#L518-1 assume !false; 23818#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 23816#L299 assume !false; 23814#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 23810#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 23742#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 23807#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 23805#L266 assume 0 != eval_~tmp~0; 23802#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 23755#L274 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 23439#L37 assume !(0 == ~m_pc~0); 23440#L40 assume 1 == ~m_pc~0; 23768#L41 assume !false; 23610#L57 ~m_pc~0 := 1;~m_st~0 := 2; 23611#L271 assume !(0 == ~t1_st~0); 23748#L285 assume !(0 == ~t2_st~0); 23744#L299 assume !false; 23743#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 23741#L234 assume !(0 == ~m_st~0); 23484#L238 assume !(0 == ~t1_st~0); 23486#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 23635#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 23633#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 23629#L266 assume !(0 != eval_~tmp~0); 23577#L314 start_simulation_~kernel_st~0 := 2; 23570#L204-1 start_simulation_~kernel_st~0 := 3; 23571#L324-2 assume !(0 == ~M_E~0); 23621#L324-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23620#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23619#L334-3 assume !(0 == ~E_1~0); 23618#L339-3 assume !(0 == ~E_2~0); 23617#L344-3 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23616#L146-9 assume 1 == ~m_pc~0; 23443#L147-3 assume !(1 == ~M_E~0); 23444#L146-11 is_master_triggered_~__retres1~0 := 0; 23522#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23553#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 23393#L395-9 assume !(0 != activate_threads_~tmp~1); 23394#L395-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23405#L165-9 assume !(1 == ~t1_pc~0); 23563#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 23596#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23514#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 23465#L403-9 assume !(0 != activate_threads_~tmp___0~0); 23466#L403-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23582#L184-9 assume !(1 == ~t2_pc~0); 23534#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 23723#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23721#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 23719#L411-9 assume !(0 != activate_threads_~tmp___1~0); 23716#L411-11 assume !(1 == ~M_E~0); 23714#L357-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23710#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23707#L367-3 assume !(1 == ~E_1~0); 23704#L372-3 assume !(1 == ~E_2~0); 23590#L377-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 23569#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 23517#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 23518#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 23856#L537 assume !(0 == start_simulation_~tmp~3); 23848#L537-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 23834#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 23833#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 23832#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 23831#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 23830#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 23829#L500 start_simulation_#t~ret9 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 23828#L550 assume !(0 != start_simulation_~tmp___0~1); 23826#L518-1 [2019-11-15 21:00:43,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,259 INFO L82 PathProgramCache]: Analyzing trace with hash -1293822236, now seen corresponding path program 1 times [2019-11-15 21:00:43,259 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,260 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438360953] [2019-11-15 21:00:43,260 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,260 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,260 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:43,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:43,271 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [438360953] [2019-11-15 21:00:43,271 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:43,271 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:00:43,271 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [430904659] [2019-11-15 21:00:43,271 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-11-15 21:00:43,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,272 INFO L82 PathProgramCache]: Analyzing trace with hash 1081139466, now seen corresponding path program 1 times [2019-11-15 21:00:43,272 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,272 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175786902] [2019-11-15 21:00:43,272 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,272 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,272 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:43,297 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-11-15 21:00:43,298 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175786902] [2019-11-15 21:00:43,298 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:43,298 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:43,298 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108884979] [2019-11-15 21:00:43,299 INFO L808 eck$LassoCheckResult]: loop already infeasible [2019-11-15 21:00:43,299 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:43,299 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:43,299 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:43,299 INFO L87 Difference]: Start difference. First operand 546 states and 691 transitions. cyclomatic complexity: 149 Second operand 3 states. [2019-11-15 21:00:43,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:43,321 INFO L93 Difference]: Finished difference Result 525 states and 660 transitions. [2019-11-15 21:00:43,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:43,322 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 525 states and 660 transitions. [2019-11-15 21:00:43,324 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 431 [2019-11-15 21:00:43,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 525 states to 525 states and 660 transitions. [2019-11-15 21:00:43,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 525 [2019-11-15 21:00:43,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 525 [2019-11-15 21:00:43,330 INFO L73 IsDeterministic]: Start isDeterministic. Operand 525 states and 660 transitions. [2019-11-15 21:00:43,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:43,331 INFO L688 BuchiCegarLoop]: Abstraction has 525 states and 660 transitions. [2019-11-15 21:00:43,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states and 660 transitions. [2019-11-15 21:00:43,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 521. [2019-11-15 21:00:43,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 521 states. [2019-11-15 21:00:43,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 656 transitions. [2019-11-15 21:00:43,341 INFO L711 BuchiCegarLoop]: Abstraction has 521 states and 656 transitions. [2019-11-15 21:00:43,341 INFO L591 BuchiCegarLoop]: Abstraction has 521 states and 656 transitions. [2019-11-15 21:00:43,341 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-11-15 21:00:43,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 521 states and 656 transitions. [2019-11-15 21:00:43,343 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 431 [2019-11-15 21:00:43,343 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:43,343 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:43,344 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,344 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,344 INFO L791 eck$LassoCheckResult]: Stem: 24667#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 24487#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24488#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 24642#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 24643#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24546#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24547#L221-1 assume !(0 == ~M_E~0); 24569#L324-1 assume !(0 == ~T1_E~0); 24497#L329-1 assume !(0 == ~T2_E~0); 24498#L334-1 assume !(0 == ~E_1~0); 24567#L339-1 assume !(0 == ~E_2~0); 24606#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24634#L146 assume !(1 == ~m_pc~0); 24628#L146-2 is_master_triggered_~__retres1~0 := 0; 24629#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24536#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 24534#L395 assume !(0 != activate_threads_~tmp~1); 24489#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24490#L165 assume !(1 == ~t1_pc~0); 24652#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 24653#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24568#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 24538#L403 assume !(0 != activate_threads_~tmp___0~0); 24539#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24548#L184 assume !(1 == ~t2_pc~0); 24619#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 24675#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24621#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 24582#L411 assume !(0 != activate_threads_~tmp___1~0); 24559#L411-2 assume !(1 == ~M_E~0); 24560#L357-1 assume !(1 == ~T1_E~0); 24491#L362-1 assume !(1 == ~T2_E~0); 24492#L367-1 assume !(1 == ~E_1~0); 24561#L372-1 assume !(1 == ~E_2~0); 24600#L518-1 assume !false; 24731#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 24725#L299 [2019-11-15 21:00:43,350 INFO L793 eck$LassoCheckResult]: Loop: 24725#L299 assume !false; 24723#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 24721#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 24718#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 24716#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 24715#L266 assume 0 != eval_~tmp~0; 24713#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 24710#L274 assume !(0 != eval_~tmp_ndt_1~0); 24711#L271 assume !(0 == ~t1_st~0); 24734#L285 assume !(0 == ~t2_st~0); 24725#L299 [2019-11-15 21:00:43,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,350 INFO L82 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 1 times [2019-11-15 21:00:43,350 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,351 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [191716785] [2019-11-15 21:00:43,351 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,351 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,351 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,364 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:43,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,365 INFO L82 PathProgramCache]: Analyzing trace with hash -1206180399, now seen corresponding path program 1 times [2019-11-15 21:00:43,366 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,366 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064561417] [2019-11-15 21:00:43,366 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,366 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,366 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,372 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:43,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,372 INFO L82 PathProgramCache]: Analyzing trace with hash 202160337, now seen corresponding path program 1 times [2019-11-15 21:00:43,373 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,373 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208951166] [2019-11-15 21:00:43,373 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,373 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,373 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:43,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:43,390 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1208951166] [2019-11-15 21:00:43,390 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:43,390 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:43,390 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1843749179] [2019-11-15 21:00:43,445 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:43,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:43,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:43,446 INFO L87 Difference]: Start difference. First operand 521 states and 656 transitions. cyclomatic complexity: 139 Second operand 3 states. [2019-11-15 21:00:43,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:43,480 INFO L93 Difference]: Finished difference Result 919 states and 1138 transitions. [2019-11-15 21:00:43,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:43,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 919 states and 1138 transitions. [2019-11-15 21:00:43,485 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 660 [2019-11-15 21:00:43,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 919 states to 919 states and 1138 transitions. [2019-11-15 21:00:43,492 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 919 [2019-11-15 21:00:43,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 919 [2019-11-15 21:00:43,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 919 states and 1138 transitions. [2019-11-15 21:00:43,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:43,495 INFO L688 BuchiCegarLoop]: Abstraction has 919 states and 1138 transitions. [2019-11-15 21:00:43,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states and 1138 transitions. [2019-11-15 21:00:43,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 880. [2019-11-15 21:00:43,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 880 states. [2019-11-15 21:00:43,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 880 states to 880 states and 1090 transitions. [2019-11-15 21:00:43,521 INFO L711 BuchiCegarLoop]: Abstraction has 880 states and 1090 transitions. [2019-11-15 21:00:43,521 INFO L591 BuchiCegarLoop]: Abstraction has 880 states and 1090 transitions. [2019-11-15 21:00:43,521 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-11-15 21:00:43,521 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 880 states and 1090 transitions. [2019-11-15 21:00:43,524 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 621 [2019-11-15 21:00:43,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:43,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:43,525 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,525 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,525 INFO L791 eck$LassoCheckResult]: Stem: 26125#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 25934#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 25935#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26095#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 26096#L211-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 25996#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25997#L221-1 assume !(0 == ~M_E~0); 26018#L324-1 assume !(0 == ~T1_E~0); 25943#L329-1 assume !(0 == ~T2_E~0); 25944#L334-1 assume !(0 == ~E_1~0); 26016#L339-1 assume !(0 == ~E_2~0); 26057#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26567#L146 assume !(1 == ~m_pc~0); 26566#L146-2 is_master_triggered_~__retres1~0 := 0; 26565#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25984#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 25985#L395 assume !(0 != activate_threads_~tmp~1); 26564#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26563#L165 assume !(1 == ~t1_pc~0); 26133#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 26134#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26562#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 26561#L403 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25990#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25998#L184 assume !(1 == ~t2_pc~0); 26138#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 26139#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26554#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 26031#L411 assume !(0 != activate_threads_~tmp___1~0); 26008#L411-2 assume !(1 == ~M_E~0); 26009#L357-1 assume !(1 == ~T1_E~0); 25938#L362-1 assume !(1 == ~T2_E~0); 25939#L367-1 assume !(1 == ~E_1~0); 26010#L372-1 assume !(1 == ~E_2~0); 26541#L518-1 assume !false; 26536#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 26533#L299 [2019-11-15 21:00:43,526 INFO L793 eck$LassoCheckResult]: Loop: 26533#L299 assume !false; 26368#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 26369#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 26361#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 26362#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 26357#L266 assume 0 != eval_~tmp~0; 26358#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 26350#L274 assume !(0 != eval_~tmp_ndt_1~0); 26348#L271 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 26345#L288 assume !(0 != eval_~tmp_ndt_2~0); 26346#L285 assume !(0 == ~t2_st~0); 26533#L299 [2019-11-15 21:00:43,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,526 INFO L82 PathProgramCache]: Analyzing trace with hash 1658994561, now seen corresponding path program 1 times [2019-11-15 21:00:43,526 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,526 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76717925] [2019-11-15 21:00:43,527 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,527 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,527 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:43,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:43,538 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [76717925] [2019-11-15 21:00:43,538 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:43,539 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-15 21:00:43,539 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402145833] [2019-11-15 21:00:43,539 INFO L796 eck$LassoCheckResult]: stem already infeasible [2019-11-15 21:00:43,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,539 INFO L82 PathProgramCache]: Analyzing trace with hash 1263010541, now seen corresponding path program 1 times [2019-11-15 21:00:43,539 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,539 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199580226] [2019-11-15 21:00:43,540 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,540 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,540 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,544 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:43,625 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:43,625 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:43,625 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:43,626 INFO L87 Difference]: Start difference. First operand 880 states and 1090 transitions. cyclomatic complexity: 216 Second operand 3 states. [2019-11-15 21:00:43,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:43,633 INFO L93 Difference]: Finished difference Result 567 states and 706 transitions. [2019-11-15 21:00:43,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:43,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 567 states and 706 transitions. [2019-11-15 21:00:43,636 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 453 [2019-11-15 21:00:43,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 567 states to 567 states and 706 transitions. [2019-11-15 21:00:43,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 567 [2019-11-15 21:00:43,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 567 [2019-11-15 21:00:43,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 567 states and 706 transitions. [2019-11-15 21:00:43,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:43,643 INFO L688 BuchiCegarLoop]: Abstraction has 567 states and 706 transitions. [2019-11-15 21:00:43,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states and 706 transitions. [2019-11-15 21:00:43,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 567. [2019-11-15 21:00:43,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 567 states. [2019-11-15 21:00:43,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 567 states to 567 states and 706 transitions. [2019-11-15 21:00:43,654 INFO L711 BuchiCegarLoop]: Abstraction has 567 states and 706 transitions. [2019-11-15 21:00:43,654 INFO L591 BuchiCegarLoop]: Abstraction has 567 states and 706 transitions. [2019-11-15 21:00:43,654 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-11-15 21:00:43,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 567 states and 706 transitions. [2019-11-15 21:00:43,656 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 453 [2019-11-15 21:00:43,656 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:43,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:43,657 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,657 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,658 INFO L791 eck$LassoCheckResult]: Stem: 27569#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 27388#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 27389#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27545#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 27546#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27450#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27451#L221-1 assume !(0 == ~M_E~0); 27471#L324-1 assume !(0 == ~T1_E~0); 27398#L329-1 assume !(0 == ~T2_E~0); 27399#L334-1 assume !(0 == ~E_1~0); 27469#L339-1 assume !(0 == ~E_2~0); 27506#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27536#L146 assume !(1 == ~m_pc~0); 27529#L146-2 is_master_triggered_~__retres1~0 := 0; 27530#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27440#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 27438#L395 assume !(0 != activate_threads_~tmp~1); 27390#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27391#L165 assume !(1 == ~t1_pc~0); 27555#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 27556#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27470#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 27443#L403 assume !(0 != activate_threads_~tmp___0~0); 27444#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27452#L184 assume !(1 == ~t2_pc~0); 27521#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 27575#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27523#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 27483#L411 assume !(0 != activate_threads_~tmp___1~0); 27461#L411-2 assume !(1 == ~M_E~0); 27462#L357-1 assume !(1 == ~T1_E~0); 27392#L362-1 assume !(1 == ~T2_E~0); 27393#L367-1 assume !(1 == ~E_1~0); 27463#L372-1 assume !(1 == ~E_2~0); 27501#L518-1 assume !false; 27825#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 27822#L299 [2019-11-15 21:00:43,658 INFO L793 eck$LassoCheckResult]: Loop: 27822#L299 assume !false; 27819#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 27815#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 27809#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 27806#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 27803#L266 assume 0 != eval_~tmp~0; 27799#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 27797#L274 assume !(0 != eval_~tmp_ndt_1~0); 27798#L271 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 27832#L288 assume !(0 != eval_~tmp_ndt_2~0); 27828#L285 assume !(0 == ~t2_st~0); 27822#L299 [2019-11-15 21:00:43,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,658 INFO L82 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 2 times [2019-11-15 21:00:43,658 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,659 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266937561] [2019-11-15 21:00:43,659 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,659 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,659 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,670 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:43,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,671 INFO L82 PathProgramCache]: Analyzing trace with hash 1263010541, now seen corresponding path program 2 times [2019-11-15 21:00:43,671 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,671 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235670053] [2019-11-15 21:00:43,671 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,671 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,671 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,681 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:43,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,682 INFO L82 PathProgramCache]: Analyzing trace with hash 1971900397, now seen corresponding path program 1 times [2019-11-15 21:00:43,682 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,682 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891977714] [2019-11-15 21:00:43,682 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,682 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,683 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-15 21:00:43,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-15 21:00:43,709 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1891977714] [2019-11-15 21:00:43,709 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-15 21:00:43,710 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-15 21:00:43,710 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361371891] [2019-11-15 21:00:43,781 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-15 21:00:43,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-15 21:00:43,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-15 21:00:43,782 INFO L87 Difference]: Start difference. First operand 567 states and 706 transitions. cyclomatic complexity: 143 Second operand 3 states. [2019-11-15 21:00:43,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-15 21:00:43,822 INFO L93 Difference]: Finished difference Result 947 states and 1164 transitions. [2019-11-15 21:00:43,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-15 21:00:43,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 947 states and 1164 transitions. [2019-11-15 21:00:43,828 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 756 [2019-11-15 21:00:43,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 947 states to 947 states and 1164 transitions. [2019-11-15 21:00:43,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 947 [2019-11-15 21:00:43,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 947 [2019-11-15 21:00:43,844 INFO L73 IsDeterministic]: Start isDeterministic. Operand 947 states and 1164 transitions. [2019-11-15 21:00:43,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-15 21:00:43,846 INFO L688 BuchiCegarLoop]: Abstraction has 947 states and 1164 transitions. [2019-11-15 21:00:43,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 947 states and 1164 transitions. [2019-11-15 21:00:43,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 947 to 947. [2019-11-15 21:00:43,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 947 states. [2019-11-15 21:00:43,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 947 states to 947 states and 1164 transitions. [2019-11-15 21:00:43,862 INFO L711 BuchiCegarLoop]: Abstraction has 947 states and 1164 transitions. [2019-11-15 21:00:43,862 INFO L591 BuchiCegarLoop]: Abstraction has 947 states and 1164 transitions. [2019-11-15 21:00:43,863 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-11-15 21:00:43,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 947 states and 1164 transitions. [2019-11-15 21:00:43,866 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 756 [2019-11-15 21:00:43,866 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-15 21:00:43,866 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-15 21:00:43,867 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,867 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-15 21:00:43,867 INFO L791 eck$LassoCheckResult]: Stem: 29091#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 28909#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28910#L481 havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 29069#L204 assume 1 == ~m_i~0;~m_st~0 := 0; 29070#L211-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28971#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28972#L221-1 assume !(0 == ~M_E~0); 28993#L324-1 assume !(0 == ~T1_E~0); 28918#L329-1 assume !(0 == ~T2_E~0); 28919#L334-1 assume !(0 == ~E_1~0); 28991#L339-1 assume !(0 == ~E_2~0); 29032#L344-1 havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29061#L146 assume !(1 == ~m_pc~0); 29055#L146-2 is_master_triggered_~__retres1~0 := 0; 29056#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28961#L158 activate_threads_#t~ret4 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 28959#L395 assume !(0 != activate_threads_~tmp~1); 28911#L395-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28912#L165 assume !(1 == ~t1_pc~0); 29076#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 29079#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28992#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 28964#L403 assume !(0 != activate_threads_~tmp___0~0); 28965#L403-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28973#L184 assume !(1 == ~t2_pc~0); 29047#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 29098#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29048#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 29006#L411 assume !(0 != activate_threads_~tmp___1~0); 28983#L411-2 assume !(1 == ~M_E~0); 28984#L357-1 assume !(1 == ~T1_E~0); 28913#L362-1 assume !(1 == ~T2_E~0); 28914#L367-1 assume !(1 == ~E_1~0); 28985#L372-1 assume !(1 == ~E_2~0); 29027#L518-1 assume !false; 29757#L519 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 29104#L299 [2019-11-15 21:00:43,867 INFO L793 eck$LassoCheckResult]: Loop: 29104#L299 assume !false; 29754#L262 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 29752#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 29750#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 29748#L252 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 29747#L266 assume 0 != eval_~tmp~0; 29746#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 29744#L274 assume !(0 != eval_~tmp_ndt_1~0); 29745#L271 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 28916#L288 assume !(0 != eval_~tmp_ndt_2~0); 28901#L285 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 28902#L302 assume !(0 != eval_~tmp_ndt_3~0); 29104#L299 [2019-11-15 21:00:43,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,868 INFO L82 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 3 times [2019-11-15 21:00:43,868 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,868 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875805661] [2019-11-15 21:00:43,868 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,869 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,869 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,880 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:43,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,881 INFO L82 PathProgramCache]: Analyzing trace with hash 498620433, now seen corresponding path program 1 times [2019-11-15 21:00:43,881 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,881 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [700978029] [2019-11-15 21:00:43,881 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,882 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,882 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,889 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:43,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-15 21:00:43,890 INFO L82 PathProgramCache]: Analyzing trace with hash 999369489, now seen corresponding path program 1 times [2019-11-15 21:00:43,890 INFO L157 tionRefinementEngine]: Executing refinement strategy CAMEL [2019-11-15 21:00:43,890 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519186482] [2019-11-15 21:00:43,890 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,891 INFO L116 rtionOrderModulation]: Craig_NestedInterpolation forces the order to NOT_INCREMENTALLY [2019-11-15 21:00:43,891 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-15 21:00:43,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-15 21:00:43,905 INFO L168 tionRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-15 21:00:44,238 WARN L191 SmtUtils]: Spent 251.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 66 [2019-11-15 21:00:44,333 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 15.11 09:00:44 BoogieIcfgContainer [2019-11-15 21:00:44,333 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-11-15 21:00:44,333 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-15 21:00:44,333 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-15 21:00:44,333 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-15 21:00:44,334 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.11 09:00:37" (3/4) ... [2019-11-15 21:00:44,336 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-11-15 21:00:44,383 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_bc37bded-ff99-48e6-af42-56aeead0a99a/bin/uautomizer/witness.graphml [2019-11-15 21:00:44,383 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-15 21:00:44,384 INFO L168 Benchmark]: Toolchain (without parser) took 8731.72 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 281.5 MB). Free memory was 950.1 MB in the beginning and 905.9 MB in the end (delta: 44.2 MB). Peak memory consumption was 325.8 MB. Max. memory is 11.5 GB. [2019-11-15 21:00:44,385 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 967.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-15 21:00:44,385 INFO L168 Benchmark]: CACSL2BoogieTranslator took 384.04 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 106.4 MB). Free memory was 950.1 MB in the beginning and 1.1 GB in the end (delta: -147.0 MB). Peak memory consumption was 23.1 MB. Max. memory is 11.5 GB. [2019-11-15 21:00:44,386 INFO L168 Benchmark]: Boogie Procedure Inliner took 47.07 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.0 MB). Peak memory consumption was 7.0 MB. Max. memory is 11.5 GB. [2019-11-15 21:00:44,386 INFO L168 Benchmark]: Boogie Preprocessor took 61.74 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-15 21:00:44,386 INFO L168 Benchmark]: RCFGBuilder took 901.91 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 59.0 MB). Peak memory consumption was 59.0 MB. Max. memory is 11.5 GB. [2019-11-15 21:00:44,387 INFO L168 Benchmark]: BuchiAutomizer took 7280.69 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 175.1 MB). Free memory was 1.0 GB in the beginning and 909.1 MB in the end (delta: 122.1 MB). Peak memory consumption was 297.2 MB. Max. memory is 11.5 GB. [2019-11-15 21:00:44,387 INFO L168 Benchmark]: Witness Printer took 49.95 ms. Allocated memory is still 1.3 GB. Free memory was 909.1 MB in the beginning and 905.9 MB in the end (delta: 3.2 MB). Peak memory consumption was 3.2 MB. Max. memory is 11.5 GB. [2019-11-15 21:00:44,389 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 967.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 384.04 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 106.4 MB). Free memory was 950.1 MB in the beginning and 1.1 GB in the end (delta: -147.0 MB). Peak memory consumption was 23.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 47.07 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.0 MB). Peak memory consumption was 7.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 61.74 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 901.91 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 59.0 MB). Peak memory consumption was 59.0 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 7280.69 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 175.1 MB). Free memory was 1.0 GB in the beginning and 909.1 MB in the end (delta: 122.1 MB). Peak memory consumption was 297.2 MB. Max. memory is 11.5 GB. * Witness Printer took 49.95 ms. Allocated memory is still 1.3 GB. Free memory was 909.1 MB in the beginning and 905.9 MB in the end (delta: 3.2 MB). Peak memory consumption was 3.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 19 terminating modules (18 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * M_E + 1 and consists of 3 locations. 18 modules have a trivial ranking function, the largest among these consists of 11 locations. The remainder module has 947 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.2s and 19 iterations. TraceHistogramMax:2. Analysis of lassos took 4.6s. Construction of modules took 0.7s. Büchi inclusion checks took 0.8s. Highest rank in rank-based complementation 3. Minimization of det autom 14. Minimization of nondet autom 5. Automata minimization 0.3s AutomataMinimizationTime, 19 MinimizatonAttempts, 2738 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had 1956 states and ocurred in iteration 12. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 5834 SDtfs, 5467 SDslu, 8352 SDs, 0 SdLazy, 517 SolverSat, 165 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time LassoAnalysisResults: nont1 unkn0 SFLI7 SFLT0 conc2 concLT1 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital116 mio100 ax100 hnf100 lsp9 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 7ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 8 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.3s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 261]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@51a2ddda=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7a1c285f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1aaa88eb=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@354ab2f5=0, kernel_st=1, __retres1=0, tmp___0=0, t2_st=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6f027a77=0, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@d86aec6=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1e2b7487=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@49ece7e9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3aec0ac8=0, t1_st=0, \result=0, t2_pc=0, m_st=0, tmp___1=0, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 261]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int m_i ; [L22] int t1_i ; [L23] int t2_i ; [L24] int M_E = 2; [L25] int T1_E = 2; [L26] int T2_E = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; [L563] int __retres1 ; [L477] m_i = 1 [L478] t1_i = 1 [L479] t2_i = 1 [L504] int kernel_st ; [L505] int tmp ; [L506] int tmp___0 ; [L510] kernel_st = 0 [L211] COND TRUE m_i == 1 [L212] m_st = 0 [L216] COND TRUE t1_i == 1 [L217] t1_st = 0 [L221] COND TRUE t2_i == 1 [L222] t2_st = 0 [L324] COND FALSE !(M_E == 0) [L329] COND FALSE !(T1_E == 0) [L334] COND FALSE !(T2_E == 0) [L339] COND FALSE !(E_1 == 0) [L344] COND FALSE !(E_2 == 0) [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; [L143] int __retres1 ; [L146] COND FALSE !(m_pc == 1) [L156] __retres1 = 0 [L158] return (__retres1); [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) [L162] int __retres1 ; [L165] COND FALSE !(t1_pc == 1) [L175] __retres1 = 0 [L177] return (__retres1); [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) [L181] int __retres1 ; [L184] COND FALSE !(t2_pc == 1) [L194] __retres1 = 0 [L196] return (__retres1); [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) [L357] COND FALSE !(M_E == 1) [L362] COND FALSE !(T1_E == 1) [L367] COND FALSE !(T2_E == 1) [L372] COND FALSE !(E_1 == 1) [L377] COND FALSE !(E_2 == 1) [L518] COND TRUE 1 [L521] kernel_st = 1 [L257] int tmp ; Loop: [L261] COND TRUE 1 [L231] int __retres1 ; [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 [L252] return (__retres1); [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND FALSE !(\read(tmp_ndt_1)) [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND FALSE !(\read(tmp_ndt_2)) [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...