./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 678e0110 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c -s /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2b1be4311b85b6fe57410228c7ae2544fffadecc ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-678e011 [2019-11-20 05:44:13,544 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-20 05:44:13,546 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-20 05:44:13,565 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-20 05:44:13,565 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-20 05:44:13,567 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-20 05:44:13,569 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-20 05:44:13,579 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-20 05:44:13,585 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-20 05:44:13,589 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-20 05:44:13,591 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-20 05:44:13,592 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-20 05:44:13,592 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-20 05:44:13,595 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-20 05:44:13,596 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-20 05:44:13,598 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-20 05:44:13,599 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-20 05:44:13,601 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-20 05:44:13,604 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-20 05:44:13,609 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-20 05:44:13,613 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-20 05:44:13,616 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-20 05:44:13,618 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-20 05:44:13,619 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-20 05:44:13,623 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-20 05:44:13,624 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-20 05:44:13,624 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-20 05:44:13,626 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-20 05:44:13,626 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-20 05:44:13,628 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-20 05:44:13,628 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-20 05:44:13,629 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-20 05:44:13,630 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-20 05:44:13,631 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-20 05:44:13,632 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-20 05:44:13,632 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-20 05:44:13,633 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-20 05:44:13,633 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-20 05:44:13,633 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-20 05:44:13,634 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-20 05:44:13,636 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-20 05:44:13,637 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-20 05:44:13,666 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-20 05:44:13,671 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-20 05:44:13,672 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-20 05:44:13,672 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-20 05:44:13,673 INFO L138 SettingsManager]: * Use SBE=true [2019-11-20 05:44:13,673 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-20 05:44:13,673 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-20 05:44:13,673 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-20 05:44:13,673 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-20 05:44:13,674 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-20 05:44:13,674 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-20 05:44:13,674 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-20 05:44:13,674 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-20 05:44:13,675 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-20 05:44:13,675 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-20 05:44:13,675 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-20 05:44:13,675 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-20 05:44:13,676 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-20 05:44:13,676 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-20 05:44:13,676 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-20 05:44:13,676 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-20 05:44:13,676 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 05:44:13,677 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-20 05:44:13,677 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-20 05:44:13,677 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-20 05:44:13,677 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-20 05:44:13,678 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-20 05:44:13,678 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-20 05:44:13,678 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2b1be4311b85b6fe57410228c7ae2544fffadecc [2019-11-20 05:44:13,884 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-20 05:44:13,898 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-20 05:44:13,901 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-20 05:44:13,903 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-20 05:44:13,903 INFO L275 PluginConnector]: CDTParser initialized [2019-11-20 05:44:13,904 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2019-11-20 05:44:13,981 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/data/623b73ba5/21ac872e0f334c5d8f3cb7fad143826a/FLAGa9de137d7 [2019-11-20 05:44:14,436 INFO L306 CDTParser]: Found 1 translation units. [2019-11-20 05:44:14,437 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2019-11-20 05:44:14,448 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/data/623b73ba5/21ac872e0f334c5d8f3cb7fad143826a/FLAGa9de137d7 [2019-11-20 05:44:14,771 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/data/623b73ba5/21ac872e0f334c5d8f3cb7fad143826a [2019-11-20 05:44:14,774 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-20 05:44:14,775 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-20 05:44:14,776 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-20 05:44:14,776 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-20 05:44:14,780 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-20 05:44:14,781 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 05:44:14" (1/1) ... [2019-11-20 05:44:14,783 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@79d3e6f6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:14, skipping insertion in model container [2019-11-20 05:44:14,783 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 05:44:14" (1/1) ... [2019-11-20 05:44:14,792 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-20 05:44:14,845 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-20 05:44:15,293 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 05:44:15,307 INFO L188 MainTranslator]: Completed pre-run [2019-11-20 05:44:15,398 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 05:44:15,418 INFO L192 MainTranslator]: Completed translation [2019-11-20 05:44:15,419 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15 WrapperNode [2019-11-20 05:44:15,419 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-20 05:44:15,420 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-20 05:44:15,420 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-20 05:44:15,420 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-20 05:44:15,427 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15" (1/1) ... [2019-11-20 05:44:15,440 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15" (1/1) ... [2019-11-20 05:44:15,516 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-20 05:44:15,517 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-20 05:44:15,517 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-20 05:44:15,517 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-20 05:44:15,528 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15" (1/1) ... [2019-11-20 05:44:15,529 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15" (1/1) ... [2019-11-20 05:44:15,538 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15" (1/1) ... [2019-11-20 05:44:15,539 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15" (1/1) ... [2019-11-20 05:44:15,564 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15" (1/1) ... [2019-11-20 05:44:15,590 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15" (1/1) ... [2019-11-20 05:44:15,606 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15" (1/1) ... [2019-11-20 05:44:15,614 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-20 05:44:15,626 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-20 05:44:15,626 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-20 05:44:15,627 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-20 05:44:15,629 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 05:44:15,706 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-20 05:44:15,707 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-20 05:44:17,176 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-20 05:44:17,176 INFO L285 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-20 05:44:17,178 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 05:44:17 BoogieIcfgContainer [2019-11-20 05:44:17,178 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-20 05:44:17,179 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-20 05:44:17,179 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-20 05:44:17,182 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-20 05:44:17,183 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.11 05:44:14" (1/3) ... [2019-11-20 05:44:17,184 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4efd0ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 05:44:17, skipping insertion in model container [2019-11-20 05:44:17,184 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 05:44:15" (2/3) ... [2019-11-20 05:44:17,185 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4efd0ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 05:44:17, skipping insertion in model container [2019-11-20 05:44:17,185 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 05:44:17" (3/3) ... [2019-11-20 05:44:17,187 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2019-11-20 05:44:17,204 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-20 05:44:17,212 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-11-20 05:44:17,225 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-11-20 05:44:17,276 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-20 05:44:17,276 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-20 05:44:17,276 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-20 05:44:17,276 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-20 05:44:17,276 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-20 05:44:17,277 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-20 05:44:17,277 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-20 05:44:17,277 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-20 05:44:17,314 INFO L276 IsEmpty]: Start isEmpty. Operand 291 states. [2019-11-20 05:44:17,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-11-20 05:44:17,322 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:17,323 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:17,324 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:17,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:17,331 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-11-20 05:44:17,341 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:17,342 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004117440] [2019-11-20 05:44:17,342 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:17,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:17,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:17,627 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004117440] [2019-11-20 05:44:17,628 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:17,629 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 05:44:17,631 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684497900] [2019-11-20 05:44:17,638 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 05:44:17,638 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:17,649 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 05:44:17,650 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:17,651 INFO L87 Difference]: Start difference. First operand 291 states. Second operand 3 states. [2019-11-20 05:44:17,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:17,773 INFO L93 Difference]: Finished difference Result 568 states and 884 transitions. [2019-11-20 05:44:17,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 05:44:17,779 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-11-20 05:44:17,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:17,794 INFO L225 Difference]: With dead ends: 568 [2019-11-20 05:44:17,794 INFO L226 Difference]: Without dead ends: 287 [2019-11-20 05:44:17,799 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:17,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2019-11-20 05:44:17,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 287. [2019-11-20 05:44:17,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 287 states. [2019-11-20 05:44:17,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 287 states to 287 states and 409 transitions. [2019-11-20 05:44:17,862 INFO L78 Accepts]: Start accepts. Automaton has 287 states and 409 transitions. Word has length 31 [2019-11-20 05:44:17,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:17,863 INFO L462 AbstractCegarLoop]: Abstraction has 287 states and 409 transitions. [2019-11-20 05:44:17,863 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 05:44:17,863 INFO L276 IsEmpty]: Start isEmpty. Operand 287 states and 409 transitions. [2019-11-20 05:44:17,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-11-20 05:44:17,865 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:17,865 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:17,866 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:17,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:17,867 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-11-20 05:44:17,867 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:17,868 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757859057] [2019-11-20 05:44:17,868 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:17,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:18,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:18,040 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757859057] [2019-11-20 05:44:18,040 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:18,040 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 05:44:18,040 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [225357218] [2019-11-20 05:44:18,042 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 05:44:18,042 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:18,042 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 05:44:18,043 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:18,043 INFO L87 Difference]: Start difference. First operand 287 states and 409 transitions. Second operand 3 states. [2019-11-20 05:44:18,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:18,135 INFO L93 Difference]: Finished difference Result 593 states and 853 transitions. [2019-11-20 05:44:18,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 05:44:18,136 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-11-20 05:44:18,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:18,140 INFO L225 Difference]: With dead ends: 593 [2019-11-20 05:44:18,141 INFO L226 Difference]: Without dead ends: 321 [2019-11-20 05:44:18,144 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:18,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2019-11-20 05:44:18,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 263. [2019-11-20 05:44:18,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 263 states. [2019-11-20 05:44:18,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 263 states to 263 states and 373 transitions. [2019-11-20 05:44:18,170 INFO L78 Accepts]: Start accepts. Automaton has 263 states and 373 transitions. Word has length 42 [2019-11-20 05:44:18,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:18,170 INFO L462 AbstractCegarLoop]: Abstraction has 263 states and 373 transitions. [2019-11-20 05:44:18,170 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 05:44:18,171 INFO L276 IsEmpty]: Start isEmpty. Operand 263 states and 373 transitions. [2019-11-20 05:44:18,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-20 05:44:18,173 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:18,173 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:18,174 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:18,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:18,174 INFO L82 PathProgramCache]: Analyzing trace with hash -365626229, now seen corresponding path program 1 times [2019-11-20 05:44:18,175 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:18,175 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592830566] [2019-11-20 05:44:18,175 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:18,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:18,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:18,368 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1592830566] [2019-11-20 05:44:18,369 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:18,369 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 05:44:18,371 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1210980672] [2019-11-20 05:44:18,372 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 05:44:18,372 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:18,373 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 05:44:18,374 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:18,375 INFO L87 Difference]: Start difference. First operand 263 states and 373 transitions. Second operand 3 states. [2019-11-20 05:44:18,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:18,441 INFO L93 Difference]: Finished difference Result 736 states and 1054 transitions. [2019-11-20 05:44:18,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 05:44:18,442 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-20 05:44:18,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:18,448 INFO L225 Difference]: With dead ends: 736 [2019-11-20 05:44:18,449 INFO L226 Difference]: Without dead ends: 488 [2019-11-20 05:44:18,450 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:18,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states. [2019-11-20 05:44:18,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 296. [2019-11-20 05:44:18,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 296 states. [2019-11-20 05:44:18,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 296 states to 296 states and 421 transitions. [2019-11-20 05:44:18,501 INFO L78 Accepts]: Start accepts. Automaton has 296 states and 421 transitions. Word has length 49 [2019-11-20 05:44:18,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:18,502 INFO L462 AbstractCegarLoop]: Abstraction has 296 states and 421 transitions. [2019-11-20 05:44:18,502 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 05:44:18,502 INFO L276 IsEmpty]: Start isEmpty. Operand 296 states and 421 transitions. [2019-11-20 05:44:18,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-11-20 05:44:18,517 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:18,517 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:18,518 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:18,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:18,519 INFO L82 PathProgramCache]: Analyzing trace with hash 744745200, now seen corresponding path program 1 times [2019-11-20 05:44:18,519 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:18,519 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878295580] [2019-11-20 05:44:18,520 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:18,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:18,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:18,691 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878295580] [2019-11-20 05:44:18,691 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:18,692 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 05:44:18,692 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359370092] [2019-11-20 05:44:18,694 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 05:44:18,694 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:18,694 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 05:44:18,695 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:18,695 INFO L87 Difference]: Start difference. First operand 296 states and 421 transitions. Second operand 5 states. [2019-11-20 05:44:19,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:19,060 INFO L93 Difference]: Finished difference Result 932 states and 1340 transitions. [2019-11-20 05:44:19,060 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 05:44:19,061 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-11-20 05:44:19,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:19,068 INFO L225 Difference]: With dead ends: 932 [2019-11-20 05:44:19,068 INFO L226 Difference]: Without dead ends: 651 [2019-11-20 05:44:19,070 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-20 05:44:19,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 651 states. [2019-11-20 05:44:19,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 651 to 382. [2019-11-20 05:44:19,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2019-11-20 05:44:19,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 544 transitions. [2019-11-20 05:44:19,106 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 544 transitions. Word has length 50 [2019-11-20 05:44:19,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:19,109 INFO L462 AbstractCegarLoop]: Abstraction has 382 states and 544 transitions. [2019-11-20 05:44:19,109 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 05:44:19,109 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 544 transitions. [2019-11-20 05:44:19,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-11-20 05:44:19,118 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:19,118 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:19,119 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:19,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:19,119 INFO L82 PathProgramCache]: Analyzing trace with hash 1614483527, now seen corresponding path program 1 times [2019-11-20 05:44:19,120 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:19,120 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60215891] [2019-11-20 05:44:19,121 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:19,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:19,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:19,276 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60215891] [2019-11-20 05:44:19,276 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:19,277 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 05:44:19,277 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242730281] [2019-11-20 05:44:19,278 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 05:44:19,278 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:19,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 05:44:19,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:19,279 INFO L87 Difference]: Start difference. First operand 382 states and 544 transitions. Second operand 5 states. [2019-11-20 05:44:19,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:19,614 INFO L93 Difference]: Finished difference Result 932 states and 1336 transitions. [2019-11-20 05:44:19,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 05:44:19,617 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-11-20 05:44:19,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:19,623 INFO L225 Difference]: With dead ends: 932 [2019-11-20 05:44:19,623 INFO L226 Difference]: Without dead ends: 651 [2019-11-20 05:44:19,625 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-20 05:44:19,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 651 states. [2019-11-20 05:44:19,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 651 to 382. [2019-11-20 05:44:19,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2019-11-20 05:44:19,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 542 transitions. [2019-11-20 05:44:19,650 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 542 transitions. Word has length 51 [2019-11-20 05:44:19,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:19,651 INFO L462 AbstractCegarLoop]: Abstraction has 382 states and 542 transitions. [2019-11-20 05:44:19,651 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 05:44:19,651 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 542 transitions. [2019-11-20 05:44:19,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-20 05:44:19,654 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:19,654 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:19,655 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:19,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:19,655 INFO L82 PathProgramCache]: Analyzing trace with hash 251892323, now seen corresponding path program 1 times [2019-11-20 05:44:19,656 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:19,656 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324585155] [2019-11-20 05:44:19,656 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:19,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:19,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:19,877 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324585155] [2019-11-20 05:44:19,877 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:19,878 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 05:44:19,878 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709552441] [2019-11-20 05:44:19,879 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 05:44:19,879 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:19,879 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 05:44:19,879 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:19,880 INFO L87 Difference]: Start difference. First operand 382 states and 542 transitions. Second operand 5 states. [2019-11-20 05:44:19,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:19,963 INFO L93 Difference]: Finished difference Result 760 states and 1089 transitions. [2019-11-20 05:44:19,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 05:44:19,963 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2019-11-20 05:44:19,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:19,969 INFO L225 Difference]: With dead ends: 760 [2019-11-20 05:44:19,969 INFO L226 Difference]: Without dead ends: 479 [2019-11-20 05:44:19,970 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-11-20 05:44:19,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states. [2019-11-20 05:44:19,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 377. [2019-11-20 05:44:19,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 377 states. [2019-11-20 05:44:19,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 377 states to 377 states and 534 transitions. [2019-11-20 05:44:19,997 INFO L78 Accepts]: Start accepts. Automaton has 377 states and 534 transitions. Word has length 52 [2019-11-20 05:44:19,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:19,997 INFO L462 AbstractCegarLoop]: Abstraction has 377 states and 534 transitions. [2019-11-20 05:44:19,998 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 05:44:19,998 INFO L276 IsEmpty]: Start isEmpty. Operand 377 states and 534 transitions. [2019-11-20 05:44:19,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-20 05:44:19,999 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:19,999 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:20,000 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:20,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:20,005 INFO L82 PathProgramCache]: Analyzing trace with hash -1519937093, now seen corresponding path program 1 times [2019-11-20 05:44:20,005 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:20,006 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513528424] [2019-11-20 05:44:20,006 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:20,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:20,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:20,186 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513528424] [2019-11-20 05:44:20,186 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:20,186 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 05:44:20,186 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905986228] [2019-11-20 05:44:20,187 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 05:44:20,187 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:20,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 05:44:20,191 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:20,191 INFO L87 Difference]: Start difference. First operand 377 states and 534 transitions. Second operand 5 states. [2019-11-20 05:44:20,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:20,350 INFO L93 Difference]: Finished difference Result 791 states and 1138 transitions. [2019-11-20 05:44:20,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 05:44:20,350 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-11-20 05:44:20,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:20,354 INFO L225 Difference]: With dead ends: 791 [2019-11-20 05:44:20,354 INFO L226 Difference]: Without dead ends: 515 [2019-11-20 05:44:20,356 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-20 05:44:20,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 515 states. [2019-11-20 05:44:20,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 515 to 347. [2019-11-20 05:44:20,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 347 states. [2019-11-20 05:44:20,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 347 states to 347 states and 488 transitions. [2019-11-20 05:44:20,381 INFO L78 Accepts]: Start accepts. Automaton has 347 states and 488 transitions. Word has length 56 [2019-11-20 05:44:20,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:20,381 INFO L462 AbstractCegarLoop]: Abstraction has 347 states and 488 transitions. [2019-11-20 05:44:20,381 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 05:44:20,382 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 488 transitions. [2019-11-20 05:44:20,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-20 05:44:20,382 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:20,383 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:20,383 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:20,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:20,383 INFO L82 PathProgramCache]: Analyzing trace with hash 1786376721, now seen corresponding path program 1 times [2019-11-20 05:44:20,384 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:20,384 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541668447] [2019-11-20 05:44:20,384 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:20,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:20,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:20,536 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541668447] [2019-11-20 05:44:20,536 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:20,536 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 05:44:20,536 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1266017443] [2019-11-20 05:44:20,537 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 05:44:20,537 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:20,537 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 05:44:20,537 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:20,537 INFO L87 Difference]: Start difference. First operand 347 states and 488 transitions. Second operand 5 states. [2019-11-20 05:44:20,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:20,696 INFO L93 Difference]: Finished difference Result 884 states and 1260 transitions. [2019-11-20 05:44:20,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 05:44:20,696 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 61 [2019-11-20 05:44:20,697 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:20,701 INFO L225 Difference]: With dead ends: 884 [2019-11-20 05:44:20,702 INFO L226 Difference]: Without dead ends: 638 [2019-11-20 05:44:20,703 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-20 05:44:20,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 638 states. [2019-11-20 05:44:20,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 638 to 317. [2019-11-20 05:44:20,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2019-11-20 05:44:20,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 442 transitions. [2019-11-20 05:44:20,731 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 442 transitions. Word has length 61 [2019-11-20 05:44:20,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:20,732 INFO L462 AbstractCegarLoop]: Abstraction has 317 states and 442 transitions. [2019-11-20 05:44:20,732 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 05:44:20,732 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 442 transitions. [2019-11-20 05:44:20,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-11-20 05:44:20,733 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:20,733 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:20,734 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:20,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:20,734 INFO L82 PathProgramCache]: Analyzing trace with hash -1245848025, now seen corresponding path program 1 times [2019-11-20 05:44:20,734 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:20,735 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379719513] [2019-11-20 05:44:20,735 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:20,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:20,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:20,878 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [379719513] [2019-11-20 05:44:20,878 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:20,878 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 05:44:20,878 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [912632834] [2019-11-20 05:44:20,879 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 05:44:20,879 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:20,879 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 05:44:20,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 05:44:20,880 INFO L87 Difference]: Start difference. First operand 317 states and 442 transitions. Second operand 6 states. [2019-11-20 05:44:21,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:21,203 INFO L93 Difference]: Finished difference Result 1081 states and 1520 transitions. [2019-11-20 05:44:21,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 05:44:21,203 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-11-20 05:44:21,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:21,209 INFO L225 Difference]: With dead ends: 1081 [2019-11-20 05:44:21,210 INFO L226 Difference]: Without dead ends: 865 [2019-11-20 05:44:21,211 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-20 05:44:21,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 865 states. [2019-11-20 05:44:21,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 865 to 356. [2019-11-20 05:44:21,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 356 states. [2019-11-20 05:44:21,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 356 states to 356 states and 496 transitions. [2019-11-20 05:44:21,269 INFO L78 Accepts]: Start accepts. Automaton has 356 states and 496 transitions. Word has length 66 [2019-11-20 05:44:21,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:21,269 INFO L462 AbstractCegarLoop]: Abstraction has 356 states and 496 transitions. [2019-11-20 05:44:21,269 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 05:44:21,270 INFO L276 IsEmpty]: Start isEmpty. Operand 356 states and 496 transitions. [2019-11-20 05:44:21,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-11-20 05:44:21,270 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:21,271 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:21,271 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:21,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:21,272 INFO L82 PathProgramCache]: Analyzing trace with hash 1591247394, now seen corresponding path program 1 times [2019-11-20 05:44:21,272 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:21,272 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1560809720] [2019-11-20 05:44:21,272 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:21,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:21,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:21,359 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1560809720] [2019-11-20 05:44:21,359 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:21,359 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 05:44:21,359 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [253905992] [2019-11-20 05:44:21,360 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 05:44:21,360 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:21,360 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 05:44:21,361 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:21,361 INFO L87 Difference]: Start difference. First operand 356 states and 496 transitions. Second operand 3 states. [2019-11-20 05:44:21,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:21,424 INFO L93 Difference]: Finished difference Result 650 states and 915 transitions. [2019-11-20 05:44:21,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 05:44:21,427 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-11-20 05:44:21,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:21,430 INFO L225 Difference]: With dead ends: 650 [2019-11-20 05:44:21,430 INFO L226 Difference]: Without dead ends: 434 [2019-11-20 05:44:21,431 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:21,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 434 states. [2019-11-20 05:44:21,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 434 to 352. [2019-11-20 05:44:21,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2019-11-20 05:44:21,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 489 transitions. [2019-11-20 05:44:21,458 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 489 transitions. Word has length 67 [2019-11-20 05:44:21,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:21,459 INFO L462 AbstractCegarLoop]: Abstraction has 352 states and 489 transitions. [2019-11-20 05:44:21,459 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 05:44:21,459 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 489 transitions. [2019-11-20 05:44:21,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-11-20 05:44:21,465 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:21,466 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:21,466 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:21,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:21,466 INFO L82 PathProgramCache]: Analyzing trace with hash 480130565, now seen corresponding path program 1 times [2019-11-20 05:44:21,467 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:21,467 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779733186] [2019-11-20 05:44:21,467 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:21,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:21,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:21,551 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779733186] [2019-11-20 05:44:21,552 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:21,552 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 05:44:21,552 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975859239] [2019-11-20 05:44:21,553 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 05:44:21,553 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:21,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 05:44:21,554 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 05:44:21,554 INFO L87 Difference]: Start difference. First operand 352 states and 489 transitions. Second operand 4 states. [2019-11-20 05:44:21,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:21,740 INFO L93 Difference]: Finished difference Result 937 states and 1304 transitions. [2019-11-20 05:44:21,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 05:44:21,741 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 70 [2019-11-20 05:44:21,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:21,746 INFO L225 Difference]: With dead ends: 937 [2019-11-20 05:44:21,746 INFO L226 Difference]: Without dead ends: 715 [2019-11-20 05:44:21,747 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:21,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 715 states. [2019-11-20 05:44:21,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 715 to 518. [2019-11-20 05:44:21,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2019-11-20 05:44:21,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 716 transitions. [2019-11-20 05:44:21,795 INFO L78 Accepts]: Start accepts. Automaton has 518 states and 716 transitions. Word has length 70 [2019-11-20 05:44:21,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:21,795 INFO L462 AbstractCegarLoop]: Abstraction has 518 states and 716 transitions. [2019-11-20 05:44:21,796 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 05:44:21,796 INFO L276 IsEmpty]: Start isEmpty. Operand 518 states and 716 transitions. [2019-11-20 05:44:21,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-11-20 05:44:21,797 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:21,797 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:21,798 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:21,798 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:21,798 INFO L82 PathProgramCache]: Analyzing trace with hash -1523824051, now seen corresponding path program 1 times [2019-11-20 05:44:21,799 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:21,799 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16907027] [2019-11-20 05:44:21,799 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:21,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:21,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:21,848 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [16907027] [2019-11-20 05:44:21,848 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:21,848 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 05:44:21,849 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778781901] [2019-11-20 05:44:21,849 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 05:44:21,849 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:21,849 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 05:44:21,850 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:21,850 INFO L87 Difference]: Start difference. First operand 518 states and 716 transitions. Second operand 3 states. [2019-11-20 05:44:21,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:21,934 INFO L93 Difference]: Finished difference Result 1223 states and 1682 transitions. [2019-11-20 05:44:21,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 05:44:21,935 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-11-20 05:44:21,935 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:21,941 INFO L225 Difference]: With dead ends: 1223 [2019-11-20 05:44:21,941 INFO L226 Difference]: Without dead ends: 852 [2019-11-20 05:44:21,942 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:21,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 852 states. [2019-11-20 05:44:21,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 852 to 579. [2019-11-20 05:44:21,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 579 states. [2019-11-20 05:44:21,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 579 states to 579 states and 793 transitions. [2019-11-20 05:44:21,998 INFO L78 Accepts]: Start accepts. Automaton has 579 states and 793 transitions. Word has length 70 [2019-11-20 05:44:21,999 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:21,999 INFO L462 AbstractCegarLoop]: Abstraction has 579 states and 793 transitions. [2019-11-20 05:44:21,999 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 05:44:21,999 INFO L276 IsEmpty]: Start isEmpty. Operand 579 states and 793 transitions. [2019-11-20 05:44:22,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-11-20 05:44:22,000 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:22,000 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:22,001 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:22,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:22,001 INFO L82 PathProgramCache]: Analyzing trace with hash -1383275441, now seen corresponding path program 1 times [2019-11-20 05:44:22,002 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:22,002 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720211355] [2019-11-20 05:44:22,002 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:22,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:22,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:22,065 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [720211355] [2019-11-20 05:44:22,065 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:22,065 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 05:44:22,065 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398591723] [2019-11-20 05:44:22,066 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 05:44:22,066 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:22,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 05:44:22,067 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:22,067 INFO L87 Difference]: Start difference. First operand 579 states and 793 transitions. Second operand 3 states. [2019-11-20 05:44:22,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:22,124 INFO L93 Difference]: Finished difference Result 984 states and 1357 transitions. [2019-11-20 05:44:22,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 05:44:22,125 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-11-20 05:44:22,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:22,129 INFO L225 Difference]: With dead ends: 984 [2019-11-20 05:44:22,129 INFO L226 Difference]: Without dead ends: 544 [2019-11-20 05:44:22,130 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:22,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 544 states. [2019-11-20 05:44:22,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 544 to 544. [2019-11-20 05:44:22,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2019-11-20 05:44:22,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 744 transitions. [2019-11-20 05:44:22,182 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 744 transitions. Word has length 70 [2019-11-20 05:44:22,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:22,183 INFO L462 AbstractCegarLoop]: Abstraction has 544 states and 744 transitions. [2019-11-20 05:44:22,183 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 05:44:22,183 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 744 transitions. [2019-11-20 05:44:22,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-11-20 05:44:22,184 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:22,184 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:22,185 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:22,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:22,185 INFO L82 PathProgramCache]: Analyzing trace with hash -1837662732, now seen corresponding path program 1 times [2019-11-20 05:44:22,185 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:22,190 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463996443] [2019-11-20 05:44:22,190 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:22,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:22,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:22,380 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [463996443] [2019-11-20 05:44:22,380 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:22,380 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 05:44:22,380 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [846095956] [2019-11-20 05:44:22,381 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 05:44:22,381 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:22,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 05:44:22,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 05:44:22,382 INFO L87 Difference]: Start difference. First operand 544 states and 744 transitions. Second operand 6 states. [2019-11-20 05:44:22,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:22,815 INFO L93 Difference]: Finished difference Result 1710 states and 2373 transitions. [2019-11-20 05:44:22,815 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 05:44:22,816 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-11-20 05:44:22,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:22,825 INFO L225 Difference]: With dead ends: 1710 [2019-11-20 05:44:22,825 INFO L226 Difference]: Without dead ends: 1386 [2019-11-20 05:44:22,827 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-20 05:44:22,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1386 states. [2019-11-20 05:44:22,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1386 to 548. [2019-11-20 05:44:22,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 548 states. [2019-11-20 05:44:22,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 548 states to 548 states and 749 transitions. [2019-11-20 05:44:22,942 INFO L78 Accepts]: Start accepts. Automaton has 548 states and 749 transitions. Word has length 71 [2019-11-20 05:44:22,942 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:22,942 INFO L462 AbstractCegarLoop]: Abstraction has 548 states and 749 transitions. [2019-11-20 05:44:22,943 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 05:44:22,943 INFO L276 IsEmpty]: Start isEmpty. Operand 548 states and 749 transitions. [2019-11-20 05:44:22,944 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-11-20 05:44:22,944 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:22,944 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:22,945 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:22,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:22,945 INFO L82 PathProgramCache]: Analyzing trace with hash 276642491, now seen corresponding path program 1 times [2019-11-20 05:44:22,945 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:22,946 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041567368] [2019-11-20 05:44:22,946 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:22,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:23,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:23,060 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041567368] [2019-11-20 05:44:23,060 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:23,061 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 05:44:23,061 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694066129] [2019-11-20 05:44:23,061 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 05:44:23,062 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:23,062 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 05:44:23,062 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:23,062 INFO L87 Difference]: Start difference. First operand 548 states and 749 transitions. Second operand 5 states. [2019-11-20 05:44:23,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:23,276 INFO L93 Difference]: Finished difference Result 858 states and 1189 transitions. [2019-11-20 05:44:23,277 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 05:44:23,277 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2019-11-20 05:44:23,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:23,283 INFO L225 Difference]: With dead ends: 858 [2019-11-20 05:44:23,284 INFO L226 Difference]: Without dead ends: 856 [2019-11-20 05:44:23,286 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-20 05:44:23,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 856 states. [2019-11-20 05:44:23,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 856 to 550. [2019-11-20 05:44:23,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 550 states. [2019-11-20 05:44:23,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 751 transitions. [2019-11-20 05:44:23,344 INFO L78 Accepts]: Start accepts. Automaton has 550 states and 751 transitions. Word has length 71 [2019-11-20 05:44:23,345 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:23,345 INFO L462 AbstractCegarLoop]: Abstraction has 550 states and 751 transitions. [2019-11-20 05:44:23,345 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 05:44:23,345 INFO L276 IsEmpty]: Start isEmpty. Operand 550 states and 751 transitions. [2019-11-20 05:44:23,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-11-20 05:44:23,346 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:23,347 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:23,347 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:23,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:23,348 INFO L82 PathProgramCache]: Analyzing trace with hash -66828782, now seen corresponding path program 1 times [2019-11-20 05:44:23,348 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:23,348 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743086046] [2019-11-20 05:44:23,348 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:23,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:23,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:23,473 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [743086046] [2019-11-20 05:44:23,476 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:23,476 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 05:44:23,476 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461218793] [2019-11-20 05:44:23,477 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 05:44:23,477 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:23,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 05:44:23,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 05:44:23,478 INFO L87 Difference]: Start difference. First operand 550 states and 751 transitions. Second operand 6 states. [2019-11-20 05:44:24,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:24,127 INFO L93 Difference]: Finished difference Result 1977 states and 2718 transitions. [2019-11-20 05:44:24,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 05:44:24,128 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-11-20 05:44:24,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:24,139 INFO L225 Difference]: With dead ends: 1977 [2019-11-20 05:44:24,140 INFO L226 Difference]: Without dead ends: 1612 [2019-11-20 05:44:24,141 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-20 05:44:24,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1612 states. [2019-11-20 05:44:24,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1612 to 596. [2019-11-20 05:44:24,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 596 states. [2019-11-20 05:44:24,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 596 states and 809 transitions. [2019-11-20 05:44:24,220 INFO L78 Accepts]: Start accepts. Automaton has 596 states and 809 transitions. Word has length 71 [2019-11-20 05:44:24,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:24,221 INFO L462 AbstractCegarLoop]: Abstraction has 596 states and 809 transitions. [2019-11-20 05:44:24,221 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 05:44:24,221 INFO L276 IsEmpty]: Start isEmpty. Operand 596 states and 809 transitions. [2019-11-20 05:44:24,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-20 05:44:24,223 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:24,223 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:24,223 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:24,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:24,224 INFO L82 PathProgramCache]: Analyzing trace with hash -624478278, now seen corresponding path program 1 times [2019-11-20 05:44:24,224 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:24,224 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992541616] [2019-11-20 05:44:24,225 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:24,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:24,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:24,382 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992541616] [2019-11-20 05:44:24,383 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:24,383 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 05:44:24,383 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082524539] [2019-11-20 05:44:24,384 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 05:44:24,384 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:24,384 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 05:44:24,384 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 05:44:24,385 INFO L87 Difference]: Start difference. First operand 596 states and 809 transitions. Second operand 6 states. [2019-11-20 05:44:25,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:25,006 INFO L93 Difference]: Finished difference Result 2304 states and 3151 transitions. [2019-11-20 05:44:25,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 05:44:25,006 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-11-20 05:44:25,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:25,020 INFO L225 Difference]: With dead ends: 2304 [2019-11-20 05:44:25,020 INFO L226 Difference]: Without dead ends: 1931 [2019-11-20 05:44:25,024 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-20 05:44:25,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1931 states. [2019-11-20 05:44:25,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1931 to 674. [2019-11-20 05:44:25,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 674 states. [2019-11-20 05:44:25,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 911 transitions. [2019-11-20 05:44:25,108 INFO L78 Accepts]: Start accepts. Automaton has 674 states and 911 transitions. Word has length 72 [2019-11-20 05:44:25,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:25,108 INFO L462 AbstractCegarLoop]: Abstraction has 674 states and 911 transitions. [2019-11-20 05:44:25,108 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 05:44:25,109 INFO L276 IsEmpty]: Start isEmpty. Operand 674 states and 911 transitions. [2019-11-20 05:44:25,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-20 05:44:25,110 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:25,110 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:25,110 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:25,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:25,111 INFO L82 PathProgramCache]: Analyzing trace with hash -2046951303, now seen corresponding path program 1 times [2019-11-20 05:44:25,111 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:25,111 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720493738] [2019-11-20 05:44:25,111 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:25,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:25,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:25,224 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [720493738] [2019-11-20 05:44:25,224 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:25,225 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 05:44:25,225 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563621781] [2019-11-20 05:44:25,225 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 05:44:25,230 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:25,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 05:44:25,231 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 05:44:25,231 INFO L87 Difference]: Start difference. First operand 674 states and 911 transitions. Second operand 6 states. [2019-11-20 05:44:25,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:25,511 INFO L93 Difference]: Finished difference Result 1500 states and 2090 transitions. [2019-11-20 05:44:25,512 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 05:44:25,512 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-11-20 05:44:25,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:25,520 INFO L225 Difference]: With dead ends: 1500 [2019-11-20 05:44:25,520 INFO L226 Difference]: Without dead ends: 1110 [2019-11-20 05:44:25,522 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-11-20 05:44:25,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2019-11-20 05:44:25,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 680. [2019-11-20 05:44:25,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 680 states. [2019-11-20 05:44:25,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 917 transitions. [2019-11-20 05:44:25,601 INFO L78 Accepts]: Start accepts. Automaton has 680 states and 917 transitions. Word has length 72 [2019-11-20 05:44:25,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:25,602 INFO L462 AbstractCegarLoop]: Abstraction has 680 states and 917 transitions. [2019-11-20 05:44:25,602 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 05:44:25,602 INFO L276 IsEmpty]: Start isEmpty. Operand 680 states and 917 transitions. [2019-11-20 05:44:25,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-20 05:44:25,603 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:25,604 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:25,604 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:25,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:25,604 INFO L82 PathProgramCache]: Analyzing trace with hash 778464989, now seen corresponding path program 1 times [2019-11-20 05:44:25,606 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:25,606 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380190037] [2019-11-20 05:44:25,606 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:25,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:25,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:25,662 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [380190037] [2019-11-20 05:44:25,662 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:25,662 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 05:44:25,662 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2012101495] [2019-11-20 05:44:25,663 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 05:44:25,664 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:25,664 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 05:44:25,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:25,665 INFO L87 Difference]: Start difference. First operand 680 states and 917 transitions. Second operand 3 states. [2019-11-20 05:44:25,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:25,809 INFO L93 Difference]: Finished difference Result 1334 states and 1821 transitions. [2019-11-20 05:44:25,809 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 05:44:25,809 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-20 05:44:25,810 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:25,816 INFO L225 Difference]: With dead ends: 1334 [2019-11-20 05:44:25,816 INFO L226 Difference]: Without dead ends: 875 [2019-11-20 05:44:25,817 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:25,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 875 states. [2019-11-20 05:44:25,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 875 to 659. [2019-11-20 05:44:25,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 659 states. [2019-11-20 05:44:25,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 880 transitions. [2019-11-20 05:44:25,898 INFO L78 Accepts]: Start accepts. Automaton has 659 states and 880 transitions. Word has length 72 [2019-11-20 05:44:25,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:25,898 INFO L462 AbstractCegarLoop]: Abstraction has 659 states and 880 transitions. [2019-11-20 05:44:25,898 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 05:44:25,899 INFO L276 IsEmpty]: Start isEmpty. Operand 659 states and 880 transitions. [2019-11-20 05:44:25,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 05:44:25,900 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:25,900 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:25,901 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:25,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:25,901 INFO L82 PathProgramCache]: Analyzing trace with hash 449594347, now seen corresponding path program 1 times [2019-11-20 05:44:25,901 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:25,902 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012344596] [2019-11-20 05:44:25,902 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:25,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:25,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:25,969 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1012344596] [2019-11-20 05:44:25,969 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:25,969 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 05:44:25,969 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017423726] [2019-11-20 05:44:25,970 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 05:44:25,970 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:25,970 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 05:44:25,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 05:44:25,971 INFO L87 Difference]: Start difference. First operand 659 states and 880 transitions. Second operand 4 states. [2019-11-20 05:44:26,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:26,227 INFO L93 Difference]: Finished difference Result 1702 states and 2282 transitions. [2019-11-20 05:44:26,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 05:44:26,228 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-11-20 05:44:26,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:26,237 INFO L225 Difference]: With dead ends: 1702 [2019-11-20 05:44:26,238 INFO L226 Difference]: Without dead ends: 1296 [2019-11-20 05:44:26,239 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:26,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1296 states. [2019-11-20 05:44:26,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1296 to 893. [2019-11-20 05:44:26,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 893 states. [2019-11-20 05:44:26,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 893 states to 893 states and 1191 transitions. [2019-11-20 05:44:26,429 INFO L78 Accepts]: Start accepts. Automaton has 893 states and 1191 transitions. Word has length 73 [2019-11-20 05:44:26,430 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:26,430 INFO L462 AbstractCegarLoop]: Abstraction has 893 states and 1191 transitions. [2019-11-20 05:44:26,430 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 05:44:26,430 INFO L276 IsEmpty]: Start isEmpty. Operand 893 states and 1191 transitions. [2019-11-20 05:44:26,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 05:44:26,431 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:26,433 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:26,433 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:26,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:26,434 INFO L82 PathProgramCache]: Analyzing trace with hash 1828954211, now seen corresponding path program 1 times [2019-11-20 05:44:26,434 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:26,434 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482465042] [2019-11-20 05:44:26,435 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:26,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:26,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:26,526 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482465042] [2019-11-20 05:44:26,527 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:26,527 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 05:44:26,527 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114450361] [2019-11-20 05:44:26,527 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 05:44:26,528 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:26,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 05:44:26,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:26,528 INFO L87 Difference]: Start difference. First operand 893 states and 1191 transitions. Second operand 3 states. [2019-11-20 05:44:26,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:26,721 INFO L93 Difference]: Finished difference Result 1870 states and 2511 transitions. [2019-11-20 05:44:26,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 05:44:26,722 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 05:44:26,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:26,730 INFO L225 Difference]: With dead ends: 1870 [2019-11-20 05:44:26,731 INFO L226 Difference]: Without dead ends: 1281 [2019-11-20 05:44:26,732 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:26,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1281 states. [2019-11-20 05:44:26,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1281 to 849. [2019-11-20 05:44:26,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 849 states. [2019-11-20 05:44:26,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 849 states to 849 states and 1127 transitions. [2019-11-20 05:44:26,839 INFO L78 Accepts]: Start accepts. Automaton has 849 states and 1127 transitions. Word has length 73 [2019-11-20 05:44:26,840 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:26,840 INFO L462 AbstractCegarLoop]: Abstraction has 849 states and 1127 transitions. [2019-11-20 05:44:26,840 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 05:44:26,840 INFO L276 IsEmpty]: Start isEmpty. Operand 849 states and 1127 transitions. [2019-11-20 05:44:26,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 05:44:26,842 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:26,842 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:26,842 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:26,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:26,843 INFO L82 PathProgramCache]: Analyzing trace with hash 1948644571, now seen corresponding path program 1 times [2019-11-20 05:44:26,843 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:26,843 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345549411] [2019-11-20 05:44:26,843 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:26,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:26,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:26,920 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345549411] [2019-11-20 05:44:26,920 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:26,920 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 05:44:26,920 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [447822270] [2019-11-20 05:44:26,921 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 05:44:26,921 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:26,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 05:44:26,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 05:44:26,922 INFO L87 Difference]: Start difference. First operand 849 states and 1127 transitions. Second operand 4 states. [2019-11-20 05:44:27,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:27,178 INFO L93 Difference]: Finished difference Result 1986 states and 2630 transitions. [2019-11-20 05:44:27,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 05:44:27,180 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-11-20 05:44:27,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:27,190 INFO L225 Difference]: With dead ends: 1986 [2019-11-20 05:44:27,190 INFO L226 Difference]: Without dead ends: 1426 [2019-11-20 05:44:27,192 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:27,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1426 states. [2019-11-20 05:44:27,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1426 to 1131. [2019-11-20 05:44:27,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1131 states. [2019-11-20 05:44:27,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1131 states to 1131 states and 1491 transitions. [2019-11-20 05:44:27,331 INFO L78 Accepts]: Start accepts. Automaton has 1131 states and 1491 transitions. Word has length 73 [2019-11-20 05:44:27,331 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:27,331 INFO L462 AbstractCegarLoop]: Abstraction has 1131 states and 1491 transitions. [2019-11-20 05:44:27,332 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 05:44:27,332 INFO L276 IsEmpty]: Start isEmpty. Operand 1131 states and 1491 transitions. [2019-11-20 05:44:27,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-20 05:44:27,333 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:27,334 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:27,334 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:27,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:27,335 INFO L82 PathProgramCache]: Analyzing trace with hash 1795806066, now seen corresponding path program 1 times [2019-11-20 05:44:27,335 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:27,335 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462626590] [2019-11-20 05:44:27,335 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:27,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:27,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:27,371 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [462626590] [2019-11-20 05:44:27,371 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:27,371 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 05:44:27,373 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1963591354] [2019-11-20 05:44:27,373 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 05:44:27,374 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:27,374 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 05:44:27,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:27,376 INFO L87 Difference]: Start difference. First operand 1131 states and 1491 transitions. Second operand 3 states. [2019-11-20 05:44:27,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:27,714 INFO L93 Difference]: Finished difference Result 2794 states and 3673 transitions. [2019-11-20 05:44:27,714 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 05:44:27,714 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-11-20 05:44:27,715 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:27,727 INFO L225 Difference]: With dead ends: 2794 [2019-11-20 05:44:27,727 INFO L226 Difference]: Without dead ends: 1896 [2019-11-20 05:44:27,729 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 05:44:27,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1896 states. [2019-11-20 05:44:27,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1896 to 1133. [2019-11-20 05:44:27,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1133 states. [2019-11-20 05:44:27,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1133 states to 1133 states and 1493 transitions. [2019-11-20 05:44:27,912 INFO L78 Accepts]: Start accepts. Automaton has 1133 states and 1493 transitions. Word has length 74 [2019-11-20 05:44:27,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:27,913 INFO L462 AbstractCegarLoop]: Abstraction has 1133 states and 1493 transitions. [2019-11-20 05:44:27,913 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 05:44:27,913 INFO L276 IsEmpty]: Start isEmpty. Operand 1133 states and 1493 transitions. [2019-11-20 05:44:27,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-20 05:44:27,915 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:27,915 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:27,915 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:27,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:27,916 INFO L82 PathProgramCache]: Analyzing trace with hash 230569326, now seen corresponding path program 1 times [2019-11-20 05:44:27,916 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:27,917 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387500542] [2019-11-20 05:44:27,917 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:27,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:28,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:28,010 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387500542] [2019-11-20 05:44:28,010 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:28,011 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 05:44:28,011 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760455133] [2019-11-20 05:44:28,011 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 05:44:28,012 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:28,012 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 05:44:28,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 05:44:28,013 INFO L87 Difference]: Start difference. First operand 1133 states and 1493 transitions. Second operand 4 states. [2019-11-20 05:44:28,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:28,231 INFO L93 Difference]: Finished difference Result 2365 states and 3103 transitions. [2019-11-20 05:44:28,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 05:44:28,231 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-11-20 05:44:28,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:28,240 INFO L225 Difference]: With dead ends: 2365 [2019-11-20 05:44:28,240 INFO L226 Difference]: Without dead ends: 1287 [2019-11-20 05:44:28,243 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:28,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1287 states. [2019-11-20 05:44:28,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1287 to 946. [2019-11-20 05:44:28,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 946 states. [2019-11-20 05:44:28,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 946 states to 946 states and 1237 transitions. [2019-11-20 05:44:28,376 INFO L78 Accepts]: Start accepts. Automaton has 946 states and 1237 transitions. Word has length 75 [2019-11-20 05:44:28,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:28,377 INFO L462 AbstractCegarLoop]: Abstraction has 946 states and 1237 transitions. [2019-11-20 05:44:28,377 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 05:44:28,377 INFO L276 IsEmpty]: Start isEmpty. Operand 946 states and 1237 transitions. [2019-11-20 05:44:28,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-11-20 05:44:28,378 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:28,379 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:28,379 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:28,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:28,380 INFO L82 PathProgramCache]: Analyzing trace with hash -818028433, now seen corresponding path program 1 times [2019-11-20 05:44:28,380 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:28,380 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427001082] [2019-11-20 05:44:28,380 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:28,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:28,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:28,468 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1427001082] [2019-11-20 05:44:28,468 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:28,468 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 05:44:28,469 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [70776965] [2019-11-20 05:44:28,469 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 05:44:28,469 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:28,470 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 05:44:28,470 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 05:44:28,470 INFO L87 Difference]: Start difference. First operand 946 states and 1237 transitions. Second operand 4 states. [2019-11-20 05:44:28,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:28,686 INFO L93 Difference]: Finished difference Result 2178 states and 2855 transitions. [2019-11-20 05:44:28,686 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 05:44:28,687 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 76 [2019-11-20 05:44:28,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:28,694 INFO L225 Difference]: With dead ends: 2178 [2019-11-20 05:44:28,695 INFO L226 Difference]: Without dead ends: 1307 [2019-11-20 05:44:28,697 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:28,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1307 states. [2019-11-20 05:44:28,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1307 to 892. [2019-11-20 05:44:28,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-11-20 05:44:28,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1159 transitions. [2019-11-20 05:44:28,827 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1159 transitions. Word has length 76 [2019-11-20 05:44:28,827 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:28,827 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1159 transitions. [2019-11-20 05:44:28,828 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 05:44:28,828 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1159 transitions. [2019-11-20 05:44:28,830 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2019-11-20 05:44:28,831 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:28,831 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:28,831 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:28,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:28,832 INFO L82 PathProgramCache]: Analyzing trace with hash 1542213080, now seen corresponding path program 1 times [2019-11-20 05:44:28,832 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:28,832 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627777987] [2019-11-20 05:44:28,833 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:28,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:29,178 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:29,179 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627777987] [2019-11-20 05:44:29,179 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [242443784] [2019-11-20 05:44:29,179 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:29,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:29,393 INFO L255 TraceCheckSpWp]: Trace formula consists of 724 conjuncts, 9 conjunts are in the unsatisfiable core [2019-11-20 05:44:29,415 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 05:44:29,537 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 05:44:29,538 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 05:44:29,538 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 05:44:29,539 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244516375] [2019-11-20 05:44:29,539 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 05:44:29,539 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:29,540 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 05:44:29,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-20 05:44:29,541 INFO L87 Difference]: Start difference. First operand 892 states and 1159 transitions. Second operand 6 states. [2019-11-20 05:44:30,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:30,061 INFO L93 Difference]: Finished difference Result 2720 states and 3672 transitions. [2019-11-20 05:44:30,062 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 05:44:30,062 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 120 [2019-11-20 05:44:30,062 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:30,091 INFO L225 Difference]: With dead ends: 2720 [2019-11-20 05:44:30,099 INFO L226 Difference]: Without dead ends: 1969 [2019-11-20 05:44:30,102 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 117 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-11-20 05:44:30,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1969 states. [2019-11-20 05:44:30,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1969 to 892. [2019-11-20 05:44:30,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-11-20 05:44:30,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1156 transitions. [2019-11-20 05:44:30,313 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1156 transitions. Word has length 120 [2019-11-20 05:44:30,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:30,313 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1156 transitions. [2019-11-20 05:44:30,313 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 05:44:30,313 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1156 transitions. [2019-11-20 05:44:30,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2019-11-20 05:44:30,316 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:30,317 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:30,522 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:30,523 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:30,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:30,523 INFO L82 PathProgramCache]: Analyzing trace with hash -1832197229, now seen corresponding path program 1 times [2019-11-20 05:44:30,524 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:30,524 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122266755] [2019-11-20 05:44:30,524 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:30,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:30,913 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:30,914 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1122266755] [2019-11-20 05:44:30,914 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1725798213] [2019-11-20 05:44:30,914 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:31,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:31,142 INFO L255 TraceCheckSpWp]: Trace formula consists of 737 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-20 05:44:31,155 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 05:44:31,296 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 05:44:31,296 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 05:44:31,297 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 05:44:31,297 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [329473318] [2019-11-20 05:44:31,297 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 05:44:31,298 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:31,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 05:44:31,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-20 05:44:31,299 INFO L87 Difference]: Start difference. First operand 892 states and 1156 transitions. Second operand 6 states. [2019-11-20 05:44:31,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:31,826 INFO L93 Difference]: Finished difference Result 2447 states and 3267 transitions. [2019-11-20 05:44:31,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 05:44:31,826 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 124 [2019-11-20 05:44:31,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:31,831 INFO L225 Difference]: With dead ends: 2447 [2019-11-20 05:44:31,831 INFO L226 Difference]: Without dead ends: 1696 [2019-11-20 05:44:31,833 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 140 GetRequests, 121 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-11-20 05:44:31,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1696 states. [2019-11-20 05:44:31,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1696 to 892. [2019-11-20 05:44:31,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-11-20 05:44:31,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1153 transitions. [2019-11-20 05:44:31,982 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1153 transitions. Word has length 124 [2019-11-20 05:44:31,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:31,983 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1153 transitions. [2019-11-20 05:44:31,983 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 05:44:31,983 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1153 transitions. [2019-11-20 05:44:31,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-11-20 05:44:31,988 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:31,989 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:32,193 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:32,193 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:32,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:32,194 INFO L82 PathProgramCache]: Analyzing trace with hash 1668386931, now seen corresponding path program 1 times [2019-11-20 05:44:32,194 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:32,194 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715167614] [2019-11-20 05:44:32,195 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:32,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:32,579 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:32,579 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715167614] [2019-11-20 05:44:32,580 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [332761282] [2019-11-20 05:44:32,580 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:32,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:32,813 INFO L255 TraceCheckSpWp]: Trace formula consists of 749 conjuncts, 12 conjunts are in the unsatisfiable core [2019-11-20 05:44:32,822 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 05:44:32,932 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 05:44:32,933 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 05:44:32,933 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 05:44:32,933 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1931172699] [2019-11-20 05:44:32,934 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 05:44:32,934 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:32,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 05:44:32,935 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-20 05:44:32,935 INFO L87 Difference]: Start difference. First operand 892 states and 1153 transitions. Second operand 6 states. [2019-11-20 05:44:33,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:33,604 INFO L93 Difference]: Finished difference Result 2811 states and 3778 transitions. [2019-11-20 05:44:33,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 05:44:33,605 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 127 [2019-11-20 05:44:33,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:33,610 INFO L225 Difference]: With dead ends: 2811 [2019-11-20 05:44:33,610 INFO L226 Difference]: Without dead ends: 2047 [2019-11-20 05:44:33,612 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2019-11-20 05:44:33,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states. [2019-11-20 05:44:33,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 840. [2019-11-20 05:44:33,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2019-11-20 05:44:33,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1075 transitions. [2019-11-20 05:44:33,755 INFO L78 Accepts]: Start accepts. Automaton has 840 states and 1075 transitions. Word has length 127 [2019-11-20 05:44:33,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:33,756 INFO L462 AbstractCegarLoop]: Abstraction has 840 states and 1075 transitions. [2019-11-20 05:44:33,756 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 05:44:33,756 INFO L276 IsEmpty]: Start isEmpty. Operand 840 states and 1075 transitions. [2019-11-20 05:44:33,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2019-11-20 05:44:33,758 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:33,759 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:33,963 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:33,963 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:33,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:33,964 INFO L82 PathProgramCache]: Analyzing trace with hash -1807241978, now seen corresponding path program 1 times [2019-11-20 05:44:33,964 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:33,964 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092586944] [2019-11-20 05:44:33,965 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:34,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:34,250 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:34,251 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092586944] [2019-11-20 05:44:34,254 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [668506678] [2019-11-20 05:44:34,254 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:34,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:34,478 INFO L255 TraceCheckSpWp]: Trace formula consists of 750 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-20 05:44:34,487 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 05:44:34,619 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-20 05:44:34,620 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 05:44:34,620 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [10] total 15 [2019-11-20 05:44:34,620 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1708436556] [2019-11-20 05:44:34,621 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 05:44:34,621 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:34,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 05:44:34,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=181, Unknown=0, NotChecked=0, Total=210 [2019-11-20 05:44:34,622 INFO L87 Difference]: Start difference. First operand 840 states and 1075 transitions. Second operand 6 states. [2019-11-20 05:44:35,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:35,063 INFO L93 Difference]: Finished difference Result 2163 states and 2880 transitions. [2019-11-20 05:44:35,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 05:44:35,063 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 128 [2019-11-20 05:44:35,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:35,067 INFO L225 Difference]: With dead ends: 2163 [2019-11-20 05:44:35,067 INFO L226 Difference]: Without dead ends: 1478 [2019-11-20 05:44:35,070 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 142 GetRequests, 125 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=48, Invalid=294, Unknown=0, NotChecked=0, Total=342 [2019-11-20 05:44:35,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1478 states. [2019-11-20 05:44:35,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1478 to 840. [2019-11-20 05:44:35,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2019-11-20 05:44:35,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1074 transitions. [2019-11-20 05:44:35,195 INFO L78 Accepts]: Start accepts. Automaton has 840 states and 1074 transitions. Word has length 128 [2019-11-20 05:44:35,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:35,196 INFO L462 AbstractCegarLoop]: Abstraction has 840 states and 1074 transitions. [2019-11-20 05:44:35,196 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 05:44:35,196 INFO L276 IsEmpty]: Start isEmpty. Operand 840 states and 1074 transitions. [2019-11-20 05:44:35,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-11-20 05:44:35,199 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:35,199 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:35,404 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:35,404 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:35,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:35,404 INFO L82 PathProgramCache]: Analyzing trace with hash 237584641, now seen corresponding path program 1 times [2019-11-20 05:44:35,405 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:35,405 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232572190] [2019-11-20 05:44:35,405 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:35,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:35,673 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:35,673 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232572190] [2019-11-20 05:44:35,673 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [306766898] [2019-11-20 05:44:35,673 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:35,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:35,894 INFO L255 TraceCheckSpWp]: Trace formula consists of 764 conjuncts, 45 conjunts are in the unsatisfiable core [2019-11-20 05:44:35,903 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 05:44:36,305 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:36,306 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 05:44:36,306 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12] total 17 [2019-11-20 05:44:36,307 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1959248602] [2019-11-20 05:44:36,308 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-11-20 05:44:36,308 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:36,308 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-11-20 05:44:36,309 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=251, Unknown=0, NotChecked=0, Total=306 [2019-11-20 05:44:36,309 INFO L87 Difference]: Start difference. First operand 840 states and 1074 transitions. Second operand 18 states. [2019-11-20 05:44:40,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:40,463 INFO L93 Difference]: Finished difference Result 3439 states and 4527 transitions. [2019-11-20 05:44:40,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2019-11-20 05:44:40,464 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 132 [2019-11-20 05:44:40,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:40,469 INFO L225 Difference]: With dead ends: 3439 [2019-11-20 05:44:40,469 INFO L226 Difference]: Without dead ends: 2760 [2019-11-20 05:44:40,473 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 199 GetRequests, 119 SyntacticMatches, 4 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1942 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1261, Invalid=4745, Unknown=0, NotChecked=0, Total=6006 [2019-11-20 05:44:40,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2760 states. [2019-11-20 05:44:40,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2760 to 1325. [2019-11-20 05:44:40,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1325 states. [2019-11-20 05:44:40,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1325 states to 1325 states and 1715 transitions. [2019-11-20 05:44:40,708 INFO L78 Accepts]: Start accepts. Automaton has 1325 states and 1715 transitions. Word has length 132 [2019-11-20 05:44:40,708 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:40,708 INFO L462 AbstractCegarLoop]: Abstraction has 1325 states and 1715 transitions. [2019-11-20 05:44:40,709 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-11-20 05:44:40,709 INFO L276 IsEmpty]: Start isEmpty. Operand 1325 states and 1715 transitions. [2019-11-20 05:44:40,712 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-20 05:44:40,712 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:40,713 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:40,917 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:40,917 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:40,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:40,918 INFO L82 PathProgramCache]: Analyzing trace with hash -700555044, now seen corresponding path program 1 times [2019-11-20 05:44:40,918 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:40,918 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339690493] [2019-11-20 05:44:40,918 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:40,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:40,986 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-11-20 05:44:40,987 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339690493] [2019-11-20 05:44:40,987 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:40,987 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 05:44:40,988 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1681986599] [2019-11-20 05:44:40,989 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 05:44:40,989 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:40,989 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 05:44:40,989 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 05:44:40,990 INFO L87 Difference]: Start difference. First operand 1325 states and 1715 transitions. Second operand 4 states. [2019-11-20 05:44:41,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:41,465 INFO L93 Difference]: Finished difference Result 3265 states and 4250 transitions. [2019-11-20 05:44:41,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 05:44:41,466 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 133 [2019-11-20 05:44:41,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:41,471 INFO L225 Difference]: With dead ends: 3265 [2019-11-20 05:44:41,472 INFO L226 Difference]: Without dead ends: 2068 [2019-11-20 05:44:41,474 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:41,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2068 states. [2019-11-20 05:44:41,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2068 to 1385. [2019-11-20 05:44:41,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1385 states. [2019-11-20 05:44:41,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1385 states to 1385 states and 1769 transitions. [2019-11-20 05:44:41,711 INFO L78 Accepts]: Start accepts. Automaton has 1385 states and 1769 transitions. Word has length 133 [2019-11-20 05:44:41,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:41,711 INFO L462 AbstractCegarLoop]: Abstraction has 1385 states and 1769 transitions. [2019-11-20 05:44:41,711 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 05:44:41,712 INFO L276 IsEmpty]: Start isEmpty. Operand 1385 states and 1769 transitions. [2019-11-20 05:44:41,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-20 05:44:41,715 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:41,716 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:41,716 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:41,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:41,717 INFO L82 PathProgramCache]: Analyzing trace with hash -709461544, now seen corresponding path program 1 times [2019-11-20 05:44:41,717 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:41,717 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647962728] [2019-11-20 05:44:41,718 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:41,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:41,860 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-11-20 05:44:41,860 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647962728] [2019-11-20 05:44:41,861 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:41,861 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 05:44:41,861 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876001846] [2019-11-20 05:44:41,861 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 05:44:41,862 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:41,862 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 05:44:41,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:41,863 INFO L87 Difference]: Start difference. First operand 1385 states and 1769 transitions. Second operand 5 states. [2019-11-20 05:44:42,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:42,193 INFO L93 Difference]: Finished difference Result 2514 states and 3258 transitions. [2019-11-20 05:44:42,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 05:44:42,193 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 133 [2019-11-20 05:44:42,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:42,196 INFO L225 Difference]: With dead ends: 2514 [2019-11-20 05:44:42,196 INFO L226 Difference]: Without dead ends: 1257 [2019-11-20 05:44:42,200 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-20 05:44:42,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1257 states. [2019-11-20 05:44:42,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1257 to 1257. [2019-11-20 05:44:42,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1257 states. [2019-11-20 05:44:42,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1257 states to 1257 states and 1621 transitions. [2019-11-20 05:44:42,426 INFO L78 Accepts]: Start accepts. Automaton has 1257 states and 1621 transitions. Word has length 133 [2019-11-20 05:44:42,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:42,427 INFO L462 AbstractCegarLoop]: Abstraction has 1257 states and 1621 transitions. [2019-11-20 05:44:42,427 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 05:44:42,427 INFO L276 IsEmpty]: Start isEmpty. Operand 1257 states and 1621 transitions. [2019-11-20 05:44:42,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-20 05:44:42,430 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:42,431 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:42,431 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:42,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:42,432 INFO L82 PathProgramCache]: Analyzing trace with hash 77500617, now seen corresponding path program 1 times [2019-11-20 05:44:42,432 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:42,432 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827637316] [2019-11-20 05:44:42,432 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:42,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:42,530 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2019-11-20 05:44:42,530 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827637316] [2019-11-20 05:44:42,531 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:42,531 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 05:44:42,531 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [972368262] [2019-11-20 05:44:42,532 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 05:44:42,532 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:42,532 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 05:44:42,532 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 05:44:42,532 INFO L87 Difference]: Start difference. First operand 1257 states and 1621 transitions. Second operand 6 states. [2019-11-20 05:44:43,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:43,851 INFO L93 Difference]: Finished difference Result 6586 states and 8686 transitions. [2019-11-20 05:44:43,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-11-20 05:44:43,852 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 134 [2019-11-20 05:44:43,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:43,863 INFO L225 Difference]: With dead ends: 6586 [2019-11-20 05:44:43,864 INFO L226 Difference]: Without dead ends: 5510 [2019-11-20 05:44:43,867 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2019-11-20 05:44:43,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5510 states. [2019-11-20 05:44:44,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5510 to 1599. [2019-11-20 05:44:44,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1599 states. [2019-11-20 05:44:44,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1599 states to 1599 states and 2021 transitions. [2019-11-20 05:44:44,167 INFO L78 Accepts]: Start accepts. Automaton has 1599 states and 2021 transitions. Word has length 134 [2019-11-20 05:44:44,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:44,168 INFO L462 AbstractCegarLoop]: Abstraction has 1599 states and 2021 transitions. [2019-11-20 05:44:44,168 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 05:44:44,168 INFO L276 IsEmpty]: Start isEmpty. Operand 1599 states and 2021 transitions. [2019-11-20 05:44:44,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-20 05:44:44,172 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:44,172 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:44,173 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:44,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:44,173 INFO L82 PathProgramCache]: Analyzing trace with hash -825335127, now seen corresponding path program 1 times [2019-11-20 05:44:44,174 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:44,174 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112459744] [2019-11-20 05:44:44,174 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:44,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:44,561 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:44,561 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112459744] [2019-11-20 05:44:44,561 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [545614415] [2019-11-20 05:44:44,562 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:44,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:44,780 INFO L255 TraceCheckSpWp]: Trace formula consists of 776 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-20 05:44:44,783 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 05:44:44,884 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 05:44:44,884 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 05:44:44,884 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 05:44:44,885 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1147658544] [2019-11-20 05:44:44,886 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 05:44:44,886 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:44,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 05:44:44,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-20 05:44:44,887 INFO L87 Difference]: Start difference. First operand 1599 states and 2021 transitions. Second operand 6 states. [2019-11-20 05:44:45,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:45,747 INFO L93 Difference]: Finished difference Result 4910 states and 6326 transitions. [2019-11-20 05:44:45,747 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 05:44:45,747 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2019-11-20 05:44:45,748 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:45,753 INFO L225 Difference]: With dead ends: 4910 [2019-11-20 05:44:45,754 INFO L226 Difference]: Without dead ends: 3472 [2019-11-20 05:44:45,757 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 132 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-11-20 05:44:45,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3472 states. [2019-11-20 05:44:46,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3472 to 1599. [2019-11-20 05:44:46,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1599 states. [2019-11-20 05:44:46,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1599 states to 1599 states and 2019 transitions. [2019-11-20 05:44:46,086 INFO L78 Accepts]: Start accepts. Automaton has 1599 states and 2019 transitions. Word has length 135 [2019-11-20 05:44:46,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:46,087 INFO L462 AbstractCegarLoop]: Abstraction has 1599 states and 2019 transitions. [2019-11-20 05:44:46,087 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 05:44:46,087 INFO L276 IsEmpty]: Start isEmpty. Operand 1599 states and 2019 transitions. [2019-11-20 05:44:46,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-20 05:44:46,096 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:46,096 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:46,300 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:46,301 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:46,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:46,301 INFO L82 PathProgramCache]: Analyzing trace with hash -1957396857, now seen corresponding path program 1 times [2019-11-20 05:44:46,301 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:46,301 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989920263] [2019-11-20 05:44:46,301 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:46,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:46,585 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:46,585 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989920263] [2019-11-20 05:44:46,585 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [693614548] [2019-11-20 05:44:46,585 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:46,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:46,812 INFO L255 TraceCheckSpWp]: Trace formula consists of 766 conjuncts, 46 conjunts are in the unsatisfiable core [2019-11-20 05:44:46,815 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 05:44:47,311 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 05:44:47,312 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 05:44:47,312 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-11-20 05:44:47,312 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [67741429] [2019-11-20 05:44:47,313 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-20 05:44:47,313 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:47,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-20 05:44:47,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2019-11-20 05:44:47,315 INFO L87 Difference]: Start difference. First operand 1599 states and 2019 transitions. Second operand 21 states. [2019-11-20 05:44:50,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:50,232 INFO L93 Difference]: Finished difference Result 4391 states and 5566 transitions. [2019-11-20 05:44:50,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-11-20 05:44:50,233 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 135 [2019-11-20 05:44:50,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:50,237 INFO L225 Difference]: With dead ends: 4391 [2019-11-20 05:44:50,237 INFO L226 Difference]: Without dead ends: 2973 [2019-11-20 05:44:50,241 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 185 GetRequests, 121 SyntacticMatches, 4 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 997 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=649, Invalid=3133, Unknown=0, NotChecked=0, Total=3782 [2019-11-20 05:44:50,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2973 states. [2019-11-20 05:44:50,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2973 to 1819. [2019-11-20 05:44:50,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1819 states. [2019-11-20 05:44:50,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1819 states to 1819 states and 2290 transitions. [2019-11-20 05:44:50,536 INFO L78 Accepts]: Start accepts. Automaton has 1819 states and 2290 transitions. Word has length 135 [2019-11-20 05:44:50,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:50,536 INFO L462 AbstractCegarLoop]: Abstraction has 1819 states and 2290 transitions. [2019-11-20 05:44:50,537 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-20 05:44:50,537 INFO L276 IsEmpty]: Start isEmpty. Operand 1819 states and 2290 transitions. [2019-11-20 05:44:50,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-20 05:44:50,540 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:50,541 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:50,744 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 05:44:50,745 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:50,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:50,745 INFO L82 PathProgramCache]: Analyzing trace with hash 470861765, now seen corresponding path program 1 times [2019-11-20 05:44:50,745 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:50,746 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301135529] [2019-11-20 05:44:50,746 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:50,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 05:44:50,843 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2019-11-20 05:44:50,843 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301135529] [2019-11-20 05:44:50,844 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 05:44:50,844 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 05:44:50,844 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1702277014] [2019-11-20 05:44:50,845 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 05:44:50,845 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 05:44:50,845 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 05:44:50,846 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-20 05:44:50,846 INFO L87 Difference]: Start difference. First operand 1819 states and 2290 transitions. Second operand 4 states. [2019-11-20 05:44:51,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 05:44:51,300 INFO L93 Difference]: Finished difference Result 3316 states and 4201 transitions. [2019-11-20 05:44:51,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 05:44:51,301 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2019-11-20 05:44:51,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 05:44:51,304 INFO L225 Difference]: With dead ends: 3316 [2019-11-20 05:44:51,304 INFO L226 Difference]: Without dead ends: 1623 [2019-11-20 05:44:51,306 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-20 05:44:51,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1623 states. [2019-11-20 05:44:51,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1623 to 1623. [2019-11-20 05:44:51,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1623 states. [2019-11-20 05:44:51,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1623 states to 1623 states and 2029 transitions. [2019-11-20 05:44:51,586 INFO L78 Accepts]: Start accepts. Automaton has 1623 states and 2029 transitions. Word has length 135 [2019-11-20 05:44:51,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 05:44:51,587 INFO L462 AbstractCegarLoop]: Abstraction has 1623 states and 2029 transitions. [2019-11-20 05:44:51,587 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 05:44:51,587 INFO L276 IsEmpty]: Start isEmpty. Operand 1623 states and 2029 transitions. [2019-11-20 05:44:51,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-20 05:44:51,590 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 05:44:51,590 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 05:44:51,591 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 05:44:51,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 05:44:51,591 INFO L82 PathProgramCache]: Analyzing trace with hash -1467051729, now seen corresponding path program 1 times [2019-11-20 05:44:51,592 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 05:44:51,592 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052016119] [2019-11-20 05:44:51,592 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 05:44:51,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 05:44:51,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 05:44:51,864 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 05:44:51,865 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-20 05:44:52,103 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 20.11 05:44:52 BoogieIcfgContainer [2019-11-20 05:44:52,103 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-20 05:44:52,104 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-20 05:44:52,104 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-20 05:44:52,104 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-20 05:44:52,105 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 05:44:17" (3/4) ... [2019-11-20 05:44:52,108 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-20 05:44:52,413 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_0fc0e031-e9f3-491e-9963-bb3bf2d5f6fd/bin/uautomizer/witness.graphml [2019-11-20 05:44:52,413 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-20 05:44:52,416 INFO L168 Benchmark]: Toolchain (without parser) took 37639.83 ms. Allocated memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: 900.7 MB). Free memory was 944.7 MB in the beginning and 1.5 GB in the end (delta: -542.7 MB). Peak memory consumption was 358.1 MB. Max. memory is 11.5 GB. [2019-11-20 05:44:52,416 INFO L168 Benchmark]: CDTParser took 0.22 ms. Allocated memory is still 1.0 GB. Free memory is still 962.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 05:44:52,417 INFO L168 Benchmark]: CACSL2BoogieTranslator took 643.28 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.3 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -185.0 MB). Peak memory consumption was 17.8 MB. Max. memory is 11.5 GB. [2019-11-20 05:44:52,417 INFO L168 Benchmark]: Boogie Procedure Inliner took 96.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-11-20 05:44:52,418 INFO L168 Benchmark]: Boogie Preprocessor took 97.75 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-11-20 05:44:52,418 INFO L168 Benchmark]: RCFGBuilder took 1552.03 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 86.9 MB). Peak memory consumption was 86.9 MB. Max. memory is 11.5 GB. [2019-11-20 05:44:52,418 INFO L168 Benchmark]: TraceAbstraction took 34924.48 ms. Allocated memory was 1.2 GB in the beginning and 1.9 GB in the end (delta: 764.4 MB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -508.5 MB). Peak memory consumption was 255.9 MB. Max. memory is 11.5 GB. [2019-11-20 05:44:52,419 INFO L168 Benchmark]: Witness Printer took 309.53 ms. Allocated memory is still 1.9 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 47.9 MB). Peak memory consumption was 47.9 MB. Max. memory is 11.5 GB. [2019-11-20 05:44:52,421 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.22 ms. Allocated memory is still 1.0 GB. Free memory is still 962.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 643.28 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.3 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -185.0 MB). Peak memory consumption was 17.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 96.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 97.75 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1552.03 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 86.9 MB). Peak memory consumption was 86.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 34924.48 ms. Allocated memory was 1.2 GB in the beginning and 1.9 GB in the end (delta: 764.4 MB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -508.5 MB). Peak memory consumption was 255.9 MB. Max. memory is 11.5 GB. * Witness Printer took 309.53 ms. Allocated memory is still 1.9 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 47.9 MB). Peak memory consumption was 47.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 654]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L455] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L577] int c1 ; [L578] int i2 ; [L581] c1 = 0 [L582] side1Failed = __VERIFIER_nondet_bool() [L583] side2Failed = __VERIFIER_nondet_bool() [L584] side1_written = __VERIFIER_nondet_char() [L585] side2_written = __VERIFIER_nondet_char() [L586] side1Failed_History_0 = __VERIFIER_nondet_bool() [L587] side1Failed_History_1 = __VERIFIER_nondet_bool() [L588] side1Failed_History_2 = __VERIFIER_nondet_bool() [L589] side2Failed_History_0 = __VERIFIER_nondet_bool() [L590] side2Failed_History_1 = __VERIFIER_nondet_bool() [L591] side2Failed_History_2 = __VERIFIER_nondet_bool() [L592] active_side_History_0 = __VERIFIER_nondet_char() [L593] active_side_History_1 = __VERIFIER_nondet_char() [L594] active_side_History_2 = __VERIFIER_nondet_char() [L595] manual_selection_History_0 = __VERIFIER_nondet_char() [L596] manual_selection_History_1 = __VERIFIER_nondet_char() [L597] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L598] i2 = init() [L600] cs1_old = nomsg [L601] cs1_new = nomsg [L602] cs2_old = nomsg [L603] cs2_new = nomsg [L604] s1s2_old = nomsg [L605] s1s2_new = nomsg [L606] s1s1_old = nomsg [L607] s1s1_new = nomsg [L608] s2s1_old = nomsg [L609] s2s1_new = nomsg [L610] s2s2_old = nomsg [L611] s2s2_new = nomsg [L612] s1p_old = nomsg [L613] s1p_new = nomsg [L614] s2p_old = nomsg [L615] s2p_new = nomsg [L616] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L485] COND TRUE ! side2Failed [L486] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] tmp___1 = read_side1_failed_history((unsigned char)1) [L494] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L495] tmp___2 = read_side1_failed_history((unsigned char)0) [L496] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] tmp___11 = read_side1_failed_history((unsigned char)1) [L538] COND TRUE ! tmp___11 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L539] tmp___12 = read_side2_failed_history((unsigned char)1) [L540] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L553] tmp___20 = read_active_side_history((unsigned char)2) [L554] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L572] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L652] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L641] i2 ++ VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-128, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-128, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND FALSE !(\read(side1Failed)) [L326] side1 = s1s1_old [L327] s1s1_old = nomsg [L328] side2 = s2s1_old [L329] s2s1_old = nomsg [L330] manual_selection = cs1_old [L331] cs1_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L332] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L335] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L336] COND TRUE (int )side2 != (int )nomsg [L337] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] EXPR next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] s1s1_new = next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new [L357] EXPR next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L357] s1s2_new = next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new [L358] EXPR next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L358] s1p_new = next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new [L359] side1_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND TRUE \read(side2Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] EXPR nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] s2s1_new = nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new [L378] EXPR nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L378] s2s2_new = nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new [L379] EXPR nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L379] s2p_new = nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new [L380] side2_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND TRUE ! side1Failed [L483] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND FALSE !(! tmp___0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND TRUE \read(tmp___7) [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L523] tmp___8 = read_side2_failed_history((unsigned char)1) [L524] COND TRUE ! tmp___8 [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L525] tmp___5 = read_active_side_history((unsigned char)0) [L526] COND TRUE ! ((int )tmp___5 == 2) [L527] return (0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L652] COND TRUE ! arg VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L654] __VERIFIER_error() VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 291 locations, 23 error locations. Result: UNSAFE, OverallTime: 34.8s, OverallIterations: 37, TraceHistogramMax: 2, AutomataDifference: 19.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 15713 SDtfs, 28413 SDslu, 34026 SDs, 0 SdLazy, 5191 SolverSat, 400 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1324 GetRequests, 950 SyntacticMatches, 19 SemanticMatches, 355 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3349 ImplicationChecksByTransitivity, 7.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1819occurred in iteration=35, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 4.4s AutomataMinimizationTime, 36 MinimizatonAttempts, 21934 StatesRemovedByMinimization, 32 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.5s SsaConstructionTime, 2.0s SatisfiabilityAnalysisTime, 5.4s InterpolantComputationTime, 4081 NumberOfCodeBlocks, 4081 NumberOfCodeBlocksAsserted, 44 NumberOfCheckSat, 3902 ConstructedInterpolants, 0 QuantifiedInterpolants, 1566655 SizeOfPredicates, 38 NumberOfNonLiveVariables, 5266 ConjunctsInSsa, 136 ConjunctsInUnsatCore, 43 InterpolantComputations, 34 PerfectInterpolantSequences, 582/673 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...