./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 678e0110 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c -s /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 75de94c5f78b6878c3cbd09fac99b01e14f23f29 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-678e011 [2019-11-20 06:46:14,978 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-20 06:46:14,980 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-20 06:46:14,994 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-20 06:46:14,994 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-20 06:46:14,995 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-20 06:46:14,997 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-20 06:46:15,006 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-20 06:46:15,010 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-20 06:46:15,014 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-20 06:46:15,015 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-20 06:46:15,016 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-20 06:46:15,017 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-20 06:46:15,019 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-20 06:46:15,020 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-20 06:46:15,021 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-20 06:46:15,021 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-20 06:46:15,022 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-20 06:46:15,025 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-20 06:46:15,028 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-20 06:46:15,032 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-20 06:46:15,034 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-20 06:46:15,037 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-20 06:46:15,037 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-20 06:46:15,040 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-20 06:46:15,040 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-20 06:46:15,040 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-20 06:46:15,042 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-20 06:46:15,042 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-20 06:46:15,043 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-20 06:46:15,043 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-20 06:46:15,044 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-20 06:46:15,045 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-20 06:46:15,045 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-20 06:46:15,046 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-20 06:46:15,046 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-20 06:46:15,047 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-20 06:46:15,047 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-20 06:46:15,047 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-20 06:46:15,048 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-20 06:46:15,049 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-20 06:46:15,050 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-20 06:46:15,071 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-20 06:46:15,071 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-20 06:46:15,072 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-20 06:46:15,072 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-20 06:46:15,073 INFO L138 SettingsManager]: * Use SBE=true [2019-11-20 06:46:15,073 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-20 06:46:15,073 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-20 06:46:15,073 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-20 06:46:15,074 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-20 06:46:15,074 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-20 06:46:15,074 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-20 06:46:15,074 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-20 06:46:15,074 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-20 06:46:15,075 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-20 06:46:15,075 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-20 06:46:15,075 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-20 06:46:15,075 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-20 06:46:15,076 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-20 06:46:15,076 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-20 06:46:15,076 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-20 06:46:15,076 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-20 06:46:15,076 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 06:46:15,077 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-20 06:46:15,077 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-20 06:46:15,077 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-20 06:46:15,077 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-20 06:46:15,078 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-20 06:46:15,078 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-20 06:46:15,078 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 75de94c5f78b6878c3cbd09fac99b01e14f23f29 [2019-11-20 06:46:15,247 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-20 06:46:15,257 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-20 06:46:15,260 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-20 06:46:15,261 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-20 06:46:15,261 INFO L275 PluginConnector]: CDTParser initialized [2019-11-20 06:46:15,262 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c [2019-11-20 06:46:15,322 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/data/260989665/ab42119d11fc485396f95400eb69ded1/FLAG79ee3aff8 [2019-11-20 06:46:15,769 INFO L306 CDTParser]: Found 1 translation units. [2019-11-20 06:46:15,770 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c [2019-11-20 06:46:15,782 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/data/260989665/ab42119d11fc485396f95400eb69ded1/FLAG79ee3aff8 [2019-11-20 06:46:16,089 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/data/260989665/ab42119d11fc485396f95400eb69ded1 [2019-11-20 06:46:16,091 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-20 06:46:16,092 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-20 06:46:16,093 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-20 06:46:16,093 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-20 06:46:16,101 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-20 06:46:16,101 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 06:46:16" (1/1) ... [2019-11-20 06:46:16,104 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@211e6e30 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16, skipping insertion in model container [2019-11-20 06:46:16,104 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 06:46:16" (1/1) ... [2019-11-20 06:46:16,111 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-20 06:46:16,167 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-20 06:46:16,475 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 06:46:16,485 INFO L188 MainTranslator]: Completed pre-run [2019-11-20 06:46:16,569 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 06:46:16,598 INFO L192 MainTranslator]: Completed translation [2019-11-20 06:46:16,599 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16 WrapperNode [2019-11-20 06:46:16,599 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-20 06:46:16,599 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-20 06:46:16,600 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-20 06:46:16,600 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-20 06:46:16,606 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16" (1/1) ... [2019-11-20 06:46:16,618 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16" (1/1) ... [2019-11-20 06:46:16,685 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-20 06:46:16,687 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-20 06:46:16,687 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-20 06:46:16,687 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-20 06:46:16,697 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16" (1/1) ... [2019-11-20 06:46:16,703 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16" (1/1) ... [2019-11-20 06:46:16,714 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16" (1/1) ... [2019-11-20 06:46:16,728 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16" (1/1) ... [2019-11-20 06:46:16,759 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16" (1/1) ... [2019-11-20 06:46:16,771 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16" (1/1) ... [2019-11-20 06:46:16,774 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16" (1/1) ... [2019-11-20 06:46:16,781 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-20 06:46:16,781 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-20 06:46:16,781 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-20 06:46:16,782 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-20 06:46:16,782 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 06:46:16,838 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-20 06:46:16,838 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-20 06:46:18,040 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-20 06:46:18,041 INFO L285 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-20 06:46:18,042 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 06:46:18 BoogieIcfgContainer [2019-11-20 06:46:18,042 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-20 06:46:18,043 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-20 06:46:18,044 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-20 06:46:18,046 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-20 06:46:18,046 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.11 06:46:16" (1/3) ... [2019-11-20 06:46:18,046 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@48c9ca0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 06:46:18, skipping insertion in model container [2019-11-20 06:46:18,046 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 06:46:16" (2/3) ... [2019-11-20 06:46:18,047 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@48c9ca0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 06:46:18, skipping insertion in model container [2019-11-20 06:46:18,047 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 06:46:18" (3/3) ... [2019-11-20 06:46:18,048 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c [2019-11-20 06:46:18,057 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-20 06:46:18,065 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-11-20 06:46:18,073 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-11-20 06:46:18,099 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-20 06:46:18,099 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-20 06:46:18,099 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-20 06:46:18,099 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-20 06:46:18,100 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-20 06:46:18,100 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-20 06:46:18,100 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-20 06:46:18,100 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-20 06:46:18,130 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states. [2019-11-20 06:46:18,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-11-20 06:46:18,137 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:18,138 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:18,139 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:18,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:18,145 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-11-20 06:46:18,154 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:18,154 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464689357] [2019-11-20 06:46:18,155 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:18,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:18,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:18,349 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464689357] [2019-11-20 06:46:18,350 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:18,350 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 06:46:18,351 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958623881] [2019-11-20 06:46:18,356 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 06:46:18,356 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:18,368 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 06:46:18,369 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:18,371 INFO L87 Difference]: Start difference. First operand 293 states. Second operand 3 states. [2019-11-20 06:46:18,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:18,461 INFO L93 Difference]: Finished difference Result 572 states and 892 transitions. [2019-11-20 06:46:18,461 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 06:46:18,463 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-11-20 06:46:18,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:18,489 INFO L225 Difference]: With dead ends: 572 [2019-11-20 06:46:18,489 INFO L226 Difference]: Without dead ends: 289 [2019-11-20 06:46:18,506 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:18,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states. [2019-11-20 06:46:18,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 289. [2019-11-20 06:46:18,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 289 states. [2019-11-20 06:46:18,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 289 states to 289 states and 413 transitions. [2019-11-20 06:46:18,589 INFO L78 Accepts]: Start accepts. Automaton has 289 states and 413 transitions. Word has length 31 [2019-11-20 06:46:18,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:18,590 INFO L462 AbstractCegarLoop]: Abstraction has 289 states and 413 transitions. [2019-11-20 06:46:18,590 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 06:46:18,590 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states and 413 transitions. [2019-11-20 06:46:18,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-11-20 06:46:18,592 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:18,592 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:18,593 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:18,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:18,593 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-11-20 06:46:18,593 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:18,593 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663480979] [2019-11-20 06:46:18,594 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:18,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:18,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:18,757 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1663480979] [2019-11-20 06:46:18,757 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:18,757 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 06:46:18,757 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953461107] [2019-11-20 06:46:18,759 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 06:46:18,759 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:18,759 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 06:46:18,759 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:18,760 INFO L87 Difference]: Start difference. First operand 289 states and 413 transitions. Second operand 3 states. [2019-11-20 06:46:18,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:18,833 INFO L93 Difference]: Finished difference Result 597 states and 861 transitions. [2019-11-20 06:46:18,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 06:46:18,834 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-11-20 06:46:18,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:18,836 INFO L225 Difference]: With dead ends: 597 [2019-11-20 06:46:18,836 INFO L226 Difference]: Without dead ends: 323 [2019-11-20 06:46:18,838 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:18,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states. [2019-11-20 06:46:18,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 265. [2019-11-20 06:46:18,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2019-11-20 06:46:18,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 377 transitions. [2019-11-20 06:46:18,850 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 377 transitions. Word has length 42 [2019-11-20 06:46:18,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:18,851 INFO L462 AbstractCegarLoop]: Abstraction has 265 states and 377 transitions. [2019-11-20 06:46:18,851 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 06:46:18,851 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 377 transitions. [2019-11-20 06:46:18,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-20 06:46:18,853 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:18,853 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:18,853 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:18,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:18,854 INFO L82 PathProgramCache]: Analyzing trace with hash 1273755287, now seen corresponding path program 1 times [2019-11-20 06:46:18,854 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:18,854 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514257081] [2019-11-20 06:46:18,854 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:18,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:18,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:18,973 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514257081] [2019-11-20 06:46:18,973 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:18,973 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 06:46:18,973 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102999033] [2019-11-20 06:46:18,974 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 06:46:18,974 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:18,974 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 06:46:18,975 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:18,975 INFO L87 Difference]: Start difference. First operand 265 states and 377 transitions. Second operand 3 states. [2019-11-20 06:46:19,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:19,020 INFO L93 Difference]: Finished difference Result 742 states and 1066 transitions. [2019-11-20 06:46:19,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 06:46:19,021 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-20 06:46:19,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:19,024 INFO L225 Difference]: With dead ends: 742 [2019-11-20 06:46:19,025 INFO L226 Difference]: Without dead ends: 492 [2019-11-20 06:46:19,026 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:19,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 492 states. [2019-11-20 06:46:19,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 492 to 300. [2019-11-20 06:46:19,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 300 states. [2019-11-20 06:46:19,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 300 states to 300 states and 429 transitions. [2019-11-20 06:46:19,043 INFO L78 Accepts]: Start accepts. Automaton has 300 states and 429 transitions. Word has length 49 [2019-11-20 06:46:19,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:19,044 INFO L462 AbstractCegarLoop]: Abstraction has 300 states and 429 transitions. [2019-11-20 06:46:19,044 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 06:46:19,044 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 429 transitions. [2019-11-20 06:46:19,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-11-20 06:46:19,051 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:19,052 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:19,052 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:19,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:19,053 INFO L82 PathProgramCache]: Analyzing trace with hash -1910840580, now seen corresponding path program 1 times [2019-11-20 06:46:19,054 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:19,054 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663436144] [2019-11-20 06:46:19,054 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:19,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:19,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:19,176 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663436144] [2019-11-20 06:46:19,176 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:19,176 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:19,176 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238011737] [2019-11-20 06:46:19,177 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 06:46:19,177 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:19,177 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 06:46:19,178 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:19,178 INFO L87 Difference]: Start difference. First operand 300 states and 429 transitions. Second operand 5 states. [2019-11-20 06:46:19,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:19,466 INFO L93 Difference]: Finished difference Result 942 states and 1360 transitions. [2019-11-20 06:46:19,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 06:46:19,467 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-11-20 06:46:19,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:19,473 INFO L225 Difference]: With dead ends: 942 [2019-11-20 06:46:19,473 INFO L226 Difference]: Without dead ends: 657 [2019-11-20 06:46:19,475 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-20 06:46:19,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states. [2019-11-20 06:46:19,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 386. [2019-11-20 06:46:19,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 386 states. [2019-11-20 06:46:19,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 386 states and 552 transitions. [2019-11-20 06:46:19,499 INFO L78 Accepts]: Start accepts. Automaton has 386 states and 552 transitions. Word has length 50 [2019-11-20 06:46:19,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:19,501 INFO L462 AbstractCegarLoop]: Abstraction has 386 states and 552 transitions. [2019-11-20 06:46:19,501 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 06:46:19,501 INFO L276 IsEmpty]: Start isEmpty. Operand 386 states and 552 transitions. [2019-11-20 06:46:19,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-11-20 06:46:19,509 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:19,509 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:19,509 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:19,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:19,510 INFO L82 PathProgramCache]: Analyzing trace with hash -1041102253, now seen corresponding path program 1 times [2019-11-20 06:46:19,510 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:19,510 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647702416] [2019-11-20 06:46:19,511 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:19,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:19,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:19,659 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1647702416] [2019-11-20 06:46:19,659 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:19,660 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:19,660 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574528766] [2019-11-20 06:46:19,660 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 06:46:19,661 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:19,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 06:46:19,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:19,661 INFO L87 Difference]: Start difference. First operand 386 states and 552 transitions. Second operand 5 states. [2019-11-20 06:46:19,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:19,929 INFO L93 Difference]: Finished difference Result 944 states and 1360 transitions. [2019-11-20 06:46:19,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 06:46:19,929 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-11-20 06:46:19,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:19,934 INFO L225 Difference]: With dead ends: 944 [2019-11-20 06:46:19,934 INFO L226 Difference]: Without dead ends: 659 [2019-11-20 06:46:19,935 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-20 06:46:19,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states. [2019-11-20 06:46:19,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 390. [2019-11-20 06:46:19,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 390 states. [2019-11-20 06:46:19,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 390 states to 390 states and 556 transitions. [2019-11-20 06:46:19,958 INFO L78 Accepts]: Start accepts. Automaton has 390 states and 556 transitions. Word has length 51 [2019-11-20 06:46:19,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:19,958 INFO L462 AbstractCegarLoop]: Abstraction has 390 states and 556 transitions. [2019-11-20 06:46:19,958 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 06:46:19,959 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 556 transitions. [2019-11-20 06:46:19,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-20 06:46:19,960 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:19,960 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:19,960 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:19,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:19,961 INFO L82 PathProgramCache]: Analyzing trace with hash -458607163, now seen corresponding path program 1 times [2019-11-20 06:46:19,961 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:19,961 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160981053] [2019-11-20 06:46:19,962 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:20,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:20,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:20,124 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160981053] [2019-11-20 06:46:20,125 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:20,125 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:20,126 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285199142] [2019-11-20 06:46:20,127 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 06:46:20,127 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:20,127 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 06:46:20,128 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:46:20,128 INFO L87 Difference]: Start difference. First operand 390 states and 556 transitions. Second operand 4 states. [2019-11-20 06:46:20,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:20,385 INFO L93 Difference]: Finished difference Result 944 states and 1356 transitions. [2019-11-20 06:46:20,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:46:20,386 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 53 [2019-11-20 06:46:20,388 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:20,392 INFO L225 Difference]: With dead ends: 944 [2019-11-20 06:46:20,392 INFO L226 Difference]: Without dead ends: 659 [2019-11-20 06:46:20,393 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:20,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states. [2019-11-20 06:46:20,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 390. [2019-11-20 06:46:20,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 390 states. [2019-11-20 06:46:20,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 390 states to 390 states and 554 transitions. [2019-11-20 06:46:20,412 INFO L78 Accepts]: Start accepts. Automaton has 390 states and 554 transitions. Word has length 53 [2019-11-20 06:46:20,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:20,412 INFO L462 AbstractCegarLoop]: Abstraction has 390 states and 554 transitions. [2019-11-20 06:46:20,413 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 06:46:20,413 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 554 transitions. [2019-11-20 06:46:20,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-20 06:46:20,414 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:20,414 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:20,414 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:20,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:20,415 INFO L82 PathProgramCache]: Analyzing trace with hash 1789775306, now seen corresponding path program 1 times [2019-11-20 06:46:20,415 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:20,415 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974423990] [2019-11-20 06:46:20,415 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:20,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:20,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:20,557 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974423990] [2019-11-20 06:46:20,557 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:20,557 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 06:46:20,558 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [341606731] [2019-11-20 06:46:20,558 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 06:46:20,558 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:20,558 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 06:46:20,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:20,559 INFO L87 Difference]: Start difference. First operand 390 states and 554 transitions. Second operand 5 states. [2019-11-20 06:46:20,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:20,615 INFO L93 Difference]: Finished difference Result 776 states and 1117 transitions. [2019-11-20 06:46:20,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 06:46:20,615 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2019-11-20 06:46:20,616 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:20,618 INFO L225 Difference]: With dead ends: 776 [2019-11-20 06:46:20,619 INFO L226 Difference]: Without dead ends: 491 [2019-11-20 06:46:20,619 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-11-20 06:46:20,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 491 states. [2019-11-20 06:46:20,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 491 to 385. [2019-11-20 06:46:20,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 385 states. [2019-11-20 06:46:20,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385 states to 385 states and 546 transitions. [2019-11-20 06:46:20,637 INFO L78 Accepts]: Start accepts. Automaton has 385 states and 546 transitions. Word has length 54 [2019-11-20 06:46:20,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:20,638 INFO L462 AbstractCegarLoop]: Abstraction has 385 states and 546 transitions. [2019-11-20 06:46:20,638 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 06:46:20,638 INFO L276 IsEmpty]: Start isEmpty. Operand 385 states and 546 transitions. [2019-11-20 06:46:20,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-20 06:46:20,639 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:20,639 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:20,639 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:20,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:20,640 INFO L82 PathProgramCache]: Analyzing trace with hash 1630366882, now seen corresponding path program 1 times [2019-11-20 06:46:20,640 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:20,640 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898766716] [2019-11-20 06:46:20,641 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:20,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:20,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:20,764 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898766716] [2019-11-20 06:46:20,764 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:20,764 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 06:46:20,764 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885249167] [2019-11-20 06:46:20,765 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 06:46:20,765 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:20,765 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 06:46:20,765 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:20,766 INFO L87 Difference]: Start difference. First operand 385 states and 546 transitions. Second operand 5 states. [2019-11-20 06:46:20,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:20,882 INFO L93 Difference]: Finished difference Result 807 states and 1166 transitions. [2019-11-20 06:46:20,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:46:20,882 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-11-20 06:46:20,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:20,886 INFO L225 Difference]: With dead ends: 807 [2019-11-20 06:46:20,886 INFO L226 Difference]: Without dead ends: 527 [2019-11-20 06:46:20,887 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-20 06:46:20,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states. [2019-11-20 06:46:20,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 355. [2019-11-20 06:46:20,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 355 states. [2019-11-20 06:46:20,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 355 states to 355 states and 500 transitions. [2019-11-20 06:46:20,907 INFO L78 Accepts]: Start accepts. Automaton has 355 states and 500 transitions. Word has length 58 [2019-11-20 06:46:20,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:20,907 INFO L462 AbstractCegarLoop]: Abstraction has 355 states and 500 transitions. [2019-11-20 06:46:20,907 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 06:46:20,908 INFO L276 IsEmpty]: Start isEmpty. Operand 355 states and 500 transitions. [2019-11-20 06:46:20,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-20 06:46:20,908 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:20,908 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:20,909 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:20,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:20,909 INFO L82 PathProgramCache]: Analyzing trace with hash 644191382, now seen corresponding path program 1 times [2019-11-20 06:46:20,910 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:20,910 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160098878] [2019-11-20 06:46:20,910 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:20,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:21,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:21,046 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160098878] [2019-11-20 06:46:21,046 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:21,046 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 06:46:21,047 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623963296] [2019-11-20 06:46:21,047 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 06:46:21,047 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:21,047 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 06:46:21,048 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:21,048 INFO L87 Difference]: Start difference. First operand 355 states and 500 transitions. Second operand 5 states. [2019-11-20 06:46:21,185 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:21,185 INFO L93 Difference]: Finished difference Result 904 states and 1296 transitions. [2019-11-20 06:46:21,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:46:21,186 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 63 [2019-11-20 06:46:21,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:21,189 INFO L225 Difference]: With dead ends: 904 [2019-11-20 06:46:21,190 INFO L226 Difference]: Without dead ends: 654 [2019-11-20 06:46:21,190 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-20 06:46:21,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2019-11-20 06:46:21,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 325. [2019-11-20 06:46:21,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 325 states. [2019-11-20 06:46:21,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 325 states to 325 states and 454 transitions. [2019-11-20 06:46:21,220 INFO L78 Accepts]: Start accepts. Automaton has 325 states and 454 transitions. Word has length 63 [2019-11-20 06:46:21,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:21,221 INFO L462 AbstractCegarLoop]: Abstraction has 325 states and 454 transitions. [2019-11-20 06:46:21,221 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 06:46:21,221 INFO L276 IsEmpty]: Start isEmpty. Operand 325 states and 454 transitions. [2019-11-20 06:46:21,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-11-20 06:46:21,222 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:21,222 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:21,222 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:21,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:21,223 INFO L82 PathProgramCache]: Analyzing trace with hash 157991886, now seen corresponding path program 1 times [2019-11-20 06:46:21,223 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:21,223 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778585643] [2019-11-20 06:46:21,223 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:21,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:21,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:21,415 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [778585643] [2019-11-20 06:46:21,416 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:21,416 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 06:46:21,416 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [698319514] [2019-11-20 06:46:21,416 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:46:21,417 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:21,417 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:46:21,417 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 06:46:21,417 INFO L87 Difference]: Start difference. First operand 325 states and 454 transitions. Second operand 6 states. [2019-11-20 06:46:21,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:21,679 INFO L93 Difference]: Finished difference Result 1105 states and 1564 transitions. [2019-11-20 06:46:21,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 06:46:21,682 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-11-20 06:46:21,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:21,686 INFO L225 Difference]: With dead ends: 1105 [2019-11-20 06:46:21,686 INFO L226 Difference]: Without dead ends: 885 [2019-11-20 06:46:21,687 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-20 06:46:21,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 885 states. [2019-11-20 06:46:21,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 885 to 364. [2019-11-20 06:46:21,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364 states. [2019-11-20 06:46:21,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 508 transitions. [2019-11-20 06:46:21,714 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 508 transitions. Word has length 68 [2019-11-20 06:46:21,714 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:21,716 INFO L462 AbstractCegarLoop]: Abstraction has 364 states and 508 transitions. [2019-11-20 06:46:21,716 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:46:21,716 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 508 transitions. [2019-11-20 06:46:21,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-11-20 06:46:21,719 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:21,719 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:21,719 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:21,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:21,719 INFO L82 PathProgramCache]: Analyzing trace with hash -2134355609, now seen corresponding path program 1 times [2019-11-20 06:46:21,719 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:21,720 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436582009] [2019-11-20 06:46:21,720 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:21,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:21,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:21,794 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [436582009] [2019-11-20 06:46:21,794 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:21,795 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 06:46:21,795 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1520790315] [2019-11-20 06:46:21,795 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 06:46:21,795 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:21,796 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 06:46:21,796 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:21,796 INFO L87 Difference]: Start difference. First operand 364 states and 508 transitions. Second operand 3 states. [2019-11-20 06:46:21,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:21,861 INFO L93 Difference]: Finished difference Result 662 states and 935 transitions. [2019-11-20 06:46:21,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 06:46:21,861 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-11-20 06:46:21,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:21,864 INFO L225 Difference]: With dead ends: 662 [2019-11-20 06:46:21,864 INFO L226 Difference]: Without dead ends: 442 [2019-11-20 06:46:21,865 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:21,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 442 states. [2019-11-20 06:46:21,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 442 to 360. [2019-11-20 06:46:21,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 360 states. [2019-11-20 06:46:21,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 360 states to 360 states and 501 transitions. [2019-11-20 06:46:21,892 INFO L78 Accepts]: Start accepts. Automaton has 360 states and 501 transitions. Word has length 69 [2019-11-20 06:46:21,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:21,893 INFO L462 AbstractCegarLoop]: Abstraction has 360 states and 501 transitions. [2019-11-20 06:46:21,893 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 06:46:21,893 INFO L276 IsEmpty]: Start isEmpty. Operand 360 states and 501 transitions. [2019-11-20 06:46:21,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-20 06:46:21,894 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:21,894 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:21,895 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:21,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:21,895 INFO L82 PathProgramCache]: Analyzing trace with hash 1585943340, now seen corresponding path program 1 times [2019-11-20 06:46:21,895 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:21,896 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953270506] [2019-11-20 06:46:21,896 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:21,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:21,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:21,955 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [953270506] [2019-11-20 06:46:21,955 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:21,956 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:21,956 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845603874] [2019-11-20 06:46:21,956 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 06:46:21,957 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:21,957 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 06:46:21,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:46:21,957 INFO L87 Difference]: Start difference. First operand 360 states and 501 transitions. Second operand 4 states. [2019-11-20 06:46:22,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:22,111 INFO L93 Difference]: Finished difference Result 953 states and 1330 transitions. [2019-11-20 06:46:22,111 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:46:22,112 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2019-11-20 06:46:22,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:22,115 INFO L225 Difference]: With dead ends: 953 [2019-11-20 06:46:22,116 INFO L226 Difference]: Without dead ends: 727 [2019-11-20 06:46:22,116 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:22,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 727 states. [2019-11-20 06:46:22,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 727 to 530. [2019-11-20 06:46:22,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 530 states. [2019-11-20 06:46:22,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 734 transitions. [2019-11-20 06:46:22,152 INFO L78 Accepts]: Start accepts. Automaton has 530 states and 734 transitions. Word has length 72 [2019-11-20 06:46:22,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:22,152 INFO L462 AbstractCegarLoop]: Abstraction has 530 states and 734 transitions. [2019-11-20 06:46:22,152 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 06:46:22,152 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 734 transitions. [2019-11-20 06:46:22,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-20 06:46:22,153 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:22,153 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:22,154 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:22,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:22,154 INFO L82 PathProgramCache]: Analyzing trace with hash -2083950892, now seen corresponding path program 1 times [2019-11-20 06:46:22,154 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:22,155 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262176575] [2019-11-20 06:46:22,155 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:22,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:22,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:22,195 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1262176575] [2019-11-20 06:46:22,196 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:22,196 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 06:46:22,196 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345328102] [2019-11-20 06:46:22,196 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 06:46:22,196 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:22,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 06:46:22,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:22,197 INFO L87 Difference]: Start difference. First operand 530 states and 734 transitions. Second operand 3 states. [2019-11-20 06:46:22,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:22,233 INFO L93 Difference]: Finished difference Result 909 states and 1264 transitions. [2019-11-20 06:46:22,234 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 06:46:22,234 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-20 06:46:22,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:22,237 INFO L225 Difference]: With dead ends: 909 [2019-11-20 06:46:22,237 INFO L226 Difference]: Without dead ends: 530 [2019-11-20 06:46:22,238 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:22,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 530 states. [2019-11-20 06:46:22,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 530 to 530. [2019-11-20 06:46:22,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 530 states. [2019-11-20 06:46:22,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 730 transitions. [2019-11-20 06:46:22,271 INFO L78 Accepts]: Start accepts. Automaton has 530 states and 730 transitions. Word has length 72 [2019-11-20 06:46:22,271 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:22,272 INFO L462 AbstractCegarLoop]: Abstraction has 530 states and 730 transitions. [2019-11-20 06:46:22,272 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 06:46:22,272 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 730 transitions. [2019-11-20 06:46:22,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-20 06:46:22,273 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:22,273 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:22,273 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:22,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:22,274 INFO L82 PathProgramCache]: Analyzing trace with hash 2070467794, now seen corresponding path program 1 times [2019-11-20 06:46:22,274 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:22,274 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219241212] [2019-11-20 06:46:22,274 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:22,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:22,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:22,312 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [219241212] [2019-11-20 06:46:22,312 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:22,313 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 06:46:22,313 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131940588] [2019-11-20 06:46:22,313 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 06:46:22,313 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:22,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 06:46:22,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:22,314 INFO L87 Difference]: Start difference. First operand 530 states and 730 transitions. Second operand 3 states. [2019-11-20 06:46:22,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:22,376 INFO L93 Difference]: Finished difference Result 1253 states and 1720 transitions. [2019-11-20 06:46:22,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 06:46:22,376 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-20 06:46:22,377 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:22,381 INFO L225 Difference]: With dead ends: 1253 [2019-11-20 06:46:22,381 INFO L226 Difference]: Without dead ends: 837 [2019-11-20 06:46:22,382 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:22,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 837 states. [2019-11-20 06:46:22,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 837 to 564. [2019-11-20 06:46:22,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 564 states. [2019-11-20 06:46:22,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 564 states to 564 states and 774 transitions. [2019-11-20 06:46:22,425 INFO L78 Accepts]: Start accepts. Automaton has 564 states and 774 transitions. Word has length 72 [2019-11-20 06:46:22,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:22,425 INFO L462 AbstractCegarLoop]: Abstraction has 564 states and 774 transitions. [2019-11-20 06:46:22,425 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 06:46:22,425 INFO L276 IsEmpty]: Start isEmpty. Operand 564 states and 774 transitions. [2019-11-20 06:46:22,426 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 06:46:22,426 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:22,427 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:22,427 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:22,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:22,427 INFO L82 PathProgramCache]: Analyzing trace with hash -1917205063, now seen corresponding path program 1 times [2019-11-20 06:46:22,427 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:22,428 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657089744] [2019-11-20 06:46:22,428 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:22,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:22,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:22,543 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [657089744] [2019-11-20 06:46:22,544 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:22,544 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 06:46:22,544 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451696234] [2019-11-20 06:46:22,544 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:46:22,544 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:22,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:46:22,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 06:46:22,545 INFO L87 Difference]: Start difference. First operand 564 states and 774 transitions. Second operand 6 states. [2019-11-20 06:46:22,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:22,888 INFO L93 Difference]: Finished difference Result 1770 states and 2483 transitions. [2019-11-20 06:46:22,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 06:46:22,889 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-11-20 06:46:22,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:22,896 INFO L225 Difference]: With dead ends: 1770 [2019-11-20 06:46:22,896 INFO L226 Difference]: Without dead ends: 1436 [2019-11-20 06:46:22,898 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-20 06:46:22,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1436 states. [2019-11-20 06:46:22,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1436 to 568. [2019-11-20 06:46:22,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 568 states. [2019-11-20 06:46:22,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 568 states to 568 states and 779 transitions. [2019-11-20 06:46:22,959 INFO L78 Accepts]: Start accepts. Automaton has 568 states and 779 transitions. Word has length 73 [2019-11-20 06:46:22,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:22,959 INFO L462 AbstractCegarLoop]: Abstraction has 568 states and 779 transitions. [2019-11-20 06:46:22,959 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:46:22,959 INFO L276 IsEmpty]: Start isEmpty. Operand 568 states and 779 transitions. [2019-11-20 06:46:22,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 06:46:22,960 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:22,960 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:22,961 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:22,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:22,961 INFO L82 PathProgramCache]: Analyzing trace with hash 197100160, now seen corresponding path program 1 times [2019-11-20 06:46:22,961 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:22,962 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536604980] [2019-11-20 06:46:22,962 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:22,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:23,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:23,058 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536604980] [2019-11-20 06:46:23,058 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:23,059 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 06:46:23,059 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1668903810] [2019-11-20 06:46:23,059 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 06:46:23,059 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:23,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 06:46:23,059 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:23,060 INFO L87 Difference]: Start difference. First operand 568 states and 779 transitions. Second operand 5 states. [2019-11-20 06:46:23,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:23,221 INFO L93 Difference]: Finished difference Result 888 states and 1239 transitions. [2019-11-20 06:46:23,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 06:46:23,222 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2019-11-20 06:46:23,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:23,226 INFO L225 Difference]: With dead ends: 888 [2019-11-20 06:46:23,226 INFO L226 Difference]: Without dead ends: 886 [2019-11-20 06:46:23,227 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-20 06:46:23,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886 states. [2019-11-20 06:46:23,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886 to 570. [2019-11-20 06:46:23,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 570 states. [2019-11-20 06:46:23,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 570 states to 570 states and 781 transitions. [2019-11-20 06:46:23,272 INFO L78 Accepts]: Start accepts. Automaton has 570 states and 781 transitions. Word has length 73 [2019-11-20 06:46:23,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:23,272 INFO L462 AbstractCegarLoop]: Abstraction has 570 states and 781 transitions. [2019-11-20 06:46:23,272 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 06:46:23,273 INFO L276 IsEmpty]: Start isEmpty. Operand 570 states and 781 transitions. [2019-11-20 06:46:23,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 06:46:23,274 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:23,274 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:23,274 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:23,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:23,274 INFO L82 PathProgramCache]: Analyzing trace with hash 2083582807, now seen corresponding path program 1 times [2019-11-20 06:46:23,275 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:23,275 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385352921] [2019-11-20 06:46:23,275 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:23,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:23,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:23,391 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385352921] [2019-11-20 06:46:23,391 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:23,391 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 06:46:23,392 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [894936530] [2019-11-20 06:46:23,392 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:46:23,392 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:23,393 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:46:23,393 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 06:46:23,393 INFO L87 Difference]: Start difference. First operand 570 states and 781 transitions. Second operand 6 states. [2019-11-20 06:46:23,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:23,972 INFO L93 Difference]: Finished difference Result 2037 states and 2828 transitions. [2019-11-20 06:46:23,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 06:46:23,972 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-11-20 06:46:23,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:23,981 INFO L225 Difference]: With dead ends: 2037 [2019-11-20 06:46:23,981 INFO L226 Difference]: Without dead ends: 1662 [2019-11-20 06:46:23,982 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-20 06:46:23,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1662 states. [2019-11-20 06:46:24,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1662 to 616. [2019-11-20 06:46:24,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 616 states. [2019-11-20 06:46:24,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 616 states to 616 states and 839 transitions. [2019-11-20 06:46:24,047 INFO L78 Accepts]: Start accepts. Automaton has 616 states and 839 transitions. Word has length 73 [2019-11-20 06:46:24,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:24,047 INFO L462 AbstractCegarLoop]: Abstraction has 616 states and 839 transitions. [2019-11-20 06:46:24,047 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:46:24,047 INFO L276 IsEmpty]: Start isEmpty. Operand 616 states and 839 transitions. [2019-11-20 06:46:24,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-20 06:46:24,050 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:24,050 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:24,051 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:24,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:24,051 INFO L82 PathProgramCache]: Analyzing trace with hash 1204676769, now seen corresponding path program 1 times [2019-11-20 06:46:24,051 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:24,052 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911548856] [2019-11-20 06:46:24,052 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:24,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:24,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:24,181 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911548856] [2019-11-20 06:46:24,181 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:24,181 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 06:46:24,181 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639977358] [2019-11-20 06:46:24,182 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:46:24,182 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:24,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:46:24,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 06:46:24,182 INFO L87 Difference]: Start difference. First operand 616 states and 839 transitions. Second operand 6 states. [2019-11-20 06:46:24,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:24,622 INFO L93 Difference]: Finished difference Result 2364 states and 3261 transitions. [2019-11-20 06:46:24,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 06:46:24,622 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-11-20 06:46:24,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:24,632 INFO L225 Difference]: With dead ends: 2364 [2019-11-20 06:46:24,633 INFO L226 Difference]: Without dead ends: 1981 [2019-11-20 06:46:24,634 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-20 06:46:24,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1981 states. [2019-11-20 06:46:24,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1981 to 694. [2019-11-20 06:46:24,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 694 states. [2019-11-20 06:46:24,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 694 states to 694 states and 941 transitions. [2019-11-20 06:46:24,703 INFO L78 Accepts]: Start accepts. Automaton has 694 states and 941 transitions. Word has length 74 [2019-11-20 06:46:24,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:24,704 INFO L462 AbstractCegarLoop]: Abstraction has 694 states and 941 transitions. [2019-11-20 06:46:24,704 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:46:24,704 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 941 transitions. [2019-11-20 06:46:24,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-20 06:46:24,705 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:24,705 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:24,705 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:24,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:24,706 INFO L82 PathProgramCache]: Analyzing trace with hash -217796256, now seen corresponding path program 1 times [2019-11-20 06:46:24,706 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:24,706 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44442457] [2019-11-20 06:46:24,706 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:24,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:24,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:24,781 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [44442457] [2019-11-20 06:46:24,781 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:24,781 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 06:46:24,781 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [179405257] [2019-11-20 06:46:24,782 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:46:24,782 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:24,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:46:24,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 06:46:24,782 INFO L87 Difference]: Start difference. First operand 694 states and 941 transitions. Second operand 6 states. [2019-11-20 06:46:24,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:24,983 INFO L93 Difference]: Finished difference Result 1560 states and 2200 transitions. [2019-11-20 06:46:24,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 06:46:24,984 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-11-20 06:46:24,984 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:24,990 INFO L225 Difference]: With dead ends: 1560 [2019-11-20 06:46:24,990 INFO L226 Difference]: Without dead ends: 1160 [2019-11-20 06:46:24,991 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-11-20 06:46:24,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1160 states. [2019-11-20 06:46:25,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1160 to 700. [2019-11-20 06:46:25,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 700 states. [2019-11-20 06:46:25,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 700 states to 700 states and 947 transitions. [2019-11-20 06:46:25,057 INFO L78 Accepts]: Start accepts. Automaton has 700 states and 947 transitions. Word has length 74 [2019-11-20 06:46:25,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:25,057 INFO L462 AbstractCegarLoop]: Abstraction has 700 states and 947 transitions. [2019-11-20 06:46:25,057 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:46:25,058 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 947 transitions. [2019-11-20 06:46:25,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-20 06:46:25,059 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:25,059 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:25,059 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:25,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:25,059 INFO L82 PathProgramCache]: Analyzing trace with hash -1278252476, now seen corresponding path program 1 times [2019-11-20 06:46:25,060 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:25,060 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963167713] [2019-11-20 06:46:25,060 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:25,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:25,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:25,103 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963167713] [2019-11-20 06:46:25,104 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:25,104 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 06:46:25,104 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526170722] [2019-11-20 06:46:25,105 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 06:46:25,105 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:25,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 06:46:25,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:25,106 INFO L87 Difference]: Start difference. First operand 700 states and 947 transitions. Second operand 3 states. [2019-11-20 06:46:25,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:25,215 INFO L93 Difference]: Finished difference Result 1374 states and 1891 transitions. [2019-11-20 06:46:25,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 06:46:25,215 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-11-20 06:46:25,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:25,220 INFO L225 Difference]: With dead ends: 1374 [2019-11-20 06:46:25,220 INFO L226 Difference]: Without dead ends: 905 [2019-11-20 06:46:25,222 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:25,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 905 states. [2019-11-20 06:46:25,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 905 to 679. [2019-11-20 06:46:25,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 679 states. [2019-11-20 06:46:25,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 679 states to 679 states and 910 transitions. [2019-11-20 06:46:25,321 INFO L78 Accepts]: Start accepts. Automaton has 679 states and 910 transitions. Word has length 74 [2019-11-20 06:46:25,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:25,322 INFO L462 AbstractCegarLoop]: Abstraction has 679 states and 910 transitions. [2019-11-20 06:46:25,322 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 06:46:25,322 INFO L276 IsEmpty]: Start isEmpty. Operand 679 states and 910 transitions. [2019-11-20 06:46:25,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-20 06:46:25,323 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:25,323 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:25,323 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:25,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:25,324 INFO L82 PathProgramCache]: Analyzing trace with hash -1698648942, now seen corresponding path program 1 times [2019-11-20 06:46:25,324 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:25,324 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078729756] [2019-11-20 06:46:25,324 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:25,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:25,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:25,384 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2078729756] [2019-11-20 06:46:25,384 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:25,384 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:25,384 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255461641] [2019-11-20 06:46:25,385 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 06:46:25,385 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:25,385 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 06:46:25,386 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:46:25,386 INFO L87 Difference]: Start difference. First operand 679 states and 910 transitions. Second operand 4 states. [2019-11-20 06:46:25,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:25,574 INFO L93 Difference]: Finished difference Result 1744 states and 2350 transitions. [2019-11-20 06:46:25,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:46:25,574 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-11-20 06:46:25,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:25,581 INFO L225 Difference]: With dead ends: 1744 [2019-11-20 06:46:25,581 INFO L226 Difference]: Without dead ends: 1328 [2019-11-20 06:46:25,583 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:25,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1328 states. [2019-11-20 06:46:25,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1328 to 923. [2019-11-20 06:46:25,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 923 states. [2019-11-20 06:46:25,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 923 states to 923 states and 1237 transitions. [2019-11-20 06:46:25,672 INFO L78 Accepts]: Start accepts. Automaton has 923 states and 1237 transitions. Word has length 75 [2019-11-20 06:46:25,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:25,672 INFO L462 AbstractCegarLoop]: Abstraction has 923 states and 1237 transitions. [2019-11-20 06:46:25,672 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 06:46:25,672 INFO L276 IsEmpty]: Start isEmpty. Operand 923 states and 1237 transitions. [2019-11-20 06:46:25,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-20 06:46:25,674 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:25,674 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:25,674 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:25,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:25,674 INFO L82 PathProgramCache]: Analyzing trace with hash -1596781464, now seen corresponding path program 1 times [2019-11-20 06:46:25,675 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:25,675 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445122612] [2019-11-20 06:46:25,675 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:25,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:25,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:25,738 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445122612] [2019-11-20 06:46:25,739 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:25,739 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 06:46:25,739 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763474293] [2019-11-20 06:46:25,739 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 06:46:25,739 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:25,739 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 06:46:25,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:25,740 INFO L87 Difference]: Start difference. First operand 923 states and 1237 transitions. Second operand 3 states. [2019-11-20 06:46:25,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:25,893 INFO L93 Difference]: Finished difference Result 1932 states and 2621 transitions. [2019-11-20 06:46:25,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 06:46:25,895 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2019-11-20 06:46:25,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:25,902 INFO L225 Difference]: With dead ends: 1932 [2019-11-20 06:46:25,902 INFO L226 Difference]: Without dead ends: 1327 [2019-11-20 06:46:25,903 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:25,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states. [2019-11-20 06:46:25,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 877. [2019-11-20 06:46:25,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 877 states. [2019-11-20 06:46:25,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 877 states to 877 states and 1171 transitions. [2019-11-20 06:46:25,990 INFO L78 Accepts]: Start accepts. Automaton has 877 states and 1171 transitions. Word has length 75 [2019-11-20 06:46:25,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:25,990 INFO L462 AbstractCegarLoop]: Abstraction has 877 states and 1171 transitions. [2019-11-20 06:46:25,990 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 06:46:25,990 INFO L276 IsEmpty]: Start isEmpty. Operand 877 states and 1171 transitions. [2019-11-20 06:46:25,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-20 06:46:25,991 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:25,991 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:25,992 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:25,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:25,992 INFO L82 PathProgramCache]: Analyzing trace with hash -216337278, now seen corresponding path program 1 times [2019-11-20 06:46:25,992 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:25,994 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41235427] [2019-11-20 06:46:25,994 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:26,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:26,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:26,047 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [41235427] [2019-11-20 06:46:26,048 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:26,048 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:26,048 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1916531636] [2019-11-20 06:46:26,048 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 06:46:26,050 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:26,050 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 06:46:26,050 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:46:26,051 INFO L87 Difference]: Start difference. First operand 877 states and 1171 transitions. Second operand 4 states. [2019-11-20 06:46:26,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:26,267 INFO L93 Difference]: Finished difference Result 2042 states and 2724 transitions. [2019-11-20 06:46:26,268 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:46:26,268 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-11-20 06:46:26,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:26,275 INFO L225 Difference]: With dead ends: 2042 [2019-11-20 06:46:26,275 INFO L226 Difference]: Without dead ends: 1466 [2019-11-20 06:46:26,277 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:26,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1466 states. [2019-11-20 06:46:26,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1466 to 1169. [2019-11-20 06:46:26,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1169 states. [2019-11-20 06:46:26,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1169 states to 1169 states and 1551 transitions. [2019-11-20 06:46:26,402 INFO L78 Accepts]: Start accepts. Automaton has 1169 states and 1551 transitions. Word has length 75 [2019-11-20 06:46:26,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:26,403 INFO L462 AbstractCegarLoop]: Abstraction has 1169 states and 1551 transitions. [2019-11-20 06:46:26,403 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 06:46:26,403 INFO L276 IsEmpty]: Start isEmpty. Operand 1169 states and 1551 transitions. [2019-11-20 06:46:26,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-11-20 06:46:26,405 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:26,405 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:26,405 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:26,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:26,406 INFO L82 PathProgramCache]: Analyzing trace with hash -1065252519, now seen corresponding path program 1 times [2019-11-20 06:46:26,406 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:26,406 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711224082] [2019-11-20 06:46:26,406 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:26,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:26,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:26,433 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1711224082] [2019-11-20 06:46:26,433 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:26,433 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 06:46:26,433 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549115876] [2019-11-20 06:46:26,434 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 06:46:26,434 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:26,435 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 06:46:26,435 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:26,435 INFO L87 Difference]: Start difference. First operand 1169 states and 1551 transitions. Second operand 3 states. [2019-11-20 06:46:26,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:26,737 INFO L93 Difference]: Finished difference Result 2882 states and 3817 transitions. [2019-11-20 06:46:26,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 06:46:26,737 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2019-11-20 06:46:26,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:26,747 INFO L225 Difference]: With dead ends: 2882 [2019-11-20 06:46:26,748 INFO L226 Difference]: Without dead ends: 1956 [2019-11-20 06:46:26,751 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 06:46:26,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1956 states. [2019-11-20 06:46:26,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1956 to 1171. [2019-11-20 06:46:26,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1171 states. [2019-11-20 06:46:26,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1171 states to 1171 states and 1553 transitions. [2019-11-20 06:46:26,909 INFO L78 Accepts]: Start accepts. Automaton has 1171 states and 1553 transitions. Word has length 76 [2019-11-20 06:46:26,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:26,909 INFO L462 AbstractCegarLoop]: Abstraction has 1171 states and 1553 transitions. [2019-11-20 06:46:26,910 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 06:46:26,910 INFO L276 IsEmpty]: Start isEmpty. Operand 1171 states and 1553 transitions. [2019-11-20 06:46:26,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2019-11-20 06:46:26,911 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:26,911 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:26,912 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:26,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:26,912 INFO L82 PathProgramCache]: Analyzing trace with hash -2019206059, now seen corresponding path program 1 times [2019-11-20 06:46:26,912 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:26,912 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924749261] [2019-11-20 06:46:26,913 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:26,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:26,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:26,975 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [924749261] [2019-11-20 06:46:26,975 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:26,975 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:26,976 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2116035622] [2019-11-20 06:46:26,976 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 06:46:26,976 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:26,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 06:46:26,977 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:46:26,977 INFO L87 Difference]: Start difference. First operand 1171 states and 1553 transitions. Second operand 4 states. [2019-11-20 06:46:27,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:27,166 INFO L93 Difference]: Finished difference Result 2437 states and 3225 transitions. [2019-11-20 06:46:27,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:46:27,167 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 77 [2019-11-20 06:46:27,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:27,173 INFO L225 Difference]: With dead ends: 2437 [2019-11-20 06:46:27,173 INFO L226 Difference]: Without dead ends: 1323 [2019-11-20 06:46:27,175 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:27,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1323 states. [2019-11-20 06:46:27,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1323 to 976. [2019-11-20 06:46:27,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 976 states. [2019-11-20 06:46:27,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 976 states to 976 states and 1289 transitions. [2019-11-20 06:46:27,289 INFO L78 Accepts]: Start accepts. Automaton has 976 states and 1289 transitions. Word has length 77 [2019-11-20 06:46:27,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:27,290 INFO L462 AbstractCegarLoop]: Abstraction has 976 states and 1289 transitions. [2019-11-20 06:46:27,290 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 06:46:27,290 INFO L276 IsEmpty]: Start isEmpty. Operand 976 states and 1289 transitions. [2019-11-20 06:46:27,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2019-11-20 06:46:27,291 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:27,291 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:27,292 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:27,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:27,292 INFO L82 PathProgramCache]: Analyzing trace with hash -113428458, now seen corresponding path program 1 times [2019-11-20 06:46:27,292 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:27,293 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142992551] [2019-11-20 06:46:27,293 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:27,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:27,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:27,362 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142992551] [2019-11-20 06:46:27,362 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:27,362 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:27,362 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1681186265] [2019-11-20 06:46:27,363 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 06:46:27,363 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:27,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 06:46:27,364 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:46:27,364 INFO L87 Difference]: Start difference. First operand 976 states and 1289 transitions. Second operand 4 states. [2019-11-20 06:46:27,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:27,556 INFO L93 Difference]: Finished difference Result 2242 states and 2971 transitions. [2019-11-20 06:46:27,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:46:27,556 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 78 [2019-11-20 06:46:27,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:27,563 INFO L225 Difference]: With dead ends: 2242 [2019-11-20 06:46:27,563 INFO L226 Difference]: Without dead ends: 1343 [2019-11-20 06:46:27,565 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:27,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1343 states. [2019-11-20 06:46:27,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1343 to 920. [2019-11-20 06:46:27,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. [2019-11-20 06:46:27,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1209 transitions. [2019-11-20 06:46:27,674 INFO L78 Accepts]: Start accepts. Automaton has 920 states and 1209 transitions. Word has length 78 [2019-11-20 06:46:27,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:27,674 INFO L462 AbstractCegarLoop]: Abstraction has 920 states and 1209 transitions. [2019-11-20 06:46:27,674 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 06:46:27,675 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1209 transitions. [2019-11-20 06:46:27,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2019-11-20 06:46:27,681 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:27,681 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:27,682 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:27,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:27,682 INFO L82 PathProgramCache]: Analyzing trace with hash 831151167, now seen corresponding path program 1 times [2019-11-20 06:46:27,682 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:27,683 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188497139] [2019-11-20 06:46:27,683 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:27,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:28,018 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:28,018 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1188497139] [2019-11-20 06:46:28,018 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [456660629] [2019-11-20 06:46:28,018 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:28,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:28,198 INFO L255 TraceCheckSpWp]: Trace formula consists of 727 conjuncts, 9 conjunts are in the unsatisfiable core [2019-11-20 06:46:28,208 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:46:28,298 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 06:46:28,299 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 06:46:28,299 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 06:46:28,299 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39395603] [2019-11-20 06:46:28,300 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:46:28,300 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:28,300 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:46:28,301 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-20 06:46:28,301 INFO L87 Difference]: Start difference. First operand 920 states and 1209 transitions. Second operand 6 states. [2019-11-20 06:46:28,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:28,726 INFO L93 Difference]: Finished difference Result 2836 states and 3898 transitions. [2019-11-20 06:46:28,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 06:46:28,726 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 122 [2019-11-20 06:46:28,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:28,748 INFO L225 Difference]: With dead ends: 2836 [2019-11-20 06:46:28,755 INFO L226 Difference]: Without dead ends: 2063 [2019-11-20 06:46:28,757 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 119 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-11-20 06:46:28,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2063 states. [2019-11-20 06:46:28,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2063 to 920. [2019-11-20 06:46:28,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. [2019-11-20 06:46:28,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1206 transitions. [2019-11-20 06:46:28,896 INFO L78 Accepts]: Start accepts. Automaton has 920 states and 1206 transitions. Word has length 122 [2019-11-20 06:46:28,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:28,896 INFO L462 AbstractCegarLoop]: Abstraction has 920 states and 1206 transitions. [2019-11-20 06:46:28,896 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:46:28,896 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1206 transitions. [2019-11-20 06:46:28,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2019-11-20 06:46:28,899 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:28,899 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:29,104 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:29,105 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:29,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:29,105 INFO L82 PathProgramCache]: Analyzing trace with hash -1351562886, now seen corresponding path program 1 times [2019-11-20 06:46:29,106 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:29,106 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208582608] [2019-11-20 06:46:29,106 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:29,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:29,461 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:29,461 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1208582608] [2019-11-20 06:46:29,461 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [593516237] [2019-11-20 06:46:29,461 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:29,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:29,644 INFO L255 TraceCheckSpWp]: Trace formula consists of 740 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-20 06:46:29,651 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:46:29,774 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 06:46:29,775 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 06:46:29,775 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 06:46:29,775 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [741937995] [2019-11-20 06:46:29,776 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:46:29,776 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:29,776 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:46:29,776 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=208, Unknown=0, NotChecked=0, Total=240 [2019-11-20 06:46:29,776 INFO L87 Difference]: Start difference. First operand 920 states and 1206 transitions. Second operand 6 states. [2019-11-20 06:46:30,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:30,214 INFO L93 Difference]: Finished difference Result 2541 states and 3449 transitions. [2019-11-20 06:46:30,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 06:46:30,214 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 126 [2019-11-20 06:46:30,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:30,218 INFO L225 Difference]: With dead ends: 2541 [2019-11-20 06:46:30,218 INFO L226 Difference]: Without dead ends: 1768 [2019-11-20 06:46:30,220 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 142 GetRequests, 123 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=56, Invalid=364, Unknown=0, NotChecked=0, Total=420 [2019-11-20 06:46:30,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1768 states. [2019-11-20 06:46:30,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1768 to 920. [2019-11-20 06:46:30,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. [2019-11-20 06:46:30,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1203 transitions. [2019-11-20 06:46:30,340 INFO L78 Accepts]: Start accepts. Automaton has 920 states and 1203 transitions. Word has length 126 [2019-11-20 06:46:30,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:30,340 INFO L462 AbstractCegarLoop]: Abstraction has 920 states and 1203 transitions. [2019-11-20 06:46:30,341 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:46:30,341 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1203 transitions. [2019-11-20 06:46:30,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2019-11-20 06:46:30,343 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:30,343 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:30,555 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:30,556 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:30,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:30,556 INFO L82 PathProgramCache]: Analyzing trace with hash -1119292744, now seen corresponding path program 1 times [2019-11-20 06:46:30,556 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:30,556 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080065499] [2019-11-20 06:46:30,557 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:30,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:30,883 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:30,884 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080065499] [2019-11-20 06:46:30,884 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [739179404] [2019-11-20 06:46:30,884 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:31,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:31,091 INFO L255 TraceCheckSpWp]: Trace formula consists of 752 conjuncts, 12 conjunts are in the unsatisfiable core [2019-11-20 06:46:31,104 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:46:31,223 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 06:46:31,223 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 06:46:31,224 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 06:46:31,224 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [459420603] [2019-11-20 06:46:31,224 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:46:31,225 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:31,225 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:46:31,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-20 06:46:31,227 INFO L87 Difference]: Start difference. First operand 920 states and 1203 transitions. Second operand 6 states. [2019-11-20 06:46:31,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:31,842 INFO L93 Difference]: Finished difference Result 2927 states and 4004 transitions. [2019-11-20 06:46:31,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 06:46:31,843 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 129 [2019-11-20 06:46:31,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:31,847 INFO L225 Difference]: With dead ends: 2927 [2019-11-20 06:46:31,847 INFO L226 Difference]: Without dead ends: 2141 [2019-11-20 06:46:31,849 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 129 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2019-11-20 06:46:31,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2141 states. [2019-11-20 06:46:31,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2141 to 868. [2019-11-20 06:46:31,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 868 states. [2019-11-20 06:46:31,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 868 states to 868 states and 1125 transitions. [2019-11-20 06:46:31,964 INFO L78 Accepts]: Start accepts. Automaton has 868 states and 1125 transitions. Word has length 129 [2019-11-20 06:46:31,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:31,965 INFO L462 AbstractCegarLoop]: Abstraction has 868 states and 1125 transitions. [2019-11-20 06:46:31,965 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:46:31,965 INFO L276 IsEmpty]: Start isEmpty. Operand 868 states and 1125 transitions. [2019-11-20 06:46:31,967 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2019-11-20 06:46:31,967 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:31,968 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:32,176 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:32,177 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:32,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:32,177 INFO L82 PathProgramCache]: Analyzing trace with hash 406746349, now seen corresponding path program 1 times [2019-11-20 06:46:32,177 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:32,177 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204335901] [2019-11-20 06:46:32,178 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:32,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:32,405 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:32,406 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204335901] [2019-11-20 06:46:32,406 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [81217581] [2019-11-20 06:46:32,406 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:32,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:32,588 INFO L255 TraceCheckSpWp]: Trace formula consists of 753 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-20 06:46:32,595 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:46:32,699 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-20 06:46:32,700 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 06:46:32,700 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [10] total 15 [2019-11-20 06:46:32,700 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [427464735] [2019-11-20 06:46:32,700 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:46:32,701 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:32,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:46:32,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=181, Unknown=0, NotChecked=0, Total=210 [2019-11-20 06:46:32,701 INFO L87 Difference]: Start difference. First operand 868 states and 1125 transitions. Second operand 6 states. [2019-11-20 06:46:33,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:33,068 INFO L93 Difference]: Finished difference Result 2257 states and 3062 transitions. [2019-11-20 06:46:33,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 06:46:33,069 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 130 [2019-11-20 06:46:33,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:33,072 INFO L225 Difference]: With dead ends: 2257 [2019-11-20 06:46:33,072 INFO L226 Difference]: Without dead ends: 1550 [2019-11-20 06:46:33,075 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=48, Invalid=294, Unknown=0, NotChecked=0, Total=342 [2019-11-20 06:46:33,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1550 states. [2019-11-20 06:46:33,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1550 to 868. [2019-11-20 06:46:33,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 868 states. [2019-11-20 06:46:33,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 868 states to 868 states and 1124 transitions. [2019-11-20 06:46:33,187 INFO L78 Accepts]: Start accepts. Automaton has 868 states and 1124 transitions. Word has length 130 [2019-11-20 06:46:33,188 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:33,188 INFO L462 AbstractCegarLoop]: Abstraction has 868 states and 1124 transitions. [2019-11-20 06:46:33,188 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:46:33,188 INFO L276 IsEmpty]: Start isEmpty. Operand 868 states and 1124 transitions. [2019-11-20 06:46:33,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-20 06:46:33,190 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:33,191 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:33,395 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:33,395 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:33,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:33,395 INFO L82 PathProgramCache]: Analyzing trace with hash 590291048, now seen corresponding path program 1 times [2019-11-20 06:46:33,396 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:33,396 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882906299] [2019-11-20 06:46:33,396 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:33,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:33,652 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:33,652 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882906299] [2019-11-20 06:46:33,652 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1653142700] [2019-11-20 06:46:33,653 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:33,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:33,835 INFO L255 TraceCheckSpWp]: Trace formula consists of 767 conjuncts, 45 conjunts are in the unsatisfiable core [2019-11-20 06:46:33,838 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:46:34,285 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:34,285 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 06:46:34,286 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-11-20 06:46:34,286 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922067296] [2019-11-20 06:46:34,288 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-20 06:46:34,289 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:34,289 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-20 06:46:34,289 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=354, Unknown=0, NotChecked=0, Total=420 [2019-11-20 06:46:34,289 INFO L87 Difference]: Start difference. First operand 868 states and 1124 transitions. Second operand 21 states. [2019-11-20 06:46:36,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:36,332 INFO L93 Difference]: Finished difference Result 2305 states and 3042 transitions. [2019-11-20 06:46:36,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-11-20 06:46:36,332 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 134 [2019-11-20 06:46:36,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:36,335 INFO L225 Difference]: With dead ends: 2305 [2019-11-20 06:46:36,336 INFO L226 Difference]: Without dead ends: 1604 [2019-11-20 06:46:36,338 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 120 SyntacticMatches, 4 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 392 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=376, Invalid=1516, Unknown=0, NotChecked=0, Total=1892 [2019-11-20 06:46:36,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1604 states. [2019-11-20 06:46:36,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1604 to 1037. [2019-11-20 06:46:36,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1037 states. [2019-11-20 06:46:36,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1037 states to 1037 states and 1339 transitions. [2019-11-20 06:46:36,468 INFO L78 Accepts]: Start accepts. Automaton has 1037 states and 1339 transitions. Word has length 134 [2019-11-20 06:46:36,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:36,468 INFO L462 AbstractCegarLoop]: Abstraction has 1037 states and 1339 transitions. [2019-11-20 06:46:36,468 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-20 06:46:36,468 INFO L276 IsEmpty]: Start isEmpty. Operand 1037 states and 1339 transitions. [2019-11-20 06:46:36,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-20 06:46:36,471 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:36,471 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:36,675 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:36,675 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:36,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:36,675 INFO L82 PathProgramCache]: Analyzing trace with hash -1443102998, now seen corresponding path program 1 times [2019-11-20 06:46:36,675 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:36,675 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873654559] [2019-11-20 06:46:36,675 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:36,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:36,724 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-20 06:46:36,724 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873654559] [2019-11-20 06:46:36,724 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:36,725 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:36,725 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262068203] [2019-11-20 06:46:36,725 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 06:46:36,725 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:36,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 06:46:36,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:46:36,726 INFO L87 Difference]: Start difference. First operand 1037 states and 1339 transitions. Second operand 4 states. [2019-11-20 06:46:37,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:37,064 INFO L93 Difference]: Finished difference Result 2513 states and 3271 transitions. [2019-11-20 06:46:37,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:46:37,064 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 134 [2019-11-20 06:46:37,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:37,067 INFO L225 Difference]: With dead ends: 2513 [2019-11-20 06:46:37,068 INFO L226 Difference]: Without dead ends: 1608 [2019-11-20 06:46:37,070 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:37,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1608 states. [2019-11-20 06:46:37,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1608 to 1069. [2019-11-20 06:46:37,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1069 states. [2019-11-20 06:46:37,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1069 states to 1069 states and 1367 transitions. [2019-11-20 06:46:37,221 INFO L78 Accepts]: Start accepts. Automaton has 1069 states and 1367 transitions. Word has length 134 [2019-11-20 06:46:37,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:37,221 INFO L462 AbstractCegarLoop]: Abstraction has 1069 states and 1367 transitions. [2019-11-20 06:46:37,221 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 06:46:37,221 INFO L276 IsEmpty]: Start isEmpty. Operand 1069 states and 1367 transitions. [2019-11-20 06:46:37,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-20 06:46:37,224 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:37,225 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:37,225 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:37,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:37,225 INFO L82 PathProgramCache]: Analyzing trace with hash -1719204498, now seen corresponding path program 1 times [2019-11-20 06:46:37,225 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:37,226 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808021442] [2019-11-20 06:46:37,226 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:37,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:37,357 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-20 06:46:37,357 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808021442] [2019-11-20 06:46:37,357 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:37,357 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:37,358 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852937309] [2019-11-20 06:46:37,358 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 06:46:37,358 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:37,359 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 06:46:37,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:37,359 INFO L87 Difference]: Start difference. First operand 1069 states and 1367 transitions. Second operand 5 states. [2019-11-20 06:46:37,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:37,662 INFO L93 Difference]: Finished difference Result 1931 states and 2505 transitions. [2019-11-20 06:46:37,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:46:37,662 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 134 [2019-11-20 06:46:37,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:37,664 INFO L225 Difference]: With dead ends: 1931 [2019-11-20 06:46:37,664 INFO L226 Difference]: Without dead ends: 994 [2019-11-20 06:46:37,666 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:46:37,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 994 states. [2019-11-20 06:46:37,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 994 to 994. [2019-11-20 06:46:37,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 994 states. [2019-11-20 06:46:37,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 994 states to 994 states and 1278 transitions. [2019-11-20 06:46:37,803 INFO L78 Accepts]: Start accepts. Automaton has 994 states and 1278 transitions. Word has length 134 [2019-11-20 06:46:37,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:37,803 INFO L462 AbstractCegarLoop]: Abstraction has 994 states and 1278 transitions. [2019-11-20 06:46:37,803 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 06:46:37,803 INFO L276 IsEmpty]: Start isEmpty. Operand 994 states and 1278 transitions. [2019-11-20 06:46:37,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-20 06:46:37,806 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:37,806 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:37,806 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:37,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:37,807 INFO L82 PathProgramCache]: Analyzing trace with hash 1616018719, now seen corresponding path program 1 times [2019-11-20 06:46:37,807 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:37,807 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277883360] [2019-11-20 06:46:37,807 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:37,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:38,022 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 16 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:38,028 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277883360] [2019-11-20 06:46:38,028 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1623111133] [2019-11-20 06:46:38,028 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:38,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:38,205 INFO L255 TraceCheckSpWp]: Trace formula consists of 768 conjuncts, 47 conjunts are in the unsatisfiable core [2019-11-20 06:46:38,208 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:46:38,508 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 26 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:38,509 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 06:46:38,509 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12] total 18 [2019-11-20 06:46:38,509 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899863981] [2019-11-20 06:46:38,510 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-11-20 06:46:38,510 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:38,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-11-20 06:46:38,511 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2019-11-20 06:46:38,511 INFO L87 Difference]: Start difference. First operand 994 states and 1278 transitions. Second operand 19 states. [2019-11-20 06:46:42,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:42,157 INFO L93 Difference]: Finished difference Result 3827 states and 4980 transitions. [2019-11-20 06:46:42,157 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2019-11-20 06:46:42,157 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 135 [2019-11-20 06:46:42,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:42,167 INFO L225 Difference]: With dead ends: 3827 [2019-11-20 06:46:42,168 INFO L226 Difference]: Without dead ends: 3020 [2019-11-20 06:46:42,172 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 224 GetRequests, 121 SyntacticMatches, 4 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3526 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1965, Invalid=8135, Unknown=0, NotChecked=0, Total=10100 [2019-11-20 06:46:42,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3020 states. [2019-11-20 06:46:42,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3020 to 1479. [2019-11-20 06:46:42,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1479 states. [2019-11-20 06:46:42,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1479 states to 1479 states and 1914 transitions. [2019-11-20 06:46:42,400 INFO L78 Accepts]: Start accepts. Automaton has 1479 states and 1914 transitions. Word has length 135 [2019-11-20 06:46:42,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:42,400 INFO L462 AbstractCegarLoop]: Abstraction has 1479 states and 1914 transitions. [2019-11-20 06:46:42,401 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-11-20 06:46:42,401 INFO L276 IsEmpty]: Start isEmpty. Operand 1479 states and 1914 transitions. [2019-11-20 06:46:42,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-20 06:46:42,403 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:42,404 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:42,607 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:42,607 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:42,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:42,608 INFO L82 PathProgramCache]: Analyzing trace with hash 1144223334, now seen corresponding path program 1 times [2019-11-20 06:46:42,608 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:42,608 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671204364] [2019-11-20 06:46:42,608 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:42,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:42,672 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-11-20 06:46:42,673 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671204364] [2019-11-20 06:46:42,673 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:42,673 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:42,673 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1998891336] [2019-11-20 06:46:42,674 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 06:46:42,674 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:42,674 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 06:46:42,674 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:46:42,675 INFO L87 Difference]: Start difference. First operand 1479 states and 1914 transitions. Second operand 4 states. [2019-11-20 06:46:42,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:42,947 INFO L93 Difference]: Finished difference Result 2656 states and 3470 transitions. [2019-11-20 06:46:42,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 06:46:42,948 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 136 [2019-11-20 06:46:42,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:42,951 INFO L225 Difference]: With dead ends: 2656 [2019-11-20 06:46:42,951 INFO L226 Difference]: Without dead ends: 1307 [2019-11-20 06:46:42,953 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:46:42,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1307 states. [2019-11-20 06:46:43,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1307 to 1307. [2019-11-20 06:46:43,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1307 states. [2019-11-20 06:46:43,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1307 states to 1307 states and 1679 transitions. [2019-11-20 06:46:43,141 INFO L78 Accepts]: Start accepts. Automaton has 1307 states and 1679 transitions. Word has length 136 [2019-11-20 06:46:43,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:43,141 INFO L462 AbstractCegarLoop]: Abstraction has 1307 states and 1679 transitions. [2019-11-20 06:46:43,141 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 06:46:43,141 INFO L276 IsEmpty]: Start isEmpty. Operand 1307 states and 1679 transitions. [2019-11-20 06:46:43,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-20 06:46:43,144 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:43,144 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:43,144 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:43,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:43,146 INFO L82 PathProgramCache]: Analyzing trace with hash 844297710, now seen corresponding path program 1 times [2019-11-20 06:46:43,146 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:43,146 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737299468] [2019-11-20 06:46:43,146 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:43,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:43,494 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:43,495 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1737299468] [2019-11-20 06:46:43,495 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1008642917] [2019-11-20 06:46:43,495 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:43,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:43,678 INFO L255 TraceCheckSpWp]: Trace formula consists of 779 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-20 06:46:43,681 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:46:43,809 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 06:46:43,810 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 06:46:43,810 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 06:46:43,810 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139172741] [2019-11-20 06:46:43,810 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:46:43,811 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:43,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:46:43,811 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=208, Unknown=0, NotChecked=0, Total=240 [2019-11-20 06:46:43,811 INFO L87 Difference]: Start difference. First operand 1307 states and 1679 transitions. Second operand 6 states. [2019-11-20 06:46:44,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:44,336 INFO L93 Difference]: Finished difference Result 4085 states and 5399 transitions. [2019-11-20 06:46:44,336 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 06:46:44,336 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 137 [2019-11-20 06:46:44,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:44,341 INFO L225 Difference]: With dead ends: 4085 [2019-11-20 06:46:44,342 INFO L226 Difference]: Without dead ends: 2945 [2019-11-20 06:46:44,344 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 153 GetRequests, 134 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=56, Invalid=364, Unknown=0, NotChecked=0, Total=420 [2019-11-20 06:46:44,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2945 states. [2019-11-20 06:46:44,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2945 to 1307. [2019-11-20 06:46:44,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1307 states. [2019-11-20 06:46:44,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1307 states to 1307 states and 1677 transitions. [2019-11-20 06:46:44,547 INFO L78 Accepts]: Start accepts. Automaton has 1307 states and 1677 transitions. Word has length 137 [2019-11-20 06:46:44,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:44,547 INFO L462 AbstractCegarLoop]: Abstraction has 1307 states and 1677 transitions. [2019-11-20 06:46:44,547 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:46:44,547 INFO L276 IsEmpty]: Start isEmpty. Operand 1307 states and 1677 transitions. [2019-11-20 06:46:44,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-20 06:46:44,551 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:44,552 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:44,763 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:44,764 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:44,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:44,764 INFO L82 PathProgramCache]: Analyzing trace with hash 2032965332, now seen corresponding path program 1 times [2019-11-20 06:46:44,765 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:44,765 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797223390] [2019-11-20 06:46:44,765 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:44,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:44,863 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-20 06:46:44,863 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [797223390] [2019-11-20 06:46:44,863 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:44,863 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 06:46:44,864 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045410798] [2019-11-20 06:46:44,864 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:46:44,864 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:44,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:46:44,865 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 06:46:44,865 INFO L87 Difference]: Start difference. First operand 1307 states and 1677 transitions. Second operand 6 states. [2019-11-20 06:46:45,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:45,641 INFO L93 Difference]: Finished difference Result 6856 states and 8970 transitions. [2019-11-20 06:46:45,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-11-20 06:46:45,641 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 137 [2019-11-20 06:46:45,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:45,649 INFO L225 Difference]: With dead ends: 6856 [2019-11-20 06:46:45,649 INFO L226 Difference]: Without dead ends: 5736 [2019-11-20 06:46:45,652 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2019-11-20 06:46:45,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5736 states. [2019-11-20 06:46:45,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5736 to 1649. [2019-11-20 06:46:45,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1649 states. [2019-11-20 06:46:45,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1649 states to 1649 states and 2077 transitions. [2019-11-20 06:46:45,958 INFO L78 Accepts]: Start accepts. Automaton has 1649 states and 2077 transitions. Word has length 137 [2019-11-20 06:46:45,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:45,959 INFO L462 AbstractCegarLoop]: Abstraction has 1649 states and 2077 transitions. [2019-11-20 06:46:45,959 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:46:45,959 INFO L276 IsEmpty]: Start isEmpty. Operand 1649 states and 2077 transitions. [2019-11-20 06:46:45,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2019-11-20 06:46:45,962 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:45,962 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:45,962 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:45,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:45,963 INFO L82 PathProgramCache]: Analyzing trace with hash -122865786, now seen corresponding path program 1 times [2019-11-20 06:46:45,963 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:45,963 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [630887854] [2019-11-20 06:46:45,963 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:46,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:46,355 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 15 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:46,355 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [630887854] [2019-11-20 06:46:46,355 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2103964557] [2019-11-20 06:46:46,355 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:46,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:46,525 INFO L255 TraceCheckSpWp]: Trace formula consists of 771 conjuncts, 25 conjunts are in the unsatisfiable core [2019-11-20 06:46:46,528 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:46:46,722 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 15 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:46,722 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 06:46:46,723 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 9] total 11 [2019-11-20 06:46:46,724 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591969074] [2019-11-20 06:46:46,725 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-11-20 06:46:46,725 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:46,725 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-11-20 06:46:46,725 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2019-11-20 06:46:46,725 INFO L87 Difference]: Start difference. First operand 1649 states and 2077 transitions. Second operand 12 states. [2019-11-20 06:46:48,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:48,069 INFO L93 Difference]: Finished difference Result 4818 states and 6122 transitions. [2019-11-20 06:46:48,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-11-20 06:46:48,069 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 139 [2019-11-20 06:46:48,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:48,073 INFO L225 Difference]: With dead ends: 4818 [2019-11-20 06:46:48,073 INFO L226 Difference]: Without dead ends: 3356 [2019-11-20 06:46:48,076 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 167 GetRequests, 129 SyntacticMatches, 7 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 256 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=278, Invalid=778, Unknown=0, NotChecked=0, Total=1056 [2019-11-20 06:46:48,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3356 states. [2019-11-20 06:46:48,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3356 to 1680. [2019-11-20 06:46:48,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1680 states. [2019-11-20 06:46:48,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1680 states to 1680 states and 2116 transitions. [2019-11-20 06:46:48,331 INFO L78 Accepts]: Start accepts. Automaton has 1680 states and 2116 transitions. Word has length 139 [2019-11-20 06:46:48,331 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:48,331 INFO L462 AbstractCegarLoop]: Abstraction has 1680 states and 2116 transitions. [2019-11-20 06:46:48,331 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-11-20 06:46:48,331 INFO L276 IsEmpty]: Start isEmpty. Operand 1680 states and 2116 transitions. [2019-11-20 06:46:48,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-11-20 06:46:48,335 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:48,335 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:48,539 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:48,539 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:48,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:48,540 INFO L82 PathProgramCache]: Analyzing trace with hash -982040414, now seen corresponding path program 1 times [2019-11-20 06:46:48,540 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:48,540 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870008600] [2019-11-20 06:46:48,540 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:48,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:48,905 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:48,905 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870008600] [2019-11-20 06:46:48,906 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [733358582] [2019-11-20 06:46:48,906 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:49,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:49,067 INFO L255 TraceCheckSpWp]: Trace formula consists of 791 conjuncts, 14 conjunts are in the unsatisfiable core [2019-11-20 06:46:49,070 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:46:49,150 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 8 proven. 33 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:49,151 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 06:46:49,151 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 7] total 17 [2019-11-20 06:46:49,151 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [362381993] [2019-11-20 06:46:49,151 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-11-20 06:46:49,151 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:49,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-11-20 06:46:49,152 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-11-20 06:46:49,152 INFO L87 Difference]: Start difference. First operand 1680 states and 2116 transitions. Second operand 17 states. [2019-11-20 06:46:55,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:55,989 INFO L93 Difference]: Finished difference Result 8464 states and 10895 transitions. [2019-11-20 06:46:55,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 128 states. [2019-11-20 06:46:55,989 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 140 [2019-11-20 06:46:55,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:55,994 INFO L225 Difference]: With dead ends: 8464 [2019-11-20 06:46:55,995 INFO L226 Difference]: Without dead ends: 6971 [2019-11-20 06:46:56,003 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 298 GetRequests, 158 SyntacticMatches, 0 SemanticMatches, 140 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8040 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=3885, Invalid=16137, Unknown=0, NotChecked=0, Total=20022 [2019-11-20 06:46:56,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6971 states. [2019-11-20 06:46:56,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6971 to 2239. [2019-11-20 06:46:56,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2239 states. [2019-11-20 06:46:56,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2239 states to 2239 states and 2790 transitions. [2019-11-20 06:46:56,405 INFO L78 Accepts]: Start accepts. Automaton has 2239 states and 2790 transitions. Word has length 140 [2019-11-20 06:46:56,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:56,405 INFO L462 AbstractCegarLoop]: Abstraction has 2239 states and 2790 transitions. [2019-11-20 06:46:56,405 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-11-20 06:46:56,405 INFO L276 IsEmpty]: Start isEmpty. Operand 2239 states and 2790 transitions. [2019-11-20 06:46:56,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-11-20 06:46:56,408 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:56,409 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:56,612 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:56,612 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:56,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:56,612 INFO L82 PathProgramCache]: Analyzing trace with hash 1504281713, now seen corresponding path program 1 times [2019-11-20 06:46:56,612 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:56,613 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560365225] [2019-11-20 06:46:56,613 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:56,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:56,792 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:56,792 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560365225] [2019-11-20 06:46:56,793 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1964973364] [2019-11-20 06:46:56,793 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:57,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:57,050 INFO L255 TraceCheckSpWp]: Trace formula consists of 773 conjuncts, 18 conjunts are in the unsatisfiable core [2019-11-20 06:46:57,052 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:46:57,086 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:46:57,086 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 06:46:57,087 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 8 [2019-11-20 06:46:57,087 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673309031] [2019-11-20 06:46:57,087 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-11-20 06:46:57,087 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:57,088 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-20 06:46:57,088 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-11-20 06:46:57,088 INFO L87 Difference]: Start difference. First operand 2239 states and 2790 transitions. Second operand 8 states. [2019-11-20 06:46:58,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:58,334 INFO L93 Difference]: Finished difference Result 7935 states and 10019 transitions. [2019-11-20 06:46:58,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-11-20 06:46:58,335 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 140 [2019-11-20 06:46:58,335 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:58,340 INFO L225 Difference]: With dead ends: 7935 [2019-11-20 06:46:58,340 INFO L226 Difference]: Without dead ends: 5946 [2019-11-20 06:46:58,344 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 144 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=129, Invalid=423, Unknown=0, NotChecked=0, Total=552 [2019-11-20 06:46:58,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5946 states. [2019-11-20 06:46:58,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5946 to 3391. [2019-11-20 06:46:58,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3391 states. [2019-11-20 06:46:58,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3391 states to 3391 states and 4245 transitions. [2019-11-20 06:46:58,892 INFO L78 Accepts]: Start accepts. Automaton has 3391 states and 4245 transitions. Word has length 140 [2019-11-20 06:46:58,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:46:58,893 INFO L462 AbstractCegarLoop]: Abstraction has 3391 states and 4245 transitions. [2019-11-20 06:46:58,893 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-11-20 06:46:58,893 INFO L276 IsEmpty]: Start isEmpty. Operand 3391 states and 4245 transitions. [2019-11-20 06:46:58,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-11-20 06:46:58,896 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:46:58,897 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:46:59,098 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:46:59,098 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:46:59,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:46:59,099 INFO L82 PathProgramCache]: Analyzing trace with hash 1622723187, now seen corresponding path program 1 times [2019-11-20 06:46:59,099 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:46:59,099 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161663690] [2019-11-20 06:46:59,099 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:46:59,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:46:59,159 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-20 06:46:59,160 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161663690] [2019-11-20 06:46:59,160 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:46:59,160 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:46:59,160 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615134579] [2019-11-20 06:46:59,161 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 06:46:59,162 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:46:59,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 06:46:59,163 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:46:59,163 INFO L87 Difference]: Start difference. First operand 3391 states and 4245 transitions. Second operand 4 states. [2019-11-20 06:46:59,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:46:59,682 INFO L93 Difference]: Finished difference Result 5881 states and 7429 transitions. [2019-11-20 06:46:59,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 06:46:59,682 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 140 [2019-11-20 06:46:59,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:46:59,684 INFO L225 Difference]: With dead ends: 5881 [2019-11-20 06:46:59,684 INFO L226 Difference]: Without dead ends: 2740 [2019-11-20 06:46:59,687 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:46:59,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2740 states. [2019-11-20 06:47:00,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2740 to 2728. [2019-11-20 06:47:00,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2728 states. [2019-11-20 06:47:00,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2728 states to 2728 states and 3407 transitions. [2019-11-20 06:47:00,071 INFO L78 Accepts]: Start accepts. Automaton has 2728 states and 3407 transitions. Word has length 140 [2019-11-20 06:47:00,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:47:00,071 INFO L462 AbstractCegarLoop]: Abstraction has 2728 states and 3407 transitions. [2019-11-20 06:47:00,071 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 06:47:00,072 INFO L276 IsEmpty]: Start isEmpty. Operand 2728 states and 3407 transitions. [2019-11-20 06:47:00,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2019-11-20 06:47:00,074 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:47:00,074 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:47:00,075 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:47:00,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:47:00,075 INFO L82 PathProgramCache]: Analyzing trace with hash -1882876842, now seen corresponding path program 1 times [2019-11-20 06:47:00,075 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:47:00,076 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998799480] [2019-11-20 06:47:00,076 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:47:00,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:47:00,205 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-20 06:47:00,205 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [998799480] [2019-11-20 06:47:00,206 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:47:00,206 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 06:47:00,206 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165955605] [2019-11-20 06:47:00,206 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 06:47:00,207 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:47:00,207 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 06:47:00,207 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 06:47:00,207 INFO L87 Difference]: Start difference. First operand 2728 states and 3407 transitions. Second operand 6 states. [2019-11-20 06:47:01,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:47:01,438 INFO L93 Difference]: Finished difference Result 9314 states and 11912 transitions. [2019-11-20 06:47:01,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 06:47:01,439 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 144 [2019-11-20 06:47:01,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:47:01,443 INFO L225 Difference]: With dead ends: 9314 [2019-11-20 06:47:01,444 INFO L226 Difference]: Without dead ends: 6856 [2019-11-20 06:47:01,446 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-20 06:47:01,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6856 states. [2019-11-20 06:47:01,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6856 to 2808. [2019-11-20 06:47:01,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2808 states. [2019-11-20 06:47:01,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2808 states to 2808 states and 3500 transitions. [2019-11-20 06:47:01,887 INFO L78 Accepts]: Start accepts. Automaton has 2808 states and 3500 transitions. Word has length 144 [2019-11-20 06:47:01,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:47:01,888 INFO L462 AbstractCegarLoop]: Abstraction has 2808 states and 3500 transitions. [2019-11-20 06:47:01,888 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 06:47:01,888 INFO L276 IsEmpty]: Start isEmpty. Operand 2808 states and 3500 transitions. [2019-11-20 06:47:01,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-11-20 06:47:01,890 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:47:01,890 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:47:01,891 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:47:01,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:47:01,892 INFO L82 PathProgramCache]: Analyzing trace with hash 27749283, now seen corresponding path program 1 times [2019-11-20 06:47:01,892 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:47:01,892 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158900984] [2019-11-20 06:47:01,892 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:47:01,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:47:01,940 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-11-20 06:47:01,941 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158900984] [2019-11-20 06:47:01,941 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 06:47:01,941 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 06:47:01,941 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2113240790] [2019-11-20 06:47:01,942 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 06:47:01,942 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:47:01,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 06:47:01,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 06:47:01,943 INFO L87 Difference]: Start difference. First operand 2808 states and 3500 transitions. Second operand 4 states. [2019-11-20 06:47:02,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:47:02,683 INFO L93 Difference]: Finished difference Result 7151 states and 8947 transitions. [2019-11-20 06:47:02,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:47:02,684 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 145 [2019-11-20 06:47:02,684 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:47:02,687 INFO L225 Difference]: With dead ends: 7151 [2019-11-20 06:47:02,687 INFO L226 Difference]: Without dead ends: 4491 [2019-11-20 06:47:02,689 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 06:47:02,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4491 states. [2019-11-20 06:47:03,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4491 to 2836. [2019-11-20 06:47:03,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2836 states. [2019-11-20 06:47:03,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2836 states to 2836 states and 3520 transitions. [2019-11-20 06:47:03,038 INFO L78 Accepts]: Start accepts. Automaton has 2836 states and 3520 transitions. Word has length 145 [2019-11-20 06:47:03,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:47:03,038 INFO L462 AbstractCegarLoop]: Abstraction has 2836 states and 3520 transitions. [2019-11-20 06:47:03,038 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 06:47:03,038 INFO L276 IsEmpty]: Start isEmpty. Operand 2836 states and 3520 transitions. [2019-11-20 06:47:03,041 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-11-20 06:47:03,041 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:47:03,041 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:47:03,042 INFO L410 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:47:03,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:47:03,042 INFO L82 PathProgramCache]: Analyzing trace with hash 1387605663, now seen corresponding path program 1 times [2019-11-20 06:47:03,042 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:47:03,042 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116748450] [2019-11-20 06:47:03,043 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:47:03,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:47:03,140 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 41 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:47:03,141 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116748450] [2019-11-20 06:47:03,141 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1956960003] [2019-11-20 06:47:03,141 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:47:03,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:47:03,302 INFO L255 TraceCheckSpWp]: Trace formula consists of 798 conjuncts, 5 conjunts are in the unsatisfiable core [2019-11-20 06:47:03,304 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:47:03,343 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-11-20 06:47:03,344 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 06:47:03,344 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 10 [2019-11-20 06:47:03,344 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1687485804] [2019-11-20 06:47:03,344 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 06:47:03,344 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:47:03,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 06:47:03,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-11-20 06:47:03,345 INFO L87 Difference]: Start difference. First operand 2836 states and 3520 transitions. Second operand 5 states. [2019-11-20 06:47:03,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:47:03,727 INFO L93 Difference]: Finished difference Result 5372 states and 6705 transitions. [2019-11-20 06:47:03,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 06:47:03,728 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 145 [2019-11-20 06:47:03,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:47:03,729 INFO L225 Difference]: With dead ends: 5372 [2019-11-20 06:47:03,730 INFO L226 Difference]: Without dead ends: 2615 [2019-11-20 06:47:03,732 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-11-20 06:47:03,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2615 states. [2019-11-20 06:47:04,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2615 to 2615. [2019-11-20 06:47:04,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2615 states. [2019-11-20 06:47:04,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2615 states to 2615 states and 3261 transitions. [2019-11-20 06:47:04,117 INFO L78 Accepts]: Start accepts. Automaton has 2615 states and 3261 transitions. Word has length 145 [2019-11-20 06:47:04,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:47:04,117 INFO L462 AbstractCegarLoop]: Abstraction has 2615 states and 3261 transitions. [2019-11-20 06:47:04,117 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 06:47:04,117 INFO L276 IsEmpty]: Start isEmpty. Operand 2615 states and 3261 transitions. [2019-11-20 06:47:04,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-11-20 06:47:04,119 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:47:04,119 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:47:04,319 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:47:04,319 INFO L410 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:47:04,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:47:04,320 INFO L82 PathProgramCache]: Analyzing trace with hash 439953908, now seen corresponding path program 1 times [2019-11-20 06:47:04,320 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:47:04,320 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697559486] [2019-11-20 06:47:04,320 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:47:04,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:47:04,529 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 17 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:47:04,529 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697559486] [2019-11-20 06:47:04,530 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [843274262] [2019-11-20 06:47:04,530 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:47:04,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 06:47:04,722 INFO L255 TraceCheckSpWp]: Trace formula consists of 787 conjuncts, 14 conjunts are in the unsatisfiable core [2019-11-20 06:47:04,725 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 06:47:04,803 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 17 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 06:47:04,803 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 06:47:04,804 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2019-11-20 06:47:04,804 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202713222] [2019-11-20 06:47:04,804 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-20 06:47:04,804 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 06:47:04,805 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-20 06:47:04,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-11-20 06:47:04,805 INFO L87 Difference]: Start difference. First operand 2615 states and 3261 transitions. Second operand 7 states. [2019-11-20 06:47:06,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 06:47:06,014 INFO L93 Difference]: Finished difference Result 7727 states and 9807 transitions. [2019-11-20 06:47:06,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-11-20 06:47:06,014 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 145 [2019-11-20 06:47:06,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 06:47:06,019 INFO L225 Difference]: With dead ends: 7727 [2019-11-20 06:47:06,019 INFO L226 Difference]: Without dead ends: 5319 [2019-11-20 06:47:06,023 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 150 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=138, Invalid=324, Unknown=0, NotChecked=0, Total=462 [2019-11-20 06:47:06,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5319 states. [2019-11-20 06:47:06,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5319 to 2615. [2019-11-20 06:47:06,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2615 states. [2019-11-20 06:47:06,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2615 states to 2615 states and 3237 transitions. [2019-11-20 06:47:06,369 INFO L78 Accepts]: Start accepts. Automaton has 2615 states and 3237 transitions. Word has length 145 [2019-11-20 06:47:06,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 06:47:06,369 INFO L462 AbstractCegarLoop]: Abstraction has 2615 states and 3237 transitions. [2019-11-20 06:47:06,369 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-20 06:47:06,369 INFO L276 IsEmpty]: Start isEmpty. Operand 2615 states and 3237 transitions. [2019-11-20 06:47:06,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-11-20 06:47:06,371 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 06:47:06,371 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 06:47:06,575 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 06:47:06,576 INFO L410 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 06:47:06,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 06:47:06,576 INFO L82 PathProgramCache]: Analyzing trace with hash -372990953, now seen corresponding path program 1 times [2019-11-20 06:47:06,576 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 06:47:06,576 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793002057] [2019-11-20 06:47:06,576 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 06:47:06,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 06:47:06,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 06:47:06,776 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 06:47:06,776 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-20 06:47:06,973 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 20.11 06:47:06 BoogieIcfgContainer [2019-11-20 06:47:06,973 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-20 06:47:06,974 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-20 06:47:06,974 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-20 06:47:06,974 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-20 06:47:06,975 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 06:46:18" (3/4) ... [2019-11-20 06:47:06,977 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-20 06:47:07,195 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_2d1698bf-2091-47d7-afbe-a21148fd3bd0/bin/uautomizer/witness.graphml [2019-11-20 06:47:07,196 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-20 06:47:07,198 INFO L168 Benchmark]: Toolchain (without parser) took 51105.04 ms. Allocated memory was 1.0 GB in the beginning and 2.5 GB in the end (delta: 1.5 GB). Free memory was 950.1 MB in the beginning and 1.1 GB in the end (delta: -137.8 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2019-11-20 06:47:07,198 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 06:47:07,199 INFO L168 Benchmark]: CACSL2BoogieTranslator took 505.85 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 165.2 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -204.6 MB). Peak memory consumption was 17.7 MB. Max. memory is 11.5 GB. [2019-11-20 06:47:07,199 INFO L168 Benchmark]: Boogie Procedure Inliner took 87.23 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.4 MB). Peak memory consumption was 6.4 MB. Max. memory is 11.5 GB. [2019-11-20 06:47:07,200 INFO L168 Benchmark]: Boogie Preprocessor took 94.11 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 06:47:07,200 INFO L168 Benchmark]: RCFGBuilder took 1260.84 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 91.0 MB). Peak memory consumption was 91.0 MB. Max. memory is 11.5 GB. [2019-11-20 06:47:07,200 INFO L168 Benchmark]: TraceAbstraction took 48930.69 ms. Allocated memory was 1.2 GB in the beginning and 2.5 GB in the end (delta: 1.3 GB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -78.2 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2019-11-20 06:47:07,201 INFO L168 Benchmark]: Witness Printer took 222.19 ms. Allocated memory is still 2.5 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 42.2 MB). Peak memory consumption was 42.2 MB. Max. memory is 11.5 GB. [2019-11-20 06:47:07,203 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 505.85 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 165.2 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -204.6 MB). Peak memory consumption was 17.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 87.23 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.4 MB). Peak memory consumption was 6.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 94.11 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 1260.84 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 91.0 MB). Peak memory consumption was 91.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 48930.69 ms. Allocated memory was 1.2 GB in the beginning and 2.5 GB in the end (delta: 1.3 GB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -78.2 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. * Witness Printer took 222.19 ms. Allocated memory is still 2.5 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 42.2 MB). Peak memory consumption was 42.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 662]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L463] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L585] int c1 ; [L586] int i2 ; [L589] c1 = 0 [L590] side1Failed = __VERIFIER_nondet_bool() [L591] side2Failed = __VERIFIER_nondet_bool() [L592] side1_written = __VERIFIER_nondet_char() [L593] side2_written = __VERIFIER_nondet_char() [L594] side1Failed_History_0 = __VERIFIER_nondet_bool() [L595] side1Failed_History_1 = __VERIFIER_nondet_bool() [L596] side1Failed_History_2 = __VERIFIER_nondet_bool() [L597] side2Failed_History_0 = __VERIFIER_nondet_bool() [L598] side2Failed_History_1 = __VERIFIER_nondet_bool() [L599] side2Failed_History_2 = __VERIFIER_nondet_bool() [L600] active_side_History_0 = __VERIFIER_nondet_char() [L601] active_side_History_1 = __VERIFIER_nondet_char() [L602] active_side_History_2 = __VERIFIER_nondet_char() [L603] manual_selection_History_0 = __VERIFIER_nondet_char() [L604] manual_selection_History_1 = __VERIFIER_nondet_char() [L605] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L606] i2 = init() [L608] cs1_old = nomsg [L609] cs1_new = nomsg [L610] cs2_old = nomsg [L611] cs2_new = nomsg [L612] s1s2_old = nomsg [L613] s1s2_new = nomsg [L614] s1s1_old = nomsg [L615] s1s1_new = nomsg [L616] s2s1_old = nomsg [L617] s2s1_new = nomsg [L618] s2s2_old = nomsg [L619] s2s2_new = nomsg [L620] s1p_old = nomsg [L621] s1p_new = nomsg [L622] s2p_old = nomsg [L623] s2p_new = nomsg [L624] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND FALSE !((int )side2 == 0) [L454] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L501] tmp___1 = read_side1_failed_history((unsigned char)1) [L502] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L503] tmp___2 = read_side1_failed_history((unsigned char)0) [L504] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L545] tmp___11 = read_side1_failed_history((unsigned char)1) [L546] COND TRUE ! tmp___11 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L547] tmp___12 = read_side2_failed_history((unsigned char)1) [L548] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L561] tmp___20 = read_active_side_history((unsigned char)2) [L562] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L580] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L660] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L649] i2 ++ VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L392] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L393] COND TRUE (int )side2 != (int )nomsg [L394] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND TRUE (int )side2 == 0 [L452] active_side = (int8_t )2 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND FALSE !(! tmp___0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND TRUE \read(tmp___7) [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L531] tmp___8 = read_side2_failed_history((unsigned char)1) [L532] COND TRUE ! tmp___8 [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L533] tmp___5 = read_active_side_history((unsigned char)0) [L534] COND FALSE !(! ((int )tmp___5 == 2)) [L160] COND TRUE (int )index == 0 [L161] return (side2Failed_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] tmp___6 = read_side2_failed_history((unsigned char)0) [L538] COND TRUE ! tmp___6 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L539] COND TRUE ! ((int )side2_written == 1) [L540] return (0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L660] COND TRUE ! arg VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L662] __VERIFIER_error() VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 293 locations, 23 error locations. Result: UNSAFE, OverallTime: 48.8s, OverallIterations: 46, TraceHistogramMax: 2, AutomataDifference: 28.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 20637 SDtfs, 43165 SDslu, 53254 SDs, 0 SdLazy, 10392 SolverSat, 622 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 7.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2329 GetRequests, 1700 SyntacticMatches, 29 SemanticMatches, 600 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12786 ImplicationChecksByTransitivity, 11.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3391occurred in iteration=40, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 6.4s AutomataMinimizationTime, 45 MinimizatonAttempts, 39349 StatesRemovedByMinimization, 40 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.7s SsaConstructionTime, 2.4s SatisfiabilityAnalysisTime, 6.0s InterpolantComputationTime, 6060 NumberOfCodeBlocks, 6060 NumberOfCodeBlocksAsserted, 58 NumberOfCheckSat, 5858 ConstructedInterpolants, 0 QuantifiedInterpolants, 2923532 SizeOfPredicates, 60 NumberOfNonLiveVariables, 9206 ConjunctsInSsa, 213 ConjunctsInUnsatCore, 57 InterpolantComputations, 39 PerfectInterpolantSequences, 915/1156 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...