./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 678e0110 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c -s /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bd3b02b89b8fe5eebc8d5c8d901354afb3132de1 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-678e011 [2019-11-20 07:00:39,265 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-20 07:00:39,267 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-20 07:00:39,281 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-20 07:00:39,282 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-20 07:00:39,283 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-20 07:00:39,285 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-20 07:00:39,293 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-20 07:00:39,298 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-20 07:00:39,302 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-20 07:00:39,304 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-20 07:00:39,305 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-20 07:00:39,305 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-20 07:00:39,307 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-20 07:00:39,308 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-20 07:00:39,309 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-20 07:00:39,310 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-20 07:00:39,311 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-20 07:00:39,314 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-20 07:00:39,317 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-20 07:00:39,321 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-20 07:00:39,323 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-20 07:00:39,326 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-20 07:00:39,327 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-20 07:00:39,330 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-20 07:00:39,330 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-20 07:00:39,330 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-20 07:00:39,332 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-20 07:00:39,332 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-20 07:00:39,333 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-20 07:00:39,333 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-20 07:00:39,334 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-20 07:00:39,335 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-20 07:00:39,336 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-20 07:00:39,338 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-20 07:00:39,338 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-20 07:00:39,339 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-20 07:00:39,339 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-20 07:00:39,339 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-20 07:00:39,340 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-20 07:00:39,341 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-20 07:00:39,342 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-20 07:00:39,369 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-20 07:00:39,380 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-20 07:00:39,382 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-20 07:00:39,382 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-20 07:00:39,382 INFO L138 SettingsManager]: * Use SBE=true [2019-11-20 07:00:39,383 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-20 07:00:39,383 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-20 07:00:39,383 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-20 07:00:39,383 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-20 07:00:39,384 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-20 07:00:39,384 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-20 07:00:39,384 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-20 07:00:39,384 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-20 07:00:39,385 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-20 07:00:39,385 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-20 07:00:39,385 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-20 07:00:39,385 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-20 07:00:39,386 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-20 07:00:39,386 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-20 07:00:39,386 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-20 07:00:39,386 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-20 07:00:39,387 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 07:00:39,387 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-20 07:00:39,387 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-20 07:00:39,388 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-20 07:00:39,388 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-20 07:00:39,389 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-20 07:00:39,389 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-20 07:00:39,390 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bd3b02b89b8fe5eebc8d5c8d901354afb3132de1 [2019-11-20 07:00:39,575 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-20 07:00:39,592 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-20 07:00:39,595 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-20 07:00:39,596 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-20 07:00:39,597 INFO L275 PluginConnector]: CDTParser initialized [2019-11-20 07:00:39,598 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2019-11-20 07:00:39,663 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/data/1dfde90be/de123bdf104945faa60cecd06165eaca/FLAG68c518160 [2019-11-20 07:00:40,141 INFO L306 CDTParser]: Found 1 translation units. [2019-11-20 07:00:40,148 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2019-11-20 07:00:40,160 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/data/1dfde90be/de123bdf104945faa60cecd06165eaca/FLAG68c518160 [2019-11-20 07:00:40,542 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/data/1dfde90be/de123bdf104945faa60cecd06165eaca [2019-11-20 07:00:40,545 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-20 07:00:40,550 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-20 07:00:40,551 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-20 07:00:40,551 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-20 07:00:40,554 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-20 07:00:40,558 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 07:00:40" (1/1) ... [2019-11-20 07:00:40,561 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@819eacd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:40, skipping insertion in model container [2019-11-20 07:00:40,564 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 07:00:40" (1/1) ... [2019-11-20 07:00:40,571 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-20 07:00:40,610 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-20 07:00:40,978 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 07:00:40,987 INFO L188 MainTranslator]: Completed pre-run [2019-11-20 07:00:41,100 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 07:00:41,125 INFO L192 MainTranslator]: Completed translation [2019-11-20 07:00:41,125 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41 WrapperNode [2019-11-20 07:00:41,125 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-20 07:00:41,126 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-20 07:00:41,126 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-20 07:00:41,126 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-20 07:00:41,133 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41" (1/1) ... [2019-11-20 07:00:41,144 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41" (1/1) ... [2019-11-20 07:00:41,196 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-20 07:00:41,197 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-20 07:00:41,197 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-20 07:00:41,197 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-20 07:00:41,206 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41" (1/1) ... [2019-11-20 07:00:41,206 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41" (1/1) ... [2019-11-20 07:00:41,214 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41" (1/1) ... [2019-11-20 07:00:41,214 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41" (1/1) ... [2019-11-20 07:00:41,247 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41" (1/1) ... [2019-11-20 07:00:41,271 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41" (1/1) ... [2019-11-20 07:00:41,277 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41" (1/1) ... [2019-11-20 07:00:41,296 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-20 07:00:41,297 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-20 07:00:41,297 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-20 07:00:41,297 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-20 07:00:41,298 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 07:00:41,374 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-20 07:00:41,374 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-20 07:00:42,587 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-20 07:00:42,587 INFO L285 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-20 07:00:42,589 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 07:00:42 BoogieIcfgContainer [2019-11-20 07:00:42,589 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-20 07:00:42,590 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-20 07:00:42,590 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-20 07:00:42,594 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-20 07:00:42,594 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.11 07:00:40" (1/3) ... [2019-11-20 07:00:42,597 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4ef5d3cb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 07:00:42, skipping insertion in model container [2019-11-20 07:00:42,598 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 07:00:41" (2/3) ... [2019-11-20 07:00:42,598 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4ef5d3cb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 07:00:42, skipping insertion in model container [2019-11-20 07:00:42,598 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 07:00:42" (3/3) ... [2019-11-20 07:00:42,600 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2019-11-20 07:00:42,611 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-20 07:00:42,623 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-11-20 07:00:42,635 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-11-20 07:00:42,663 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-20 07:00:42,663 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-20 07:00:42,664 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-20 07:00:42,664 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-20 07:00:42,664 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-20 07:00:42,664 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-20 07:00:42,664 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-20 07:00:42,664 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-20 07:00:42,695 INFO L276 IsEmpty]: Start isEmpty. Operand 292 states. [2019-11-20 07:00:42,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-11-20 07:00:42,702 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:42,703 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:42,704 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:42,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:42,710 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-11-20 07:00:42,716 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:42,717 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396221111] [2019-11-20 07:00:42,717 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:42,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:42,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:42,917 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396221111] [2019-11-20 07:00:42,918 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:42,918 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 07:00:42,924 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589566900] [2019-11-20 07:00:42,928 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 07:00:42,929 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:42,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 07:00:42,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:42,950 INFO L87 Difference]: Start difference. First operand 292 states. Second operand 3 states. [2019-11-20 07:00:43,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:43,088 INFO L93 Difference]: Finished difference Result 566 states and 887 transitions. [2019-11-20 07:00:43,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 07:00:43,090 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-11-20 07:00:43,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:43,119 INFO L225 Difference]: With dead ends: 566 [2019-11-20 07:00:43,119 INFO L226 Difference]: Without dead ends: 288 [2019-11-20 07:00:43,136 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:43,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2019-11-20 07:00:43,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2019-11-20 07:00:43,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 288 states. [2019-11-20 07:00:43,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 412 transitions. [2019-11-20 07:00:43,194 INFO L78 Accepts]: Start accepts. Automaton has 288 states and 412 transitions. Word has length 31 [2019-11-20 07:00:43,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:43,195 INFO L462 AbstractCegarLoop]: Abstraction has 288 states and 412 transitions. [2019-11-20 07:00:43,195 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 07:00:43,195 INFO L276 IsEmpty]: Start isEmpty. Operand 288 states and 412 transitions. [2019-11-20 07:00:43,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-11-20 07:00:43,196 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:43,197 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:43,197 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:43,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:43,198 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-11-20 07:00:43,198 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:43,198 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587991903] [2019-11-20 07:00:43,198 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:43,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:43,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:43,419 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1587991903] [2019-11-20 07:00:43,419 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:43,420 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 07:00:43,420 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053985143] [2019-11-20 07:00:43,421 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 07:00:43,422 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:43,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 07:00:43,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:43,422 INFO L87 Difference]: Start difference. First operand 288 states and 412 transitions. Second operand 3 states. [2019-11-20 07:00:43,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:43,493 INFO L93 Difference]: Finished difference Result 594 states and 858 transitions. [2019-11-20 07:00:43,494 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 07:00:43,494 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-11-20 07:00:43,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:43,497 INFO L225 Difference]: With dead ends: 594 [2019-11-20 07:00:43,497 INFO L226 Difference]: Without dead ends: 321 [2019-11-20 07:00:43,499 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:43,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2019-11-20 07:00:43,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 264. [2019-11-20 07:00:43,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 264 states. [2019-11-20 07:00:43,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 264 states to 264 states and 376 transitions. [2019-11-20 07:00:43,522 INFO L78 Accepts]: Start accepts. Automaton has 264 states and 376 transitions. Word has length 42 [2019-11-20 07:00:43,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:43,523 INFO L462 AbstractCegarLoop]: Abstraction has 264 states and 376 transitions. [2019-11-20 07:00:43,523 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 07:00:43,523 INFO L276 IsEmpty]: Start isEmpty. Operand 264 states and 376 transitions. [2019-11-20 07:00:43,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-20 07:00:43,525 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:43,525 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:43,526 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:43,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:43,526 INFO L82 PathProgramCache]: Analyzing trace with hash 1273755287, now seen corresponding path program 1 times [2019-11-20 07:00:43,526 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:43,527 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873626939] [2019-11-20 07:00:43,527 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:43,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:43,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:43,665 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873626939] [2019-11-20 07:00:43,665 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:43,666 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 07:00:43,666 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1693016953] [2019-11-20 07:00:43,666 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 07:00:43,667 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:43,667 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 07:00:43,667 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:43,667 INFO L87 Difference]: Start difference. First operand 264 states and 376 transitions. Second operand 3 states. [2019-11-20 07:00:43,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:43,721 INFO L93 Difference]: Finished difference Result 739 states and 1063 transitions. [2019-11-20 07:00:43,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 07:00:43,722 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-20 07:00:43,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:43,730 INFO L225 Difference]: With dead ends: 739 [2019-11-20 07:00:43,730 INFO L226 Difference]: Without dead ends: 490 [2019-11-20 07:00:43,732 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:43,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490 states. [2019-11-20 07:00:43,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490 to 299. [2019-11-20 07:00:43,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 299 states. [2019-11-20 07:00:43,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 299 states to 299 states and 428 transitions. [2019-11-20 07:00:43,782 INFO L78 Accepts]: Start accepts. Automaton has 299 states and 428 transitions. Word has length 49 [2019-11-20 07:00:43,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:43,783 INFO L462 AbstractCegarLoop]: Abstraction has 299 states and 428 transitions. [2019-11-20 07:00:43,784 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 07:00:43,784 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 428 transitions. [2019-11-20 07:00:43,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-11-20 07:00:43,797 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:43,797 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:43,798 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:43,798 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:43,798 INFO L82 PathProgramCache]: Analyzing trace with hash -1910840580, now seen corresponding path program 1 times [2019-11-20 07:00:43,798 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:43,798 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059454113] [2019-11-20 07:00:43,799 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:43,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:43,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:43,934 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059454113] [2019-11-20 07:00:43,935 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:43,935 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:00:43,935 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2110738442] [2019-11-20 07:00:43,936 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 07:00:43,937 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:43,937 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 07:00:43,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:43,938 INFO L87 Difference]: Start difference. First operand 299 states and 428 transitions. Second operand 5 states. [2019-11-20 07:00:44,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:44,407 INFO L93 Difference]: Finished difference Result 939 states and 1357 transitions. [2019-11-20 07:00:44,408 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 07:00:44,408 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-11-20 07:00:44,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:44,415 INFO L225 Difference]: With dead ends: 939 [2019-11-20 07:00:44,415 INFO L226 Difference]: Without dead ends: 655 [2019-11-20 07:00:44,417 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-20 07:00:44,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 655 states. [2019-11-20 07:00:44,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 655 to 385. [2019-11-20 07:00:44,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 385 states. [2019-11-20 07:00:44,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385 states to 385 states and 551 transitions. [2019-11-20 07:00:44,449 INFO L78 Accepts]: Start accepts. Automaton has 385 states and 551 transitions. Word has length 50 [2019-11-20 07:00:44,451 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:44,451 INFO L462 AbstractCegarLoop]: Abstraction has 385 states and 551 transitions. [2019-11-20 07:00:44,451 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 07:00:44,451 INFO L276 IsEmpty]: Start isEmpty. Operand 385 states and 551 transitions. [2019-11-20 07:00:44,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-11-20 07:00:44,459 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:44,459 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:44,459 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:44,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:44,460 INFO L82 PathProgramCache]: Analyzing trace with hash -1041102253, now seen corresponding path program 1 times [2019-11-20 07:00:44,460 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:44,460 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613385111] [2019-11-20 07:00:44,460 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:44,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:44,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:44,604 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613385111] [2019-11-20 07:00:44,605 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:44,605 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:00:44,605 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2014490638] [2019-11-20 07:00:44,605 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 07:00:44,606 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:44,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 07:00:44,606 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:44,606 INFO L87 Difference]: Start difference. First operand 385 states and 551 transitions. Second operand 5 states. [2019-11-20 07:00:44,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:44,900 INFO L93 Difference]: Finished difference Result 941 states and 1357 transitions. [2019-11-20 07:00:44,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 07:00:44,901 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-11-20 07:00:44,901 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:44,905 INFO L225 Difference]: With dead ends: 941 [2019-11-20 07:00:44,906 INFO L226 Difference]: Without dead ends: 657 [2019-11-20 07:00:44,907 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-20 07:00:44,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states. [2019-11-20 07:00:44,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 389. [2019-11-20 07:00:44,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389 states. [2019-11-20 07:00:44,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 555 transitions. [2019-11-20 07:00:44,929 INFO L78 Accepts]: Start accepts. Automaton has 389 states and 555 transitions. Word has length 51 [2019-11-20 07:00:44,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:44,929 INFO L462 AbstractCegarLoop]: Abstraction has 389 states and 555 transitions. [2019-11-20 07:00:44,929 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 07:00:44,930 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 555 transitions. [2019-11-20 07:00:44,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-20 07:00:44,931 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:44,931 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:44,931 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:44,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:44,932 INFO L82 PathProgramCache]: Analyzing trace with hash -458607163, now seen corresponding path program 1 times [2019-11-20 07:00:44,932 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:44,932 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039299922] [2019-11-20 07:00:44,933 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:44,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:45,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:45,035 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039299922] [2019-11-20 07:00:45,035 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:45,035 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:00:45,036 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067574707] [2019-11-20 07:00:45,036 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 07:00:45,037 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:45,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 07:00:45,037 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:00:45,037 INFO L87 Difference]: Start difference. First operand 389 states and 555 transitions. Second operand 4 states. [2019-11-20 07:00:45,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:45,341 INFO L93 Difference]: Finished difference Result 941 states and 1353 transitions. [2019-11-20 07:00:45,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:00:45,342 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 53 [2019-11-20 07:00:45,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:45,348 INFO L225 Difference]: With dead ends: 941 [2019-11-20 07:00:45,348 INFO L226 Difference]: Without dead ends: 657 [2019-11-20 07:00:45,349 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:45,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states. [2019-11-20 07:00:45,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 389. [2019-11-20 07:00:45,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389 states. [2019-11-20 07:00:45,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 553 transitions. [2019-11-20 07:00:45,373 INFO L78 Accepts]: Start accepts. Automaton has 389 states and 553 transitions. Word has length 53 [2019-11-20 07:00:45,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:45,375 INFO L462 AbstractCegarLoop]: Abstraction has 389 states and 553 transitions. [2019-11-20 07:00:45,375 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 07:00:45,376 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 553 transitions. [2019-11-20 07:00:45,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-20 07:00:45,377 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:45,377 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:45,378 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:45,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:45,383 INFO L82 PathProgramCache]: Analyzing trace with hash 1789775306, now seen corresponding path program 1 times [2019-11-20 07:00:45,383 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:45,383 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749915282] [2019-11-20 07:00:45,383 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:45,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:45,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:45,566 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749915282] [2019-11-20 07:00:45,566 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:45,567 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 07:00:45,567 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547460446] [2019-11-20 07:00:45,567 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 07:00:45,567 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:45,568 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 07:00:45,568 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:45,568 INFO L87 Difference]: Start difference. First operand 389 states and 553 transitions. Second operand 5 states. [2019-11-20 07:00:45,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:45,640 INFO L93 Difference]: Finished difference Result 773 states and 1114 transitions. [2019-11-20 07:00:45,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 07:00:45,641 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2019-11-20 07:00:45,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:45,645 INFO L225 Difference]: With dead ends: 773 [2019-11-20 07:00:45,646 INFO L226 Difference]: Without dead ends: 489 [2019-11-20 07:00:45,647 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-11-20 07:00:45,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 489 states. [2019-11-20 07:00:45,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 489 to 384. [2019-11-20 07:00:45,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 384 states. [2019-11-20 07:00:45,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 545 transitions. [2019-11-20 07:00:45,670 INFO L78 Accepts]: Start accepts. Automaton has 384 states and 545 transitions. Word has length 54 [2019-11-20 07:00:45,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:45,671 INFO L462 AbstractCegarLoop]: Abstraction has 384 states and 545 transitions. [2019-11-20 07:00:45,671 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 07:00:45,671 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 545 transitions. [2019-11-20 07:00:45,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-20 07:00:45,672 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:45,673 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:45,673 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:45,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:45,674 INFO L82 PathProgramCache]: Analyzing trace with hash 1630366882, now seen corresponding path program 1 times [2019-11-20 07:00:45,674 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:45,674 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588303076] [2019-11-20 07:00:45,675 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:45,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:45,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:45,836 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588303076] [2019-11-20 07:00:45,837 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:45,837 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 07:00:45,837 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1559974561] [2019-11-20 07:00:45,837 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 07:00:45,837 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:45,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 07:00:45,838 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:45,838 INFO L87 Difference]: Start difference. First operand 384 states and 545 transitions. Second operand 5 states. [2019-11-20 07:00:45,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:45,973 INFO L93 Difference]: Finished difference Result 804 states and 1163 transitions. [2019-11-20 07:00:45,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:00:45,974 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-11-20 07:00:45,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:45,977 INFO L225 Difference]: With dead ends: 804 [2019-11-20 07:00:45,978 INFO L226 Difference]: Without dead ends: 525 [2019-11-20 07:00:45,979 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-20 07:00:45,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states. [2019-11-20 07:00:46,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 354. [2019-11-20 07:00:46,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354 states. [2019-11-20 07:00:46,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 499 transitions. [2019-11-20 07:00:46,006 INFO L78 Accepts]: Start accepts. Automaton has 354 states and 499 transitions. Word has length 58 [2019-11-20 07:00:46,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:46,006 INFO L462 AbstractCegarLoop]: Abstraction has 354 states and 499 transitions. [2019-11-20 07:00:46,006 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 07:00:46,006 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 499 transitions. [2019-11-20 07:00:46,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-20 07:00:46,007 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:46,007 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:46,008 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:46,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:46,009 INFO L82 PathProgramCache]: Analyzing trace with hash 644191382, now seen corresponding path program 1 times [2019-11-20 07:00:46,009 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:46,009 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046878434] [2019-11-20 07:00:46,010 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:46,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:46,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:46,154 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1046878434] [2019-11-20 07:00:46,154 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:46,154 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 07:00:46,155 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1296609433] [2019-11-20 07:00:46,155 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 07:00:46,156 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:46,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 07:00:46,157 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:46,157 INFO L87 Difference]: Start difference. First operand 354 states and 499 transitions. Second operand 5 states. [2019-11-20 07:00:46,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:46,285 INFO L93 Difference]: Finished difference Result 900 states and 1292 transitions. [2019-11-20 07:00:46,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:00:46,285 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 63 [2019-11-20 07:00:46,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:46,289 INFO L225 Difference]: With dead ends: 900 [2019-11-20 07:00:46,289 INFO L226 Difference]: Without dead ends: 651 [2019-11-20 07:00:46,290 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-20 07:00:46,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 651 states. [2019-11-20 07:00:46,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 651 to 324. [2019-11-20 07:00:46,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 324 states. [2019-11-20 07:00:46,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324 states to 324 states and 453 transitions. [2019-11-20 07:00:46,317 INFO L78 Accepts]: Start accepts. Automaton has 324 states and 453 transitions. Word has length 63 [2019-11-20 07:00:46,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:46,317 INFO L462 AbstractCegarLoop]: Abstraction has 324 states and 453 transitions. [2019-11-20 07:00:46,317 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 07:00:46,317 INFO L276 IsEmpty]: Start isEmpty. Operand 324 states and 453 transitions. [2019-11-20 07:00:46,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-11-20 07:00:46,318 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:46,318 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:46,319 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:46,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:46,319 INFO L82 PathProgramCache]: Analyzing trace with hash 157991886, now seen corresponding path program 1 times [2019-11-20 07:00:46,320 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:46,320 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897672199] [2019-11-20 07:00:46,320 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:46,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:46,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:46,519 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [897672199] [2019-11-20 07:00:46,520 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:46,520 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 07:00:46,520 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953689902] [2019-11-20 07:00:46,521 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:00:46,521 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:46,521 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:00:46,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 07:00:46,522 INFO L87 Difference]: Start difference. First operand 324 states and 453 transitions. Second operand 6 states. [2019-11-20 07:00:46,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:46,801 INFO L93 Difference]: Finished difference Result 1098 states and 1557 transitions. [2019-11-20 07:00:46,801 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 07:00:46,801 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-11-20 07:00:46,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:46,807 INFO L225 Difference]: With dead ends: 1098 [2019-11-20 07:00:46,807 INFO L226 Difference]: Without dead ends: 879 [2019-11-20 07:00:46,808 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-20 07:00:46,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 879 states. [2019-11-20 07:00:46,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 879 to 363. [2019-11-20 07:00:46,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 363 states. [2019-11-20 07:00:46,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 363 states to 363 states and 507 transitions. [2019-11-20 07:00:46,842 INFO L78 Accepts]: Start accepts. Automaton has 363 states and 507 transitions. Word has length 68 [2019-11-20 07:00:46,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:46,844 INFO L462 AbstractCegarLoop]: Abstraction has 363 states and 507 transitions. [2019-11-20 07:00:46,844 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:00:46,844 INFO L276 IsEmpty]: Start isEmpty. Operand 363 states and 507 transitions. [2019-11-20 07:00:46,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-11-20 07:00:46,847 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:46,847 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:46,848 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:46,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:46,848 INFO L82 PathProgramCache]: Analyzing trace with hash -2134355609, now seen corresponding path program 1 times [2019-11-20 07:00:46,848 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:46,849 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890244696] [2019-11-20 07:00:46,849 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:46,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:46,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:46,921 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [890244696] [2019-11-20 07:00:46,921 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:46,921 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 07:00:46,921 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320365966] [2019-11-20 07:00:46,922 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 07:00:46,922 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:46,922 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 07:00:46,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:46,922 INFO L87 Difference]: Start difference. First operand 363 states and 507 transitions. Second operand 3 states. [2019-11-20 07:00:46,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:46,992 INFO L93 Difference]: Finished difference Result 659 states and 932 transitions. [2019-11-20 07:00:46,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 07:00:46,992 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-11-20 07:00:46,993 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:46,995 INFO L225 Difference]: With dead ends: 659 [2019-11-20 07:00:46,995 INFO L226 Difference]: Without dead ends: 440 [2019-11-20 07:00:46,996 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:46,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 440 states. [2019-11-20 07:00:47,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 440 to 359. [2019-11-20 07:00:47,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 359 states. [2019-11-20 07:00:47,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 359 states to 359 states and 500 transitions. [2019-11-20 07:00:47,026 INFO L78 Accepts]: Start accepts. Automaton has 359 states and 500 transitions. Word has length 69 [2019-11-20 07:00:47,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:47,027 INFO L462 AbstractCegarLoop]: Abstraction has 359 states and 500 transitions. [2019-11-20 07:00:47,027 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 07:00:47,027 INFO L276 IsEmpty]: Start isEmpty. Operand 359 states and 500 transitions. [2019-11-20 07:00:47,028 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-20 07:00:47,028 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:47,028 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:47,028 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:47,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:47,029 INFO L82 PathProgramCache]: Analyzing trace with hash 1585943340, now seen corresponding path program 1 times [2019-11-20 07:00:47,029 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:47,030 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244614953] [2019-11-20 07:00:47,031 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:47,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:47,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:47,109 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1244614953] [2019-11-20 07:00:47,109 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:47,109 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:00:47,110 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2049344272] [2019-11-20 07:00:47,110 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 07:00:47,110 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:47,110 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 07:00:47,111 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:00:47,111 INFO L87 Difference]: Start difference. First operand 359 states and 500 transitions. Second operand 4 states. [2019-11-20 07:00:47,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:47,291 INFO L93 Difference]: Finished difference Result 949 states and 1326 transitions. [2019-11-20 07:00:47,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:00:47,292 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2019-11-20 07:00:47,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:47,296 INFO L225 Difference]: With dead ends: 949 [2019-11-20 07:00:47,296 INFO L226 Difference]: Without dead ends: 724 [2019-11-20 07:00:47,297 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:47,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 724 states. [2019-11-20 07:00:47,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 724 to 529. [2019-11-20 07:00:47,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 529 states. [2019-11-20 07:00:47,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 529 states to 529 states and 733 transitions. [2019-11-20 07:00:47,359 INFO L78 Accepts]: Start accepts. Automaton has 529 states and 733 transitions. Word has length 72 [2019-11-20 07:00:47,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:47,360 INFO L462 AbstractCegarLoop]: Abstraction has 529 states and 733 transitions. [2019-11-20 07:00:47,360 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 07:00:47,360 INFO L276 IsEmpty]: Start isEmpty. Operand 529 states and 733 transitions. [2019-11-20 07:00:47,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-20 07:00:47,361 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:47,362 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:47,362 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:47,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:47,363 INFO L82 PathProgramCache]: Analyzing trace with hash -2083950892, now seen corresponding path program 1 times [2019-11-20 07:00:47,363 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:47,363 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996022156] [2019-11-20 07:00:47,363 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:47,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:47,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:47,458 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996022156] [2019-11-20 07:00:47,459 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:47,459 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 07:00:47,459 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063641865] [2019-11-20 07:00:47,460 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 07:00:47,460 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:47,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 07:00:47,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:47,461 INFO L87 Difference]: Start difference. First operand 529 states and 733 transitions. Second operand 3 states. [2019-11-20 07:00:47,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:47,542 INFO L93 Difference]: Finished difference Result 907 states and 1262 transitions. [2019-11-20 07:00:47,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 07:00:47,542 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-20 07:00:47,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:47,546 INFO L225 Difference]: With dead ends: 907 [2019-11-20 07:00:47,546 INFO L226 Difference]: Without dead ends: 529 [2019-11-20 07:00:47,547 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:47,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 529 states. [2019-11-20 07:00:47,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 529 to 529. [2019-11-20 07:00:47,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 529 states. [2019-11-20 07:00:47,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 529 states to 529 states and 729 transitions. [2019-11-20 07:00:47,587 INFO L78 Accepts]: Start accepts. Automaton has 529 states and 729 transitions. Word has length 72 [2019-11-20 07:00:47,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:47,588 INFO L462 AbstractCegarLoop]: Abstraction has 529 states and 729 transitions. [2019-11-20 07:00:47,588 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 07:00:47,588 INFO L276 IsEmpty]: Start isEmpty. Operand 529 states and 729 transitions. [2019-11-20 07:00:47,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-20 07:00:47,589 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:47,589 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:47,590 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:47,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:47,590 INFO L82 PathProgramCache]: Analyzing trace with hash 2070467794, now seen corresponding path program 1 times [2019-11-20 07:00:47,590 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:47,591 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563729662] [2019-11-20 07:00:47,591 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:47,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:47,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:47,639 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563729662] [2019-11-20 07:00:47,639 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:47,640 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 07:00:47,640 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552287201] [2019-11-20 07:00:47,640 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 07:00:47,640 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:47,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 07:00:47,641 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:47,641 INFO L87 Difference]: Start difference. First operand 529 states and 729 transitions. Second operand 3 states. [2019-11-20 07:00:47,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:47,724 INFO L93 Difference]: Finished difference Result 1250 states and 1717 transitions. [2019-11-20 07:00:47,725 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 07:00:47,725 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-20 07:00:47,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:47,730 INFO L225 Difference]: With dead ends: 1250 [2019-11-20 07:00:47,730 INFO L226 Difference]: Without dead ends: 835 [2019-11-20 07:00:47,732 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:47,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states. [2019-11-20 07:00:47,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 563. [2019-11-20 07:00:47,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 563 states. [2019-11-20 07:00:47,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 773 transitions. [2019-11-20 07:00:47,780 INFO L78 Accepts]: Start accepts. Automaton has 563 states and 773 transitions. Word has length 72 [2019-11-20 07:00:47,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:47,780 INFO L462 AbstractCegarLoop]: Abstraction has 563 states and 773 transitions. [2019-11-20 07:00:47,780 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 07:00:47,780 INFO L276 IsEmpty]: Start isEmpty. Operand 563 states and 773 transitions. [2019-11-20 07:00:47,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 07:00:47,781 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:47,781 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:47,782 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:47,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:47,782 INFO L82 PathProgramCache]: Analyzing trace with hash -1917205063, now seen corresponding path program 1 times [2019-11-20 07:00:47,783 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:47,783 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808858406] [2019-11-20 07:00:47,783 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:47,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:47,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:47,934 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808858406] [2019-11-20 07:00:47,934 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:47,934 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 07:00:47,935 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586004806] [2019-11-20 07:00:47,935 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:00:47,935 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:47,935 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:00:47,936 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 07:00:47,936 INFO L87 Difference]: Start difference. First operand 563 states and 773 transitions. Second operand 6 states. [2019-11-20 07:00:48,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:48,291 INFO L93 Difference]: Finished difference Result 1763 states and 2476 transitions. [2019-11-20 07:00:48,292 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 07:00:48,292 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-11-20 07:00:48,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:48,300 INFO L225 Difference]: With dead ends: 1763 [2019-11-20 07:00:48,300 INFO L226 Difference]: Without dead ends: 1430 [2019-11-20 07:00:48,303 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-20 07:00:48,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1430 states. [2019-11-20 07:00:48,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1430 to 567. [2019-11-20 07:00:48,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 567 states. [2019-11-20 07:00:48,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 567 states to 567 states and 778 transitions. [2019-11-20 07:00:48,359 INFO L78 Accepts]: Start accepts. Automaton has 567 states and 778 transitions. Word has length 73 [2019-11-20 07:00:48,359 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:48,359 INFO L462 AbstractCegarLoop]: Abstraction has 567 states and 778 transitions. [2019-11-20 07:00:48,360 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:00:48,360 INFO L276 IsEmpty]: Start isEmpty. Operand 567 states and 778 transitions. [2019-11-20 07:00:48,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 07:00:48,361 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:48,361 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:48,361 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:48,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:48,362 INFO L82 PathProgramCache]: Analyzing trace with hash 197100160, now seen corresponding path program 1 times [2019-11-20 07:00:48,362 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:48,362 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621801854] [2019-11-20 07:00:48,362 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:48,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:48,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:48,471 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621801854] [2019-11-20 07:00:48,473 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:48,473 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 07:00:48,474 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1072634256] [2019-11-20 07:00:48,474 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 07:00:48,474 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:48,474 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 07:00:48,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:48,475 INFO L87 Difference]: Start difference. First operand 567 states and 778 transitions. Second operand 5 states. [2019-11-20 07:00:48,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:48,665 INFO L93 Difference]: Finished difference Result 886 states and 1237 transitions. [2019-11-20 07:00:48,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 07:00:48,666 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2019-11-20 07:00:48,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:48,671 INFO L225 Difference]: With dead ends: 886 [2019-11-20 07:00:48,671 INFO L226 Difference]: Without dead ends: 884 [2019-11-20 07:00:48,672 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-20 07:00:48,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 884 states. [2019-11-20 07:00:48,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 884 to 569. [2019-11-20 07:00:48,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 569 states. [2019-11-20 07:00:48,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 780 transitions. [2019-11-20 07:00:48,727 INFO L78 Accepts]: Start accepts. Automaton has 569 states and 780 transitions. Word has length 73 [2019-11-20 07:00:48,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:48,728 INFO L462 AbstractCegarLoop]: Abstraction has 569 states and 780 transitions. [2019-11-20 07:00:48,728 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 07:00:48,728 INFO L276 IsEmpty]: Start isEmpty. Operand 569 states and 780 transitions. [2019-11-20 07:00:48,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 07:00:48,729 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:48,729 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:48,730 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:48,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:48,730 INFO L82 PathProgramCache]: Analyzing trace with hash 2083582807, now seen corresponding path program 1 times [2019-11-20 07:00:48,730 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:48,731 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065339520] [2019-11-20 07:00:48,731 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:48,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:48,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:48,853 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1065339520] [2019-11-20 07:00:48,853 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:48,854 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 07:00:48,854 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508777454] [2019-11-20 07:00:48,854 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:00:48,855 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:48,855 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:00:48,855 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 07:00:48,855 INFO L87 Difference]: Start difference. First operand 569 states and 780 transitions. Second operand 6 states. [2019-11-20 07:00:49,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:49,449 INFO L93 Difference]: Finished difference Result 2030 states and 2821 transitions. [2019-11-20 07:00:49,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 07:00:49,450 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-11-20 07:00:49,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:49,461 INFO L225 Difference]: With dead ends: 2030 [2019-11-20 07:00:49,462 INFO L226 Difference]: Without dead ends: 1656 [2019-11-20 07:00:49,464 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-20 07:00:49,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1656 states. [2019-11-20 07:00:49,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1656 to 615. [2019-11-20 07:00:49,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 615 states. [2019-11-20 07:00:49,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 615 states to 615 states and 838 transitions. [2019-11-20 07:00:49,552 INFO L78 Accepts]: Start accepts. Automaton has 615 states and 838 transitions. Word has length 73 [2019-11-20 07:00:49,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:49,552 INFO L462 AbstractCegarLoop]: Abstraction has 615 states and 838 transitions. [2019-11-20 07:00:49,552 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:00:49,553 INFO L276 IsEmpty]: Start isEmpty. Operand 615 states and 838 transitions. [2019-11-20 07:00:49,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-20 07:00:49,556 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:49,556 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:49,557 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:49,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:49,557 INFO L82 PathProgramCache]: Analyzing trace with hash 1204676769, now seen corresponding path program 1 times [2019-11-20 07:00:49,558 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:49,558 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041748842] [2019-11-20 07:00:49,558 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:49,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:49,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:49,706 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041748842] [2019-11-20 07:00:49,706 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:49,706 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 07:00:49,706 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523354209] [2019-11-20 07:00:49,707 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:00:49,707 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:49,707 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:00:49,708 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 07:00:49,708 INFO L87 Difference]: Start difference. First operand 615 states and 838 transitions. Second operand 6 states. [2019-11-20 07:00:50,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:50,200 INFO L93 Difference]: Finished difference Result 2356 states and 3253 transitions. [2019-11-20 07:00:50,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 07:00:50,200 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-11-20 07:00:50,200 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:50,212 INFO L225 Difference]: With dead ends: 2356 [2019-11-20 07:00:50,212 INFO L226 Difference]: Without dead ends: 1974 [2019-11-20 07:00:50,213 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-20 07:00:50,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1974 states. [2019-11-20 07:00:50,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1974 to 693. [2019-11-20 07:00:50,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 693 states. [2019-11-20 07:00:50,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 940 transitions. [2019-11-20 07:00:50,295 INFO L78 Accepts]: Start accepts. Automaton has 693 states and 940 transitions. Word has length 74 [2019-11-20 07:00:50,295 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:50,295 INFO L462 AbstractCegarLoop]: Abstraction has 693 states and 940 transitions. [2019-11-20 07:00:50,295 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:00:50,296 INFO L276 IsEmpty]: Start isEmpty. Operand 693 states and 940 transitions. [2019-11-20 07:00:50,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-20 07:00:50,297 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:50,297 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:50,297 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:50,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:50,298 INFO L82 PathProgramCache]: Analyzing trace with hash -217796256, now seen corresponding path program 1 times [2019-11-20 07:00:50,298 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:50,298 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052181587] [2019-11-20 07:00:50,298 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:50,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:50,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:50,368 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052181587] [2019-11-20 07:00:50,368 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:50,368 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 07:00:50,368 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027444430] [2019-11-20 07:00:50,369 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:00:50,369 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:50,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:00:50,369 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 07:00:50,369 INFO L87 Difference]: Start difference. First operand 693 states and 940 transitions. Second operand 6 states. [2019-11-20 07:00:50,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:50,595 INFO L93 Difference]: Finished difference Result 1555 states and 2195 transitions. [2019-11-20 07:00:50,596 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 07:00:50,596 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-11-20 07:00:50,596 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:50,603 INFO L225 Difference]: With dead ends: 1555 [2019-11-20 07:00:50,603 INFO L226 Difference]: Without dead ends: 1156 [2019-11-20 07:00:50,604 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-11-20 07:00:50,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1156 states. [2019-11-20 07:00:50,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1156 to 699. [2019-11-20 07:00:50,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 699 states. [2019-11-20 07:00:50,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 699 states to 699 states and 946 transitions. [2019-11-20 07:00:50,681 INFO L78 Accepts]: Start accepts. Automaton has 699 states and 946 transitions. Word has length 74 [2019-11-20 07:00:50,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:50,681 INFO L462 AbstractCegarLoop]: Abstraction has 699 states and 946 transitions. [2019-11-20 07:00:50,681 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:00:50,681 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 946 transitions. [2019-11-20 07:00:50,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-20 07:00:50,682 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:50,683 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:50,683 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:50,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:50,683 INFO L82 PathProgramCache]: Analyzing trace with hash -1278252476, now seen corresponding path program 1 times [2019-11-20 07:00:50,684 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:50,684 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079244317] [2019-11-20 07:00:50,684 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:50,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:50,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:50,730 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079244317] [2019-11-20 07:00:50,730 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:50,730 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 07:00:50,731 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1207070271] [2019-11-20 07:00:50,731 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 07:00:50,731 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:50,731 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 07:00:50,732 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:50,732 INFO L87 Difference]: Start difference. First operand 699 states and 946 transitions. Second operand 3 states. [2019-11-20 07:00:50,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:50,858 INFO L93 Difference]: Finished difference Result 1371 states and 1888 transitions. [2019-11-20 07:00:50,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 07:00:50,858 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-11-20 07:00:50,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:50,863 INFO L225 Difference]: With dead ends: 1371 [2019-11-20 07:00:50,864 INFO L226 Difference]: Without dead ends: 903 [2019-11-20 07:00:50,865 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:50,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 903 states. [2019-11-20 07:00:50,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 903 to 678. [2019-11-20 07:00:50,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 678 states. [2019-11-20 07:00:50,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678 states to 678 states and 909 transitions. [2019-11-20 07:00:50,934 INFO L78 Accepts]: Start accepts. Automaton has 678 states and 909 transitions. Word has length 74 [2019-11-20 07:00:50,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:50,934 INFO L462 AbstractCegarLoop]: Abstraction has 678 states and 909 transitions. [2019-11-20 07:00:50,934 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 07:00:50,934 INFO L276 IsEmpty]: Start isEmpty. Operand 678 states and 909 transitions. [2019-11-20 07:00:50,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-20 07:00:50,935 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:50,936 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:50,936 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:50,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:50,936 INFO L82 PathProgramCache]: Analyzing trace with hash -1698648942, now seen corresponding path program 1 times [2019-11-20 07:00:50,936 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:50,937 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851065774] [2019-11-20 07:00:50,937 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:50,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:50,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:50,990 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1851065774] [2019-11-20 07:00:50,990 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:50,991 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:00:50,991 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463010776] [2019-11-20 07:00:50,991 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 07:00:50,991 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:50,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 07:00:50,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:00:50,992 INFO L87 Difference]: Start difference. First operand 678 states and 909 transitions. Second operand 4 states. [2019-11-20 07:00:51,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:51,205 INFO L93 Difference]: Finished difference Result 1740 states and 2346 transitions. [2019-11-20 07:00:51,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:00:51,206 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-11-20 07:00:51,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:51,214 INFO L225 Difference]: With dead ends: 1740 [2019-11-20 07:00:51,214 INFO L226 Difference]: Without dead ends: 1325 [2019-11-20 07:00:51,215 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:51,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1325 states. [2019-11-20 07:00:51,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1325 to 922. [2019-11-20 07:00:51,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 922 states. [2019-11-20 07:00:51,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 922 states to 922 states and 1236 transitions. [2019-11-20 07:00:51,343 INFO L78 Accepts]: Start accepts. Automaton has 922 states and 1236 transitions. Word has length 75 [2019-11-20 07:00:51,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:51,344 INFO L462 AbstractCegarLoop]: Abstraction has 922 states and 1236 transitions. [2019-11-20 07:00:51,344 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 07:00:51,344 INFO L276 IsEmpty]: Start isEmpty. Operand 922 states and 1236 transitions. [2019-11-20 07:00:51,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-20 07:00:51,345 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:51,345 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:51,346 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:51,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:51,346 INFO L82 PathProgramCache]: Analyzing trace with hash -1596781464, now seen corresponding path program 1 times [2019-11-20 07:00:51,346 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:51,346 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126167154] [2019-11-20 07:00:51,347 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:51,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:51,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:51,399 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126167154] [2019-11-20 07:00:51,399 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:51,399 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 07:00:51,400 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97081913] [2019-11-20 07:00:51,400 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 07:00:51,400 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:51,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 07:00:51,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:51,401 INFO L87 Difference]: Start difference. First operand 922 states and 1236 transitions. Second operand 3 states. [2019-11-20 07:00:51,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:51,568 INFO L93 Difference]: Finished difference Result 1929 states and 2618 transitions. [2019-11-20 07:00:51,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 07:00:51,568 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2019-11-20 07:00:51,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:51,576 INFO L225 Difference]: With dead ends: 1929 [2019-11-20 07:00:51,577 INFO L226 Difference]: Without dead ends: 1325 [2019-11-20 07:00:51,578 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:51,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1325 states. [2019-11-20 07:00:51,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1325 to 876. [2019-11-20 07:00:51,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 876 states. [2019-11-20 07:00:51,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 876 states to 876 states and 1170 transitions. [2019-11-20 07:00:51,678 INFO L78 Accepts]: Start accepts. Automaton has 876 states and 1170 transitions. Word has length 75 [2019-11-20 07:00:51,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:51,678 INFO L462 AbstractCegarLoop]: Abstraction has 876 states and 1170 transitions. [2019-11-20 07:00:51,678 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 07:00:51,679 INFO L276 IsEmpty]: Start isEmpty. Operand 876 states and 1170 transitions. [2019-11-20 07:00:51,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-20 07:00:51,680 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:51,680 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:51,680 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:51,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:51,680 INFO L82 PathProgramCache]: Analyzing trace with hash -216337278, now seen corresponding path program 1 times [2019-11-20 07:00:51,681 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:51,681 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799233318] [2019-11-20 07:00:51,681 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:51,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:51,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:51,735 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799233318] [2019-11-20 07:00:51,735 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:51,735 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:00:51,735 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741333528] [2019-11-20 07:00:51,735 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 07:00:51,736 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:51,736 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 07:00:51,736 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:00:51,736 INFO L87 Difference]: Start difference. First operand 876 states and 1170 transitions. Second operand 4 states. [2019-11-20 07:00:51,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:51,973 INFO L93 Difference]: Finished difference Result 2038 states and 2720 transitions. [2019-11-20 07:00:51,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:00:51,973 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-11-20 07:00:51,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:51,981 INFO L225 Difference]: With dead ends: 2038 [2019-11-20 07:00:51,981 INFO L226 Difference]: Without dead ends: 1463 [2019-11-20 07:00:51,982 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:51,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1463 states. [2019-11-20 07:00:52,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1463 to 1168. [2019-11-20 07:00:52,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1168 states. [2019-11-20 07:00:52,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1168 states to 1168 states and 1550 transitions. [2019-11-20 07:00:52,104 INFO L78 Accepts]: Start accepts. Automaton has 1168 states and 1550 transitions. Word has length 75 [2019-11-20 07:00:52,104 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:52,105 INFO L462 AbstractCegarLoop]: Abstraction has 1168 states and 1550 transitions. [2019-11-20 07:00:52,105 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 07:00:52,105 INFO L276 IsEmpty]: Start isEmpty. Operand 1168 states and 1550 transitions. [2019-11-20 07:00:52,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-11-20 07:00:52,106 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:52,106 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:52,106 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:52,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:52,107 INFO L82 PathProgramCache]: Analyzing trace with hash -1065252519, now seen corresponding path program 1 times [2019-11-20 07:00:52,107 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:52,107 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594147432] [2019-11-20 07:00:52,107 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:52,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:52,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:52,139 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1594147432] [2019-11-20 07:00:52,139 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:52,139 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 07:00:52,139 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780926408] [2019-11-20 07:00:52,140 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 07:00:52,140 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:52,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 07:00:52,140 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:52,140 INFO L87 Difference]: Start difference. First operand 1168 states and 1550 transitions. Second operand 3 states. [2019-11-20 07:00:52,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:52,422 INFO L93 Difference]: Finished difference Result 2879 states and 3814 transitions. [2019-11-20 07:00:52,422 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 07:00:52,422 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2019-11-20 07:00:52,423 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:52,434 INFO L225 Difference]: With dead ends: 2879 [2019-11-20 07:00:52,434 INFO L226 Difference]: Without dead ends: 1954 [2019-11-20 07:00:52,437 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 07:00:52,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1954 states. [2019-11-20 07:00:52,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1954 to 1170. [2019-11-20 07:00:52,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1170 states. [2019-11-20 07:00:52,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1552 transitions. [2019-11-20 07:00:52,574 INFO L78 Accepts]: Start accepts. Automaton has 1170 states and 1552 transitions. Word has length 76 [2019-11-20 07:00:52,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:52,574 INFO L462 AbstractCegarLoop]: Abstraction has 1170 states and 1552 transitions. [2019-11-20 07:00:52,574 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 07:00:52,574 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1552 transitions. [2019-11-20 07:00:52,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2019-11-20 07:00:52,576 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:52,576 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:52,576 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:52,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:52,576 INFO L82 PathProgramCache]: Analyzing trace with hash -2019206059, now seen corresponding path program 1 times [2019-11-20 07:00:52,577 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:52,577 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488200360] [2019-11-20 07:00:52,577 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:52,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:52,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:52,649 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [488200360] [2019-11-20 07:00:52,650 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:52,650 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:00:52,650 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452526655] [2019-11-20 07:00:52,651 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 07:00:52,651 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:52,651 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 07:00:52,651 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:00:52,651 INFO L87 Difference]: Start difference. First operand 1170 states and 1552 transitions. Second operand 4 states. [2019-11-20 07:00:52,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:52,919 INFO L93 Difference]: Finished difference Result 2434 states and 3222 transitions. [2019-11-20 07:00:52,919 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:00:52,920 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 77 [2019-11-20 07:00:52,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:52,927 INFO L225 Difference]: With dead ends: 2434 [2019-11-20 07:00:52,928 INFO L226 Difference]: Without dead ends: 1321 [2019-11-20 07:00:52,929 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:52,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1321 states. [2019-11-20 07:00:53,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1321 to 975. [2019-11-20 07:00:53,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 975 states. [2019-11-20 07:00:53,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 975 states to 975 states and 1288 transitions. [2019-11-20 07:00:53,047 INFO L78 Accepts]: Start accepts. Automaton has 975 states and 1288 transitions. Word has length 77 [2019-11-20 07:00:53,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:53,047 INFO L462 AbstractCegarLoop]: Abstraction has 975 states and 1288 transitions. [2019-11-20 07:00:53,048 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 07:00:53,048 INFO L276 IsEmpty]: Start isEmpty. Operand 975 states and 1288 transitions. [2019-11-20 07:00:53,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2019-11-20 07:00:53,049 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:53,049 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:53,049 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:53,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:53,050 INFO L82 PathProgramCache]: Analyzing trace with hash -113428458, now seen corresponding path program 1 times [2019-11-20 07:00:53,050 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:53,050 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814741961] [2019-11-20 07:00:53,050 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:53,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:53,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:53,127 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814741961] [2019-11-20 07:00:53,127 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:00:53,127 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:00:53,127 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154207729] [2019-11-20 07:00:53,128 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 07:00:53,128 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:53,128 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 07:00:53,128 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:00:53,129 INFO L87 Difference]: Start difference. First operand 975 states and 1288 transitions. Second operand 4 states. [2019-11-20 07:00:53,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:53,334 INFO L93 Difference]: Finished difference Result 2239 states and 2968 transitions. [2019-11-20 07:00:53,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:00:53,335 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 78 [2019-11-20 07:00:53,335 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:53,341 INFO L225 Difference]: With dead ends: 2239 [2019-11-20 07:00:53,342 INFO L226 Difference]: Without dead ends: 1341 [2019-11-20 07:00:53,343 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:00:53,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1341 states. [2019-11-20 07:00:53,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1341 to 919. [2019-11-20 07:00:53,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 919 states. [2019-11-20 07:00:53,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 919 states to 919 states and 1208 transitions. [2019-11-20 07:00:53,460 INFO L78 Accepts]: Start accepts. Automaton has 919 states and 1208 transitions. Word has length 78 [2019-11-20 07:00:53,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:53,461 INFO L462 AbstractCegarLoop]: Abstraction has 919 states and 1208 transitions. [2019-11-20 07:00:53,461 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 07:00:53,461 INFO L276 IsEmpty]: Start isEmpty. Operand 919 states and 1208 transitions. [2019-11-20 07:00:53,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2019-11-20 07:00:53,463 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:53,464 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:53,464 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:53,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:53,465 INFO L82 PathProgramCache]: Analyzing trace with hash 691547713, now seen corresponding path program 1 times [2019-11-20 07:00:53,465 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:53,465 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135382443] [2019-11-20 07:00:53,465 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:53,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:53,782 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:53,782 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135382443] [2019-11-20 07:00:53,783 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1113344787] [2019-11-20 07:00:53,783 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:00:53,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:53,983 INFO L255 TraceCheckSpWp]: Trace formula consists of 723 conjuncts, 9 conjunts are in the unsatisfiable core [2019-11-20 07:00:54,001 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:00:54,117 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 07:00:54,117 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 07:00:54,118 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 07:00:54,118 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [765916856] [2019-11-20 07:00:54,118 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:00:54,119 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:54,119 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:00:54,119 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-20 07:00:54,119 INFO L87 Difference]: Start difference. First operand 919 states and 1208 transitions. Second operand 6 states. [2019-11-20 07:00:54,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:54,550 INFO L93 Difference]: Finished difference Result 2830 states and 3892 transitions. [2019-11-20 07:00:54,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 07:00:54,551 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 121 [2019-11-20 07:00:54,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:54,567 INFO L225 Difference]: With dead ends: 2830 [2019-11-20 07:00:54,567 INFO L226 Difference]: Without dead ends: 2058 [2019-11-20 07:00:54,569 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 118 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-11-20 07:00:54,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2058 states. [2019-11-20 07:00:54,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2058 to 919. [2019-11-20 07:00:54,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 919 states. [2019-11-20 07:00:54,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 919 states to 919 states and 1205 transitions. [2019-11-20 07:00:54,709 INFO L78 Accepts]: Start accepts. Automaton has 919 states and 1205 transitions. Word has length 121 [2019-11-20 07:00:54,709 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:54,709 INFO L462 AbstractCegarLoop]: Abstraction has 919 states and 1205 transitions. [2019-11-20 07:00:54,709 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:00:54,710 INFO L276 IsEmpty]: Start isEmpty. Operand 919 states and 1205 transitions. [2019-11-20 07:00:54,712 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2019-11-20 07:00:54,712 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:54,712 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:54,920 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:00:54,920 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:54,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:54,920 INFO L82 PathProgramCache]: Analyzing trace with hash 344042918, now seen corresponding path program 1 times [2019-11-20 07:00:54,920 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:54,921 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [193216630] [2019-11-20 07:00:54,921 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:54,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:55,309 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:55,310 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [193216630] [2019-11-20 07:00:55,310 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2000994243] [2019-11-20 07:00:55,310 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:00:55,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:55,512 INFO L255 TraceCheckSpWp]: Trace formula consists of 736 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-20 07:00:55,522 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:00:55,681 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 07:00:55,682 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 07:00:55,682 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 07:00:55,682 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [251062283] [2019-11-20 07:00:55,683 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:00:55,683 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:55,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:00:55,683 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-20 07:00:55,684 INFO L87 Difference]: Start difference. First operand 919 states and 1205 transitions. Second operand 6 states. [2019-11-20 07:00:56,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:56,110 INFO L93 Difference]: Finished difference Result 2537 states and 3445 transitions. [2019-11-20 07:00:56,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 07:00:56,110 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 125 [2019-11-20 07:00:56,110 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:56,125 INFO L225 Difference]: With dead ends: 2537 [2019-11-20 07:00:56,125 INFO L226 Difference]: Without dead ends: 1765 [2019-11-20 07:00:56,127 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 141 GetRequests, 122 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-11-20 07:00:56,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1765 states. [2019-11-20 07:00:56,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1765 to 919. [2019-11-20 07:00:56,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 919 states. [2019-11-20 07:00:56,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 919 states to 919 states and 1202 transitions. [2019-11-20 07:00:56,253 INFO L78 Accepts]: Start accepts. Automaton has 919 states and 1202 transitions. Word has length 125 [2019-11-20 07:00:56,253 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:56,253 INFO L462 AbstractCegarLoop]: Abstraction has 919 states and 1202 transitions. [2019-11-20 07:00:56,254 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:00:56,254 INFO L276 IsEmpty]: Start isEmpty. Operand 919 states and 1202 transitions. [2019-11-20 07:00:56,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2019-11-20 07:00:56,258 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:56,258 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:56,464 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:00:56,464 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:56,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:56,467 INFO L82 PathProgramCache]: Analyzing trace with hash 1182819496, now seen corresponding path program 1 times [2019-11-20 07:00:56,467 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:56,467 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273065888] [2019-11-20 07:00:56,468 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:56,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:56,779 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:56,779 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1273065888] [2019-11-20 07:00:56,780 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [440665183] [2019-11-20 07:00:56,780 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:00:56,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:56,973 INFO L255 TraceCheckSpWp]: Trace formula consists of 748 conjuncts, 12 conjunts are in the unsatisfiable core [2019-11-20 07:00:56,978 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:00:57,065 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 07:00:57,065 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 07:00:57,065 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 07:00:57,066 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281516311] [2019-11-20 07:00:57,066 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:00:57,066 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:57,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:00:57,068 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-20 07:00:57,068 INFO L87 Difference]: Start difference. First operand 919 states and 1202 transitions. Second operand 6 states. [2019-11-20 07:00:57,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:57,682 INFO L93 Difference]: Finished difference Result 2921 states and 3998 transitions. [2019-11-20 07:00:57,683 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 07:00:57,683 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 128 [2019-11-20 07:00:57,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:57,688 INFO L225 Difference]: With dead ends: 2921 [2019-11-20 07:00:57,688 INFO L226 Difference]: Without dead ends: 2136 [2019-11-20 07:00:57,691 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 128 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2019-11-20 07:00:57,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2136 states. [2019-11-20 07:00:57,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2136 to 867. [2019-11-20 07:00:57,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 867 states. [2019-11-20 07:00:57,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 867 states to 867 states and 1124 transitions. [2019-11-20 07:00:57,878 INFO L78 Accepts]: Start accepts. Automaton has 867 states and 1124 transitions. Word has length 128 [2019-11-20 07:00:57,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:57,879 INFO L462 AbstractCegarLoop]: Abstraction has 867 states and 1124 transitions. [2019-11-20 07:00:57,879 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:00:57,879 INFO L276 IsEmpty]: Start isEmpty. Operand 867 states and 1124 transitions. [2019-11-20 07:00:57,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2019-11-20 07:00:57,882 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:57,883 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:58,087 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:00:58,087 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:58,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:58,088 INFO L82 PathProgramCache]: Analyzing trace with hash 677857235, now seen corresponding path program 1 times [2019-11-20 07:00:58,088 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:58,089 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227566726] [2019-11-20 07:00:58,089 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:58,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:58,375 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:58,376 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227566726] [2019-11-20 07:00:58,376 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [896468006] [2019-11-20 07:00:58,376 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:00:58,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:58,571 INFO L255 TraceCheckSpWp]: Trace formula consists of 749 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-20 07:00:58,580 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:00:58,691 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-20 07:00:58,691 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 07:00:58,692 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 13 [2019-11-20 07:00:58,692 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242855413] [2019-11-20 07:00:58,692 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:00:58,693 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:00:58,693 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:00:58,693 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2019-11-20 07:00:58,693 INFO L87 Difference]: Start difference. First operand 867 states and 1124 transitions. Second operand 6 states. [2019-11-20 07:00:59,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:00:59,134 INFO L93 Difference]: Finished difference Result 2253 states and 3058 transitions. [2019-11-20 07:00:59,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 07:00:59,135 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 129 [2019-11-20 07:00:59,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:00:59,138 INFO L225 Difference]: With dead ends: 2253 [2019-11-20 07:00:59,138 INFO L226 Difference]: Without dead ends: 1547 [2019-11-20 07:00:59,140 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 141 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=44, Invalid=228, Unknown=0, NotChecked=0, Total=272 [2019-11-20 07:00:59,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1547 states. [2019-11-20 07:00:59,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1547 to 867. [2019-11-20 07:00:59,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 867 states. [2019-11-20 07:00:59,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 867 states to 867 states and 1123 transitions. [2019-11-20 07:00:59,272 INFO L78 Accepts]: Start accepts. Automaton has 867 states and 1123 transitions. Word has length 129 [2019-11-20 07:00:59,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:00:59,272 INFO L462 AbstractCegarLoop]: Abstraction has 867 states and 1123 transitions. [2019-11-20 07:00:59,272 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:00:59,272 INFO L276 IsEmpty]: Start isEmpty. Operand 867 states and 1123 transitions. [2019-11-20 07:00:59,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-20 07:00:59,275 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:00:59,275 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:00:59,479 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:00:59,483 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:00:59,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:00:59,483 INFO L82 PathProgramCache]: Analyzing trace with hash 960872696, now seen corresponding path program 1 times [2019-11-20 07:00:59,483 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:00:59,483 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1475070408] [2019-11-20 07:00:59,483 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:00:59,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:59,761 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:00:59,761 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1475070408] [2019-11-20 07:00:59,762 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1898907423] [2019-11-20 07:00:59,762 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:00:59,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:00:59,961 INFO L255 TraceCheckSpWp]: Trace formula consists of 763 conjuncts, 45 conjunts are in the unsatisfiable core [2019-11-20 07:00:59,966 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:01:00,388 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:00,389 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 07:01:00,389 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-11-20 07:01:00,389 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1757711815] [2019-11-20 07:01:00,390 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-20 07:01:00,391 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:00,391 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-20 07:01:00,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=354, Unknown=0, NotChecked=0, Total=420 [2019-11-20 07:01:00,392 INFO L87 Difference]: Start difference. First operand 867 states and 1123 transitions. Second operand 21 states. [2019-11-20 07:01:02,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:02,670 INFO L93 Difference]: Finished difference Result 2300 states and 3037 transitions. [2019-11-20 07:01:02,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-11-20 07:01:02,670 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 133 [2019-11-20 07:01:02,671 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:02,673 INFO L225 Difference]: With dead ends: 2300 [2019-11-20 07:01:02,673 INFO L226 Difference]: Without dead ends: 1600 [2019-11-20 07:01:02,675 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 119 SyntacticMatches, 4 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 392 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=376, Invalid=1516, Unknown=0, NotChecked=0, Total=1892 [2019-11-20 07:01:02,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1600 states. [2019-11-20 07:01:02,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1600 to 1035. [2019-11-20 07:01:02,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1035 states. [2019-11-20 07:01:02,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1035 states to 1035 states and 1337 transitions. [2019-11-20 07:01:02,832 INFO L78 Accepts]: Start accepts. Automaton has 1035 states and 1337 transitions. Word has length 133 [2019-11-20 07:01:02,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:02,832 INFO L462 AbstractCegarLoop]: Abstraction has 1035 states and 1337 transitions. [2019-11-20 07:01:02,833 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-20 07:01:02,833 INFO L276 IsEmpty]: Start isEmpty. Operand 1035 states and 1337 transitions. [2019-11-20 07:01:02,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-20 07:01:02,835 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:02,836 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:03,043 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:03,043 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:03,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:03,043 INFO L82 PathProgramCache]: Analyzing trace with hash -905835978, now seen corresponding path program 1 times [2019-11-20 07:01:03,043 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:03,044 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470577516] [2019-11-20 07:01:03,044 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:03,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:03,108 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-20 07:01:03,109 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470577516] [2019-11-20 07:01:03,109 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:01:03,109 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:01:03,109 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429490025] [2019-11-20 07:01:03,110 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 07:01:03,110 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:03,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 07:01:03,111 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:01:03,112 INFO L87 Difference]: Start difference. First operand 1035 states and 1337 transitions. Second operand 4 states. [2019-11-20 07:01:03,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:03,457 INFO L93 Difference]: Finished difference Result 2508 states and 3266 transitions. [2019-11-20 07:01:03,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:01:03,458 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 133 [2019-11-20 07:01:03,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:03,461 INFO L225 Difference]: With dead ends: 2508 [2019-11-20 07:01:03,461 INFO L226 Difference]: Without dead ends: 1605 [2019-11-20 07:01:03,465 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:01:03,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1605 states. [2019-11-20 07:01:03,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1605 to 1067. [2019-11-20 07:01:03,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1067 states. [2019-11-20 07:01:03,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1067 states to 1067 states and 1365 transitions. [2019-11-20 07:01:03,630 INFO L78 Accepts]: Start accepts. Automaton has 1067 states and 1365 transitions. Word has length 133 [2019-11-20 07:01:03,630 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:03,630 INFO L462 AbstractCegarLoop]: Abstraction has 1067 states and 1365 transitions. [2019-11-20 07:01:03,631 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 07:01:03,631 INFO L276 IsEmpty]: Start isEmpty. Operand 1067 states and 1365 transitions. [2019-11-20 07:01:03,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-20 07:01:03,633 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:03,634 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:03,634 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:03,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:03,634 INFO L82 PathProgramCache]: Analyzing trace with hash -914742478, now seen corresponding path program 1 times [2019-11-20 07:01:03,634 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:03,635 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723833961] [2019-11-20 07:01:03,635 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:03,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:03,751 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-20 07:01:03,751 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723833961] [2019-11-20 07:01:03,752 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:01:03,752 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:01:03,754 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [472756097] [2019-11-20 07:01:03,754 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 07:01:03,754 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:03,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 07:01:03,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:01:03,755 INFO L87 Difference]: Start difference. First operand 1067 states and 1365 transitions. Second operand 5 states. [2019-11-20 07:01:03,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:04,000 INFO L93 Difference]: Finished difference Result 1927 states and 2501 transitions. [2019-11-20 07:01:04,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:01:04,000 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 133 [2019-11-20 07:01:04,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:04,002 INFO L225 Difference]: With dead ends: 1927 [2019-11-20 07:01:04,002 INFO L226 Difference]: Without dead ends: 992 [2019-11-20 07:01:04,005 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:01:04,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 992 states. [2019-11-20 07:01:04,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 992 to 992. [2019-11-20 07:01:04,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 992 states. [2019-11-20 07:01:04,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 992 states to 992 states and 1276 transitions. [2019-11-20 07:01:04,154 INFO L78 Accepts]: Start accepts. Automaton has 992 states and 1276 transitions. Word has length 133 [2019-11-20 07:01:04,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:04,155 INFO L462 AbstractCegarLoop]: Abstraction has 992 states and 1276 transitions. [2019-11-20 07:01:04,155 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 07:01:04,155 INFO L276 IsEmpty]: Start isEmpty. Operand 992 states and 1276 transitions. [2019-11-20 07:01:04,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-20 07:01:04,158 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:04,158 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:04,158 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:04,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:04,159 INFO L82 PathProgramCache]: Analyzing trace with hash 219147919, now seen corresponding path program 1 times [2019-11-20 07:01:04,159 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:04,159 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982382637] [2019-11-20 07:01:04,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:04,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:04,426 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 26 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:04,426 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982382637] [2019-11-20 07:01:04,426 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [800040315] [2019-11-20 07:01:04,427 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:04,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:04,622 INFO L255 TraceCheckSpWp]: Trace formula consists of 764 conjuncts, 47 conjunts are in the unsatisfiable core [2019-11-20 07:01:04,625 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:01:05,072 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 26 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:05,073 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 07:01:05,073 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-11-20 07:01:05,074 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727258091] [2019-11-20 07:01:05,074 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-20 07:01:05,074 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:05,075 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-20 07:01:05,075 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2019-11-20 07:01:05,075 INFO L87 Difference]: Start difference. First operand 992 states and 1276 transitions. Second operand 21 states. [2019-11-20 07:01:08,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:08,228 INFO L93 Difference]: Finished difference Result 2980 states and 3873 transitions. [2019-11-20 07:01:08,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2019-11-20 07:01:08,228 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 134 [2019-11-20 07:01:08,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:08,232 INFO L225 Difference]: With dead ends: 2980 [2019-11-20 07:01:08,232 INFO L226 Difference]: Without dead ends: 2175 [2019-11-20 07:01:08,235 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 194 GetRequests, 120 SyntacticMatches, 4 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1431 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=927, Invalid=4185, Unknown=0, NotChecked=0, Total=5112 [2019-11-20 07:01:08,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2175 states. [2019-11-20 07:01:08,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2175 to 1178. [2019-11-20 07:01:08,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1178 states. [2019-11-20 07:01:08,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1178 states to 1178 states and 1510 transitions. [2019-11-20 07:01:08,412 INFO L78 Accepts]: Start accepts. Automaton has 1178 states and 1510 transitions. Word has length 134 [2019-11-20 07:01:08,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:08,412 INFO L462 AbstractCegarLoop]: Abstraction has 1178 states and 1510 transitions. [2019-11-20 07:01:08,412 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-20 07:01:08,412 INFO L276 IsEmpty]: Start isEmpty. Operand 1178 states and 1510 transitions. [2019-11-20 07:01:08,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-20 07:01:08,415 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:08,415 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:08,627 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:08,628 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:08,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:08,629 INFO L82 PathProgramCache]: Analyzing trace with hash -1087994479, now seen corresponding path program 1 times [2019-11-20 07:01:08,629 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:08,629 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347048898] [2019-11-20 07:01:08,629 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:08,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:08,688 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-20 07:01:08,688 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347048898] [2019-11-20 07:01:08,688 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:01:08,688 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:01:08,689 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058475290] [2019-11-20 07:01:08,689 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 07:01:08,689 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:08,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 07:01:08,690 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:01:08,690 INFO L87 Difference]: Start difference. First operand 1178 states and 1510 transitions. Second operand 4 states. [2019-11-20 07:01:08,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:08,942 INFO L93 Difference]: Finished difference Result 2062 states and 2671 transitions. [2019-11-20 07:01:08,942 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 07:01:08,942 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 134 [2019-11-20 07:01:08,943 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:08,944 INFO L225 Difference]: With dead ends: 2062 [2019-11-20 07:01:08,945 INFO L226 Difference]: Without dead ends: 1014 [2019-11-20 07:01:08,946 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:01:08,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1014 states. [2019-11-20 07:01:09,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1014 to 1014. [2019-11-20 07:01:09,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1014 states. [2019-11-20 07:01:09,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1014 states to 1014 states and 1292 transitions. [2019-11-20 07:01:09,090 INFO L78 Accepts]: Start accepts. Automaton has 1014 states and 1292 transitions. Word has length 134 [2019-11-20 07:01:09,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:09,090 INFO L462 AbstractCegarLoop]: Abstraction has 1014 states and 1292 transitions. [2019-11-20 07:01:09,091 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 07:01:09,091 INFO L276 IsEmpty]: Start isEmpty. Operand 1014 states and 1292 transitions. [2019-11-20 07:01:09,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-20 07:01:09,093 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:09,094 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:09,094 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:09,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:09,095 INFO L82 PathProgramCache]: Analyzing trace with hash 440475699, now seen corresponding path program 1 times [2019-11-20 07:01:09,095 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:09,095 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [846354023] [2019-11-20 07:01:09,095 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:09,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:09,323 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:09,323 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [846354023] [2019-11-20 07:01:09,324 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1541325277] [2019-11-20 07:01:09,324 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:09,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:09,511 INFO L255 TraceCheckSpWp]: Trace formula consists of 765 conjuncts, 31 conjunts are in the unsatisfiable core [2019-11-20 07:01:09,514 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:01:09,779 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:09,779 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 07:01:09,780 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 11] total 17 [2019-11-20 07:01:09,780 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [811521254] [2019-11-20 07:01:09,780 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-11-20 07:01:09,780 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:09,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-11-20 07:01:09,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=239, Unknown=0, NotChecked=0, Total=306 [2019-11-20 07:01:09,781 INFO L87 Difference]: Start difference. First operand 1014 states and 1292 transitions. Second operand 18 states. [2019-11-20 07:01:12,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:12,074 INFO L93 Difference]: Finished difference Result 4336 states and 5610 transitions. [2019-11-20 07:01:12,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-11-20 07:01:12,074 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 135 [2019-11-20 07:01:12,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:12,080 INFO L225 Difference]: With dead ends: 4336 [2019-11-20 07:01:12,081 INFO L226 Difference]: Without dead ends: 3509 [2019-11-20 07:01:12,084 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 189 GetRequests, 123 SyntacticMatches, 3 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1399 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=942, Invalid=3218, Unknown=0, NotChecked=0, Total=4160 [2019-11-20 07:01:12,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3509 states. [2019-11-20 07:01:12,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3509 to 1471. [2019-11-20 07:01:12,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1471 states. [2019-11-20 07:01:12,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1471 states to 1471 states and 1889 transitions. [2019-11-20 07:01:12,381 INFO L78 Accepts]: Start accepts. Automaton has 1471 states and 1889 transitions. Word has length 135 [2019-11-20 07:01:12,382 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:12,382 INFO L462 AbstractCegarLoop]: Abstraction has 1471 states and 1889 transitions. [2019-11-20 07:01:12,382 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-11-20 07:01:12,382 INFO L276 IsEmpty]: Start isEmpty. Operand 1471 states and 1889 transitions. [2019-11-20 07:01:12,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-20 07:01:12,385 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:12,385 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:12,588 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:12,588 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:12,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:12,589 INFO L82 PathProgramCache]: Analyzing trace with hash -416406862, now seen corresponding path program 1 times [2019-11-20 07:01:12,589 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:12,589 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647566595] [2019-11-20 07:01:12,589 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:12,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:12,913 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:12,913 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1647566595] [2019-11-20 07:01:12,913 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2032110418] [2019-11-20 07:01:12,913 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:13,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:13,090 INFO L255 TraceCheckSpWp]: Trace formula consists of 775 conjuncts, 8 conjunts are in the unsatisfiable core [2019-11-20 07:01:13,092 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:01:13,163 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 07:01:13,164 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 07:01:13,164 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-11-20 07:01:13,164 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328679652] [2019-11-20 07:01:13,165 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:01:13,165 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:13,165 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:01:13,165 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-11-20 07:01:13,166 INFO L87 Difference]: Start difference. First operand 1471 states and 1889 transitions. Second operand 6 states. [2019-11-20 07:01:13,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:13,655 INFO L93 Difference]: Finished difference Result 4365 states and 5753 transitions. [2019-11-20 07:01:13,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-20 07:01:13,655 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 136 [2019-11-20 07:01:13,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:13,661 INFO L225 Difference]: With dead ends: 4365 [2019-11-20 07:01:13,662 INFO L226 Difference]: Without dead ends: 3228 [2019-11-20 07:01:13,664 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 152 GetRequests, 133 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-11-20 07:01:13,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3228 states. [2019-11-20 07:01:13,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3228 to 1471. [2019-11-20 07:01:13,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1471 states. [2019-11-20 07:01:13,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1471 states to 1471 states and 1887 transitions. [2019-11-20 07:01:13,888 INFO L78 Accepts]: Start accepts. Automaton has 1471 states and 1887 transitions. Word has length 136 [2019-11-20 07:01:13,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:13,889 INFO L462 AbstractCegarLoop]: Abstraction has 1471 states and 1887 transitions. [2019-11-20 07:01:13,889 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:01:13,889 INFO L276 IsEmpty]: Start isEmpty. Operand 1471 states and 1887 transitions. [2019-11-20 07:01:13,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-20 07:01:13,892 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:13,892 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:14,095 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:14,099 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:14,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:14,100 INFO L82 PathProgramCache]: Analyzing trace with hash -330077116, now seen corresponding path program 1 times [2019-11-20 07:01:14,100 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:14,100 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458601446] [2019-11-20 07:01:14,100 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:14,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:14,188 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-20 07:01:14,188 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458601446] [2019-11-20 07:01:14,188 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:01:14,189 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 07:01:14,189 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018688625] [2019-11-20 07:01:14,189 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:01:14,189 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:14,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:01:14,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 07:01:14,190 INFO L87 Difference]: Start difference. First operand 1471 states and 1887 transitions. Second operand 6 states. [2019-11-20 07:01:15,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:15,178 INFO L93 Difference]: Finished difference Result 7797 states and 10159 transitions. [2019-11-20 07:01:15,179 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-11-20 07:01:15,179 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 136 [2019-11-20 07:01:15,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:15,190 INFO L225 Difference]: With dead ends: 7797 [2019-11-20 07:01:15,190 INFO L226 Difference]: Without dead ends: 6513 [2019-11-20 07:01:15,193 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2019-11-20 07:01:15,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6513 states. [2019-11-20 07:01:15,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6513 to 1841. [2019-11-20 07:01:15,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1841 states. [2019-11-20 07:01:15,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1841 states to 1841 states and 2319 transitions. [2019-11-20 07:01:15,518 INFO L78 Accepts]: Start accepts. Automaton has 1841 states and 2319 transitions. Word has length 136 [2019-11-20 07:01:15,519 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:15,519 INFO L462 AbstractCegarLoop]: Abstraction has 1841 states and 2319 transitions. [2019-11-20 07:01:15,519 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:01:15,519 INFO L276 IsEmpty]: Start isEmpty. Operand 1841 states and 2319 transitions. [2019-11-20 07:01:15,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2019-11-20 07:01:15,524 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:15,524 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:15,524 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:15,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:15,525 INFO L82 PathProgramCache]: Analyzing trace with hash 633057662, now seen corresponding path program 1 times [2019-11-20 07:01:15,525 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:15,525 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430268127] [2019-11-20 07:01:15,525 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:15,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:15,792 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:15,792 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430268127] [2019-11-20 07:01:15,792 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1612043328] [2019-11-20 07:01:15,792 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:15,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:15,954 INFO L255 TraceCheckSpWp]: Trace formula consists of 787 conjuncts, 14 conjunts are in the unsatisfiable core [2019-11-20 07:01:15,956 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:01:16,051 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 8 proven. 33 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:16,051 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 07:01:16,051 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 7] total 17 [2019-11-20 07:01:16,052 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262407518] [2019-11-20 07:01:16,054 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-11-20 07:01:16,055 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:16,055 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-11-20 07:01:16,056 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-11-20 07:01:16,056 INFO L87 Difference]: Start difference. First operand 1841 states and 2319 transitions. Second operand 17 states. [2019-11-20 07:01:24,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:24,208 INFO L93 Difference]: Finished difference Result 9713 states and 12603 transitions. [2019-11-20 07:01:24,208 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 147 states. [2019-11-20 07:01:24,208 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 139 [2019-11-20 07:01:24,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:24,214 INFO L225 Difference]: With dead ends: 9713 [2019-11-20 07:01:24,214 INFO L226 Difference]: Without dead ends: 8254 [2019-11-20 07:01:24,223 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 320 GetRequests, 161 SyntacticMatches, 0 SemanticMatches, 159 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10632 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=4619, Invalid=21141, Unknown=0, NotChecked=0, Total=25760 [2019-11-20 07:01:24,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8254 states. [2019-11-20 07:01:24,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8254 to 2444. [2019-11-20 07:01:24,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2444 states. [2019-11-20 07:01:24,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2444 states to 2444 states and 3084 transitions. [2019-11-20 07:01:24,653 INFO L78 Accepts]: Start accepts. Automaton has 2444 states and 3084 transitions. Word has length 139 [2019-11-20 07:01:24,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:24,653 INFO L462 AbstractCegarLoop]: Abstraction has 2444 states and 3084 transitions. [2019-11-20 07:01:24,654 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-11-20 07:01:24,654 INFO L276 IsEmpty]: Start isEmpty. Operand 2444 states and 3084 transitions. [2019-11-20 07:01:24,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2019-11-20 07:01:24,656 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:24,656 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:24,857 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:24,857 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:24,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:24,858 INFO L82 PathProgramCache]: Analyzing trace with hash -1379305215, now seen corresponding path program 1 times [2019-11-20 07:01:24,858 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:24,858 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183363771] [2019-11-20 07:01:24,858 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:24,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:25,002 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:25,002 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [183363771] [2019-11-20 07:01:25,002 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1961970613] [2019-11-20 07:01:25,003 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:25,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:25,194 INFO L255 TraceCheckSpWp]: Trace formula consists of 769 conjuncts, 18 conjunts are in the unsatisfiable core [2019-11-20 07:01:25,196 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:01:25,229 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:25,229 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 07:01:25,230 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 8 [2019-11-20 07:01:25,230 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343960465] [2019-11-20 07:01:25,230 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-11-20 07:01:25,230 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:25,231 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-20 07:01:25,231 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-11-20 07:01:25,231 INFO L87 Difference]: Start difference. First operand 2444 states and 3084 transitions. Second operand 8 states. [2019-11-20 07:01:26,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:26,482 INFO L93 Difference]: Finished difference Result 9037 states and 11497 transitions. [2019-11-20 07:01:26,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-11-20 07:01:26,483 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 139 [2019-11-20 07:01:26,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:26,489 INFO L225 Difference]: With dead ends: 9037 [2019-11-20 07:01:26,489 INFO L226 Difference]: Without dead ends: 6843 [2019-11-20 07:01:26,493 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=129, Invalid=423, Unknown=0, NotChecked=0, Total=552 [2019-11-20 07:01:26,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6843 states. [2019-11-20 07:01:27,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6843 to 3832. [2019-11-20 07:01:27,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3832 states. [2019-11-20 07:01:27,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3832 states to 3832 states and 4851 transitions. [2019-11-20 07:01:27,053 INFO L78 Accepts]: Start accepts. Automaton has 3832 states and 4851 transitions. Word has length 139 [2019-11-20 07:01:27,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:27,054 INFO L462 AbstractCegarLoop]: Abstraction has 3832 states and 4851 transitions. [2019-11-20 07:01:27,054 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-11-20 07:01:27,054 INFO L276 IsEmpty]: Start isEmpty. Operand 3832 states and 4851 transitions. [2019-11-20 07:01:27,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2019-11-20 07:01:27,057 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:27,057 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:27,261 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:27,261 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:27,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:27,262 INFO L82 PathProgramCache]: Analyzing trace with hash 9988799, now seen corresponding path program 1 times [2019-11-20 07:01:27,262 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:27,262 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434315216] [2019-11-20 07:01:27,262 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:27,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:27,319 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-20 07:01:27,319 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1434315216] [2019-11-20 07:01:27,320 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:01:27,320 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:01:27,320 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465871974] [2019-11-20 07:01:27,321 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 07:01:27,322 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:27,322 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 07:01:27,322 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:01:27,323 INFO L87 Difference]: Start difference. First operand 3832 states and 4851 transitions. Second operand 4 states. [2019-11-20 07:01:27,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:27,929 INFO L93 Difference]: Finished difference Result 6501 states and 8303 transitions. [2019-11-20 07:01:27,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 07:01:27,929 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 139 [2019-11-20 07:01:27,929 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:27,932 INFO L225 Difference]: With dead ends: 6501 [2019-11-20 07:01:27,932 INFO L226 Difference]: Without dead ends: 2919 [2019-11-20 07:01:27,936 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:01:27,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2919 states. [2019-11-20 07:01:28,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2919 to 2907. [2019-11-20 07:01:28,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2907 states. [2019-11-20 07:01:28,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2907 states to 2907 states and 3673 transitions. [2019-11-20 07:01:28,555 INFO L78 Accepts]: Start accepts. Automaton has 2907 states and 3673 transitions. Word has length 139 [2019-11-20 07:01:28,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:28,556 INFO L462 AbstractCegarLoop]: Abstraction has 2907 states and 3673 transitions. [2019-11-20 07:01:28,556 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 07:01:28,556 INFO L276 IsEmpty]: Start isEmpty. Operand 2907 states and 3673 transitions. [2019-11-20 07:01:28,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2019-11-20 07:01:28,559 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:28,559 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:28,560 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:28,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:28,560 INFO L82 PathProgramCache]: Analyzing trace with hash 850968806, now seen corresponding path program 1 times [2019-11-20 07:01:28,560 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:28,561 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835325934] [2019-11-20 07:01:28,561 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:28,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:28,698 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-20 07:01:28,699 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1835325934] [2019-11-20 07:01:28,699 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:01:28,699 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 07:01:28,699 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561939441] [2019-11-20 07:01:28,700 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-20 07:01:28,700 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:28,700 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 07:01:28,700 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 07:01:28,701 INFO L87 Difference]: Start difference. First operand 2907 states and 3673 transitions. Second operand 6 states. [2019-11-20 07:01:29,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:29,860 INFO L93 Difference]: Finished difference Result 9661 states and 12524 transitions. [2019-11-20 07:01:29,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-20 07:01:29,861 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 143 [2019-11-20 07:01:29,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:29,872 INFO L225 Difference]: With dead ends: 9661 [2019-11-20 07:01:29,872 INFO L226 Difference]: Without dead ends: 7191 [2019-11-20 07:01:29,875 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-20 07:01:29,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7191 states. [2019-11-20 07:01:30,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7191 to 2987. [2019-11-20 07:01:30,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2987 states. [2019-11-20 07:01:30,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2987 states to 2987 states and 3766 transitions. [2019-11-20 07:01:30,261 INFO L78 Accepts]: Start accepts. Automaton has 2987 states and 3766 transitions. Word has length 143 [2019-11-20 07:01:30,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:30,262 INFO L462 AbstractCegarLoop]: Abstraction has 2987 states and 3766 transitions. [2019-11-20 07:01:30,262 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-20 07:01:30,262 INFO L276 IsEmpty]: Start isEmpty. Operand 2987 states and 3766 transitions. [2019-11-20 07:01:30,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2019-11-20 07:01:30,265 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:30,265 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:30,265 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:30,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:30,266 INFO L82 PathProgramCache]: Analyzing trace with hash 1499523083, now seen corresponding path program 1 times [2019-11-20 07:01:30,266 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:30,266 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351185759] [2019-11-20 07:01:30,266 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:30,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:30,312 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-11-20 07:01:30,312 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351185759] [2019-11-20 07:01:30,312 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 07:01:30,313 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 07:01:30,313 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226158295] [2019-11-20 07:01:30,313 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 07:01:30,313 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:30,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 07:01:30,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 07:01:30,314 INFO L87 Difference]: Start difference. First operand 2987 states and 3766 transitions. Second operand 4 states. [2019-11-20 07:01:31,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:31,147 INFO L93 Difference]: Finished difference Result 7420 states and 9386 transitions. [2019-11-20 07:01:31,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:01:31,148 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 144 [2019-11-20 07:01:31,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:31,151 INFO L225 Difference]: With dead ends: 7420 [2019-11-20 07:01:31,151 INFO L226 Difference]: Without dead ends: 4714 [2019-11-20 07:01:31,154 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 07:01:31,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4714 states. [2019-11-20 07:01:31,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4714 to 3019. [2019-11-20 07:01:31,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3019 states. [2019-11-20 07:01:31,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3019 states to 3019 states and 3790 transitions. [2019-11-20 07:01:31,546 INFO L78 Accepts]: Start accepts. Automaton has 3019 states and 3790 transitions. Word has length 144 [2019-11-20 07:01:31,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:31,546 INFO L462 AbstractCegarLoop]: Abstraction has 3019 states and 3790 transitions. [2019-11-20 07:01:31,546 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 07:01:31,546 INFO L276 IsEmpty]: Start isEmpty. Operand 3019 states and 3790 transitions. [2019-11-20 07:01:31,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2019-11-20 07:01:31,549 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:31,549 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:31,550 INFO L410 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:31,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:31,550 INFO L82 PathProgramCache]: Analyzing trace with hash -1504651889, now seen corresponding path program 1 times [2019-11-20 07:01:31,550 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:31,551 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [525730818] [2019-11-20 07:01:31,551 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:31,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:31,654 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 41 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:31,655 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [525730818] [2019-11-20 07:01:31,655 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [33614270] [2019-11-20 07:01:31,655 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:31,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:31,844 INFO L255 TraceCheckSpWp]: Trace formula consists of 794 conjuncts, 5 conjunts are in the unsatisfiable core [2019-11-20 07:01:31,847 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:01:31,886 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-11-20 07:01:31,886 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-11-20 07:01:31,886 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 10 [2019-11-20 07:01:31,886 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [746001646] [2019-11-20 07:01:31,887 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 07:01:31,887 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:31,887 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 07:01:31,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-11-20 07:01:31,887 INFO L87 Difference]: Start difference. First operand 3019 states and 3790 transitions. Second operand 5 states. [2019-11-20 07:01:32,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:32,310 INFO L93 Difference]: Finished difference Result 5566 states and 7031 transitions. [2019-11-20 07:01:32,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 07:01:32,310 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 144 [2019-11-20 07:01:32,310 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:32,312 INFO L225 Difference]: With dead ends: 5566 [2019-11-20 07:01:32,312 INFO L226 Difference]: Without dead ends: 2797 [2019-11-20 07:01:32,314 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 142 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-11-20 07:01:32,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2797 states. [2019-11-20 07:01:32,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2797 to 2797. [2019-11-20 07:01:32,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2797 states. [2019-11-20 07:01:32,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2797 states to 2797 states and 3527 transitions. [2019-11-20 07:01:32,665 INFO L78 Accepts]: Start accepts. Automaton has 2797 states and 3527 transitions. Word has length 144 [2019-11-20 07:01:32,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:32,665 INFO L462 AbstractCegarLoop]: Abstraction has 2797 states and 3527 transitions. [2019-11-20 07:01:32,665 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 07:01:32,666 INFO L276 IsEmpty]: Start isEmpty. Operand 2797 states and 3527 transitions. [2019-11-20 07:01:32,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2019-11-20 07:01:32,667 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:32,667 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:32,868 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:32,868 INFO L410 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:32,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:32,868 INFO L82 PathProgramCache]: Analyzing trace with hash -710176924, now seen corresponding path program 1 times [2019-11-20 07:01:32,868 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:32,869 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080444996] [2019-11-20 07:01:32,869 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:32,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:33,155 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 17 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:33,156 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080444996] [2019-11-20 07:01:33,156 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [279266760] [2019-11-20 07:01:33,156 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:33,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 07:01:33,340 INFO L255 TraceCheckSpWp]: Trace formula consists of 783 conjuncts, 14 conjunts are in the unsatisfiable core [2019-11-20 07:01:33,343 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 07:01:33,416 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 17 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 07:01:33,416 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 07:01:33,417 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2019-11-20 07:01:33,417 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607750666] [2019-11-20 07:01:33,417 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-20 07:01:33,417 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 07:01:33,418 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-20 07:01:33,418 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-11-20 07:01:33,418 INFO L87 Difference]: Start difference. First operand 2797 states and 3527 transitions. Second operand 7 states. [2019-11-20 07:01:34,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 07:01:34,699 INFO L93 Difference]: Finished difference Result 8201 states and 10547 transitions. [2019-11-20 07:01:34,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-11-20 07:01:34,699 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 144 [2019-11-20 07:01:34,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 07:01:34,704 INFO L225 Difference]: With dead ends: 8201 [2019-11-20 07:01:34,705 INFO L226 Difference]: Without dead ends: 5611 [2019-11-20 07:01:34,708 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 149 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=138, Invalid=324, Unknown=0, NotChecked=0, Total=462 [2019-11-20 07:01:34,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5611 states. [2019-11-20 07:01:35,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5611 to 2797. [2019-11-20 07:01:35,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2797 states. [2019-11-20 07:01:35,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2797 states to 2797 states and 3502 transitions. [2019-11-20 07:01:35,081 INFO L78 Accepts]: Start accepts. Automaton has 2797 states and 3502 transitions. Word has length 144 [2019-11-20 07:01:35,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 07:01:35,081 INFO L462 AbstractCegarLoop]: Abstraction has 2797 states and 3502 transitions. [2019-11-20 07:01:35,081 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-20 07:01:35,081 INFO L276 IsEmpty]: Start isEmpty. Operand 2797 states and 3502 transitions. [2019-11-20 07:01:35,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2019-11-20 07:01:35,083 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 07:01:35,083 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 07:01:35,284 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 07:01:35,284 INFO L410 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 07:01:35,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 07:01:35,284 INFO L82 PathProgramCache]: Analyzing trace with hash -1523121785, now seen corresponding path program 1 times [2019-11-20 07:01:35,284 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 07:01:35,285 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882926174] [2019-11-20 07:01:35,285 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 07:01:35,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 07:01:35,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 07:01:35,453 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 07:01:35,453 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-20 07:01:35,635 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 20.11 07:01:35 BoogieIcfgContainer [2019-11-20 07:01:35,636 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-20 07:01:35,636 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-20 07:01:35,636 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-20 07:01:35,637 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-20 07:01:35,637 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 07:00:42" (3/4) ... [2019-11-20 07:01:35,639 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-20 07:01:35,836 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_849034f1-d6c2-453d-8553-a6c7c47d6895/bin/uautomizer/witness.graphml [2019-11-20 07:01:35,836 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-20 07:01:35,838 INFO L168 Benchmark]: Toolchain (without parser) took 55291.41 ms. Allocated memory was 1.0 GB in the beginning and 2.5 GB in the end (delta: 1.5 GB). Free memory was 951.4 MB in the beginning and 1.1 GB in the end (delta: -177.1 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2019-11-20 07:01:35,838 INFO L168 Benchmark]: CDTParser took 0.30 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 07:01:35,839 INFO L168 Benchmark]: CACSL2BoogieTranslator took 575.00 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.8 MB). Free memory was 946.0 MB in the beginning and 1.1 GB in the end (delta: -173.0 MB). Peak memory consumption was 17.7 MB. Max. memory is 11.5 GB. [2019-11-20 07:01:35,839 INFO L168 Benchmark]: Boogie Procedure Inliner took 70.47 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.0 MB). Peak memory consumption was 7.0 MB. Max. memory is 11.5 GB. [2019-11-20 07:01:35,839 INFO L168 Benchmark]: Boogie Preprocessor took 100.01 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 07:01:35,840 INFO L168 Benchmark]: RCFGBuilder took 1292.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 91.7 MB). Peak memory consumption was 91.7 MB. Max. memory is 11.5 GB. [2019-11-20 07:01:35,840 INFO L168 Benchmark]: TraceAbstraction took 53046.01 ms. Allocated memory was 1.2 GB in the beginning and 2.5 GB in the end (delta: 1.4 GB). Free memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: -185.8 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2019-11-20 07:01:35,840 INFO L168 Benchmark]: Witness Printer took 200.10 ms. Allocated memory is still 2.5 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 77.7 MB). Peak memory consumption was 77.7 MB. Max. memory is 11.5 GB. [2019-11-20 07:01:35,842 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.30 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 575.00 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.8 MB). Free memory was 946.0 MB in the beginning and 1.1 GB in the end (delta: -173.0 MB). Peak memory consumption was 17.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 70.47 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.0 MB). Peak memory consumption was 7.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 100.01 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 1292.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 91.7 MB). Peak memory consumption was 91.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 53046.01 ms. Allocated memory was 1.2 GB in the beginning and 2.5 GB in the end (delta: 1.4 GB). Free memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: -185.8 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. * Witness Printer took 200.10 ms. Allocated memory is still 2.5 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 77.7 MB). Peak memory consumption was 77.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 661]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L463] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L585] int c1 ; [L586] int i2 ; [L589] c1 = 0 [L590] side1Failed = __VERIFIER_nondet_bool() [L591] side2Failed = __VERIFIER_nondet_bool() [L592] side1_written = __VERIFIER_nondet_char() [L593] side2_written = __VERIFIER_nondet_char() [L594] side1Failed_History_0 = __VERIFIER_nondet_bool() [L595] side1Failed_History_1 = __VERIFIER_nondet_bool() [L596] side1Failed_History_2 = __VERIFIER_nondet_bool() [L597] side2Failed_History_0 = __VERIFIER_nondet_bool() [L598] side2Failed_History_1 = __VERIFIER_nondet_bool() [L599] side2Failed_History_2 = __VERIFIER_nondet_bool() [L600] active_side_History_0 = __VERIFIER_nondet_char() [L601] active_side_History_1 = __VERIFIER_nondet_char() [L602] active_side_History_2 = __VERIFIER_nondet_char() [L603] manual_selection_History_0 = __VERIFIER_nondet_char() [L604] manual_selection_History_1 = __VERIFIER_nondet_char() [L605] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L606] i2 = init() [L608] cs1_old = nomsg [L609] cs1_new = nomsg [L610] cs2_old = nomsg [L611] cs2_new = nomsg [L612] s1s2_old = nomsg [L613] s1s2_new = nomsg [L614] s1s1_old = nomsg [L615] s1s1_new = nomsg [L616] s2s1_old = nomsg [L617] s2s1_new = nomsg [L618] s2s2_old = nomsg [L619] s2s2_new = nomsg [L620] s1p_old = nomsg [L621] s1p_new = nomsg [L622] s2p_old = nomsg [L623] s2p_new = nomsg [L624] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE 1 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND FALSE !((int )side2 == 0) [L454] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L501] tmp___1 = read_side1_failed_history((unsigned char)1) [L502] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L503] tmp___2 = read_side1_failed_history((unsigned char)0) [L504] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L545] tmp___11 = read_side1_failed_history((unsigned char)1) [L546] COND TRUE ! tmp___11 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L547] tmp___12 = read_side2_failed_history((unsigned char)1) [L548] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L561] tmp___20 = read_active_side_history((unsigned char)2) [L562] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L580] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L659] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE 1 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L392] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L393] COND TRUE (int )side2 != (int )nomsg [L394] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND TRUE (int )side2 == 0 [L452] active_side = (int8_t )2 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND FALSE !(! tmp___0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND TRUE \read(tmp___7) [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L531] tmp___8 = read_side2_failed_history((unsigned char)1) [L532] COND TRUE ! tmp___8 [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L533] tmp___5 = read_active_side_history((unsigned char)0) [L534] COND FALSE !(! ((int )tmp___5 == 2)) [L160] COND TRUE (int )index == 0 [L161] return (side2Failed_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] tmp___6 = read_side2_failed_history((unsigned char)0) [L538] COND TRUE ! tmp___6 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L539] COND TRUE ! ((int )side2_written == 1) [L540] return (0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L659] COND TRUE ! arg VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L661] __VERIFIER_error() VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 292 locations, 23 error locations. Result: UNSAFE, OverallTime: 52.9s, OverallIterations: 46, TraceHistogramMax: 2, AutomataDifference: 31.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 20833 SDtfs, 43914 SDslu, 57800 SDs, 0 SdLazy, 11322 SolverSat, 632 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 8.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2332 GetRequests, 1687 SyntacticMatches, 25 SemanticMatches, 620 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14472 ImplicationChecksByTransitivity, 12.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3832occurred in iteration=40, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 6.9s AutomataMinimizationTime, 45 MinimizatonAttempts, 41649 StatesRemovedByMinimization, 40 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.7s SsaConstructionTime, 2.4s SatisfiabilityAnalysisTime, 6.4s InterpolantComputationTime, 6021 NumberOfCodeBlocks, 6021 NumberOfCodeBlocksAsserted, 58 NumberOfCheckSat, 5820 ConstructedInterpolants, 0 QuantifiedInterpolants, 2762353 SizeOfPredicates, 63 NumberOfNonLiveVariables, 9156 ConjunctsInSsa, 219 ConjunctsInUnsatCore, 57 InterpolantComputations, 39 PerfectInterpolantSequences, 918/1149 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...