./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/toy1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 678e0110 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/toy1.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-678e011 [2019-11-20 04:35:30,327 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-20 04:35:30,329 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-20 04:35:30,344 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-20 04:35:30,344 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-20 04:35:30,345 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-20 04:35:30,347 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-20 04:35:30,355 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-20 04:35:30,359 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-20 04:35:30,363 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-20 04:35:30,364 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-20 04:35:30,365 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-20 04:35:30,365 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-20 04:35:30,367 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-20 04:35:30,368 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-20 04:35:30,369 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-20 04:35:30,370 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-20 04:35:30,370 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-20 04:35:30,372 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-20 04:35:30,376 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-20 04:35:30,379 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-20 04:35:30,380 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-20 04:35:30,383 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-20 04:35:30,384 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-20 04:35:30,386 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-20 04:35:30,387 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-20 04:35:30,387 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-20 04:35:30,388 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-20 04:35:30,388 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-20 04:35:30,389 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-20 04:35:30,389 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-20 04:35:30,390 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-20 04:35:30,390 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-20 04:35:30,391 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-20 04:35:30,392 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-20 04:35:30,392 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-20 04:35:30,393 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-20 04:35:30,393 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-20 04:35:30,393 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-20 04:35:30,394 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-20 04:35:30,395 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-20 04:35:30,395 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-20 04:35:30,418 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-20 04:35:30,419 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-20 04:35:30,419 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-20 04:35:30,420 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-20 04:35:30,420 INFO L138 SettingsManager]: * Use SBE=true [2019-11-20 04:35:30,420 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-20 04:35:30,420 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-20 04:35:30,420 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-20 04:35:30,421 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-20 04:35:30,421 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-20 04:35:30,421 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-20 04:35:30,421 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-20 04:35:30,421 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-20 04:35:30,421 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-20 04:35:30,422 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-20 04:35:30,422 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-20 04:35:30,422 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-20 04:35:30,422 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-20 04:35:30,422 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-20 04:35:30,422 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-20 04:35:30,423 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-20 04:35:30,423 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 04:35:30,423 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-20 04:35:30,423 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-20 04:35:30,423 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-20 04:35:30,424 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-20 04:35:30,424 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-20 04:35:30,424 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-20 04:35:30,424 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 [2019-11-20 04:35:30,567 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-20 04:35:30,581 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-20 04:35:30,583 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-20 04:35:30,585 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-20 04:35:30,585 INFO L275 PluginConnector]: CDTParser initialized [2019-11-20 04:35:30,586 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/../../sv-benchmarks/c/systemc/toy1.cil.c [2019-11-20 04:35:30,641 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/data/f56392db6/1492fa6f1619418399fe1d93e864bd35/FLAG0fa03afed [2019-11-20 04:35:31,067 INFO L306 CDTParser]: Found 1 translation units. [2019-11-20 04:35:31,068 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/sv-benchmarks/c/systemc/toy1.cil.c [2019-11-20 04:35:31,085 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/data/f56392db6/1492fa6f1619418399fe1d93e864bd35/FLAG0fa03afed [2019-11-20 04:35:31,434 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/data/f56392db6/1492fa6f1619418399fe1d93e864bd35 [2019-11-20 04:35:31,436 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-20 04:35:31,437 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-20 04:35:31,437 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-20 04:35:31,437 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-20 04:35:31,439 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-20 04:35:31,440 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 04:35:31" (1/1) ... [2019-11-20 04:35:31,441 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7c912e4d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31, skipping insertion in model container [2019-11-20 04:35:31,441 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 04:35:31" (1/1) ... [2019-11-20 04:35:31,460 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-20 04:35:31,509 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-20 04:35:31,842 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 04:35:31,847 INFO L188 MainTranslator]: Completed pre-run [2019-11-20 04:35:31,895 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 04:35:31,910 INFO L192 MainTranslator]: Completed translation [2019-11-20 04:35:31,911 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31 WrapperNode [2019-11-20 04:35:31,911 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-20 04:35:31,912 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-20 04:35:31,912 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-20 04:35:31,912 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-20 04:35:31,923 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31" (1/1) ... [2019-11-20 04:35:31,936 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31" (1/1) ... [2019-11-20 04:35:31,977 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-20 04:35:31,977 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-20 04:35:31,978 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-20 04:35:31,978 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-20 04:35:31,985 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31" (1/1) ... [2019-11-20 04:35:31,985 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31" (1/1) ... [2019-11-20 04:35:31,988 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31" (1/1) ... [2019-11-20 04:35:31,988 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31" (1/1) ... [2019-11-20 04:35:31,993 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31" (1/1) ... [2019-11-20 04:35:32,018 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31" (1/1) ... [2019-11-20 04:35:32,025 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31" (1/1) ... [2019-11-20 04:35:32,028 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-20 04:35:32,029 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-20 04:35:32,029 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-20 04:35:32,029 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-20 04:35:32,038 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 04:35:32,083 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-20 04:35:32,083 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-20 04:35:32,741 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-20 04:35:32,741 INFO L285 CfgBuilder]: Removed 28 assume(true) statements. [2019-11-20 04:35:32,742 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 04:35:32 BoogieIcfgContainer [2019-11-20 04:35:32,742 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-20 04:35:32,743 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-20 04:35:32,743 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-20 04:35:32,746 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-20 04:35:32,746 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.11 04:35:31" (1/3) ... [2019-11-20 04:35:32,746 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@140b5931 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 04:35:32, skipping insertion in model container [2019-11-20 04:35:32,747 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:35:31" (2/3) ... [2019-11-20 04:35:32,747 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@140b5931 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 04:35:32, skipping insertion in model container [2019-11-20 04:35:32,747 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 04:35:32" (3/3) ... [2019-11-20 04:35:32,749 INFO L109 eAbstractionObserver]: Analyzing ICFG toy1.cil.c [2019-11-20 04:35:32,760 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-20 04:35:32,769 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-20 04:35:32,784 INFO L249 AbstractCegarLoop]: Starting to check reachability of 2 error locations. [2019-11-20 04:35:32,811 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-20 04:35:32,812 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-20 04:35:32,812 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-20 04:35:32,812 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-20 04:35:32,813 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-20 04:35:32,813 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-20 04:35:32,813 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-20 04:35:32,816 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-20 04:35:32,831 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states. [2019-11-20 04:35:32,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-20 04:35:32,840 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:32,841 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:32,841 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:32,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:32,845 INFO L82 PathProgramCache]: Analyzing trace with hash -895778166, now seen corresponding path program 1 times [2019-11-20 04:35:32,852 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:32,853 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43736090] [2019-11-20 04:35:32,853 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:32,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:33,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:33,004 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [43736090] [2019-11-20 04:35:33,004 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:33,004 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:33,006 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [68865713] [2019-11-20 04:35:33,010 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:33,010 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:33,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:33,023 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:33,024 INFO L87 Difference]: Start difference. First operand 129 states. Second operand 3 states. [2019-11-20 04:35:33,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:33,066 INFO L93 Difference]: Finished difference Result 250 states and 461 transitions. [2019-11-20 04:35:33,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:33,068 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-20 04:35:33,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:33,077 INFO L225 Difference]: With dead ends: 250 [2019-11-20 04:35:33,077 INFO L226 Difference]: Without dead ends: 125 [2019-11-20 04:35:33,079 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:33,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2019-11-20 04:35:33,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 125. [2019-11-20 04:35:33,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2019-11-20 04:35:33,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 218 transitions. [2019-11-20 04:35:33,126 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 218 transitions. Word has length 36 [2019-11-20 04:35:33,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:33,127 INFO L462 AbstractCegarLoop]: Abstraction has 125 states and 218 transitions. [2019-11-20 04:35:33,127 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:33,127 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 218 transitions. [2019-11-20 04:35:33,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-20 04:35:33,129 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:33,129 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:33,129 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:33,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:33,130 INFO L82 PathProgramCache]: Analyzing trace with hash -1597378040, now seen corresponding path program 1 times [2019-11-20 04:35:33,130 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:33,130 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447258755] [2019-11-20 04:35:33,131 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:33,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:33,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:33,178 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1447258755] [2019-11-20 04:35:33,178 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:33,179 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:33,179 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2138077252] [2019-11-20 04:35:33,180 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:33,180 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:33,180 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:33,181 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:33,181 INFO L87 Difference]: Start difference. First operand 125 states and 218 transitions. Second operand 3 states. [2019-11-20 04:35:33,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:33,205 INFO L93 Difference]: Finished difference Result 240 states and 420 transitions. [2019-11-20 04:35:33,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:33,206 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-20 04:35:33,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:33,208 INFO L225 Difference]: With dead ends: 240 [2019-11-20 04:35:33,208 INFO L226 Difference]: Without dead ends: 125 [2019-11-20 04:35:33,210 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:33,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2019-11-20 04:35:33,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 125. [2019-11-20 04:35:33,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2019-11-20 04:35:33,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 217 transitions. [2019-11-20 04:35:33,223 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 217 transitions. Word has length 36 [2019-11-20 04:35:33,223 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:33,223 INFO L462 AbstractCegarLoop]: Abstraction has 125 states and 217 transitions. [2019-11-20 04:35:33,223 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:33,224 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 217 transitions. [2019-11-20 04:35:33,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-20 04:35:33,225 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:33,225 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:33,226 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:33,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:33,226 INFO L82 PathProgramCache]: Analyzing trace with hash -211174646, now seen corresponding path program 1 times [2019-11-20 04:35:33,226 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:33,227 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259267729] [2019-11-20 04:35:33,227 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:33,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:33,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:33,308 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259267729] [2019-11-20 04:35:33,308 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:33,308 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:33,309 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116227751] [2019-11-20 04:35:33,309 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:33,309 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:33,309 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:33,309 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:33,310 INFO L87 Difference]: Start difference. First operand 125 states and 217 transitions. Second operand 3 states. [2019-11-20 04:35:33,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:33,408 INFO L93 Difference]: Finished difference Result 328 states and 568 transitions. [2019-11-20 04:35:33,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:33,409 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-20 04:35:33,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:33,411 INFO L225 Difference]: With dead ends: 328 [2019-11-20 04:35:33,411 INFO L226 Difference]: Without dead ends: 214 [2019-11-20 04:35:33,412 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:33,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2019-11-20 04:35:33,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 200. [2019-11-20 04:35:33,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200 states. [2019-11-20 04:35:33,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 335 transitions. [2019-11-20 04:35:33,434 INFO L78 Accepts]: Start accepts. Automaton has 200 states and 335 transitions. Word has length 36 [2019-11-20 04:35:33,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:33,434 INFO L462 AbstractCegarLoop]: Abstraction has 200 states and 335 transitions. [2019-11-20 04:35:33,434 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:33,434 INFO L276 IsEmpty]: Start isEmpty. Operand 200 states and 335 transitions. [2019-11-20 04:35:33,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-20 04:35:33,436 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:33,436 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:33,436 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:33,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:33,437 INFO L82 PathProgramCache]: Analyzing trace with hash 1832431686, now seen corresponding path program 1 times [2019-11-20 04:35:33,437 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:33,437 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907868125] [2019-11-20 04:35:33,437 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:33,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:33,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:33,484 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [907868125] [2019-11-20 04:35:33,484 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:33,484 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 04:35:33,484 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900840998] [2019-11-20 04:35:33,485 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 04:35:33,485 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:33,485 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 04:35:33,485 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 04:35:33,486 INFO L87 Difference]: Start difference. First operand 200 states and 335 transitions. Second operand 4 states. [2019-11-20 04:35:33,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:33,635 INFO L93 Difference]: Finished difference Result 542 states and 911 transitions. [2019-11-20 04:35:33,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 04:35:33,636 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-20 04:35:33,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:33,639 INFO L225 Difference]: With dead ends: 542 [2019-11-20 04:35:33,639 INFO L226 Difference]: Without dead ends: 354 [2019-11-20 04:35:33,640 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 04:35:33,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states. [2019-11-20 04:35:33,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 344. [2019-11-20 04:35:33,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 344 states. [2019-11-20 04:35:33,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 344 states to 344 states and 577 transitions. [2019-11-20 04:35:33,671 INFO L78 Accepts]: Start accepts. Automaton has 344 states and 577 transitions. Word has length 36 [2019-11-20 04:35:33,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:33,671 INFO L462 AbstractCegarLoop]: Abstraction has 344 states and 577 transitions. [2019-11-20 04:35:33,671 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 04:35:33,672 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 577 transitions. [2019-11-20 04:35:33,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-20 04:35:33,674 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:33,674 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:33,674 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:33,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:33,675 INFO L82 PathProgramCache]: Analyzing trace with hash -539307576, now seen corresponding path program 1 times [2019-11-20 04:35:33,675 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:33,675 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329588014] [2019-11-20 04:35:33,676 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:33,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:33,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:33,734 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1329588014] [2019-11-20 04:35:33,735 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:33,735 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 04:35:33,735 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1651551387] [2019-11-20 04:35:33,735 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 04:35:33,736 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:33,736 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 04:35:33,736 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 04:35:33,736 INFO L87 Difference]: Start difference. First operand 344 states and 577 transitions. Second operand 4 states. [2019-11-20 04:35:33,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:33,853 INFO L93 Difference]: Finished difference Result 967 states and 1626 transitions. [2019-11-20 04:35:33,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 04:35:33,854 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-20 04:35:33,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:33,858 INFO L225 Difference]: With dead ends: 967 [2019-11-20 04:35:33,858 INFO L226 Difference]: Without dead ends: 636 [2019-11-20 04:35:33,861 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 04:35:33,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states. [2019-11-20 04:35:33,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 626. [2019-11-20 04:35:33,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 626 states. [2019-11-20 04:35:33,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 1047 transitions. [2019-11-20 04:35:33,914 INFO L78 Accepts]: Start accepts. Automaton has 626 states and 1047 transitions. Word has length 36 [2019-11-20 04:35:33,915 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:33,915 INFO L462 AbstractCegarLoop]: Abstraction has 626 states and 1047 transitions. [2019-11-20 04:35:33,915 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 04:35:33,915 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 1047 transitions. [2019-11-20 04:35:33,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-20 04:35:33,922 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:33,922 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:33,923 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:33,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:33,923 INFO L82 PathProgramCache]: Analyzing trace with hash -477267962, now seen corresponding path program 1 times [2019-11-20 04:35:33,923 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:33,924 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1929046765] [2019-11-20 04:35:33,924 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:33,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:34,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:34,002 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1929046765] [2019-11-20 04:35:34,002 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:34,002 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 04:35:34,003 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164067283] [2019-11-20 04:35:34,003 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 04:35:34,003 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:34,003 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 04:35:34,004 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 04:35:34,004 INFO L87 Difference]: Start difference. First operand 626 states and 1047 transitions. Second operand 4 states. [2019-11-20 04:35:34,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:34,162 INFO L93 Difference]: Finished difference Result 1903 states and 3163 transitions. [2019-11-20 04:35:34,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 04:35:34,163 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-20 04:35:34,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:34,171 INFO L225 Difference]: With dead ends: 1903 [2019-11-20 04:35:34,172 INFO L226 Difference]: Without dead ends: 1291 [2019-11-20 04:35:34,173 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 04:35:34,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1291 states. [2019-11-20 04:35:34,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1291 to 1281. [2019-11-20 04:35:34,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1281 states. [2019-11-20 04:35:34,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1281 states to 1281 states and 2107 transitions. [2019-11-20 04:35:34,244 INFO L78 Accepts]: Start accepts. Automaton has 1281 states and 2107 transitions. Word has length 36 [2019-11-20 04:35:34,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:34,247 INFO L462 AbstractCegarLoop]: Abstraction has 1281 states and 2107 transitions. [2019-11-20 04:35:34,247 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 04:35:34,247 INFO L276 IsEmpty]: Start isEmpty. Operand 1281 states and 2107 transitions. [2019-11-20 04:35:34,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-20 04:35:34,251 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:34,251 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:34,251 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:34,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:34,257 INFO L82 PathProgramCache]: Analyzing trace with hash -336719352, now seen corresponding path program 1 times [2019-11-20 04:35:34,257 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:34,258 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394057197] [2019-11-20 04:35:34,258 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:34,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:34,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:34,343 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394057197] [2019-11-20 04:35:34,343 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:34,343 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:34,344 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [870917010] [2019-11-20 04:35:34,344 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:34,344 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:34,344 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:34,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:34,345 INFO L87 Difference]: Start difference. First operand 1281 states and 2107 transitions. Second operand 3 states. [2019-11-20 04:35:34,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:34,469 INFO L93 Difference]: Finished difference Result 2615 states and 4310 transitions. [2019-11-20 04:35:34,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:34,470 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-20 04:35:34,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:34,478 INFO L225 Difference]: With dead ends: 2615 [2019-11-20 04:35:34,478 INFO L226 Difference]: Without dead ends: 1391 [2019-11-20 04:35:34,480 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:34,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1391 states. [2019-11-20 04:35:34,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1391 to 1382. [2019-11-20 04:35:34,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1382 states. [2019-11-20 04:35:34,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1382 states to 1382 states and 2266 transitions. [2019-11-20 04:35:34,543 INFO L78 Accepts]: Start accepts. Automaton has 1382 states and 2266 transitions. Word has length 36 [2019-11-20 04:35:34,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:34,543 INFO L462 AbstractCegarLoop]: Abstraction has 1382 states and 2266 transitions. [2019-11-20 04:35:34,544 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:34,544 INFO L276 IsEmpty]: Start isEmpty. Operand 1382 states and 2266 transitions. [2019-11-20 04:35:34,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-20 04:35:34,546 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:34,547 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:34,547 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:34,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:34,547 INFO L82 PathProgramCache]: Analyzing trace with hash 952985988, now seen corresponding path program 1 times [2019-11-20 04:35:34,548 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:34,548 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655591747] [2019-11-20 04:35:34,548 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:34,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:34,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:34,596 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [655591747] [2019-11-20 04:35:34,596 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:34,596 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 04:35:34,596 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105467168] [2019-11-20 04:35:34,597 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 04:35:34,597 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:34,597 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 04:35:34,597 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 04:35:34,597 INFO L87 Difference]: Start difference. First operand 1382 states and 2266 transitions. Second operand 4 states. [2019-11-20 04:35:34,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:34,733 INFO L93 Difference]: Finished difference Result 2900 states and 4764 transitions. [2019-11-20 04:35:34,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 04:35:34,733 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-20 04:35:34,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:34,742 INFO L225 Difference]: With dead ends: 2900 [2019-11-20 04:35:34,742 INFO L226 Difference]: Without dead ends: 1552 [2019-11-20 04:35:34,744 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 04:35:34,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1552 states. [2019-11-20 04:35:34,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1552 to 1539. [2019-11-20 04:35:34,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1539 states. [2019-11-20 04:35:34,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1539 states to 1539 states and 2488 transitions. [2019-11-20 04:35:34,838 INFO L78 Accepts]: Start accepts. Automaton has 1539 states and 2488 transitions. Word has length 36 [2019-11-20 04:35:34,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:34,838 INFO L462 AbstractCegarLoop]: Abstraction has 1539 states and 2488 transitions. [2019-11-20 04:35:34,838 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 04:35:34,838 INFO L276 IsEmpty]: Start isEmpty. Operand 1539 states and 2488 transitions. [2019-11-20 04:35:34,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-20 04:35:34,839 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:34,839 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:34,840 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:34,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:34,840 INFO L82 PathProgramCache]: Analyzing trace with hash -635361914, now seen corresponding path program 1 times [2019-11-20 04:35:34,840 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:34,840 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721445299] [2019-11-20 04:35:34,841 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:34,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:34,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:34,862 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1721445299] [2019-11-20 04:35:34,862 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:34,863 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 04:35:34,863 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1063611311] [2019-11-20 04:35:34,863 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 04:35:34,863 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:34,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 04:35:34,864 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 04:35:34,864 INFO L87 Difference]: Start difference. First operand 1539 states and 2488 transitions. Second operand 4 states. [2019-11-20 04:35:34,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:34,997 INFO L93 Difference]: Finished difference Result 3378 states and 5467 transitions. [2019-11-20 04:35:34,997 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 04:35:34,997 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-20 04:35:34,997 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:35,007 INFO L225 Difference]: With dead ends: 3378 [2019-11-20 04:35:35,008 INFO L226 Difference]: Without dead ends: 1885 [2019-11-20 04:35:35,010 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 04:35:35,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1885 states. [2019-11-20 04:35:35,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1885 to 1859. [2019-11-20 04:35:35,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1859 states. [2019-11-20 04:35:35,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1859 states to 1859 states and 2968 transitions. [2019-11-20 04:35:35,087 INFO L78 Accepts]: Start accepts. Automaton has 1859 states and 2968 transitions. Word has length 36 [2019-11-20 04:35:35,087 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:35,087 INFO L462 AbstractCegarLoop]: Abstraction has 1859 states and 2968 transitions. [2019-11-20 04:35:35,087 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 04:35:35,087 INFO L276 IsEmpty]: Start isEmpty. Operand 1859 states and 2968 transitions. [2019-11-20 04:35:35,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-20 04:35:35,088 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:35,088 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:35,088 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:35,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:35,089 INFO L82 PathProgramCache]: Analyzing trace with hash -1915225592, now seen corresponding path program 1 times [2019-11-20 04:35:35,089 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:35,089 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901668057] [2019-11-20 04:35:35,089 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:35,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:35,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:35,113 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1901668057] [2019-11-20 04:35:35,113 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:35,114 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:35,114 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1536428019] [2019-11-20 04:35:35,114 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:35,114 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:35,114 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:35,115 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:35,115 INFO L87 Difference]: Start difference. First operand 1859 states and 2968 transitions. Second operand 3 states. [2019-11-20 04:35:35,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:35,210 INFO L93 Difference]: Finished difference Result 3335 states and 5328 transitions. [2019-11-20 04:35:35,211 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:35,211 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-20 04:35:35,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:35,219 INFO L225 Difference]: With dead ends: 3335 [2019-11-20 04:35:35,219 INFO L226 Difference]: Without dead ends: 1504 [2019-11-20 04:35:35,222 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:35,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1504 states. [2019-11-20 04:35:35,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1504 to 1493. [2019-11-20 04:35:35,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1493 states. [2019-11-20 04:35:35,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1493 states to 1493 states and 2352 transitions. [2019-11-20 04:35:35,286 INFO L78 Accepts]: Start accepts. Automaton has 1493 states and 2352 transitions. Word has length 36 [2019-11-20 04:35:35,286 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:35,286 INFO L462 AbstractCegarLoop]: Abstraction has 1493 states and 2352 transitions. [2019-11-20 04:35:35,286 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:35,287 INFO L276 IsEmpty]: Start isEmpty. Operand 1493 states and 2352 transitions. [2019-11-20 04:35:35,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-20 04:35:35,288 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:35,288 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:35,288 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:35,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:35,289 INFO L82 PathProgramCache]: Analyzing trace with hash -547155332, now seen corresponding path program 1 times [2019-11-20 04:35:35,289 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:35,289 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121288779] [2019-11-20 04:35:35,289 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:35,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:35,311 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:35,311 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1121288779] [2019-11-20 04:35:35,311 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:35,312 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:35,312 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [981554998] [2019-11-20 04:35:35,312 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:35,312 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:35,313 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:35,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:35,313 INFO L87 Difference]: Start difference. First operand 1493 states and 2352 transitions. Second operand 3 states. [2019-11-20 04:35:35,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:35,420 INFO L93 Difference]: Finished difference Result 3728 states and 5928 transitions. [2019-11-20 04:35:35,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:35,421 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-20 04:35:35,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:35,433 INFO L225 Difference]: With dead ends: 3728 [2019-11-20 04:35:35,433 INFO L226 Difference]: Without dead ends: 2289 [2019-11-20 04:35:35,435 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:35,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2289 states. [2019-11-20 04:35:35,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2289 to 2285. [2019-11-20 04:35:35,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2285 states. [2019-11-20 04:35:35,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2285 states to 2285 states and 3596 transitions. [2019-11-20 04:35:35,539 INFO L78 Accepts]: Start accepts. Automaton has 2285 states and 3596 transitions. Word has length 46 [2019-11-20 04:35:35,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:35,539 INFO L462 AbstractCegarLoop]: Abstraction has 2285 states and 3596 transitions. [2019-11-20 04:35:35,539 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:35,539 INFO L276 IsEmpty]: Start isEmpty. Operand 2285 states and 3596 transitions. [2019-11-20 04:35:35,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-20 04:35:35,541 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:35,541 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:35,541 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:35,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:35,542 INFO L82 PathProgramCache]: Analyzing trace with hash -299008838, now seen corresponding path program 1 times [2019-11-20 04:35:35,542 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:35,542 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179333956] [2019-11-20 04:35:35,542 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:35,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:35,558 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-20 04:35:35,558 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179333956] [2019-11-20 04:35:35,559 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:35,559 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:35,559 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [641436488] [2019-11-20 04:35:35,559 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:35,560 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:35,560 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:35,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:35,560 INFO L87 Difference]: Start difference. First operand 2285 states and 3596 transitions. Second operand 3 states. [2019-11-20 04:35:35,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:35,648 INFO L93 Difference]: Finished difference Result 4472 states and 7066 transitions. [2019-11-20 04:35:35,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:35,648 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-20 04:35:35,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:35,660 INFO L225 Difference]: With dead ends: 4472 [2019-11-20 04:35:35,660 INFO L226 Difference]: Without dead ends: 2241 [2019-11-20 04:35:35,663 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:35,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2241 states. [2019-11-20 04:35:35,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2241 to 2241. [2019-11-20 04:35:35,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2241 states. [2019-11-20 04:35:35,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3539 transitions. [2019-11-20 04:35:35,759 INFO L78 Accepts]: Start accepts. Automaton has 2241 states and 3539 transitions. Word has length 46 [2019-11-20 04:35:35,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:35,759 INFO L462 AbstractCegarLoop]: Abstraction has 2241 states and 3539 transitions. [2019-11-20 04:35:35,759 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:35,760 INFO L276 IsEmpty]: Start isEmpty. Operand 2241 states and 3539 transitions. [2019-11-20 04:35:35,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-11-20 04:35:35,761 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:35,761 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:35,761 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:35,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:35,762 INFO L82 PathProgramCache]: Analyzing trace with hash -336670593, now seen corresponding path program 1 times [2019-11-20 04:35:35,762 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:35,762 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511822453] [2019-11-20 04:35:35,762 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:35,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:35,809 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:35,810 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511822453] [2019-11-20 04:35:35,810 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:35,810 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:35,810 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886790741] [2019-11-20 04:35:35,811 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:35,811 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:35,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:35,812 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:35,812 INFO L87 Difference]: Start difference. First operand 2241 states and 3539 transitions. Second operand 3 states. [2019-11-20 04:35:36,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:36,006 INFO L93 Difference]: Finished difference Result 5761 states and 9163 transitions. [2019-11-20 04:35:36,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:36,006 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-11-20 04:35:36,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:36,025 INFO L225 Difference]: With dead ends: 5761 [2019-11-20 04:35:36,026 INFO L226 Difference]: Without dead ends: 3574 [2019-11-20 04:35:36,030 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:36,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3574 states. [2019-11-20 04:35:36,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3574 to 3570. [2019-11-20 04:35:36,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3570 states. [2019-11-20 04:35:36,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3570 states to 3570 states and 5623 transitions. [2019-11-20 04:35:36,234 INFO L78 Accepts]: Start accepts. Automaton has 3570 states and 5623 transitions. Word has length 47 [2019-11-20 04:35:36,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:36,235 INFO L462 AbstractCegarLoop]: Abstraction has 3570 states and 5623 transitions. [2019-11-20 04:35:36,235 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:36,235 INFO L276 IsEmpty]: Start isEmpty. Operand 3570 states and 5623 transitions. [2019-11-20 04:35:36,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-20 04:35:36,237 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:36,237 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:36,237 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:36,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:36,238 INFO L82 PathProgramCache]: Analyzing trace with hash 1825522215, now seen corresponding path program 1 times [2019-11-20 04:35:36,238 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:36,241 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390334529] [2019-11-20 04:35:36,242 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:36,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:36,275 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:36,275 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390334529] [2019-11-20 04:35:36,276 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:36,276 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:36,276 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744178506] [2019-11-20 04:35:36,276 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:36,276 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:36,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:36,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:36,277 INFO L87 Difference]: Start difference. First operand 3570 states and 5623 transitions. Second operand 3 states. [2019-11-20 04:35:36,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:36,544 INFO L93 Difference]: Finished difference Result 9081 states and 14487 transitions. [2019-11-20 04:35:36,545 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:36,545 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-20 04:35:36,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:36,576 INFO L225 Difference]: With dead ends: 9081 [2019-11-20 04:35:36,576 INFO L226 Difference]: Without dead ends: 5569 [2019-11-20 04:35:36,581 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:36,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5569 states. [2019-11-20 04:35:36,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5569 to 5565. [2019-11-20 04:35:36,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5565 states. [2019-11-20 04:35:36,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5565 states to 5565 states and 8840 transitions. [2019-11-20 04:35:36,889 INFO L78 Accepts]: Start accepts. Automaton has 5565 states and 8840 transitions. Word has length 48 [2019-11-20 04:35:36,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:36,890 INFO L462 AbstractCegarLoop]: Abstraction has 5565 states and 8840 transitions. [2019-11-20 04:35:36,890 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:36,890 INFO L276 IsEmpty]: Start isEmpty. Operand 5565 states and 8840 transitions. [2019-11-20 04:35:36,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-20 04:35:36,896 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:36,896 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:36,896 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:36,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:36,897 INFO L82 PathProgramCache]: Analyzing trace with hash 2073668709, now seen corresponding path program 1 times [2019-11-20 04:35:36,897 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:36,897 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028325659] [2019-11-20 04:35:36,897 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:36,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:36,915 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-20 04:35:36,916 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028325659] [2019-11-20 04:35:36,916 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:36,916 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:36,916 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414244840] [2019-11-20 04:35:36,917 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:36,917 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:36,917 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:36,917 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:36,917 INFO L87 Difference]: Start difference. First operand 5565 states and 8840 transitions. Second operand 3 states. [2019-11-20 04:35:37,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:37,182 INFO L93 Difference]: Finished difference Result 11028 states and 17554 transitions. [2019-11-20 04:35:37,183 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:37,183 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-20 04:35:37,183 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:37,216 INFO L225 Difference]: With dead ends: 11028 [2019-11-20 04:35:37,216 INFO L226 Difference]: Without dead ends: 5521 [2019-11-20 04:35:37,225 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:37,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5521 states. [2019-11-20 04:35:37,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5521 to 5521. [2019-11-20 04:35:37,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5521 states. [2019-11-20 04:35:37,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5521 states to 5521 states and 8785 transitions. [2019-11-20 04:35:37,539 INFO L78 Accepts]: Start accepts. Automaton has 5521 states and 8785 transitions. Word has length 48 [2019-11-20 04:35:37,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:37,539 INFO L462 AbstractCegarLoop]: Abstraction has 5521 states and 8785 transitions. [2019-11-20 04:35:37,539 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:37,540 INFO L276 IsEmpty]: Start isEmpty. Operand 5521 states and 8785 transitions. [2019-11-20 04:35:37,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-20 04:35:37,543 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:37,543 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:37,543 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:37,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:37,543 INFO L82 PathProgramCache]: Analyzing trace with hash 963117268, now seen corresponding path program 1 times [2019-11-20 04:35:37,544 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:37,544 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514330191] [2019-11-20 04:35:37,544 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:37,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:37,577 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:37,578 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514330191] [2019-11-20 04:35:37,578 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:37,578 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:37,578 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085479728] [2019-11-20 04:35:37,578 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:37,579 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:37,579 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:37,579 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:37,579 INFO L87 Difference]: Start difference. First operand 5521 states and 8785 transitions. Second operand 3 states. [2019-11-20 04:35:37,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:37,905 INFO L93 Difference]: Finished difference Result 15573 states and 24710 transitions. [2019-11-20 04:35:37,905 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:37,905 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-20 04:35:37,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:37,920 INFO L225 Difference]: With dead ends: 15573 [2019-11-20 04:35:37,920 INFO L226 Difference]: Without dead ends: 8340 [2019-11-20 04:35:37,930 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:37,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8340 states. [2019-11-20 04:35:38,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8340 to 8340. [2019-11-20 04:35:38,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8340 states. [2019-11-20 04:35:38,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8340 states to 8340 states and 13079 transitions. [2019-11-20 04:35:38,233 INFO L78 Accepts]: Start accepts. Automaton has 8340 states and 13079 transitions. Word has length 49 [2019-11-20 04:35:38,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:38,233 INFO L462 AbstractCegarLoop]: Abstraction has 8340 states and 13079 transitions. [2019-11-20 04:35:38,234 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:38,234 INFO L276 IsEmpty]: Start isEmpty. Operand 8340 states and 13079 transitions. [2019-11-20 04:35:38,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-20 04:35:38,238 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:38,238 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:38,239 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:38,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:38,239 INFO L82 PathProgramCache]: Analyzing trace with hash 1798060104, now seen corresponding path program 1 times [2019-11-20 04:35:38,239 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:38,239 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749389886] [2019-11-20 04:35:38,240 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:38,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:38,274 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:38,274 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749389886] [2019-11-20 04:35:38,274 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:38,274 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:38,274 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489245363] [2019-11-20 04:35:38,275 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:38,275 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:38,275 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:38,275 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:38,275 INFO L87 Difference]: Start difference. First operand 8340 states and 13079 transitions. Second operand 3 states. [2019-11-20 04:35:38,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:38,601 INFO L93 Difference]: Finished difference Result 17187 states and 26897 transitions. [2019-11-20 04:35:38,601 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:38,601 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2019-11-20 04:35:38,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:38,617 INFO L225 Difference]: With dead ends: 17187 [2019-11-20 04:35:38,618 INFO L226 Difference]: Without dead ends: 8883 [2019-11-20 04:35:38,628 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:38,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8883 states. [2019-11-20 04:35:38,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8883 to 8322. [2019-11-20 04:35:38,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8322 states. [2019-11-20 04:35:38,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8322 states to 8322 states and 12796 transitions. [2019-11-20 04:35:38,951 INFO L78 Accepts]: Start accepts. Automaton has 8322 states and 12796 transitions. Word has length 53 [2019-11-20 04:35:38,952 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:38,952 INFO L462 AbstractCegarLoop]: Abstraction has 8322 states and 12796 transitions. [2019-11-20 04:35:38,952 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:38,952 INFO L276 IsEmpty]: Start isEmpty. Operand 8322 states and 12796 transitions. [2019-11-20 04:35:38,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-20 04:35:38,957 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:38,957 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:38,957 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:38,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:38,958 INFO L82 PathProgramCache]: Analyzing trace with hash -833394239, now seen corresponding path program 1 times [2019-11-20 04:35:38,958 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:38,958 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070353720] [2019-11-20 04:35:38,959 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:38,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:38,980 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-20 04:35:38,980 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070353720] [2019-11-20 04:35:38,981 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:38,981 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:38,981 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277493756] [2019-11-20 04:35:38,981 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:38,981 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:38,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:38,982 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:38,982 INFO L87 Difference]: Start difference. First operand 8322 states and 12796 transitions. Second operand 3 states. [2019-11-20 04:35:39,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:39,584 INFO L93 Difference]: Finished difference Result 24654 states and 37995 transitions. [2019-11-20 04:35:39,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:39,584 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-20 04:35:39,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:39,611 INFO L225 Difference]: With dead ends: 24654 [2019-11-20 04:35:39,611 INFO L226 Difference]: Without dead ends: 16335 [2019-11-20 04:35:39,621 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:39,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16335 states. [2019-11-20 04:35:40,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16335 to 16203. [2019-11-20 04:35:40,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16203 states. [2019-11-20 04:35:40,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16203 states to 16203 states and 25040 transitions. [2019-11-20 04:35:40,192 INFO L78 Accepts]: Start accepts. Automaton has 16203 states and 25040 transitions. Word has length 55 [2019-11-20 04:35:40,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:40,193 INFO L462 AbstractCegarLoop]: Abstraction has 16203 states and 25040 transitions. [2019-11-20 04:35:40,193 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:40,193 INFO L276 IsEmpty]: Start isEmpty. Operand 16203 states and 25040 transitions. [2019-11-20 04:35:40,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-20 04:35:40,203 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:40,203 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:40,203 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:40,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:40,204 INFO L82 PathProgramCache]: Analyzing trace with hash -539805076, now seen corresponding path program 1 times [2019-11-20 04:35:40,205 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:40,205 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073802975] [2019-11-20 04:35:40,205 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:40,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:40,254 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:40,255 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2073802975] [2019-11-20 04:35:40,255 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:40,255 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:40,255 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191999400] [2019-11-20 04:35:40,256 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:40,256 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:40,256 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:40,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:40,256 INFO L87 Difference]: Start difference. First operand 16203 states and 25040 transitions. Second operand 3 states. [2019-11-20 04:35:40,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:40,875 INFO L93 Difference]: Finished difference Result 33061 states and 51038 transitions. [2019-11-20 04:35:40,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:40,876 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-11-20 04:35:40,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:40,902 INFO L225 Difference]: With dead ends: 33061 [2019-11-20 04:35:40,902 INFO L226 Difference]: Without dead ends: 16887 [2019-11-20 04:35:40,920 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:40,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16887 states. [2019-11-20 04:35:41,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16887 to 16823. [2019-11-20 04:35:41,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16823 states. [2019-11-20 04:35:41,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16823 states to 16823 states and 25342 transitions. [2019-11-20 04:35:41,488 INFO L78 Accepts]: Start accepts. Automaton has 16823 states and 25342 transitions. Word has length 86 [2019-11-20 04:35:41,489 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:41,489 INFO L462 AbstractCegarLoop]: Abstraction has 16823 states and 25342 transitions. [2019-11-20 04:35:41,489 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:41,489 INFO L276 IsEmpty]: Start isEmpty. Operand 16823 states and 25342 transitions. [2019-11-20 04:35:41,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-11-20 04:35:41,499 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:41,499 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:41,499 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:41,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:41,500 INFO L82 PathProgramCache]: Analyzing trace with hash -1404681213, now seen corresponding path program 1 times [2019-11-20 04:35:41,500 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:41,500 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853126725] [2019-11-20 04:35:41,500 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:41,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:41,543 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-20 04:35:41,543 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1853126725] [2019-11-20 04:35:41,543 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:41,543 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 04:35:41,544 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896530390] [2019-11-20 04:35:41,544 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 04:35:41,544 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:41,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 04:35:41,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 04:35:41,545 INFO L87 Difference]: Start difference. First operand 16823 states and 25342 transitions. Second operand 4 states. [2019-11-20 04:35:42,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:42,409 INFO L93 Difference]: Finished difference Result 27813 states and 42042 transitions. [2019-11-20 04:35:42,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 04:35:42,410 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 87 [2019-11-20 04:35:42,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:42,434 INFO L225 Difference]: With dead ends: 27813 [2019-11-20 04:35:42,434 INFO L226 Difference]: Without dead ends: 15935 [2019-11-20 04:35:42,439 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 04:35:42,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15935 states. [2019-11-20 04:35:42,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15935 to 15811. [2019-11-20 04:35:42,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15811 states. [2019-11-20 04:35:42,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15811 states to 15811 states and 23636 transitions. [2019-11-20 04:35:42,998 INFO L78 Accepts]: Start accepts. Automaton has 15811 states and 23636 transitions. Word has length 87 [2019-11-20 04:35:42,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:42,999 INFO L462 AbstractCegarLoop]: Abstraction has 15811 states and 23636 transitions. [2019-11-20 04:35:42,999 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 04:35:42,999 INFO L276 IsEmpty]: Start isEmpty. Operand 15811 states and 23636 transitions. [2019-11-20 04:35:43,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-11-20 04:35:43,008 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:43,008 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:43,008 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:43,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:43,009 INFO L82 PathProgramCache]: Analyzing trace with hash 1520792899, now seen corresponding path program 1 times [2019-11-20 04:35:43,009 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:43,009 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905664344] [2019-11-20 04:35:43,009 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:43,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:43,038 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:43,039 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1905664344] [2019-11-20 04:35:43,039 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:43,039 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:43,039 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832634827] [2019-11-20 04:35:43,040 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:43,040 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:43,040 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:43,040 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:43,040 INFO L87 Difference]: Start difference. First operand 15811 states and 23636 transitions. Second operand 3 states. [2019-11-20 04:35:43,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:43,541 INFO L93 Difference]: Finished difference Result 32391 states and 48370 transitions. [2019-11-20 04:35:43,541 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:43,541 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 87 [2019-11-20 04:35:43,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:43,570 INFO L225 Difference]: With dead ends: 32391 [2019-11-20 04:35:43,570 INFO L226 Difference]: Without dead ends: 16621 [2019-11-20 04:35:43,581 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:43,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16621 states. [2019-11-20 04:35:44,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16621 to 16541. [2019-11-20 04:35:44,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16541 states. [2019-11-20 04:35:44,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16541 states to 16541 states and 24008 transitions. [2019-11-20 04:35:44,310 INFO L78 Accepts]: Start accepts. Automaton has 16541 states and 24008 transitions. Word has length 87 [2019-11-20 04:35:44,310 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:44,310 INFO L462 AbstractCegarLoop]: Abstraction has 16541 states and 24008 transitions. [2019-11-20 04:35:44,310 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:44,311 INFO L276 IsEmpty]: Start isEmpty. Operand 16541 states and 24008 transitions. [2019-11-20 04:35:44,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2019-11-20 04:35:44,318 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:44,318 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:44,318 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:44,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:44,319 INFO L82 PathProgramCache]: Analyzing trace with hash -1973365524, now seen corresponding path program 1 times [2019-11-20 04:35:44,319 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:44,319 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092684074] [2019-11-20 04:35:44,319 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:44,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:44,345 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:35:44,346 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1092684074] [2019-11-20 04:35:44,346 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:44,346 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:44,346 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1546011413] [2019-11-20 04:35:44,347 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:44,347 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:44,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:44,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:44,347 INFO L87 Difference]: Start difference. First operand 16541 states and 24008 transitions. Second operand 3 states. [2019-11-20 04:35:44,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:44,779 INFO L93 Difference]: Finished difference Result 33498 states and 48738 transitions. [2019-11-20 04:35:44,779 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:44,779 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 88 [2019-11-20 04:35:44,780 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:44,801 INFO L225 Difference]: With dead ends: 33498 [2019-11-20 04:35:44,802 INFO L226 Difference]: Without dead ends: 17018 [2019-11-20 04:35:44,814 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:44,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17018 states. [2019-11-20 04:35:45,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17018 to 13513. [2019-11-20 04:35:45,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13513 states. [2019-11-20 04:35:45,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13513 states to 13513 states and 18922 transitions. [2019-11-20 04:35:45,622 INFO L78 Accepts]: Start accepts. Automaton has 13513 states and 18922 transitions. Word has length 88 [2019-11-20 04:35:45,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:45,622 INFO L462 AbstractCegarLoop]: Abstraction has 13513 states and 18922 transitions. [2019-11-20 04:35:45,622 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:45,622 INFO L276 IsEmpty]: Start isEmpty. Operand 13513 states and 18922 transitions. [2019-11-20 04:35:45,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2019-11-20 04:35:45,629 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:45,629 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:45,629 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:45,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:45,630 INFO L82 PathProgramCache]: Analyzing trace with hash 663253701, now seen corresponding path program 1 times [2019-11-20 04:35:45,630 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:45,630 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [289841389] [2019-11-20 04:35:45,630 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:45,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:45,664 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-20 04:35:45,664 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [289841389] [2019-11-20 04:35:45,664 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:45,665 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:45,665 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139763515] [2019-11-20 04:35:45,665 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:45,666 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:45,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:45,667 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:45,668 INFO L87 Difference]: Start difference. First operand 13513 states and 18922 transitions. Second operand 3 states. [2019-11-20 04:35:46,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:46,193 INFO L93 Difference]: Finished difference Result 24045 states and 33699 transitions. [2019-11-20 04:35:46,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:46,194 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 89 [2019-11-20 04:35:46,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:46,210 INFO L225 Difference]: With dead ends: 24045 [2019-11-20 04:35:46,210 INFO L226 Difference]: Without dead ends: 15655 [2019-11-20 04:35:46,218 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:46,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15655 states. [2019-11-20 04:35:46,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15655 to 15175. [2019-11-20 04:35:46,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15175 states. [2019-11-20 04:35:46,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15175 states to 15175 states and 20753 transitions. [2019-11-20 04:35:46,637 INFO L78 Accepts]: Start accepts. Automaton has 15175 states and 20753 transitions. Word has length 89 [2019-11-20 04:35:46,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:46,637 INFO L462 AbstractCegarLoop]: Abstraction has 15175 states and 20753 transitions. [2019-11-20 04:35:46,637 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:46,637 INFO L276 IsEmpty]: Start isEmpty. Operand 15175 states and 20753 transitions. [2019-11-20 04:35:46,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2019-11-20 04:35:46,648 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:46,648 INFO L410 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:46,648 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:46,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:46,649 INFO L82 PathProgramCache]: Analyzing trace with hash 1690650567, now seen corresponding path program 1 times [2019-11-20 04:35:46,649 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:46,649 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010111283] [2019-11-20 04:35:46,649 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:46,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:46,682 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-20 04:35:46,682 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1010111283] [2019-11-20 04:35:46,683 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:46,683 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:46,683 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [775499560] [2019-11-20 04:35:46,683 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:46,683 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:46,684 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:46,684 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:46,684 INFO L87 Difference]: Start difference. First operand 15175 states and 20753 transitions. Second operand 3 states. [2019-11-20 04:35:47,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:47,299 INFO L93 Difference]: Finished difference Result 29588 states and 40424 transitions. [2019-11-20 04:35:47,299 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:47,299 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 116 [2019-11-20 04:35:47,299 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:47,308 INFO L225 Difference]: With dead ends: 29588 [2019-11-20 04:35:47,309 INFO L226 Difference]: Without dead ends: 15105 [2019-11-20 04:35:47,315 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:47,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15105 states. [2019-11-20 04:35:47,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15105 to 15105. [2019-11-20 04:35:47,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15105 states. [2019-11-20 04:35:47,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15105 states to 15105 states and 20599 transitions. [2019-11-20 04:35:47,761 INFO L78 Accepts]: Start accepts. Automaton has 15105 states and 20599 transitions. Word has length 116 [2019-11-20 04:35:47,761 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:47,761 INFO L462 AbstractCegarLoop]: Abstraction has 15105 states and 20599 transitions. [2019-11-20 04:35:47,761 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:47,761 INFO L276 IsEmpty]: Start isEmpty. Operand 15105 states and 20599 transitions. [2019-11-20 04:35:47,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-11-20 04:35:47,772 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:47,772 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:47,772 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:47,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:47,773 INFO L82 PathProgramCache]: Analyzing trace with hash -1184080698, now seen corresponding path program 1 times [2019-11-20 04:35:47,773 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:47,773 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590440102] [2019-11-20 04:35:47,773 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:47,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:47,806 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2019-11-20 04:35:47,807 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1590440102] [2019-11-20 04:35:47,807 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:47,807 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:47,807 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [439623357] [2019-11-20 04:35:47,808 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:47,808 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:47,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:47,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:47,809 INFO L87 Difference]: Start difference. First operand 15105 states and 20599 transitions. Second operand 3 states. [2019-11-20 04:35:48,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:48,147 INFO L93 Difference]: Finished difference Result 25662 states and 34928 transitions. [2019-11-20 04:35:48,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:48,148 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 127 [2019-11-20 04:35:48,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:48,156 INFO L225 Difference]: With dead ends: 25662 [2019-11-20 04:35:48,156 INFO L226 Difference]: Without dead ends: 10614 [2019-11-20 04:35:48,162 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:48,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10614 states. [2019-11-20 04:35:48,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10614 to 8646. [2019-11-20 04:35:48,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8646 states. [2019-11-20 04:35:48,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8646 states to 8646 states and 11323 transitions. [2019-11-20 04:35:48,402 INFO L78 Accepts]: Start accepts. Automaton has 8646 states and 11323 transitions. Word has length 127 [2019-11-20 04:35:48,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:48,402 INFO L462 AbstractCegarLoop]: Abstraction has 8646 states and 11323 transitions. [2019-11-20 04:35:48,402 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:48,402 INFO L276 IsEmpty]: Start isEmpty. Operand 8646 states and 11323 transitions. [2019-11-20 04:35:48,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2019-11-20 04:35:48,410 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:48,410 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:48,410 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:48,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:48,411 INFO L82 PathProgramCache]: Analyzing trace with hash 762576065, now seen corresponding path program 1 times [2019-11-20 04:35:48,411 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:48,411 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499667812] [2019-11-20 04:35:48,411 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:48,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:48,446 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 43 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-20 04:35:48,446 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [499667812] [2019-11-20 04:35:48,446 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:48,446 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:48,447 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1152138095] [2019-11-20 04:35:48,447 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:48,447 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:48,447 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:48,447 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:48,448 INFO L87 Difference]: Start difference. First operand 8646 states and 11323 transitions. Second operand 3 states. [2019-11-20 04:35:48,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:48,659 INFO L93 Difference]: Finished difference Result 14253 states and 18666 transitions. [2019-11-20 04:35:48,659 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:48,659 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 128 [2019-11-20 04:35:48,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:48,664 INFO L225 Difference]: With dead ends: 14253 [2019-11-20 04:35:48,664 INFO L226 Difference]: Without dead ends: 6761 [2019-11-20 04:35:48,667 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:48,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6761 states. [2019-11-20 04:35:48,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6761 to 6175. [2019-11-20 04:35:48,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6175 states. [2019-11-20 04:35:48,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6175 states to 6175 states and 7922 transitions. [2019-11-20 04:35:48,896 INFO L78 Accepts]: Start accepts. Automaton has 6175 states and 7922 transitions. Word has length 128 [2019-11-20 04:35:48,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:48,896 INFO L462 AbstractCegarLoop]: Abstraction has 6175 states and 7922 transitions. [2019-11-20 04:35:48,896 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:48,897 INFO L276 IsEmpty]: Start isEmpty. Operand 6175 states and 7922 transitions. [2019-11-20 04:35:48,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-20 04:35:48,900 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:48,900 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:48,900 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:48,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:48,901 INFO L82 PathProgramCache]: Analyzing trace with hash 843157933, now seen corresponding path program 1 times [2019-11-20 04:35:48,901 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:48,901 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942983416] [2019-11-20 04:35:48,901 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:48,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:48,954 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-20 04:35:48,954 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942983416] [2019-11-20 04:35:48,955 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:48,955 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:48,955 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539252080] [2019-11-20 04:35:48,955 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:48,956 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:48,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:48,956 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:48,956 INFO L87 Difference]: Start difference. First operand 6175 states and 7922 transitions. Second operand 3 states. [2019-11-20 04:35:49,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:49,299 INFO L93 Difference]: Finished difference Result 11963 states and 15332 transitions. [2019-11-20 04:35:49,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:49,300 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2019-11-20 04:35:49,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:49,306 INFO L225 Difference]: With dead ends: 11963 [2019-11-20 04:35:49,307 INFO L226 Difference]: Without dead ends: 6174 [2019-11-20 04:35:49,311 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:49,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6174 states. [2019-11-20 04:35:49,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6174 to 6134. [2019-11-20 04:35:49,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6134 states. [2019-11-20 04:35:49,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6134 states to 6134 states and 7839 transitions. [2019-11-20 04:35:49,805 INFO L78 Accepts]: Start accepts. Automaton has 6134 states and 7839 transitions. Word has length 134 [2019-11-20 04:35:49,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:49,805 INFO L462 AbstractCegarLoop]: Abstraction has 6134 states and 7839 transitions. [2019-11-20 04:35:49,805 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:49,806 INFO L276 IsEmpty]: Start isEmpty. Operand 6134 states and 7839 transitions. [2019-11-20 04:35:49,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-20 04:35:49,808 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:49,808 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:49,808 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:49,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:49,809 INFO L82 PathProgramCache]: Analyzing trace with hash 713131341, now seen corresponding path program 1 times [2019-11-20 04:35:49,809 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:49,809 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1777843347] [2019-11-20 04:35:49,809 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:49,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:49,844 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-20 04:35:49,844 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1777843347] [2019-11-20 04:35:49,845 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:49,845 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:49,845 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204118390] [2019-11-20 04:35:49,845 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:49,846 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:49,846 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:49,846 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:49,846 INFO L87 Difference]: Start difference. First operand 6134 states and 7839 transitions. Second operand 3 states. [2019-11-20 04:35:50,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:50,101 INFO L93 Difference]: Finished difference Result 11902 states and 15193 transitions. [2019-11-20 04:35:50,101 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:50,101 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2019-11-20 04:35:50,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:50,107 INFO L225 Difference]: With dead ends: 11902 [2019-11-20 04:35:50,107 INFO L226 Difference]: Without dead ends: 6144 [2019-11-20 04:35:50,110 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:50,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6144 states. [2019-11-20 04:35:50,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6144 to 6104. [2019-11-20 04:35:50,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6104 states. [2019-11-20 04:35:50,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6104 states to 6104 states and 7768 transitions. [2019-11-20 04:35:50,359 INFO L78 Accepts]: Start accepts. Automaton has 6104 states and 7768 transitions. Word has length 134 [2019-11-20 04:35:50,359 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:50,360 INFO L462 AbstractCegarLoop]: Abstraction has 6104 states and 7768 transitions. [2019-11-20 04:35:50,360 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:50,360 INFO L276 IsEmpty]: Start isEmpty. Operand 6104 states and 7768 transitions. [2019-11-20 04:35:50,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-20 04:35:50,364 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:50,364 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:50,364 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:50,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:50,365 INFO L82 PathProgramCache]: Analyzing trace with hash -57826629, now seen corresponding path program 1 times [2019-11-20 04:35:50,365 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:50,365 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877181987] [2019-11-20 04:35:50,365 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:50,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:50,396 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-20 04:35:50,396 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877181987] [2019-11-20 04:35:50,396 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:50,397 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:50,397 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896606695] [2019-11-20 04:35:50,397 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:50,397 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:50,397 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:50,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:50,398 INFO L87 Difference]: Start difference. First operand 6104 states and 7768 transitions. Second operand 3 states. [2019-11-20 04:35:50,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:50,632 INFO L93 Difference]: Finished difference Result 10914 states and 13936 transitions. [2019-11-20 04:35:50,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:50,633 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 137 [2019-11-20 04:35:50,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:50,637 INFO L225 Difference]: With dead ends: 10914 [2019-11-20 04:35:50,637 INFO L226 Difference]: Without dead ends: 5174 [2019-11-20 04:35:50,641 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:50,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5174 states. [2019-11-20 04:35:50,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5174 to 5102. [2019-11-20 04:35:50,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5102 states. [2019-11-20 04:35:50,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5102 states to 5102 states and 6390 transitions. [2019-11-20 04:35:50,777 INFO L78 Accepts]: Start accepts. Automaton has 5102 states and 6390 transitions. Word has length 137 [2019-11-20 04:35:50,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:50,777 INFO L462 AbstractCegarLoop]: Abstraction has 5102 states and 6390 transitions. [2019-11-20 04:35:50,777 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:50,777 INFO L276 IsEmpty]: Start isEmpty. Operand 5102 states and 6390 transitions. [2019-11-20 04:35:50,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-20 04:35:50,778 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:50,779 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:50,779 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:50,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:50,779 INFO L82 PathProgramCache]: Analyzing trace with hash -76782736, now seen corresponding path program 1 times [2019-11-20 04:35:50,779 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:50,779 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307998432] [2019-11-20 04:35:50,780 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:50,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:50,833 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2019-11-20 04:35:50,834 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307998432] [2019-11-20 04:35:50,834 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:50,834 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:50,834 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2008503323] [2019-11-20 04:35:50,835 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:50,835 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:50,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:50,835 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:50,835 INFO L87 Difference]: Start difference. First operand 5102 states and 6390 transitions. Second operand 3 states. [2019-11-20 04:35:50,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:50,968 INFO L93 Difference]: Finished difference Result 9187 states and 11545 transitions. [2019-11-20 04:35:50,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:50,968 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 137 [2019-11-20 04:35:50,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:50,971 INFO L225 Difference]: With dead ends: 9187 [2019-11-20 04:35:50,971 INFO L226 Difference]: Without dead ends: 4126 [2019-11-20 04:35:50,973 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:50,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4126 states. [2019-11-20 04:35:51,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4126 to 4106. [2019-11-20 04:35:51,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4106 states. [2019-11-20 04:35:51,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4106 states to 4106 states and 5057 transitions. [2019-11-20 04:35:51,075 INFO L78 Accepts]: Start accepts. Automaton has 4106 states and 5057 transitions. Word has length 137 [2019-11-20 04:35:51,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:51,075 INFO L462 AbstractCegarLoop]: Abstraction has 4106 states and 5057 transitions. [2019-11-20 04:35:51,075 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:51,075 INFO L276 IsEmpty]: Start isEmpty. Operand 4106 states and 5057 transitions. [2019-11-20 04:35:51,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2019-11-20 04:35:51,077 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:51,077 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:51,077 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:51,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:51,078 INFO L82 PathProgramCache]: Analyzing trace with hash -691267920, now seen corresponding path program 1 times [2019-11-20 04:35:51,078 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:51,078 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996741366] [2019-11-20 04:35:51,078 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:51,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:51,120 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 75 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-11-20 04:35:51,121 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996741366] [2019-11-20 04:35:51,121 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:51,121 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:51,121 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [584841502] [2019-11-20 04:35:51,122 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:51,122 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:51,122 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:51,122 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:51,122 INFO L87 Difference]: Start difference. First operand 4106 states and 5057 transitions. Second operand 3 states. [2019-11-20 04:35:51,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:51,300 INFO L93 Difference]: Finished difference Result 7627 states and 9455 transitions. [2019-11-20 04:35:51,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:51,301 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 170 [2019-11-20 04:35:51,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:51,304 INFO L225 Difference]: With dead ends: 7627 [2019-11-20 04:35:51,304 INFO L226 Difference]: Without dead ends: 3797 [2019-11-20 04:35:51,307 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:51,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3797 states. [2019-11-20 04:35:51,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3797 to 3568. [2019-11-20 04:35:51,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3568 states. [2019-11-20 04:35:51,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3568 states to 3568 states and 4348 transitions. [2019-11-20 04:35:51,461 INFO L78 Accepts]: Start accepts. Automaton has 3568 states and 4348 transitions. Word has length 170 [2019-11-20 04:35:51,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:51,462 INFO L462 AbstractCegarLoop]: Abstraction has 3568 states and 4348 transitions. [2019-11-20 04:35:51,462 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:51,462 INFO L276 IsEmpty]: Start isEmpty. Operand 3568 states and 4348 transitions. [2019-11-20 04:35:51,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 178 [2019-11-20 04:35:51,464 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:51,465 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:51,465 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:51,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:51,465 INFO L82 PathProgramCache]: Analyzing trace with hash 307077909, now seen corresponding path program 1 times [2019-11-20 04:35:51,466 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:51,466 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1943436872] [2019-11-20 04:35:51,466 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:51,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:51,511 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-20 04:35:51,512 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1943436872] [2019-11-20 04:35:51,512 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:51,512 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:51,512 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [189411039] [2019-11-20 04:35:51,513 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:51,513 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:51,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:51,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:51,514 INFO L87 Difference]: Start difference. First operand 3568 states and 4348 transitions. Second operand 3 states. [2019-11-20 04:35:51,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:51,763 INFO L93 Difference]: Finished difference Result 8940 states and 10936 transitions. [2019-11-20 04:35:51,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:51,764 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 177 [2019-11-20 04:35:51,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:51,769 INFO L225 Difference]: With dead ends: 8940 [2019-11-20 04:35:51,769 INFO L226 Difference]: Without dead ends: 5648 [2019-11-20 04:35:51,772 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:51,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5648 states. [2019-11-20 04:35:52,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5648 to 5422. [2019-11-20 04:35:52,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5422 states. [2019-11-20 04:35:52,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5422 states to 5422 states and 6526 transitions. [2019-11-20 04:35:52,090 INFO L78 Accepts]: Start accepts. Automaton has 5422 states and 6526 transitions. Word has length 177 [2019-11-20 04:35:52,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:52,090 INFO L462 AbstractCegarLoop]: Abstraction has 5422 states and 6526 transitions. [2019-11-20 04:35:52,090 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:52,090 INFO L276 IsEmpty]: Start isEmpty. Operand 5422 states and 6526 transitions. [2019-11-20 04:35:52,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-20 04:35:52,092 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:52,093 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:52,093 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:52,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:52,093 INFO L82 PathProgramCache]: Analyzing trace with hash -2095538940, now seen corresponding path program 1 times [2019-11-20 04:35:52,093 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:52,094 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634780660] [2019-11-20 04:35:52,094 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:52,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:52,133 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 79 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2019-11-20 04:35:52,133 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [634780660] [2019-11-20 04:35:52,133 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:52,134 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:52,134 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229147925] [2019-11-20 04:35:52,134 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:52,134 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:52,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:52,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:52,135 INFO L87 Difference]: Start difference. First operand 5422 states and 6526 transitions. Second operand 3 states. [2019-11-20 04:35:52,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:52,316 INFO L93 Difference]: Finished difference Result 8854 states and 10720 transitions. [2019-11-20 04:35:52,316 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:52,316 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 180 [2019-11-20 04:35:52,316 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:52,319 INFO L225 Difference]: With dead ends: 8854 [2019-11-20 04:35:52,319 INFO L226 Difference]: Without dead ends: 3708 [2019-11-20 04:35:52,321 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:52,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3708 states. [2019-11-20 04:35:52,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3708 to 3100. [2019-11-20 04:35:52,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3100 states. [2019-11-20 04:35:52,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3100 states to 3100 states and 3693 transitions. [2019-11-20 04:35:52,416 INFO L78 Accepts]: Start accepts. Automaton has 3100 states and 3693 transitions. Word has length 180 [2019-11-20 04:35:52,416 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:52,416 INFO L462 AbstractCegarLoop]: Abstraction has 3100 states and 3693 transitions. [2019-11-20 04:35:52,417 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:52,417 INFO L276 IsEmpty]: Start isEmpty. Operand 3100 states and 3693 transitions. [2019-11-20 04:35:52,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-20 04:35:52,419 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:52,419 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:52,419 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:52,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:52,420 INFO L82 PathProgramCache]: Analyzing trace with hash -1037700862, now seen corresponding path program 1 times [2019-11-20 04:35:52,420 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:52,420 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764583062] [2019-11-20 04:35:52,420 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:52,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:52,473 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 91 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-20 04:35:52,474 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764583062] [2019-11-20 04:35:52,474 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:52,474 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 04:35:52,474 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099965856] [2019-11-20 04:35:52,475 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 04:35:52,475 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:52,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 04:35:52,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 04:35:52,476 INFO L87 Difference]: Start difference. First operand 3100 states and 3693 transitions. Second operand 4 states. [2019-11-20 04:35:52,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:52,614 INFO L93 Difference]: Finished difference Result 4701 states and 5585 transitions. [2019-11-20 04:35:52,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 04:35:52,614 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 180 [2019-11-20 04:35:52,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:52,616 INFO L225 Difference]: With dead ends: 4701 [2019-11-20 04:35:52,616 INFO L226 Difference]: Without dead ends: 1877 [2019-11-20 04:35:52,617 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 04:35:52,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1877 states. [2019-11-20 04:35:52,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1877 to 1590. [2019-11-20 04:35:52,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1590 states. [2019-11-20 04:35:52,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1590 states to 1590 states and 1853 transitions. [2019-11-20 04:35:52,670 INFO L78 Accepts]: Start accepts. Automaton has 1590 states and 1853 transitions. Word has length 180 [2019-11-20 04:35:52,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:52,670 INFO L462 AbstractCegarLoop]: Abstraction has 1590 states and 1853 transitions. [2019-11-20 04:35:52,670 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 04:35:52,670 INFO L276 IsEmpty]: Start isEmpty. Operand 1590 states and 1853 transitions. [2019-11-20 04:35:52,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-11-20 04:35:52,671 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:52,671 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:52,671 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:52,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:52,671 INFO L82 PathProgramCache]: Analyzing trace with hash 1351947795, now seen corresponding path program 1 times [2019-11-20 04:35:52,671 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:52,671 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983928717] [2019-11-20 04:35:52,672 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:52,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:52,727 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 04:35:52,727 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983928717] [2019-11-20 04:35:52,727 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:52,727 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:52,727 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268451115] [2019-11-20 04:35:52,728 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:52,728 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:52,728 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:52,728 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:52,729 INFO L87 Difference]: Start difference. First operand 1590 states and 1853 transitions. Second operand 3 states. [2019-11-20 04:35:52,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:52,866 INFO L93 Difference]: Finished difference Result 4058 states and 4759 transitions. [2019-11-20 04:35:52,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:52,867 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 184 [2019-11-20 04:35:52,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:52,869 INFO L225 Difference]: With dead ends: 4058 [2019-11-20 04:35:52,869 INFO L226 Difference]: Without dead ends: 2438 [2019-11-20 04:35:52,870 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:52,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2438 states. [2019-11-20 04:35:52,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2438 to 2426. [2019-11-20 04:35:52,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2426 states. [2019-11-20 04:35:52,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2426 states to 2426 states and 2829 transitions. [2019-11-20 04:35:52,952 INFO L78 Accepts]: Start accepts. Automaton has 2426 states and 2829 transitions. Word has length 184 [2019-11-20 04:35:52,952 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:52,952 INFO L462 AbstractCegarLoop]: Abstraction has 2426 states and 2829 transitions. [2019-11-20 04:35:52,952 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:52,952 INFO L276 IsEmpty]: Start isEmpty. Operand 2426 states and 2829 transitions. [2019-11-20 04:35:52,953 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-11-20 04:35:52,953 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:52,953 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:52,954 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:52,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:52,954 INFO L82 PathProgramCache]: Analyzing trace with hash 1047126543, now seen corresponding path program 1 times [2019-11-20 04:35:52,954 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:52,954 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001576867] [2019-11-20 04:35:52,955 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:52,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:53,005 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 93 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-20 04:35:53,005 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001576867] [2019-11-20 04:35:53,005 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:53,005 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:53,005 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109191700] [2019-11-20 04:35:53,006 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:53,006 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:53,006 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:53,006 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:53,007 INFO L87 Difference]: Start difference. First operand 2426 states and 2829 transitions. Second operand 3 states. [2019-11-20 04:35:53,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:53,110 INFO L93 Difference]: Finished difference Result 3380 states and 3910 transitions. [2019-11-20 04:35:53,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:53,111 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 184 [2019-11-20 04:35:53,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:53,112 INFO L225 Difference]: With dead ends: 3380 [2019-11-20 04:35:53,112 INFO L226 Difference]: Without dead ends: 1220 [2019-11-20 04:35:53,113 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:53,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1220 states. [2019-11-20 04:35:53,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1220 to 1198. [2019-11-20 04:35:53,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1198 states. [2019-11-20 04:35:53,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1198 states to 1198 states and 1326 transitions. [2019-11-20 04:35:53,173 INFO L78 Accepts]: Start accepts. Automaton has 1198 states and 1326 transitions. Word has length 184 [2019-11-20 04:35:53,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:53,173 INFO L462 AbstractCegarLoop]: Abstraction has 1198 states and 1326 transitions. [2019-11-20 04:35:53,173 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:53,173 INFO L276 IsEmpty]: Start isEmpty. Operand 1198 states and 1326 transitions. [2019-11-20 04:35:53,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2019-11-20 04:35:53,174 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:53,174 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:53,174 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:53,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:53,174 INFO L82 PathProgramCache]: Analyzing trace with hash -1330592792, now seen corresponding path program 1 times [2019-11-20 04:35:53,174 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:53,175 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289387335] [2019-11-20 04:35:53,175 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:53,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:53,214 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 107 trivial. 0 not checked. [2019-11-20 04:35:53,214 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289387335] [2019-11-20 04:35:53,214 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:35:53,214 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:35:53,215 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633388440] [2019-11-20 04:35:53,215 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:35:53,215 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:53,215 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:35:53,215 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:53,216 INFO L87 Difference]: Start difference. First operand 1198 states and 1326 transitions. Second operand 3 states. [2019-11-20 04:35:53,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:53,296 INFO L93 Difference]: Finished difference Result 1202 states and 1331 transitions. [2019-11-20 04:35:53,297 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:35:53,297 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 185 [2019-11-20 04:35:53,297 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:53,298 INFO L225 Difference]: With dead ends: 1202 [2019-11-20 04:35:53,298 INFO L226 Difference]: Without dead ends: 1200 [2019-11-20 04:35:53,299 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:35:53,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1200 states. [2019-11-20 04:35:53,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1200 to 1200. [2019-11-20 04:35:53,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1200 states. [2019-11-20 04:35:53,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1200 states to 1200 states and 1328 transitions. [2019-11-20 04:35:53,379 INFO L78 Accepts]: Start accepts. Automaton has 1200 states and 1328 transitions. Word has length 185 [2019-11-20 04:35:53,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:53,379 INFO L462 AbstractCegarLoop]: Abstraction has 1200 states and 1328 transitions. [2019-11-20 04:35:53,379 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:35:53,379 INFO L276 IsEmpty]: Start isEmpty. Operand 1200 states and 1328 transitions. [2019-11-20 04:35:53,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2019-11-20 04:35:53,381 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:53,381 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:53,381 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:53,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:53,382 INFO L82 PathProgramCache]: Analyzing trace with hash -1330591190, now seen corresponding path program 1 times [2019-11-20 04:35:53,382 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:53,382 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606482999] [2019-11-20 04:35:53,382 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:53,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:53,597 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 81 proven. 15 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-20 04:35:53,598 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [606482999] [2019-11-20 04:35:53,598 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [577080544] [2019-11-20 04:35:53,598 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 04:35:53,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:35:53,709 INFO L255 TraceCheckSpWp]: Trace formula consists of 499 conjuncts, 19 conjunts are in the unsatisfiable core [2019-11-20 04:35:53,731 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 04:35:53,875 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 81 proven. 15 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-20 04:35:53,875 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-20 04:35:53,876 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2019-11-20 04:35:53,876 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1305526055] [2019-11-20 04:35:53,877 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-11-20 04:35:53,877 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:35:53,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-11-20 04:35:53,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2019-11-20 04:35:53,877 INFO L87 Difference]: Start difference. First operand 1200 states and 1328 transitions. Second operand 10 states. [2019-11-20 04:35:54,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:35:54,411 INFO L93 Difference]: Finished difference Result 2336 states and 2602 transitions. [2019-11-20 04:35:54,411 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-11-20 04:35:54,412 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 185 [2019-11-20 04:35:54,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:35:54,415 INFO L225 Difference]: With dead ends: 2336 [2019-11-20 04:35:54,415 INFO L226 Difference]: Without dead ends: 1732 [2019-11-20 04:35:54,416 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 206 GetRequests, 188 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=64, Invalid=242, Unknown=0, NotChecked=0, Total=306 [2019-11-20 04:35:54,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1732 states. [2019-11-20 04:35:54,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1732 to 1546. [2019-11-20 04:35:54,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1546 states. [2019-11-20 04:35:54,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1546 states to 1546 states and 1714 transitions. [2019-11-20 04:35:54,593 INFO L78 Accepts]: Start accepts. Automaton has 1546 states and 1714 transitions. Word has length 185 [2019-11-20 04:35:54,593 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:35:54,593 INFO L462 AbstractCegarLoop]: Abstraction has 1546 states and 1714 transitions. [2019-11-20 04:35:54,593 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-11-20 04:35:54,593 INFO L276 IsEmpty]: Start isEmpty. Operand 1546 states and 1714 transitions. [2019-11-20 04:35:54,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2019-11-20 04:35:54,596 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:35:54,596 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:35:54,799 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-20 04:35:54,800 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:35:54,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:35:54,800 INFO L82 PathProgramCache]: Analyzing trace with hash 1701344696, now seen corresponding path program 1 times [2019-11-20 04:35:54,800 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:35:54,801 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [559715390] [2019-11-20 04:35:54,801 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:35:54,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 04:35:54,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 04:35:54,898 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 04:35:54,898 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-20 04:35:55,080 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 20.11 04:35:55 BoogieIcfgContainer [2019-11-20 04:35:55,080 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-20 04:35:55,081 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-20 04:35:55,081 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-20 04:35:55,081 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-20 04:35:55,082 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 04:35:32" (3/4) ... [2019-11-20 04:35:55,083 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-20 04:35:55,243 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_edbff937-8b53-4517-a39a-a4a4ecd71254/bin/uautomizer/witness.graphml [2019-11-20 04:35:55,243 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-20 04:35:55,245 INFO L168 Benchmark]: Toolchain (without parser) took 23807.63 ms. Allocated memory was 1.0 GB in the beginning and 3.5 GB in the end (delta: 2.5 GB). Free memory was 944.7 MB in the beginning and 1.6 GB in the end (delta: -615.1 MB). Peak memory consumption was 1.9 GB. Max. memory is 11.5 GB. [2019-11-20 04:35:55,245 INFO L168 Benchmark]: CDTParser took 0.26 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 04:35:55,246 INFO L168 Benchmark]: CACSL2BoogieTranslator took 474.13 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.0 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -187.9 MB). Peak memory consumption was 22.9 MB. Max. memory is 11.5 GB. [2019-11-20 04:35:55,246 INFO L168 Benchmark]: Boogie Procedure Inliner took 65.73 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-11-20 04:35:55,246 INFO L168 Benchmark]: Boogie Preprocessor took 51.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 11.5 GB. [2019-11-20 04:35:55,247 INFO L168 Benchmark]: RCFGBuilder took 713.49 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.9 MB). Peak memory consumption was 47.9 MB. Max. memory is 11.5 GB. [2019-11-20 04:35:55,247 INFO L168 Benchmark]: TraceAbstraction took 22337.48 ms. Allocated memory was 1.2 GB in the beginning and 3.5 GB in the end (delta: 2.4 GB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -551.9 MB). Peak memory consumption was 1.8 GB. Max. memory is 11.5 GB. [2019-11-20 04:35:55,247 INFO L168 Benchmark]: Witness Printer took 162.35 ms. Allocated memory is still 3.5 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 68.5 MB). Peak memory consumption was 68.5 MB. Max. memory is 11.5 GB. [2019-11-20 04:35:55,249 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.26 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 474.13 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.0 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -187.9 MB). Peak memory consumption was 22.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 65.73 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 51.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 713.49 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 47.9 MB). Peak memory consumption was 47.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 22337.48 ms. Allocated memory was 1.2 GB in the beginning and 3.5 GB in the end (delta: 2.4 GB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -551.9 MB). Peak memory consumption was 1.8 GB. Max. memory is 11.5 GB. * Witness Printer took 162.35 ms. Allocated memory is still 3.5 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 68.5 MB). Peak memory consumption was 68.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L691] int __retres1 ; [L695] e_wl = 2 [L696] e_c = e_wl [L697] e_g = e_c [L698] e_f = e_g [L699] e_e = e_f [L700] wl_pc = 0 [L701] c1_pc = 0 [L702] c2_pc = 0 [L703] wb_pc = 0 [L704] wb_i = 1 [L705] c2_i = wb_i [L706] c1_i = c2_i [L707] wl_i = c1_i [L708] r_i = 0 [L709] c_req_up = 0 [L710] d = 0 [L711] c = 0 [L402] int kernel_st ; [L405] kernel_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L406] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L417] COND TRUE (int )wl_i == 1 [L418] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L422] COND TRUE (int )c1_i == 1 [L423] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L427] COND TRUE (int )c2_i == 1 [L428] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L432] COND TRUE (int )wb_i == 1 [L433] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L437] COND FALSE !((int )r_i == 1) [L440] r_st = 2 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L442] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L447] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L452] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L457] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L462] COND FALSE !((int )e_wl == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L467] COND FALSE !((int )wl_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L475] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L485] COND FALSE !((int )c1_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L494] COND FALSE !((int )c2_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L503] COND FALSE !((int )wb_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L512] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L517] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L522] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L527] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L532] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L537] COND FALSE !((int )e_wl == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L543] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L139] COND TRUE (int )c1_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L150] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L184] COND TRUE (int )c2_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L195] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L229] COND TRUE (int )wb_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L240] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L561] kernel_st = 3 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L577] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L582] COND TRUE (int )e_wl == 0 [L583] e_wl = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L587] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L588] COND TRUE (int )e_wl == 1 [L589] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L605] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L606] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L614] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L615] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L623] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L624] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L632] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L637] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L642] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L647] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L652] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L657] COND TRUE (int )e_wl == 1 [L658] e_wl = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L662] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L543] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L139] COND FALSE !((int )c1_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L142] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L157] COND TRUE ! processed [L158] data += 1 [L159] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L160] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L161] COND TRUE (int )e_g == 1 [L162] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L169] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L150] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L184] COND FALSE !((int )c2_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L187] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] COND TRUE ! processed [L203] data += 1 [L204] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L205] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L206] COND TRUE (int )e_g == 1 [L207] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L214] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L195] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L229] COND FALSE !((int )wb_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L232] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L247] c_t = data [L248] c_req_up = 1 [L249] processed = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L240] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND TRUE (int )c_req_up == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L551] COND TRUE c != c_t [L552] c = c_t [L553] e_c = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L557] c_req_up = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L561] kernel_st = 3 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L577] COND TRUE (int )e_c == 0 [L578] e_c = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L582] COND FALSE !((int )e_wl == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L587] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L595] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L596] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L605] COND TRUE (int )c1_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L606] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L614] COND TRUE (int )c2_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L615] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L623] COND TRUE (int )wb_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L624] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L632] COND TRUE (int )e_c == 1 [L633] r_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L637] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L642] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L647] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L652] COND TRUE (int )e_c == 1 [L653] e_c = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L657] COND FALSE !((int )e_wl == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L665] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L668] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L671] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L674] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L543] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L319] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L349] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L364] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND TRUE (int )r_st == 0 [L381] tmp___3 = __VERIFIER_nondet_int() [L383] COND TRUE \read(tmp___3) [L385] r_st = 1 [L261] d = c [L262] e_e = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L263] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L271] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L272] COND TRUE (int )e_e == 1 [L273] wl_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L281] e_e = 2 [L282] r_st = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L296] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L112] COND TRUE d == t + 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L120] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 129 locations, 2 error locations. Result: UNSAFE, OverallTime: 22.2s, OverallIterations: 39, TraceHistogramMax: 6, AutomataDifference: 10.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 8305 SDtfs, 6676 SDslu, 6853 SDs, 0 SdLazy, 904 SolverSat, 221 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 337 GetRequests, 266 SyntacticMatches, 4 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=16823occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 8.7s AutomataMinimizationTime, 38 MinimizatonAttempts, 9357 StatesRemovedByMinimization, 31 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.2s InterpolantComputationTime, 3918 NumberOfCodeBlocks, 3918 NumberOfCodeBlocksAsserted, 40 NumberOfCheckSat, 3693 ConstructedInterpolants, 0 QuantifiedInterpolants, 995189 SizeOfPredicates, 8 NumberOfNonLiveVariables, 499 ConjunctsInSsa, 19 ConjunctsInUnsatCore, 39 InterpolantComputations, 37 PerfectInterpolantSequences, 1373/1403 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...