./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/toy2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 678e0110 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/toy2.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c8989412e094655bcf4508d76eb9764ed06d0b34 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-678e011 [2019-11-20 01:46:36,152 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-20 01:46:36,153 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-20 01:46:36,163 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-20 01:46:36,164 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-20 01:46:36,165 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-20 01:46:36,166 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-20 01:46:36,168 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-20 01:46:36,176 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-20 01:46:36,177 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-20 01:46:36,178 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-20 01:46:36,180 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-20 01:46:36,181 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-20 01:46:36,183 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-20 01:46:36,184 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-20 01:46:36,186 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-20 01:46:36,187 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-20 01:46:36,192 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-20 01:46:36,195 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-20 01:46:36,197 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-20 01:46:36,200 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-20 01:46:36,203 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-20 01:46:36,205 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-20 01:46:36,207 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-20 01:46:36,210 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-20 01:46:36,211 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-20 01:46:36,212 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-20 01:46:36,213 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-20 01:46:36,214 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-20 01:46:36,215 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-20 01:46:36,215 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-20 01:46:36,216 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-20 01:46:36,217 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-20 01:46:36,218 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-20 01:46:36,219 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-20 01:46:36,219 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-20 01:46:36,220 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-20 01:46:36,220 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-20 01:46:36,221 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-20 01:46:36,222 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-20 01:46:36,223 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-20 01:46:36,224 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-20 01:46:36,249 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-20 01:46:36,260 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-20 01:46:36,261 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-20 01:46:36,261 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-20 01:46:36,262 INFO L138 SettingsManager]: * Use SBE=true [2019-11-20 01:46:36,262 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-20 01:46:36,262 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-20 01:46:36,262 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-20 01:46:36,262 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-20 01:46:36,263 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-20 01:46:36,263 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-20 01:46:36,263 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-20 01:46:36,263 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-20 01:46:36,263 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-20 01:46:36,264 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-20 01:46:36,264 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-20 01:46:36,264 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-20 01:46:36,264 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-20 01:46:36,265 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-20 01:46:36,265 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-20 01:46:36,265 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-20 01:46:36,265 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 01:46:36,265 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-20 01:46:36,266 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-20 01:46:36,266 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-20 01:46:36,266 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-20 01:46:36,266 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-20 01:46:36,266 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-20 01:46:36,267 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c8989412e094655bcf4508d76eb9764ed06d0b34 [2019-11-20 01:46:36,403 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-20 01:46:36,414 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-20 01:46:36,416 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-20 01:46:36,418 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-20 01:46:36,418 INFO L275 PluginConnector]: CDTParser initialized [2019-11-20 01:46:36,419 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/../../sv-benchmarks/c/systemc/toy2.cil.c [2019-11-20 01:46:36,472 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/data/cf749adf0/7fda405a30cd4dd7875040c6a3cc0406/FLAG554142caa [2019-11-20 01:46:36,873 INFO L306 CDTParser]: Found 1 translation units. [2019-11-20 01:46:36,874 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/sv-benchmarks/c/systemc/toy2.cil.c [2019-11-20 01:46:36,883 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/data/cf749adf0/7fda405a30cd4dd7875040c6a3cc0406/FLAG554142caa [2019-11-20 01:46:37,274 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/data/cf749adf0/7fda405a30cd4dd7875040c6a3cc0406 [2019-11-20 01:46:37,276 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-20 01:46:37,277 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-20 01:46:37,278 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-20 01:46:37,278 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-20 01:46:37,281 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-20 01:46:37,282 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 01:46:37" (1/1) ... [2019-11-20 01:46:37,284 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@681ef91f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37, skipping insertion in model container [2019-11-20 01:46:37,284 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 01:46:37" (1/1) ... [2019-11-20 01:46:37,291 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-20 01:46:37,348 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-20 01:46:37,684 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 01:46:37,689 INFO L188 MainTranslator]: Completed pre-run [2019-11-20 01:46:37,735 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 01:46:37,764 INFO L192 MainTranslator]: Completed translation [2019-11-20 01:46:37,764 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37 WrapperNode [2019-11-20 01:46:37,765 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-20 01:46:37,765 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-20 01:46:37,766 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-20 01:46:37,766 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-20 01:46:37,773 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37" (1/1) ... [2019-11-20 01:46:37,780 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37" (1/1) ... [2019-11-20 01:46:37,813 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-20 01:46:37,815 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-20 01:46:37,816 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-20 01:46:37,816 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-20 01:46:37,825 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37" (1/1) ... [2019-11-20 01:46:37,825 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37" (1/1) ... [2019-11-20 01:46:37,827 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37" (1/1) ... [2019-11-20 01:46:37,828 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37" (1/1) ... [2019-11-20 01:46:37,834 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37" (1/1) ... [2019-11-20 01:46:37,861 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37" (1/1) ... [2019-11-20 01:46:37,863 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37" (1/1) ... [2019-11-20 01:46:37,867 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-20 01:46:37,867 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-20 01:46:37,867 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-20 01:46:37,868 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-20 01:46:37,868 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 01:46:37,944 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-20 01:46:37,945 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-20 01:46:38,611 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-20 01:46:38,611 INFO L285 CfgBuilder]: Removed 26 assume(true) statements. [2019-11-20 01:46:38,612 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 01:46:38 BoogieIcfgContainer [2019-11-20 01:46:38,612 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-20 01:46:38,613 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-20 01:46:38,613 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-20 01:46:38,616 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-20 01:46:38,616 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.11 01:46:37" (1/3) ... [2019-11-20 01:46:38,617 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2c879ad7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 01:46:38, skipping insertion in model container [2019-11-20 01:46:38,617 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:46:37" (2/3) ... [2019-11-20 01:46:38,618 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2c879ad7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 01:46:38, skipping insertion in model container [2019-11-20 01:46:38,618 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 01:46:38" (3/3) ... [2019-11-20 01:46:38,619 INFO L109 eAbstractionObserver]: Analyzing ICFG toy2.cil.c [2019-11-20 01:46:38,628 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-20 01:46:38,635 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-20 01:46:38,645 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-20 01:46:38,678 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-20 01:46:38,678 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-20 01:46:38,678 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-20 01:46:38,679 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-20 01:46:38,679 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-20 01:46:38,680 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-20 01:46:38,680 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-20 01:46:38,680 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-20 01:46:38,707 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states. [2019-11-20 01:46:38,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-20 01:46:38,719 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:38,720 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:38,721 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:38,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:38,726 INFO L82 PathProgramCache]: Analyzing trace with hash 1633671955, now seen corresponding path program 1 times [2019-11-20 01:46:38,731 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:38,732 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935324003] [2019-11-20 01:46:38,732 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:38,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:38,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:38,895 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935324003] [2019-11-20 01:46:38,896 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:38,896 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:38,897 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [236478349] [2019-11-20 01:46:38,902 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:38,903 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:38,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:38,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:38,918 INFO L87 Difference]: Start difference. First operand 125 states. Second operand 3 states. [2019-11-20 01:46:38,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:38,958 INFO L93 Difference]: Finished difference Result 242 states and 449 transitions. [2019-11-20 01:46:38,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:38,960 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-20 01:46:38,961 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:38,971 INFO L225 Difference]: With dead ends: 242 [2019-11-20 01:46:38,972 INFO L226 Difference]: Without dead ends: 121 [2019-11-20 01:46:38,975 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:38,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2019-11-20 01:46:39,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 121. [2019-11-20 01:46:39,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2019-11-20 01:46:39,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 213 transitions. [2019-11-20 01:46:39,017 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 213 transitions. Word has length 35 [2019-11-20 01:46:39,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:39,018 INFO L462 AbstractCegarLoop]: Abstraction has 121 states and 213 transitions. [2019-11-20 01:46:39,018 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:39,018 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 213 transitions. [2019-11-20 01:46:39,020 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-20 01:46:39,020 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:39,020 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:39,020 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:39,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:39,021 INFO L82 PathProgramCache]: Analyzing trace with hash 1611039701, now seen corresponding path program 1 times [2019-11-20 01:46:39,021 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:39,022 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590023194] [2019-11-20 01:46:39,022 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:39,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:39,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:39,072 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1590023194] [2019-11-20 01:46:39,072 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:39,072 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:39,073 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664076152] [2019-11-20 01:46:39,074 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:39,074 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:39,075 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:39,075 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:39,075 INFO L87 Difference]: Start difference. First operand 121 states and 213 transitions. Second operand 3 states. [2019-11-20 01:46:39,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:39,099 INFO L93 Difference]: Finished difference Result 232 states and 410 transitions. [2019-11-20 01:46:39,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:39,100 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-20 01:46:39,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:39,102 INFO L225 Difference]: With dead ends: 232 [2019-11-20 01:46:39,102 INFO L226 Difference]: Without dead ends: 121 [2019-11-20 01:46:39,105 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:39,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2019-11-20 01:46:39,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 121. [2019-11-20 01:46:39,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2019-11-20 01:46:39,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 212 transitions. [2019-11-20 01:46:39,118 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 212 transitions. Word has length 35 [2019-11-20 01:46:39,119 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:39,119 INFO L462 AbstractCegarLoop]: Abstraction has 121 states and 212 transitions. [2019-11-20 01:46:39,119 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:39,119 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 212 transitions. [2019-11-20 01:46:39,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-20 01:46:39,121 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:39,121 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:39,121 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:39,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:39,122 INFO L82 PathProgramCache]: Analyzing trace with hash 1101566611, now seen corresponding path program 1 times [2019-11-20 01:46:39,122 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:39,122 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423631746] [2019-11-20 01:46:39,123 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:39,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:39,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:39,209 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1423631746] [2019-11-20 01:46:39,209 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:39,209 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:39,209 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [555286030] [2019-11-20 01:46:39,210 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:39,210 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:39,210 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:39,210 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:39,210 INFO L87 Difference]: Start difference. First operand 121 states and 212 transitions. Second operand 3 states. [2019-11-20 01:46:39,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:39,340 INFO L93 Difference]: Finished difference Result 316 states and 553 transitions. [2019-11-20 01:46:39,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:39,341 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-20 01:46:39,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:39,343 INFO L225 Difference]: With dead ends: 316 [2019-11-20 01:46:39,344 INFO L226 Difference]: Without dead ends: 206 [2019-11-20 01:46:39,345 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:39,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2019-11-20 01:46:39,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 196. [2019-11-20 01:46:39,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 196 states. [2019-11-20 01:46:39,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 330 transitions. [2019-11-20 01:46:39,381 INFO L78 Accepts]: Start accepts. Automaton has 196 states and 330 transitions. Word has length 35 [2019-11-20 01:46:39,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:39,381 INFO L462 AbstractCegarLoop]: Abstraction has 196 states and 330 transitions. [2019-11-20 01:46:39,382 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:39,382 INFO L276 IsEmpty]: Start isEmpty. Operand 196 states and 330 transitions. [2019-11-20 01:46:39,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-20 01:46:39,386 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:39,386 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:39,386 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:39,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:39,387 INFO L82 PathProgramCache]: Analyzing trace with hash 197658071, now seen corresponding path program 1 times [2019-11-20 01:46:39,387 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:39,388 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179834193] [2019-11-20 01:46:39,388 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:39,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:39,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:39,464 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1179834193] [2019-11-20 01:46:39,464 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:39,464 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 01:46:39,464 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878912085] [2019-11-20 01:46:39,465 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 01:46:39,465 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:39,465 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 01:46:39,465 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 01:46:39,465 INFO L87 Difference]: Start difference. First operand 196 states and 330 transitions. Second operand 4 states. [2019-11-20 01:46:39,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:39,594 INFO L93 Difference]: Finished difference Result 530 states and 896 transitions. [2019-11-20 01:46:39,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 01:46:39,595 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-20 01:46:39,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:39,597 INFO L225 Difference]: With dead ends: 530 [2019-11-20 01:46:39,598 INFO L226 Difference]: Without dead ends: 346 [2019-11-20 01:46:39,599 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:46:39,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346 states. [2019-11-20 01:46:39,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346 to 340. [2019-11-20 01:46:39,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2019-11-20 01:46:39,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 572 transitions. [2019-11-20 01:46:39,628 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 572 transitions. Word has length 35 [2019-11-20 01:46:39,628 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:39,629 INFO L462 AbstractCegarLoop]: Abstraction has 340 states and 572 transitions. [2019-11-20 01:46:39,629 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 01:46:39,629 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 572 transitions. [2019-11-20 01:46:39,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-20 01:46:39,631 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:39,631 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:39,631 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:39,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:39,632 INFO L82 PathProgramCache]: Analyzing trace with hash 259697685, now seen corresponding path program 1 times [2019-11-20 01:46:39,632 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:39,632 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394084032] [2019-11-20 01:46:39,632 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:39,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:39,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:39,684 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394084032] [2019-11-20 01:46:39,685 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:39,685 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 01:46:39,685 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1731415763] [2019-11-20 01:46:39,685 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 01:46:39,686 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:39,686 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 01:46:39,686 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 01:46:39,686 INFO L87 Difference]: Start difference. First operand 340 states and 572 transitions. Second operand 4 states. [2019-11-20 01:46:39,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:39,807 INFO L93 Difference]: Finished difference Result 955 states and 1611 transitions. [2019-11-20 01:46:39,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 01:46:39,808 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-20 01:46:39,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:39,812 INFO L225 Difference]: With dead ends: 955 [2019-11-20 01:46:39,812 INFO L226 Difference]: Without dead ends: 628 [2019-11-20 01:46:39,814 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:46:39,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 628 states. [2019-11-20 01:46:39,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 628 to 622. [2019-11-20 01:46:39,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2019-11-20 01:46:39,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 1042 transitions. [2019-11-20 01:46:39,867 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 1042 transitions. Word has length 35 [2019-11-20 01:46:39,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:39,868 INFO L462 AbstractCegarLoop]: Abstraction has 622 states and 1042 transitions. [2019-11-20 01:46:39,868 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 01:46:39,869 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 1042 transitions. [2019-11-20 01:46:39,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-20 01:46:39,875 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:39,876 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:39,876 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:39,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:39,876 INFO L82 PathProgramCache]: Analyzing trace with hash 400246295, now seen corresponding path program 1 times [2019-11-20 01:46:39,877 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:39,877 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2147060040] [2019-11-20 01:46:39,877 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:39,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:39,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:39,945 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2147060040] [2019-11-20 01:46:39,946 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:39,946 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 01:46:39,946 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475505128] [2019-11-20 01:46:39,946 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 01:46:39,947 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:39,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 01:46:39,947 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 01:46:39,947 INFO L87 Difference]: Start difference. First operand 622 states and 1042 transitions. Second operand 4 states. [2019-11-20 01:46:40,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:40,110 INFO L93 Difference]: Finished difference Result 1891 states and 3148 transitions. [2019-11-20 01:46:40,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 01:46:40,111 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-20 01:46:40,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:40,120 INFO L225 Difference]: With dead ends: 1891 [2019-11-20 01:46:40,120 INFO L226 Difference]: Without dead ends: 1283 [2019-11-20 01:46:40,122 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:46:40,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1283 states. [2019-11-20 01:46:40,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1283 to 1277. [2019-11-20 01:46:40,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1277 states. [2019-11-20 01:46:40,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1277 states to 1277 states and 2102 transitions. [2019-11-20 01:46:40,189 INFO L78 Accepts]: Start accepts. Automaton has 1277 states and 2102 transitions. Word has length 35 [2019-11-20 01:46:40,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:40,192 INFO L462 AbstractCegarLoop]: Abstraction has 1277 states and 2102 transitions. [2019-11-20 01:46:40,192 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 01:46:40,193 INFO L276 IsEmpty]: Start isEmpty. Operand 1277 states and 2102 transitions. [2019-11-20 01:46:40,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-20 01:46:40,195 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:40,196 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:40,196 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:40,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:40,201 INFO L82 PathProgramCache]: Analyzing trace with hash 266232789, now seen corresponding path program 1 times [2019-11-20 01:46:40,201 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:40,201 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276978270] [2019-11-20 01:46:40,202 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:40,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:40,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:40,257 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276978270] [2019-11-20 01:46:40,257 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:40,257 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:40,258 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331682340] [2019-11-20 01:46:40,258 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:40,258 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:40,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:40,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:40,259 INFO L87 Difference]: Start difference. First operand 1277 states and 2102 transitions. Second operand 3 states. [2019-11-20 01:46:40,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:40,374 INFO L93 Difference]: Finished difference Result 2603 states and 4295 transitions. [2019-11-20 01:46:40,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:40,374 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-20 01:46:40,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:40,382 INFO L225 Difference]: With dead ends: 2603 [2019-11-20 01:46:40,383 INFO L226 Difference]: Without dead ends: 1383 [2019-11-20 01:46:40,385 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:40,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1383 states. [2019-11-20 01:46:40,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1383 to 1376. [2019-11-20 01:46:40,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1376 states. [2019-11-20 01:46:40,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1376 states to 1376 states and 2257 transitions. [2019-11-20 01:46:40,449 INFO L78 Accepts]: Start accepts. Automaton has 1376 states and 2257 transitions. Word has length 35 [2019-11-20 01:46:40,450 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:40,450 INFO L462 AbstractCegarLoop]: Abstraction has 1376 states and 2257 transitions. [2019-11-20 01:46:40,450 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:40,450 INFO L276 IsEmpty]: Start isEmpty. Operand 1376 states and 2257 transitions. [2019-11-20 01:46:40,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-20 01:46:40,452 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:40,452 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:40,452 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:40,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:40,453 INFO L82 PathProgramCache]: Analyzing trace with hash -1908921127, now seen corresponding path program 1 times [2019-11-20 01:46:40,453 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:40,453 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317047972] [2019-11-20 01:46:40,454 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:40,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:40,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:40,506 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [317047972] [2019-11-20 01:46:40,507 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:40,507 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 01:46:40,507 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967199988] [2019-11-20 01:46:40,507 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 01:46:40,508 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:40,508 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 01:46:40,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 01:46:40,508 INFO L87 Difference]: Start difference. First operand 1376 states and 2257 transitions. Second operand 4 states. [2019-11-20 01:46:40,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:40,649 INFO L93 Difference]: Finished difference Result 2882 states and 4737 transitions. [2019-11-20 01:46:40,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 01:46:40,650 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-20 01:46:40,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:40,659 INFO L225 Difference]: With dead ends: 2882 [2019-11-20 01:46:40,660 INFO L226 Difference]: Without dead ends: 1540 [2019-11-20 01:46:40,662 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:46:40,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1540 states. [2019-11-20 01:46:40,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1540 to 1529. [2019-11-20 01:46:40,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1529 states. [2019-11-20 01:46:40,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1529 states to 1529 states and 2471 transitions. [2019-11-20 01:46:40,751 INFO L78 Accepts]: Start accepts. Automaton has 1529 states and 2471 transitions. Word has length 35 [2019-11-20 01:46:40,751 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:40,751 INFO L462 AbstractCegarLoop]: Abstraction has 1529 states and 2471 transitions. [2019-11-20 01:46:40,752 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 01:46:40,752 INFO L276 IsEmpty]: Start isEmpty. Operand 1529 states and 2471 transitions. [2019-11-20 01:46:40,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-20 01:46:40,776 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:40,776 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:40,777 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:40,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:40,778 INFO L82 PathProgramCache]: Analyzing trace with hash 1364977815, now seen corresponding path program 1 times [2019-11-20 01:46:40,778 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:40,778 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249692712] [2019-11-20 01:46:40,778 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:40,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:40,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:40,814 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249692712] [2019-11-20 01:46:40,814 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:40,814 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 01:46:40,814 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1539404119] [2019-11-20 01:46:40,815 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 01:46:40,815 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:40,815 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 01:46:40,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 01:46:40,815 INFO L87 Difference]: Start difference. First operand 1529 states and 2471 transitions. Second operand 4 states. [2019-11-20 01:46:40,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:40,957 INFO L93 Difference]: Finished difference Result 3348 states and 5416 transitions. [2019-11-20 01:46:40,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 01:46:40,958 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-20 01:46:40,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:40,969 INFO L225 Difference]: With dead ends: 3348 [2019-11-20 01:46:40,969 INFO L226 Difference]: Without dead ends: 1865 [2019-11-20 01:46:40,972 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:46:40,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1865 states. [2019-11-20 01:46:41,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1865 to 1841. [2019-11-20 01:46:41,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1841 states. [2019-11-20 01:46:41,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1841 states to 1841 states and 2935 transitions. [2019-11-20 01:46:41,056 INFO L78 Accepts]: Start accepts. Automaton has 1841 states and 2935 transitions. Word has length 35 [2019-11-20 01:46:41,056 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:41,057 INFO L462 AbstractCegarLoop]: Abstraction has 1841 states and 2935 transitions. [2019-11-20 01:46:41,057 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 01:46:41,057 INFO L276 IsEmpty]: Start isEmpty. Operand 1841 states and 2935 transitions. [2019-11-20 01:46:41,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-20 01:46:41,058 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:41,058 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:41,058 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:41,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:41,059 INFO L82 PathProgramCache]: Analyzing trace with hash 353860565, now seen corresponding path program 1 times [2019-11-20 01:46:41,059 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:41,059 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333943401] [2019-11-20 01:46:41,060 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:41,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:41,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:41,098 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333943401] [2019-11-20 01:46:41,098 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:41,098 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:41,098 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2018625494] [2019-11-20 01:46:41,099 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:41,099 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:41,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:41,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:41,099 INFO L87 Difference]: Start difference. First operand 1841 states and 2935 transitions. Second operand 3 states. [2019-11-20 01:46:41,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:41,194 INFO L93 Difference]: Finished difference Result 3307 states and 5278 transitions. [2019-11-20 01:46:41,194 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:41,194 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-20 01:46:41,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:41,203 INFO L225 Difference]: With dead ends: 3307 [2019-11-20 01:46:41,203 INFO L226 Difference]: Without dead ends: 1494 [2019-11-20 01:46:41,206 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:41,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1494 states. [2019-11-20 01:46:41,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1494 to 1483. [2019-11-20 01:46:41,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1483 states. [2019-11-20 01:46:41,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1483 states to 1483 states and 2335 transitions. [2019-11-20 01:46:41,271 INFO L78 Accepts]: Start accepts. Automaton has 1483 states and 2335 transitions. Word has length 35 [2019-11-20 01:46:41,271 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:41,271 INFO L462 AbstractCegarLoop]: Abstraction has 1483 states and 2335 transitions. [2019-11-20 01:46:41,271 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:41,272 INFO L276 IsEmpty]: Start isEmpty. Operand 1483 states and 2335 transitions. [2019-11-20 01:46:41,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-11-20 01:46:41,273 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:41,273 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:41,274 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:41,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:41,274 INFO L82 PathProgramCache]: Analyzing trace with hash -209495903, now seen corresponding path program 1 times [2019-11-20 01:46:41,274 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:41,274 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670430025] [2019-11-20 01:46:41,275 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:41,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:41,298 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:41,298 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670430025] [2019-11-20 01:46:41,298 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:41,298 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:41,298 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [837138306] [2019-11-20 01:46:41,299 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:41,299 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:41,299 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:41,299 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:41,299 INFO L87 Difference]: Start difference. First operand 1483 states and 2335 transitions. Second operand 3 states. [2019-11-20 01:46:41,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:41,395 INFO L93 Difference]: Finished difference Result 3698 states and 5877 transitions. [2019-11-20 01:46:41,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:41,395 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2019-11-20 01:46:41,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:41,408 INFO L225 Difference]: With dead ends: 3698 [2019-11-20 01:46:41,409 INFO L226 Difference]: Without dead ends: 2269 [2019-11-20 01:46:41,411 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:41,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2269 states. [2019-11-20 01:46:41,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2269 to 2267. [2019-11-20 01:46:41,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2267 states. [2019-11-20 01:46:41,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2267 states to 2267 states and 3563 transitions. [2019-11-20 01:46:41,507 INFO L78 Accepts]: Start accepts. Automaton has 2267 states and 3563 transitions. Word has length 45 [2019-11-20 01:46:41,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:41,508 INFO L462 AbstractCegarLoop]: Abstraction has 2267 states and 3563 transitions. [2019-11-20 01:46:41,508 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:41,508 INFO L276 IsEmpty]: Start isEmpty. Operand 2267 states and 3563 transitions. [2019-11-20 01:46:41,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-11-20 01:46:41,510 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:41,510 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:41,511 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:41,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:41,511 INFO L82 PathProgramCache]: Analyzing trace with hash 214150819, now seen corresponding path program 1 times [2019-11-20 01:46:41,511 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:41,512 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043787387] [2019-11-20 01:46:41,512 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:41,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:41,537 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-20 01:46:41,537 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043787387] [2019-11-20 01:46:41,537 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:41,537 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:41,537 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872651641] [2019-11-20 01:46:41,538 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:41,538 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:41,538 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:41,538 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:41,539 INFO L87 Difference]: Start difference. First operand 2267 states and 3563 transitions. Second operand 3 states. [2019-11-20 01:46:41,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:41,619 INFO L93 Difference]: Finished difference Result 4436 states and 7000 transitions. [2019-11-20 01:46:41,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:41,619 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2019-11-20 01:46:41,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:41,632 INFO L225 Difference]: With dead ends: 4436 [2019-11-20 01:46:41,632 INFO L226 Difference]: Without dead ends: 2223 [2019-11-20 01:46:41,635 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:41,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2223 states. [2019-11-20 01:46:41,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2223 to 2223. [2019-11-20 01:46:41,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2223 states. [2019-11-20 01:46:41,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2223 states to 2223 states and 3506 transitions. [2019-11-20 01:46:41,730 INFO L78 Accepts]: Start accepts. Automaton has 2223 states and 3506 transitions. Word has length 45 [2019-11-20 01:46:41,730 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:41,730 INFO L462 AbstractCegarLoop]: Abstraction has 2223 states and 3506 transitions. [2019-11-20 01:46:41,730 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:41,730 INFO L276 IsEmpty]: Start isEmpty. Operand 2223 states and 3506 transitions. [2019-11-20 01:46:41,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-20 01:46:41,732 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:41,732 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:41,732 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:41,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:41,733 INFO L82 PathProgramCache]: Analyzing trace with hash 1700232685, now seen corresponding path program 1 times [2019-11-20 01:46:41,733 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:41,733 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299254698] [2019-11-20 01:46:41,733 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:41,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:41,755 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:41,755 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1299254698] [2019-11-20 01:46:41,756 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:41,756 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:41,756 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101645216] [2019-11-20 01:46:41,756 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:41,756 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:41,756 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:41,757 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:41,757 INFO L87 Difference]: Start difference. First operand 2223 states and 3506 transitions. Second operand 3 states. [2019-11-20 01:46:41,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:41,904 INFO L93 Difference]: Finished difference Result 5707 states and 9064 transitions. [2019-11-20 01:46:41,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:41,905 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-20 01:46:41,905 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:41,925 INFO L225 Difference]: With dead ends: 5707 [2019-11-20 01:46:41,925 INFO L226 Difference]: Without dead ends: 3538 [2019-11-20 01:46:41,929 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:41,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3538 states. [2019-11-20 01:46:42,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3538 to 3536. [2019-11-20 01:46:42,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3536 states. [2019-11-20 01:46:42,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3536 states to 3536 states and 5558 transitions. [2019-11-20 01:46:42,116 INFO L78 Accepts]: Start accepts. Automaton has 3536 states and 5558 transitions. Word has length 46 [2019-11-20 01:46:42,116 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:42,116 INFO L462 AbstractCegarLoop]: Abstraction has 3536 states and 5558 transitions. [2019-11-20 01:46:42,116 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:42,117 INFO L276 IsEmpty]: Start isEmpty. Operand 3536 states and 5558 transitions. [2019-11-20 01:46:42,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-11-20 01:46:42,119 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:42,119 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:42,120 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:42,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:42,120 INFO L82 PathProgramCache]: Analyzing trace with hash 1601371510, now seen corresponding path program 1 times [2019-11-20 01:46:42,120 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:42,121 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459311716] [2019-11-20 01:46:42,121 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:42,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:42,146 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:42,146 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459311716] [2019-11-20 01:46:42,147 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:42,147 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:42,147 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1743172698] [2019-11-20 01:46:42,148 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:42,148 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:42,148 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:42,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:42,149 INFO L87 Difference]: Start difference. First operand 3536 states and 5558 transitions. Second operand 3 states. [2019-11-20 01:46:42,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:42,411 INFO L93 Difference]: Finished difference Result 8979 states and 14292 transitions. [2019-11-20 01:46:42,411 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:42,411 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-11-20 01:46:42,411 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:42,443 INFO L225 Difference]: With dead ends: 8979 [2019-11-20 01:46:42,443 INFO L226 Difference]: Without dead ends: 5501 [2019-11-20 01:46:42,448 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:42,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5501 states. [2019-11-20 01:46:42,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5501 to 5499. [2019-11-20 01:46:42,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5499 states. [2019-11-20 01:46:42,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5499 states to 5499 states and 8711 transitions. [2019-11-20 01:46:42,701 INFO L78 Accepts]: Start accepts. Automaton has 5499 states and 8711 transitions. Word has length 47 [2019-11-20 01:46:42,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:42,701 INFO L462 AbstractCegarLoop]: Abstraction has 5499 states and 8711 transitions. [2019-11-20 01:46:42,701 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:42,701 INFO L276 IsEmpty]: Start isEmpty. Operand 5499 states and 8711 transitions. [2019-11-20 01:46:42,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-11-20 01:46:42,705 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:42,705 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:42,705 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:42,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:42,706 INFO L82 PathProgramCache]: Analyzing trace with hash 2025018232, now seen corresponding path program 1 times [2019-11-20 01:46:42,706 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:42,706 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119739045] [2019-11-20 01:46:42,706 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:42,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:42,721 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-20 01:46:42,722 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119739045] [2019-11-20 01:46:42,722 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:42,722 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:42,722 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [175072053] [2019-11-20 01:46:42,723 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:42,723 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:42,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:42,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:42,723 INFO L87 Difference]: Start difference. First operand 5499 states and 8711 transitions. Second operand 3 states. [2019-11-20 01:46:42,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:42,917 INFO L93 Difference]: Finished difference Result 10896 states and 17296 transitions. [2019-11-20 01:46:42,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:42,918 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-11-20 01:46:42,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:42,939 INFO L225 Difference]: With dead ends: 10896 [2019-11-20 01:46:42,940 INFO L226 Difference]: Without dead ends: 5455 [2019-11-20 01:46:42,947 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:42,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5455 states. [2019-11-20 01:46:43,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5455 to 5455. [2019-11-20 01:46:43,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5455 states. [2019-11-20 01:46:43,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5455 states to 5455 states and 8656 transitions. [2019-11-20 01:46:43,165 INFO L78 Accepts]: Start accepts. Automaton has 5455 states and 8656 transitions. Word has length 47 [2019-11-20 01:46:43,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:43,165 INFO L462 AbstractCegarLoop]: Abstraction has 5455 states and 8656 transitions. [2019-11-20 01:46:43,166 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:43,166 INFO L276 IsEmpty]: Start isEmpty. Operand 5455 states and 8656 transitions. [2019-11-20 01:46:43,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-20 01:46:43,169 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:43,169 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:43,170 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:43,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:43,170 INFO L82 PathProgramCache]: Analyzing trace with hash -2129316584, now seen corresponding path program 1 times [2019-11-20 01:46:43,170 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:43,171 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739049057] [2019-11-20 01:46:43,171 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:43,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:43,200 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:43,201 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739049057] [2019-11-20 01:46:43,201 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:43,201 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:43,202 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176902992] [2019-11-20 01:46:43,202 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:43,202 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:43,202 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:43,203 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:43,203 INFO L87 Difference]: Start difference. First operand 5455 states and 8656 transitions. Second operand 3 states. [2019-11-20 01:46:43,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:43,569 INFO L93 Difference]: Finished difference Result 15441 states and 24452 transitions. [2019-11-20 01:46:43,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:43,569 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-20 01:46:43,570 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:43,587 INFO L225 Difference]: With dead ends: 15441 [2019-11-20 01:46:43,587 INFO L226 Difference]: Without dead ends: 8274 [2019-11-20 01:46:43,597 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:43,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8274 states. [2019-11-20 01:46:43,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8274 to 8274. [2019-11-20 01:46:43,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8274 states. [2019-11-20 01:46:43,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8274 states to 8274 states and 12950 transitions. [2019-11-20 01:46:43,899 INFO L78 Accepts]: Start accepts. Automaton has 8274 states and 12950 transitions. Word has length 48 [2019-11-20 01:46:43,899 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:43,900 INFO L462 AbstractCegarLoop]: Abstraction has 8274 states and 12950 transitions. [2019-11-20 01:46:43,900 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:43,900 INFO L276 IsEmpty]: Start isEmpty. Operand 8274 states and 12950 transitions. [2019-11-20 01:46:43,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-20 01:46:43,905 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:43,906 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:43,906 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:43,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:43,906 INFO L82 PathProgramCache]: Analyzing trace with hash -1392856220, now seen corresponding path program 1 times [2019-11-20 01:46:43,906 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:43,907 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1908065273] [2019-11-20 01:46:43,907 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:43,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:43,943 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:43,944 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1908065273] [2019-11-20 01:46:43,944 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:43,944 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:43,944 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73039930] [2019-11-20 01:46:43,945 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:43,945 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:43,945 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:43,945 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:43,945 INFO L87 Difference]: Start difference. First operand 8274 states and 12950 transitions. Second operand 3 states. [2019-11-20 01:46:44,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:44,313 INFO L93 Difference]: Finished difference Result 17053 states and 26638 transitions. [2019-11-20 01:46:44,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:44,313 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 52 [2019-11-20 01:46:44,314 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:44,332 INFO L225 Difference]: With dead ends: 17053 [2019-11-20 01:46:44,332 INFO L226 Difference]: Without dead ends: 8815 [2019-11-20 01:46:44,341 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:44,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8815 states. [2019-11-20 01:46:44,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8815 to 8272. [2019-11-20 01:46:44,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8272 states. [2019-11-20 01:46:44,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8272 states to 8272 states and 12699 transitions. [2019-11-20 01:46:44,655 INFO L78 Accepts]: Start accepts. Automaton has 8272 states and 12699 transitions. Word has length 52 [2019-11-20 01:46:44,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:44,655 INFO L462 AbstractCegarLoop]: Abstraction has 8272 states and 12699 transitions. [2019-11-20 01:46:44,656 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:44,656 INFO L276 IsEmpty]: Start isEmpty. Operand 8272 states and 12699 transitions. [2019-11-20 01:46:44,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-20 01:46:44,661 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:44,661 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:44,661 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:44,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:44,662 INFO L82 PathProgramCache]: Analyzing trace with hash 1708846795, now seen corresponding path program 1 times [2019-11-20 01:46:44,662 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:44,662 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863248089] [2019-11-20 01:46:44,662 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:44,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:44,692 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-20 01:46:44,693 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [863248089] [2019-11-20 01:46:44,693 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:44,693 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:44,693 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006367111] [2019-11-20 01:46:44,693 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:44,694 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:44,694 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:44,694 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:44,694 INFO L87 Difference]: Start difference. First operand 8272 states and 12699 transitions. Second operand 3 states. [2019-11-20 01:46:45,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:45,200 INFO L93 Difference]: Finished difference Result 24504 states and 37704 transitions. [2019-11-20 01:46:45,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:45,201 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 54 [2019-11-20 01:46:45,201 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:45,234 INFO L225 Difference]: With dead ends: 24504 [2019-11-20 01:46:45,235 INFO L226 Difference]: Without dead ends: 16235 [2019-11-20 01:46:45,248 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:45,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16235 states. [2019-11-20 01:46:46,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16235 to 16105. [2019-11-20 01:46:46,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16105 states. [2019-11-20 01:46:46,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16105 states to 16105 states and 24847 transitions. [2019-11-20 01:46:46,031 INFO L78 Accepts]: Start accepts. Automaton has 16105 states and 24847 transitions. Word has length 54 [2019-11-20 01:46:46,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:46,032 INFO L462 AbstractCegarLoop]: Abstraction has 16105 states and 24847 transitions. [2019-11-20 01:46:46,032 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:46,032 INFO L276 IsEmpty]: Start isEmpty. Operand 16105 states and 24847 transitions. [2019-11-20 01:46:46,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-11-20 01:46:46,043 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:46,044 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:46,044 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:46,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:46,044 INFO L82 PathProgramCache]: Analyzing trace with hash 194830513, now seen corresponding path program 1 times [2019-11-20 01:46:46,046 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:46,046 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143148105] [2019-11-20 01:46:46,046 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:46,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:46,077 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:46,077 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143148105] [2019-11-20 01:46:46,078 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:46,078 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:46,078 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752198372] [2019-11-20 01:46:46,079 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:46,079 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:46,080 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:46,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:46,080 INFO L87 Difference]: Start difference. First operand 16105 states and 24847 transitions. Second operand 3 states. [2019-11-20 01:46:46,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:46,791 INFO L93 Difference]: Finished difference Result 32865 states and 50652 transitions. [2019-11-20 01:46:46,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:46,791 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-11-20 01:46:46,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:46,824 INFO L225 Difference]: With dead ends: 32865 [2019-11-20 01:46:46,824 INFO L226 Difference]: Without dead ends: 16789 [2019-11-20 01:46:46,844 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:46,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16789 states. [2019-11-20 01:46:47,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16789 to 16725. [2019-11-20 01:46:47,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16725 states. [2019-11-20 01:46:47,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16725 states to 16725 states and 25149 transitions. [2019-11-20 01:46:47,448 INFO L78 Accepts]: Start accepts. Automaton has 16725 states and 25149 transitions. Word has length 85 [2019-11-20 01:46:47,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:47,448 INFO L462 AbstractCegarLoop]: Abstraction has 16725 states and 25149 transitions. [2019-11-20 01:46:47,449 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:47,449 INFO L276 IsEmpty]: Start isEmpty. Operand 16725 states and 25149 transitions. [2019-11-20 01:46:47,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-20 01:46:47,460 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:47,460 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:47,461 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:47,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:47,461 INFO L82 PathProgramCache]: Analyzing trace with hash 164482089, now seen corresponding path program 1 times [2019-11-20 01:46:47,461 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:47,462 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010675190] [2019-11-20 01:46:47,462 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:47,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:47,502 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-20 01:46:47,503 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1010675190] [2019-11-20 01:46:47,503 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:47,503 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 01:46:47,503 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1403525363] [2019-11-20 01:46:47,504 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 01:46:47,504 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:47,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 01:46:47,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 01:46:47,505 INFO L87 Difference]: Start difference. First operand 16725 states and 25149 transitions. Second operand 4 states. [2019-11-20 01:46:48,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:48,085 INFO L93 Difference]: Finished difference Result 27583 states and 41591 transitions. [2019-11-20 01:46:48,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-20 01:46:48,085 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 86 [2019-11-20 01:46:48,086 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:48,122 INFO L225 Difference]: With dead ends: 27583 [2019-11-20 01:46:48,122 INFO L226 Difference]: Without dead ends: 15803 [2019-11-20 01:46:48,133 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:46:48,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15803 states. [2019-11-20 01:46:48,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15803 to 15713. [2019-11-20 01:46:48,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15713 states. [2019-11-20 01:46:48,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15713 states to 15713 states and 23443 transitions. [2019-11-20 01:46:48,930 INFO L78 Accepts]: Start accepts. Automaton has 15713 states and 23443 transitions. Word has length 86 [2019-11-20 01:46:48,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:48,931 INFO L462 AbstractCegarLoop]: Abstraction has 15713 states and 23443 transitions. [2019-11-20 01:46:48,931 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 01:46:48,931 INFO L276 IsEmpty]: Start isEmpty. Operand 15713 states and 23443 transitions. [2019-11-20 01:46:48,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-20 01:46:48,940 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:48,940 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:48,941 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:48,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:48,941 INFO L82 PathProgramCache]: Analyzing trace with hash -433884439, now seen corresponding path program 1 times [2019-11-20 01:46:48,941 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:48,941 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124252536] [2019-11-20 01:46:48,942 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:48,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:48,973 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:48,974 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [124252536] [2019-11-20 01:46:48,975 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:48,975 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:48,975 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726208647] [2019-11-20 01:46:48,976 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:48,976 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:48,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:48,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:48,976 INFO L87 Difference]: Start difference. First operand 15713 states and 23443 transitions. Second operand 3 states. [2019-11-20 01:46:49,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:49,427 INFO L93 Difference]: Finished difference Result 32195 states and 47984 transitions. [2019-11-20 01:46:49,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:49,428 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-11-20 01:46:49,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:49,455 INFO L225 Difference]: With dead ends: 32195 [2019-11-20 01:46:49,455 INFO L226 Difference]: Without dead ends: 16523 [2019-11-20 01:46:49,467 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:49,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16523 states. [2019-11-20 01:46:50,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16523 to 16443. [2019-11-20 01:46:50,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16443 states. [2019-11-20 01:46:50,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16443 states to 16443 states and 23815 transitions. [2019-11-20 01:46:50,338 INFO L78 Accepts]: Start accepts. Automaton has 16443 states and 23815 transitions. Word has length 86 [2019-11-20 01:46:50,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:50,338 INFO L462 AbstractCegarLoop]: Abstraction has 16443 states and 23815 transitions. [2019-11-20 01:46:50,339 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:50,339 INFO L276 IsEmpty]: Start isEmpty. Operand 16443 states and 23815 transitions. [2019-11-20 01:46:50,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-11-20 01:46:50,346 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:50,346 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:50,346 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:50,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:50,347 INFO L82 PathProgramCache]: Analyzing trace with hash -1869450223, now seen corresponding path program 1 times [2019-11-20 01:46:50,347 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:50,347 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151762840] [2019-11-20 01:46:50,348 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:50,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:50,383 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:46:50,383 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151762840] [2019-11-20 01:46:50,383 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:50,384 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:50,384 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610368482] [2019-11-20 01:46:50,384 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:50,384 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:50,384 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:50,385 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:50,385 INFO L87 Difference]: Start difference. First operand 16443 states and 23815 transitions. Second operand 3 states. [2019-11-20 01:46:50,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:51,000 INFO L93 Difference]: Finished difference Result 33302 states and 48352 transitions. [2019-11-20 01:46:51,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:51,001 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 87 [2019-11-20 01:46:51,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:51,019 INFO L225 Difference]: With dead ends: 33302 [2019-11-20 01:46:51,020 INFO L226 Difference]: Without dead ends: 16920 [2019-11-20 01:46:51,033 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:51,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16920 states. [2019-11-20 01:46:51,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16920 to 13439. [2019-11-20 01:46:51,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13439 states. [2019-11-20 01:46:51,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13439 states to 13439 states and 18777 transitions. [2019-11-20 01:46:51,558 INFO L78 Accepts]: Start accepts. Automaton has 13439 states and 18777 transitions. Word has length 87 [2019-11-20 01:46:51,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:51,558 INFO L462 AbstractCegarLoop]: Abstraction has 13439 states and 18777 transitions. [2019-11-20 01:46:51,558 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:51,558 INFO L276 IsEmpty]: Start isEmpty. Operand 13439 states and 18777 transitions. [2019-11-20 01:46:51,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2019-11-20 01:46:51,565 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:51,566 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:51,566 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:51,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:51,566 INFO L82 PathProgramCache]: Analyzing trace with hash -2059863225, now seen corresponding path program 1 times [2019-11-20 01:46:51,566 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:51,567 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018396261] [2019-11-20 01:46:51,567 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:51,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:51,602 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-20 01:46:51,602 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018396261] [2019-11-20 01:46:51,603 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:51,603 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:51,603 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804083956] [2019-11-20 01:46:51,603 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:51,604 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:51,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:51,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:51,604 INFO L87 Difference]: Start difference. First operand 13439 states and 18777 transitions. Second operand 3 states. [2019-11-20 01:46:52,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:52,361 INFO L93 Difference]: Finished difference Result 23921 states and 33457 transitions. [2019-11-20 01:46:52,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:52,361 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 88 [2019-11-20 01:46:52,362 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:52,373 INFO L225 Difference]: With dead ends: 23921 [2019-11-20 01:46:52,373 INFO L226 Difference]: Without dead ends: 15605 [2019-11-20 01:46:52,379 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:52,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15605 states. [2019-11-20 01:46:52,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15605 to 15125. [2019-11-20 01:46:52,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15125 states. [2019-11-20 01:46:52,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15125 states to 15125 states and 20656 transitions. [2019-11-20 01:46:52,800 INFO L78 Accepts]: Start accepts. Automaton has 15125 states and 20656 transitions. Word has length 88 [2019-11-20 01:46:52,800 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:52,800 INFO L462 AbstractCegarLoop]: Abstraction has 15125 states and 20656 transitions. [2019-11-20 01:46:52,800 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:52,800 INFO L276 IsEmpty]: Start isEmpty. Operand 15125 states and 20656 transitions. [2019-11-20 01:46:52,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2019-11-20 01:46:52,815 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:52,815 INFO L410 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:52,815 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:52,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:52,816 INFO L82 PathProgramCache]: Analyzing trace with hash 1061949686, now seen corresponding path program 1 times [2019-11-20 01:46:52,816 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:52,816 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877706156] [2019-11-20 01:46:52,816 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:52,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:52,855 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-20 01:46:52,855 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1877706156] [2019-11-20 01:46:52,855 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:52,856 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:52,856 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1316778917] [2019-11-20 01:46:52,856 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:52,856 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:52,857 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:52,857 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:52,857 INFO L87 Difference]: Start difference. First operand 15125 states and 20656 transitions. Second operand 3 states. [2019-11-20 01:46:53,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:53,254 INFO L93 Difference]: Finished difference Result 29488 states and 40230 transitions. [2019-11-20 01:46:53,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:53,254 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 115 [2019-11-20 01:46:53,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:53,266 INFO L225 Difference]: With dead ends: 29488 [2019-11-20 01:46:53,266 INFO L226 Difference]: Without dead ends: 15055 [2019-11-20 01:46:53,276 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:53,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15055 states. [2019-11-20 01:46:53,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15055 to 15055. [2019-11-20 01:46:53,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15055 states. [2019-11-20 01:46:53,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15055 states to 15055 states and 20502 transitions. [2019-11-20 01:46:53,937 INFO L78 Accepts]: Start accepts. Automaton has 15055 states and 20502 transitions. Word has length 115 [2019-11-20 01:46:53,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:53,937 INFO L462 AbstractCegarLoop]: Abstraction has 15055 states and 20502 transitions. [2019-11-20 01:46:53,937 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:53,937 INFO L276 IsEmpty]: Start isEmpty. Operand 15055 states and 20502 transitions. [2019-11-20 01:46:53,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2019-11-20 01:46:53,948 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:53,949 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:53,949 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:53,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:53,949 INFO L82 PathProgramCache]: Analyzing trace with hash -1410428474, now seen corresponding path program 1 times [2019-11-20 01:46:53,949 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:53,950 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452087421] [2019-11-20 01:46:53,950 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:53,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:53,986 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2019-11-20 01:46:53,986 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452087421] [2019-11-20 01:46:53,986 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:53,986 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:53,987 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1898339580] [2019-11-20 01:46:53,987 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:53,987 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:53,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:53,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:53,988 INFO L87 Difference]: Start difference. First operand 15055 states and 20502 transitions. Second operand 3 states. [2019-11-20 01:46:54,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:54,337 INFO L93 Difference]: Finished difference Result 25586 states and 34782 transitions. [2019-11-20 01:46:54,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:54,338 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 126 [2019-11-20 01:46:54,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:54,346 INFO L225 Difference]: With dead ends: 25586 [2019-11-20 01:46:54,346 INFO L226 Difference]: Without dead ends: 10588 [2019-11-20 01:46:54,353 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:54,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10588 states. [2019-11-20 01:46:54,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10588 to 8620. [2019-11-20 01:46:54,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8620 states. [2019-11-20 01:46:54,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8620 states to 8620 states and 11274 transitions. [2019-11-20 01:46:54,612 INFO L78 Accepts]: Start accepts. Automaton has 8620 states and 11274 transitions. Word has length 126 [2019-11-20 01:46:54,612 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:54,612 INFO L462 AbstractCegarLoop]: Abstraction has 8620 states and 11274 transitions. [2019-11-20 01:46:54,612 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:54,612 INFO L276 IsEmpty]: Start isEmpty. Operand 8620 states and 11274 transitions. [2019-11-20 01:46:54,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-11-20 01:46:54,620 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:54,621 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:54,621 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:54,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:54,621 INFO L82 PathProgramCache]: Analyzing trace with hash 314934891, now seen corresponding path program 1 times [2019-11-20 01:46:54,621 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:54,622 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144493942] [2019-11-20 01:46:54,622 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:54,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:54,658 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 43 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-20 01:46:54,658 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2144493942] [2019-11-20 01:46:54,659 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:54,659 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:54,659 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257608200] [2019-11-20 01:46:54,659 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:54,660 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:54,660 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:54,660 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:54,660 INFO L87 Difference]: Start difference. First operand 8620 states and 11274 transitions. Second operand 3 states. [2019-11-20 01:46:54,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:54,897 INFO L93 Difference]: Finished difference Result 14199 states and 18567 transitions. [2019-11-20 01:46:54,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:54,897 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 127 [2019-11-20 01:46:54,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:54,902 INFO L225 Difference]: With dead ends: 14199 [2019-11-20 01:46:54,902 INFO L226 Difference]: Without dead ends: 6733 [2019-11-20 01:46:54,906 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:54,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6733 states. [2019-11-20 01:46:55,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6733 to 6149. [2019-11-20 01:46:55,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6149 states. [2019-11-20 01:46:55,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6149 states to 6149 states and 7873 transitions. [2019-11-20 01:46:55,079 INFO L78 Accepts]: Start accepts. Automaton has 6149 states and 7873 transitions. Word has length 127 [2019-11-20 01:46:55,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:55,079 INFO L462 AbstractCegarLoop]: Abstraction has 6149 states and 7873 transitions. [2019-11-20 01:46:55,079 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:55,079 INFO L276 IsEmpty]: Start isEmpty. Operand 6149 states and 7873 transitions. [2019-11-20 01:46:55,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-20 01:46:55,084 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:55,084 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:55,084 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:55,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:55,085 INFO L82 PathProgramCache]: Analyzing trace with hash -146147841, now seen corresponding path program 1 times [2019-11-20 01:46:55,085 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:55,085 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126520010] [2019-11-20 01:46:55,085 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:55,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:55,125 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-20 01:46:55,126 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1126520010] [2019-11-20 01:46:55,126 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:55,126 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:55,126 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1673493498] [2019-11-20 01:46:55,127 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:55,127 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:55,127 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:55,127 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:55,127 INFO L87 Difference]: Start difference. First operand 6149 states and 7873 transitions. Second operand 3 states. [2019-11-20 01:46:55,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:55,381 INFO L93 Difference]: Finished difference Result 11907 states and 15226 transitions. [2019-11-20 01:46:55,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:55,381 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 133 [2019-11-20 01:46:55,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:55,386 INFO L225 Difference]: With dead ends: 11907 [2019-11-20 01:46:55,386 INFO L226 Difference]: Without dead ends: 6149 [2019-11-20 01:46:55,389 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:55,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6149 states. [2019-11-20 01:46:55,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6149 to 6109. [2019-11-20 01:46:55,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6109 states. [2019-11-20 01:46:55,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6109 states to 6109 states and 7791 transitions. [2019-11-20 01:46:55,561 INFO L78 Accepts]: Start accepts. Automaton has 6109 states and 7791 transitions. Word has length 133 [2019-11-20 01:46:55,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:55,561 INFO L462 AbstractCegarLoop]: Abstraction has 6109 states and 7791 transitions. [2019-11-20 01:46:55,561 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:55,561 INFO L276 IsEmpty]: Start isEmpty. Operand 6109 states and 7791 transitions. [2019-11-20 01:46:55,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-20 01:46:55,564 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:55,564 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:55,564 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:55,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:55,564 INFO L82 PathProgramCache]: Analyzing trace with hash 1797709215, now seen corresponding path program 1 times [2019-11-20 01:46:55,565 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:55,565 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124108455] [2019-11-20 01:46:55,565 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:55,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:55,604 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-20 01:46:55,605 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [124108455] [2019-11-20 01:46:55,605 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:55,605 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:55,605 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7949745] [2019-11-20 01:46:55,606 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:55,606 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:55,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:55,606 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:55,606 INFO L87 Difference]: Start difference. First operand 6109 states and 7791 transitions. Second operand 3 states. [2019-11-20 01:46:55,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:55,953 INFO L93 Difference]: Finished difference Result 11855 states and 15104 transitions. [2019-11-20 01:46:55,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:55,953 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 133 [2019-11-20 01:46:55,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:55,960 INFO L225 Difference]: With dead ends: 11855 [2019-11-20 01:46:55,960 INFO L226 Difference]: Without dead ends: 6118 [2019-11-20 01:46:55,965 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:55,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6118 states. [2019-11-20 01:46:56,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6118 to 6078. [2019-11-20 01:46:56,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6078 states. [2019-11-20 01:46:56,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6078 states to 6078 states and 7719 transitions. [2019-11-20 01:46:56,304 INFO L78 Accepts]: Start accepts. Automaton has 6078 states and 7719 transitions. Word has length 133 [2019-11-20 01:46:56,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:56,305 INFO L462 AbstractCegarLoop]: Abstraction has 6078 states and 7719 transitions. [2019-11-20 01:46:56,305 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:56,305 INFO L276 IsEmpty]: Start isEmpty. Operand 6078 states and 7719 transitions. [2019-11-20 01:46:56,310 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-20 01:46:56,310 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:56,311 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:56,311 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:56,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:56,311 INFO L82 PathProgramCache]: Analyzing trace with hash 282610594, now seen corresponding path program 1 times [2019-11-20 01:46:56,312 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:56,312 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [491844583] [2019-11-20 01:46:56,312 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:56,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:56,354 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-20 01:46:56,355 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [491844583] [2019-11-20 01:46:56,355 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:56,355 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:56,355 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494134586] [2019-11-20 01:46:56,356 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:56,356 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:56,356 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:56,357 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:56,357 INFO L87 Difference]: Start difference. First operand 6078 states and 7719 transitions. Second operand 3 states. [2019-11-20 01:46:56,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:56,638 INFO L93 Difference]: Finished difference Result 10860 states and 13837 transitions. [2019-11-20 01:46:56,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:56,639 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 136 [2019-11-20 01:46:56,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:56,644 INFO L225 Difference]: With dead ends: 10860 [2019-11-20 01:46:56,644 INFO L226 Difference]: Without dead ends: 5146 [2019-11-20 01:46:56,648 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:56,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5146 states. [2019-11-20 01:46:56,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5146 to 5076. [2019-11-20 01:46:56,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5076 states. [2019-11-20 01:46:56,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5076 states to 5076 states and 6341 transitions. [2019-11-20 01:46:56,863 INFO L78 Accepts]: Start accepts. Automaton has 5076 states and 6341 transitions. Word has length 136 [2019-11-20 01:46:56,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:56,864 INFO L462 AbstractCegarLoop]: Abstraction has 5076 states and 6341 transitions. [2019-11-20 01:46:56,864 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:56,864 INFO L276 IsEmpty]: Start isEmpty. Operand 5076 states and 6341 transitions. [2019-11-20 01:46:56,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-20 01:46:56,866 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:56,867 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:56,867 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:56,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:56,867 INFO L82 PathProgramCache]: Analyzing trace with hash -1519116211, now seen corresponding path program 1 times [2019-11-20 01:46:56,867 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:56,868 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707887143] [2019-11-20 01:46:56,868 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:56,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:56,908 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2019-11-20 01:46:56,908 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707887143] [2019-11-20 01:46:56,909 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:56,909 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:56,910 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495093307] [2019-11-20 01:46:56,911 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:56,911 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:56,911 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:56,911 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:56,912 INFO L87 Difference]: Start difference. First operand 5076 states and 6341 transitions. Second operand 3 states. [2019-11-20 01:46:57,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:57,094 INFO L93 Difference]: Finished difference Result 9133 states and 11446 transitions. [2019-11-20 01:46:57,094 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:57,094 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 136 [2019-11-20 01:46:57,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:57,098 INFO L225 Difference]: With dead ends: 9133 [2019-11-20 01:46:57,098 INFO L226 Difference]: Without dead ends: 4098 [2019-11-20 01:46:57,102 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:57,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4098 states. [2019-11-20 01:46:57,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4098 to 4080. [2019-11-20 01:46:57,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4080 states. [2019-11-20 01:46:57,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4080 states to 4080 states and 5008 transitions. [2019-11-20 01:46:57,265 INFO L78 Accepts]: Start accepts. Automaton has 4080 states and 5008 transitions. Word has length 136 [2019-11-20 01:46:57,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:57,265 INFO L462 AbstractCegarLoop]: Abstraction has 4080 states and 5008 transitions. [2019-11-20 01:46:57,265 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:57,265 INFO L276 IsEmpty]: Start isEmpty. Operand 4080 states and 5008 transitions. [2019-11-20 01:46:57,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2019-11-20 01:46:57,268 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:57,268 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:57,269 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:57,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:57,269 INFO L82 PathProgramCache]: Analyzing trace with hash -1856914244, now seen corresponding path program 1 times [2019-11-20 01:46:57,269 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:57,269 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256975817] [2019-11-20 01:46:57,270 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:57,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:57,327 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 75 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-11-20 01:46:57,328 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256975817] [2019-11-20 01:46:57,328 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:57,328 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:57,328 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016747792] [2019-11-20 01:46:57,329 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:57,329 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:57,329 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:57,329 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:57,329 INFO L87 Difference]: Start difference. First operand 4080 states and 5008 transitions. Second operand 3 states. [2019-11-20 01:46:57,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:57,527 INFO L93 Difference]: Finished difference Result 7575 states and 9357 transitions. [2019-11-20 01:46:57,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:57,528 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 169 [2019-11-20 01:46:57,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:57,532 INFO L225 Difference]: With dead ends: 7575 [2019-11-20 01:46:57,532 INFO L226 Difference]: Without dead ends: 3771 [2019-11-20 01:46:57,535 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:57,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3771 states. [2019-11-20 01:46:57,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3771 to 3560. [2019-11-20 01:46:57,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3560 states. [2019-11-20 01:46:57,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3560 states to 3560 states and 4335 transitions. [2019-11-20 01:46:57,695 INFO L78 Accepts]: Start accepts. Automaton has 3560 states and 4335 transitions. Word has length 169 [2019-11-20 01:46:57,697 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:57,697 INFO L462 AbstractCegarLoop]: Abstraction has 3560 states and 4335 transitions. [2019-11-20 01:46:57,697 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:57,697 INFO L276 IsEmpty]: Start isEmpty. Operand 3560 states and 4335 transitions. [2019-11-20 01:46:57,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-11-20 01:46:57,699 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:57,700 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:57,700 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:57,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:57,701 INFO L82 PathProgramCache]: Analyzing trace with hash 38014472, now seen corresponding path program 1 times [2019-11-20 01:46:57,701 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:57,701 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1640659372] [2019-11-20 01:46:57,701 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:57,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:57,748 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-20 01:46:57,748 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1640659372] [2019-11-20 01:46:57,748 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:57,748 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:57,749 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077210208] [2019-11-20 01:46:57,749 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:57,749 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:57,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:57,750 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:57,750 INFO L87 Difference]: Start difference. First operand 3560 states and 4335 transitions. Second operand 3 states. [2019-11-20 01:46:57,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:57,993 INFO L93 Difference]: Finished difference Result 8918 states and 10901 transitions. [2019-11-20 01:46:57,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:57,994 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2019-11-20 01:46:57,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:57,999 INFO L225 Difference]: With dead ends: 8918 [2019-11-20 01:46:58,000 INFO L226 Difference]: Without dead ends: 5634 [2019-11-20 01:46:58,003 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:58,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5634 states. [2019-11-20 01:46:58,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5634 to 5414. [2019-11-20 01:46:58,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5414 states. [2019-11-20 01:46:58,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5414 states to 5414 states and 6513 transitions. [2019-11-20 01:46:58,242 INFO L78 Accepts]: Start accepts. Automaton has 5414 states and 6513 transitions. Word has length 176 [2019-11-20 01:46:58,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:58,242 INFO L462 AbstractCegarLoop]: Abstraction has 5414 states and 6513 transitions. [2019-11-20 01:46:58,242 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:58,242 INFO L276 IsEmpty]: Start isEmpty. Operand 5414 states and 6513 transitions. [2019-11-20 01:46:58,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-20 01:46:58,246 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:58,247 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:58,247 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:58,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:58,247 INFO L82 PathProgramCache]: Analyzing trace with hash -1974043446, now seen corresponding path program 1 times [2019-11-20 01:46:58,248 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:58,248 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824676837] [2019-11-20 01:46:58,248 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:58,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:58,290 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 79 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2019-11-20 01:46:58,290 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824676837] [2019-11-20 01:46:58,291 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:58,291 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:58,291 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333983870] [2019-11-20 01:46:58,291 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:58,291 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:58,292 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:58,292 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:58,292 INFO L87 Difference]: Start difference. First operand 5414 states and 6513 transitions. Second operand 3 states. [2019-11-20 01:46:58,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:58,458 INFO L93 Difference]: Finished difference Result 8838 states and 10694 transitions. [2019-11-20 01:46:58,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:58,459 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 179 [2019-11-20 01:46:58,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:58,461 INFO L225 Difference]: With dead ends: 8838 [2019-11-20 01:46:58,462 INFO L226 Difference]: Without dead ends: 3700 [2019-11-20 01:46:58,464 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:58,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3700 states. [2019-11-20 01:46:58,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3700 to 3094. [2019-11-20 01:46:58,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3094 states. [2019-11-20 01:46:58,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3094 states to 3094 states and 3684 transitions. [2019-11-20 01:46:58,567 INFO L78 Accepts]: Start accepts. Automaton has 3094 states and 3684 transitions. Word has length 179 [2019-11-20 01:46:58,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:58,568 INFO L462 AbstractCegarLoop]: Abstraction has 3094 states and 3684 transitions. [2019-11-20 01:46:58,568 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:58,568 INFO L276 IsEmpty]: Start isEmpty. Operand 3094 states and 3684 transitions. [2019-11-20 01:46:58,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-20 01:46:58,570 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:58,570 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:58,570 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:58,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:58,571 INFO L82 PathProgramCache]: Analyzing trace with hash -831540980, now seen corresponding path program 1 times [2019-11-20 01:46:58,571 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:58,571 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [656686587] [2019-11-20 01:46:58,571 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:58,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:58,624 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 91 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-20 01:46:58,625 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [656686587] [2019-11-20 01:46:58,625 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:58,625 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-20 01:46:58,625 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2078904347] [2019-11-20 01:46:58,626 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-20 01:46:58,626 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:58,626 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-20 01:46:58,626 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-20 01:46:58,627 INFO L87 Difference]: Start difference. First operand 3094 states and 3684 transitions. Second operand 4 states. [2019-11-20 01:46:58,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:58,778 INFO L93 Difference]: Finished difference Result 4689 states and 5567 transitions. [2019-11-20 01:46:58,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-20 01:46:58,779 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 179 [2019-11-20 01:46:58,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:58,781 INFO L225 Difference]: With dead ends: 4689 [2019-11-20 01:46:58,781 INFO L226 Difference]: Without dead ends: 1871 [2019-11-20 01:46:58,783 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:46:58,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1871 states. [2019-11-20 01:46:58,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1871 to 1584. [2019-11-20 01:46:58,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1584 states. [2019-11-20 01:46:58,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1584 states to 1584 states and 1844 transitions. [2019-11-20 01:46:58,847 INFO L78 Accepts]: Start accepts. Automaton has 1584 states and 1844 transitions. Word has length 179 [2019-11-20 01:46:58,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:58,847 INFO L462 AbstractCegarLoop]: Abstraction has 1584 states and 1844 transitions. [2019-11-20 01:46:58,847 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-20 01:46:58,847 INFO L276 IsEmpty]: Start isEmpty. Operand 1584 states and 1844 transitions. [2019-11-20 01:46:58,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2019-11-20 01:46:58,848 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:58,848 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:58,848 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:58,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:58,849 INFO L82 PathProgramCache]: Analyzing trace with hash 1681635082, now seen corresponding path program 1 times [2019-11-20 01:46:58,849 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:58,849 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396031912] [2019-11-20 01:46:58,849 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:58,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:58,899 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-20 01:46:58,899 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396031912] [2019-11-20 01:46:58,900 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:58,900 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:58,900 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657048605] [2019-11-20 01:46:58,900 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:58,901 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:58,901 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:58,901 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:58,901 INFO L87 Difference]: Start difference. First operand 1584 states and 1844 transitions. Second operand 3 states. [2019-11-20 01:46:59,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:59,031 INFO L93 Difference]: Finished difference Result 4040 states and 4732 transitions. [2019-11-20 01:46:59,031 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:59,031 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 183 [2019-11-20 01:46:59,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:59,033 INFO L225 Difference]: With dead ends: 4040 [2019-11-20 01:46:59,033 INFO L226 Difference]: Without dead ends: 2426 [2019-11-20 01:46:59,034 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:59,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2426 states. [2019-11-20 01:46:59,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2426 to 2416. [2019-11-20 01:46:59,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2416 states. [2019-11-20 01:46:59,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2416 states to 2416 states and 2812 transitions. [2019-11-20 01:46:59,114 INFO L78 Accepts]: Start accepts. Automaton has 2416 states and 2812 transitions. Word has length 183 [2019-11-20 01:46:59,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:59,114 INFO L462 AbstractCegarLoop]: Abstraction has 2416 states and 2812 transitions. [2019-11-20 01:46:59,114 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:59,114 INFO L276 IsEmpty]: Start isEmpty. Operand 2416 states and 2812 transitions. [2019-11-20 01:46:59,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2019-11-20 01:46:59,115 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:59,116 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:59,116 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:59,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:59,116 INFO L82 PathProgramCache]: Analyzing trace with hash 1256160142, now seen corresponding path program 1 times [2019-11-20 01:46:59,116 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:59,116 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827041188] [2019-11-20 01:46:59,116 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:59,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:46:59,201 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 93 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-20 01:46:59,202 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827041188] [2019-11-20 01:46:59,202 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:46:59,202 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:46:59,202 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319956538] [2019-11-20 01:46:59,203 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:46:59,203 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:46:59,203 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:46:59,203 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:59,203 INFO L87 Difference]: Start difference. First operand 2416 states and 2812 transitions. Second operand 3 states. [2019-11-20 01:46:59,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:46:59,297 INFO L93 Difference]: Finished difference Result 3364 states and 3884 transitions. [2019-11-20 01:46:59,298 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:46:59,298 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 183 [2019-11-20 01:46:59,298 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:46:59,299 INFO L225 Difference]: With dead ends: 3364 [2019-11-20 01:46:59,299 INFO L226 Difference]: Without dead ends: 1214 [2019-11-20 01:46:59,301 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:46:59,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states. [2019-11-20 01:46:59,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1192. [2019-11-20 01:46:59,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1192 states. [2019-11-20 01:46:59,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1192 states to 1192 states and 1317 transitions. [2019-11-20 01:46:59,362 INFO L78 Accepts]: Start accepts. Automaton has 1192 states and 1317 transitions. Word has length 183 [2019-11-20 01:46:59,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:46:59,363 INFO L462 AbstractCegarLoop]: Abstraction has 1192 states and 1317 transitions. [2019-11-20 01:46:59,363 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:46:59,363 INFO L276 IsEmpty]: Start isEmpty. Operand 1192 states and 1317 transitions. [2019-11-20 01:46:59,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-11-20 01:46:59,364 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:46:59,365 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:46:59,365 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:46:59,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:46:59,365 INFO L82 PathProgramCache]: Analyzing trace with hash 1772258692, now seen corresponding path program 1 times [2019-11-20 01:46:59,366 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:46:59,366 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414291270] [2019-11-20 01:46:59,366 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:46:59,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 01:46:59,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 01:46:59,481 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 01:46:59,481 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-20 01:46:59,670 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 20.11 01:46:59 BoogieIcfgContainer [2019-11-20 01:46:59,670 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-20 01:46:59,670 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-20 01:46:59,671 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-20 01:46:59,671 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-20 01:46:59,671 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 01:46:38" (3/4) ... [2019-11-20 01:46:59,673 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-20 01:46:59,896 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_def62e31-1599-41f8-8b19-233b38eb20ca/bin/uautomizer/witness.graphml [2019-11-20 01:46:59,896 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-20 01:46:59,899 INFO L168 Benchmark]: Toolchain (without parser) took 22620.66 ms. Allocated memory was 1.0 GB in the beginning and 3.6 GB in the end (delta: 2.6 GB). Free memory was 951.5 MB in the beginning and 3.1 GB in the end (delta: -2.1 GB). Peak memory consumption was 441.7 MB. Max. memory is 11.5 GB. [2019-11-20 01:46:59,899 INFO L168 Benchmark]: CDTParser took 0.24 ms. Allocated memory is still 1.0 GB. Free memory is still 967.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 01:46:59,899 INFO L168 Benchmark]: CACSL2BoogieTranslator took 486.69 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 120.1 MB). Free memory was 951.5 MB in the beginning and 1.1 GB in the end (delta: -158.8 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. [2019-11-20 01:46:59,900 INFO L168 Benchmark]: Boogie Procedure Inliner took 49.92 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.3 MB). Peak memory consumption was 7.3 MB. Max. memory is 11.5 GB. [2019-11-20 01:46:59,900 INFO L168 Benchmark]: Boogie Preprocessor took 51.46 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 01:46:59,900 INFO L168 Benchmark]: RCFGBuilder took 745.39 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 46.7 MB). Peak memory consumption was 46.7 MB. Max. memory is 11.5 GB. [2019-11-20 01:46:59,901 INFO L168 Benchmark]: TraceAbstraction took 21056.80 ms. Allocated memory was 1.1 GB in the beginning and 3.6 GB in the end (delta: 2.5 GB). Free memory was 1.1 GB in the beginning and 3.2 GB in the end (delta: -2.1 GB). Peak memory consumption was 353.5 MB. Max. memory is 11.5 GB. [2019-11-20 01:46:59,901 INFO L168 Benchmark]: Witness Printer took 226.21 ms. Allocated memory is still 3.6 GB. Free memory was 3.2 GB in the beginning and 3.1 GB in the end (delta: 73.1 MB). Peak memory consumption was 73.1 MB. Max. memory is 11.5 GB. [2019-11-20 01:46:59,903 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24 ms. Allocated memory is still 1.0 GB. Free memory is still 967.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 486.69 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 120.1 MB). Free memory was 951.5 MB in the beginning and 1.1 GB in the end (delta: -158.8 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 49.92 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.3 MB). Peak memory consumption was 7.3 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 51.46 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 745.39 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 46.7 MB). Peak memory consumption was 46.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 21056.80 ms. Allocated memory was 1.1 GB in the beginning and 3.6 GB in the end (delta: 2.5 GB). Free memory was 1.1 GB in the beginning and 3.2 GB in the end (delta: -2.1 GB). Peak memory consumption was 353.5 MB. Max. memory is 11.5 GB. * Witness Printer took 226.21 ms. Allocated memory is still 3.6 GB. Free memory was 3.2 GB in the beginning and 3.1 GB in the end (delta: 73.1 MB). Peak memory consumption was 73.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L679] int __retres1 ; [L683] e_wl = 2 [L684] e_c = e_wl [L685] e_g = e_c [L686] e_f = e_g [L687] e_e = e_f [L688] wl_pc = 0 [L689] c1_pc = 0 [L690] c2_pc = 0 [L691] wb_pc = 0 [L692] wb_i = 1 [L693] c2_i = wb_i [L694] c1_i = c2_i [L695] wl_i = c1_i [L696] r_i = 0 [L697] c_req_up = 0 [L698] d = 0 [L699] c = 0 [L390] int kernel_st ; [L393] kernel_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L394] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L405] COND TRUE (int )wl_i == 1 [L406] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L410] COND TRUE (int )c1_i == 1 [L411] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L415] COND TRUE (int )c2_i == 1 [L416] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L420] COND TRUE (int )wb_i == 1 [L421] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L425] COND FALSE !((int )r_i == 1) [L428] r_st = 2 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L430] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L435] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L440] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L445] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L450] COND FALSE !((int )e_wl == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L455] COND FALSE !((int )wl_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L463] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L473] COND FALSE !((int )c1_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L482] COND FALSE !((int )c2_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L491] COND FALSE !((int )wb_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L500] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L505] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L510] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L515] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L520] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L525] COND FALSE !((int )e_wl == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L531] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L127] COND TRUE (int )c1_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L138] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L172] COND TRUE (int )c2_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L183] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L217] COND TRUE (int )wb_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L228] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L537] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L538] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 3 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L565] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L570] COND TRUE (int )e_wl == 0 [L571] e_wl = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L575] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L576] COND TRUE (int )e_wl == 1 [L577] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L593] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L594] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L602] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L603] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L611] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L612] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L620] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L625] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L630] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L635] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L640] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L645] COND TRUE (int )e_wl == 1 [L646] e_wl = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L650] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L531] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L127] COND FALSE !((int )c1_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L130] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L145] COND TRUE ! processed [L146] data += 1 [L147] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L148] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L149] COND TRUE (int )e_g == 1 [L150] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L157] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L138] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L172] COND FALSE !((int )c2_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L175] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L190] COND TRUE ! processed [L191] data += 1 [L192] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L193] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L194] COND TRUE (int )e_g == 1 [L195] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L183] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L217] COND FALSE !((int )wb_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L220] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L235] c_t = data [L236] c_req_up = 1 [L237] processed = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L228] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L537] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L538] COND TRUE (int )c_req_up == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L539] COND TRUE c != c_t [L540] c = c_t [L541] e_c = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L545] c_req_up = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 3 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L565] COND TRUE (int )e_c == 0 [L566] e_c = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L570] COND FALSE !((int )e_wl == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L575] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L583] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L584] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L593] COND TRUE (int )c1_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L594] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L602] COND TRUE (int )c2_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L603] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L611] COND TRUE (int )wb_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L612] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L620] COND TRUE (int )e_c == 1 [L621] r_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L625] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L630] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L635] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L640] COND TRUE (int )e_c == 1 [L641] e_c = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L645] COND FALSE !((int )e_wl == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L650] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L653] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L656] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L659] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L531] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L337] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L352] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND TRUE (int )r_st == 0 [L369] tmp___3 = __VERIFIER_nondet_int() [L371] COND TRUE \read(tmp___3) [L373] r_st = 1 [L249] d = c [L250] e_e = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L251] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L259] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L260] COND TRUE (int )e_e == 1 [L261] wl_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L269] e_e = 2 [L270] r_st = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L284] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 125 locations, 1 error locations. Result: UNSAFE, OverallTime: 20.9s, OverallIterations: 37, TraceHistogramMax: 6, AutomataDifference: 9.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 7566 SDtfs, 5932 SDslu, 4273 SDs, 0 SdLazy, 705 SolverSat, 210 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 128 GetRequests, 76 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=16725occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 8.6s AutomataMinimizationTime, 36 MinimizatonAttempts, 9031 StatesRemovedByMinimization, 30 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.9s InterpolantComputationTime, 3325 NumberOfCodeBlocks, 3325 NumberOfCodeBlocksAsserted, 37 NumberOfCheckSat, 3105 ConstructedInterpolants, 0 QuantifiedInterpolants, 546256 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 36 InterpolantComputations, 36 PerfectInterpolantSequences, 1082/1082 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...