./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 678e0110 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 447c919af4e106e36f468570351956f4c77293d2 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-678e011 [2019-11-20 04:42:12,065 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-20 04:42:12,067 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-20 04:42:12,077 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-20 04:42:12,077 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-20 04:42:12,078 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-20 04:42:12,080 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-20 04:42:12,082 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-20 04:42:12,084 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-20 04:42:12,085 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-20 04:42:12,086 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-20 04:42:12,087 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-20 04:42:12,088 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-20 04:42:12,095 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-20 04:42:12,096 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-20 04:42:12,097 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-20 04:42:12,098 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-20 04:42:12,099 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-20 04:42:12,101 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-20 04:42:12,103 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-20 04:42:12,108 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-20 04:42:12,111 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-20 04:42:12,119 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-20 04:42:12,120 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-20 04:42:12,126 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-20 04:42:12,127 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-20 04:42:12,127 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-20 04:42:12,129 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-20 04:42:12,130 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-20 04:42:12,132 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-20 04:42:12,132 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-20 04:42:12,133 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-20 04:42:12,134 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-20 04:42:12,135 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-20 04:42:12,138 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-20 04:42:12,138 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-20 04:42:12,139 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-20 04:42:12,139 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-20 04:42:12,139 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-20 04:42:12,141 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-20 04:42:12,142 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-20 04:42:12,143 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-20 04:42:12,163 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-20 04:42:12,163 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-20 04:42:12,164 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-20 04:42:12,164 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-20 04:42:12,165 INFO L138 SettingsManager]: * Use SBE=true [2019-11-20 04:42:12,165 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-20 04:42:12,166 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-20 04:42:12,166 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-20 04:42:12,166 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-20 04:42:12,166 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-20 04:42:12,167 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-20 04:42:12,167 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-20 04:42:12,168 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-20 04:42:12,168 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-20 04:42:12,168 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-20 04:42:12,168 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-20 04:42:12,169 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-20 04:42:12,169 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-20 04:42:12,169 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-20 04:42:12,169 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-20 04:42:12,169 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-20 04:42:12,170 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 04:42:12,170 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-20 04:42:12,170 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-20 04:42:12,170 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-20 04:42:12,171 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-20 04:42:12,171 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-20 04:42:12,171 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-20 04:42:12,171 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 447c919af4e106e36f468570351956f4c77293d2 [2019-11-20 04:42:12,368 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-20 04:42:12,381 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-20 04:42:12,384 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-20 04:42:12,386 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-20 04:42:12,387 INFO L275 PluginConnector]: CDTParser initialized [2019-11-20 04:42:12,387 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-11-20 04:42:12,453 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/data/7ec375a28/7dafd051d26148bcb0668dcfa33f77b9/FLAG8e31ad39d [2019-11-20 04:42:12,927 INFO L306 CDTParser]: Found 1 translation units. [2019-11-20 04:42:12,937 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-11-20 04:42:12,954 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/data/7ec375a28/7dafd051d26148bcb0668dcfa33f77b9/FLAG8e31ad39d [2019-11-20 04:42:13,285 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/data/7ec375a28/7dafd051d26148bcb0668dcfa33f77b9 [2019-11-20 04:42:13,287 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-20 04:42:13,289 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-20 04:42:13,290 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-20 04:42:13,290 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-20 04:42:13,294 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-20 04:42:13,295 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 04:42:13" (1/1) ... [2019-11-20 04:42:13,297 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1dad0900 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13, skipping insertion in model container [2019-11-20 04:42:13,297 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 04:42:13" (1/1) ... [2019-11-20 04:42:13,304 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-20 04:42:13,353 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-20 04:42:13,716 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 04:42:13,723 INFO L188 MainTranslator]: Completed pre-run [2019-11-20 04:42:13,782 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 04:42:13,805 INFO L192 MainTranslator]: Completed translation [2019-11-20 04:42:13,806 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13 WrapperNode [2019-11-20 04:42:13,806 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-20 04:42:13,807 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-20 04:42:13,807 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-20 04:42:13,807 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-20 04:42:13,814 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13" (1/1) ... [2019-11-20 04:42:13,822 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13" (1/1) ... [2019-11-20 04:42:13,869 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-20 04:42:13,869 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-20 04:42:13,870 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-20 04:42:13,870 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-20 04:42:13,880 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13" (1/1) ... [2019-11-20 04:42:13,881 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13" (1/1) ... [2019-11-20 04:42:13,887 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13" (1/1) ... [2019-11-20 04:42:13,887 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13" (1/1) ... [2019-11-20 04:42:13,900 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13" (1/1) ... [2019-11-20 04:42:13,916 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13" (1/1) ... [2019-11-20 04:42:13,921 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13" (1/1) ... [2019-11-20 04:42:13,929 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-20 04:42:13,930 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-20 04:42:13,930 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-20 04:42:13,931 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-20 04:42:13,932 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 04:42:14,012 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-20 04:42:14,013 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-20 04:42:15,088 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-20 04:42:15,088 INFO L285 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-20 04:42:15,089 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 04:42:15 BoogieIcfgContainer [2019-11-20 04:42:15,089 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-20 04:42:15,090 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-20 04:42:15,090 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-20 04:42:15,094 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-20 04:42:15,094 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.11 04:42:13" (1/3) ... [2019-11-20 04:42:15,095 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ab880c3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 04:42:15, skipping insertion in model container [2019-11-20 04:42:15,095 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 04:42:13" (2/3) ... [2019-11-20 04:42:15,096 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ab880c3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 04:42:15, skipping insertion in model container [2019-11-20 04:42:15,096 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 04:42:15" (3/3) ... [2019-11-20 04:42:15,097 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.03.cil.c [2019-11-20 04:42:15,107 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-20 04:42:15,114 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-20 04:42:15,126 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-20 04:42:15,163 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-20 04:42:15,164 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-20 04:42:15,164 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-20 04:42:15,164 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-20 04:42:15,164 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-20 04:42:15,165 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-20 04:42:15,165 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-20 04:42:15,165 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-20 04:42:15,186 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states. [2019-11-20 04:42:15,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-20 04:42:15,195 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:15,196 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:15,196 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:15,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:15,201 INFO L82 PathProgramCache]: Analyzing trace with hash -1838342379, now seen corresponding path program 1 times [2019-11-20 04:42:15,209 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:15,209 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359963377] [2019-11-20 04:42:15,209 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:15,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:15,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:15,367 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359963377] [2019-11-20 04:42:15,368 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:15,369 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:15,370 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883880031] [2019-11-20 04:42:15,375 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:15,375 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:15,389 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:15,390 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:15,393 INFO L87 Difference]: Start difference. First operand 276 states. Second operand 3 states. [2019-11-20 04:42:15,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:15,471 INFO L93 Difference]: Finished difference Result 547 states and 857 transitions. [2019-11-20 04:42:15,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:15,473 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-20 04:42:15,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:15,488 INFO L225 Difference]: With dead ends: 547 [2019-11-20 04:42:15,488 INFO L226 Difference]: Without dead ends: 272 [2019-11-20 04:42:15,493 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:15,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2019-11-20 04:42:15,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 272. [2019-11-20 04:42:15,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 272 states. [2019-11-20 04:42:15,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 272 states to 272 states and 412 transitions. [2019-11-20 04:42:15,564 INFO L78 Accepts]: Start accepts. Automaton has 272 states and 412 transitions. Word has length 61 [2019-11-20 04:42:15,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:15,564 INFO L462 AbstractCegarLoop]: Abstraction has 272 states and 412 transitions. [2019-11-20 04:42:15,564 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:15,564 INFO L276 IsEmpty]: Start isEmpty. Operand 272 states and 412 transitions. [2019-11-20 04:42:15,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-20 04:42:15,567 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:15,567 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:15,568 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:15,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:15,568 INFO L82 PathProgramCache]: Analyzing trace with hash 1195707667, now seen corresponding path program 1 times [2019-11-20 04:42:15,568 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:15,569 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566913693] [2019-11-20 04:42:15,569 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:15,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:15,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:15,626 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [566913693] [2019-11-20 04:42:15,627 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:15,627 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 04:42:15,627 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [205412587] [2019-11-20 04:42:15,629 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:15,629 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:15,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:15,630 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:15,630 INFO L87 Difference]: Start difference. First operand 272 states and 412 transitions. Second operand 3 states. [2019-11-20 04:42:15,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:15,780 INFO L93 Difference]: Finished difference Result 730 states and 1104 transitions. [2019-11-20 04:42:15,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:15,781 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-20 04:42:15,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:15,787 INFO L225 Difference]: With dead ends: 730 [2019-11-20 04:42:15,787 INFO L226 Difference]: Without dead ends: 466 [2019-11-20 04:42:15,789 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:15,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states. [2019-11-20 04:42:15,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 464. [2019-11-20 04:42:15,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-20 04:42:15,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 694 transitions. [2019-11-20 04:42:15,872 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 694 transitions. Word has length 61 [2019-11-20 04:42:15,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:15,873 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 694 transitions. [2019-11-20 04:42:15,873 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:15,873 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 694 transitions. [2019-11-20 04:42:15,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-20 04:42:15,876 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:15,876 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:15,876 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:15,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:15,877 INFO L82 PathProgramCache]: Analyzing trace with hash 266288339, now seen corresponding path program 1 times [2019-11-20 04:42:15,877 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:15,877 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297100262] [2019-11-20 04:42:15,877 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:15,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:15,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:15,935 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297100262] [2019-11-20 04:42:15,935 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:15,935 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 04:42:15,935 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673223528] [2019-11-20 04:42:15,936 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:15,936 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:15,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:15,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:15,937 INFO L87 Difference]: Start difference. First operand 464 states and 694 transitions. Second operand 3 states. [2019-11-20 04:42:15,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:15,973 INFO L93 Difference]: Finished difference Result 919 states and 1375 transitions. [2019-11-20 04:42:15,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:15,973 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-20 04:42:15,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:15,977 INFO L225 Difference]: With dead ends: 919 [2019-11-20 04:42:15,977 INFO L226 Difference]: Without dead ends: 464 [2019-11-20 04:42:15,978 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:15,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-20 04:42:16,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-20 04:42:16,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-20 04:42:16,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 686 transitions. [2019-11-20 04:42:16,005 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 686 transitions. Word has length 61 [2019-11-20 04:42:16,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:16,005 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 686 transitions. [2019-11-20 04:42:16,005 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:16,005 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 686 transitions. [2019-11-20 04:42:16,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-20 04:42:16,007 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:16,007 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:16,007 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:16,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:16,008 INFO L82 PathProgramCache]: Analyzing trace with hash 710189013, now seen corresponding path program 1 times [2019-11-20 04:42:16,008 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:16,008 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995067745] [2019-11-20 04:42:16,009 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:16,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:16,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:16,053 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [995067745] [2019-11-20 04:42:16,053 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:16,053 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 04:42:16,054 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1316626247] [2019-11-20 04:42:16,054 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:16,054 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:16,055 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:16,055 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:16,055 INFO L87 Difference]: Start difference. First operand 464 states and 686 transitions. Second operand 3 states. [2019-11-20 04:42:16,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:16,094 INFO L93 Difference]: Finished difference Result 918 states and 1358 transitions. [2019-11-20 04:42:16,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:16,095 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-20 04:42:16,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:16,098 INFO L225 Difference]: With dead ends: 918 [2019-11-20 04:42:16,099 INFO L226 Difference]: Without dead ends: 464 [2019-11-20 04:42:16,100 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:16,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-20 04:42:16,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-20 04:42:16,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-20 04:42:16,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 678 transitions. [2019-11-20 04:42:16,132 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 678 transitions. Word has length 61 [2019-11-20 04:42:16,134 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:16,134 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 678 transitions. [2019-11-20 04:42:16,134 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:16,134 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 678 transitions. [2019-11-20 04:42:16,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-20 04:42:16,136 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:16,136 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:16,136 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:16,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:16,137 INFO L82 PathProgramCache]: Analyzing trace with hash -1623736427, now seen corresponding path program 1 times [2019-11-20 04:42:16,138 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:16,138 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365859446] [2019-11-20 04:42:16,138 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:16,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:16,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:16,210 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365859446] [2019-11-20 04:42:16,210 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:16,210 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 04:42:16,210 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [376387206] [2019-11-20 04:42:16,211 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:16,211 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:16,211 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:16,212 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:16,212 INFO L87 Difference]: Start difference. First operand 464 states and 678 transitions. Second operand 3 states. [2019-11-20 04:42:16,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:16,264 INFO L93 Difference]: Finished difference Result 917 states and 1341 transitions. [2019-11-20 04:42:16,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:16,265 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-20 04:42:16,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:16,268 INFO L225 Difference]: With dead ends: 917 [2019-11-20 04:42:16,269 INFO L226 Difference]: Without dead ends: 464 [2019-11-20 04:42:16,271 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:16,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-20 04:42:16,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-20 04:42:16,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-20 04:42:16,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 670 transitions. [2019-11-20 04:42:16,301 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 670 transitions. Word has length 61 [2019-11-20 04:42:16,301 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:16,301 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 670 transitions. [2019-11-20 04:42:16,301 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:16,301 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 670 transitions. [2019-11-20 04:42:16,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-20 04:42:16,303 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:16,303 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:16,304 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:16,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:16,304 INFO L82 PathProgramCache]: Analyzing trace with hash -175003691, now seen corresponding path program 1 times [2019-11-20 04:42:16,305 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:16,305 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59060146] [2019-11-20 04:42:16,305 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:16,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:16,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:16,358 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [59060146] [2019-11-20 04:42:16,358 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:16,359 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 04:42:16,359 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665884307] [2019-11-20 04:42:16,359 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:16,360 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:16,360 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:16,360 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:16,361 INFO L87 Difference]: Start difference. First operand 464 states and 670 transitions. Second operand 3 states. [2019-11-20 04:42:16,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:16,427 INFO L93 Difference]: Finished difference Result 916 states and 1324 transitions. [2019-11-20 04:42:16,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:16,428 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-20 04:42:16,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:16,431 INFO L225 Difference]: With dead ends: 916 [2019-11-20 04:42:16,432 INFO L226 Difference]: Without dead ends: 464 [2019-11-20 04:42:16,433 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:16,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-20 04:42:16,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-20 04:42:16,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-20 04:42:16,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 654 transitions. [2019-11-20 04:42:16,461 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 654 transitions. Word has length 61 [2019-11-20 04:42:16,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:16,463 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 654 transitions. [2019-11-20 04:42:16,463 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:16,463 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 654 transitions. [2019-11-20 04:42:16,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-20 04:42:16,466 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:16,466 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:16,467 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:16,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:16,472 INFO L82 PathProgramCache]: Analyzing trace with hash -1945036492, now seen corresponding path program 1 times [2019-11-20 04:42:16,473 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:16,473 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [710774384] [2019-11-20 04:42:16,473 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:16,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:16,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:16,517 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [710774384] [2019-11-20 04:42:16,517 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:16,518 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 04:42:16,518 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1745745179] [2019-11-20 04:42:16,518 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:16,519 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:16,519 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:16,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:16,519 INFO L87 Difference]: Start difference. First operand 464 states and 654 transitions. Second operand 3 states. [2019-11-20 04:42:16,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:16,605 INFO L93 Difference]: Finished difference Result 914 states and 1289 transitions. [2019-11-20 04:42:16,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:16,607 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-20 04:42:16,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:16,610 INFO L225 Difference]: With dead ends: 914 [2019-11-20 04:42:16,612 INFO L226 Difference]: Without dead ends: 464 [2019-11-20 04:42:16,613 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:16,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-20 04:42:16,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-20 04:42:16,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-20 04:42:16,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 638 transitions. [2019-11-20 04:42:16,639 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 638 transitions. Word has length 61 [2019-11-20 04:42:16,640 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:16,640 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 638 transitions. [2019-11-20 04:42:16,640 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:16,640 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 638 transitions. [2019-11-20 04:42:16,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-20 04:42:16,641 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:16,642 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:16,642 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:16,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:16,642 INFO L82 PathProgramCache]: Analyzing trace with hash -1902661357, now seen corresponding path program 1 times [2019-11-20 04:42:16,643 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:16,643 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510498921] [2019-11-20 04:42:16,643 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:16,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:16,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:16,745 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510498921] [2019-11-20 04:42:16,746 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:16,746 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 04:42:16,747 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597063530] [2019-11-20 04:42:16,747 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:16,748 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:16,748 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:16,748 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:16,748 INFO L87 Difference]: Start difference. First operand 464 states and 638 transitions. Second operand 3 states. [2019-11-20 04:42:16,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:16,811 INFO L93 Difference]: Finished difference Result 915 states and 1259 transitions. [2019-11-20 04:42:16,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:16,812 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-20 04:42:16,813 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:16,816 INFO L225 Difference]: With dead ends: 915 [2019-11-20 04:42:16,816 INFO L226 Difference]: Without dead ends: 464 [2019-11-20 04:42:16,817 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:16,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-20 04:42:16,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-20 04:42:16,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-20 04:42:16,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 622 transitions. [2019-11-20 04:42:16,844 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 622 transitions. Word has length 61 [2019-11-20 04:42:16,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:16,845 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 622 transitions. [2019-11-20 04:42:16,845 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:16,845 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 622 transitions. [2019-11-20 04:42:16,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-20 04:42:16,846 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:16,846 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:16,846 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:16,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:16,847 INFO L82 PathProgramCache]: Analyzing trace with hash 398161233, now seen corresponding path program 1 times [2019-11-20 04:42:16,847 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:16,848 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322706218] [2019-11-20 04:42:16,848 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:16,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:16,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:16,908 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1322706218] [2019-11-20 04:42:16,908 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:16,908 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:16,909 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1562821146] [2019-11-20 04:42:16,910 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:16,910 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:16,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:16,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:16,911 INFO L87 Difference]: Start difference. First operand 464 states and 622 transitions. Second operand 3 states. [2019-11-20 04:42:16,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:16,995 INFO L93 Difference]: Finished difference Result 1299 states and 1732 transitions. [2019-11-20 04:42:16,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:16,996 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-20 04:42:16,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:17,002 INFO L225 Difference]: With dead ends: 1299 [2019-11-20 04:42:17,002 INFO L226 Difference]: Without dead ends: 884 [2019-11-20 04:42:17,003 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:17,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 884 states. [2019-11-20 04:42:17,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 884 to 834. [2019-11-20 04:42:17,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 834 states. [2019-11-20 04:42:17,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 834 states to 834 states and 1099 transitions. [2019-11-20 04:42:17,047 INFO L78 Accepts]: Start accepts. Automaton has 834 states and 1099 transitions. Word has length 61 [2019-11-20 04:42:17,048 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:17,048 INFO L462 AbstractCegarLoop]: Abstraction has 834 states and 1099 transitions. [2019-11-20 04:42:17,048 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:17,049 INFO L276 IsEmpty]: Start isEmpty. Operand 834 states and 1099 transitions. [2019-11-20 04:42:17,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2019-11-20 04:42:17,050 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:17,050 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:17,050 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:17,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:17,051 INFO L82 PathProgramCache]: Analyzing trace with hash -276756042, now seen corresponding path program 1 times [2019-11-20 04:42:17,051 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:17,051 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578320451] [2019-11-20 04:42:17,052 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:17,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:17,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:17,090 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1578320451] [2019-11-20 04:42:17,090 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:17,090 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:17,091 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142949481] [2019-11-20 04:42:17,091 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:17,091 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:17,092 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:17,092 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:17,092 INFO L87 Difference]: Start difference. First operand 834 states and 1099 transitions. Second operand 3 states. [2019-11-20 04:42:17,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:17,203 INFO L93 Difference]: Finished difference Result 2234 states and 2945 transitions. [2019-11-20 04:42:17,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:17,203 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 62 [2019-11-20 04:42:17,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:17,213 INFO L225 Difference]: With dead ends: 2234 [2019-11-20 04:42:17,214 INFO L226 Difference]: Without dead ends: 1494 [2019-11-20 04:42:17,215 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:17,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1494 states. [2019-11-20 04:42:17,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1494 to 1424. [2019-11-20 04:42:17,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1424 states. [2019-11-20 04:42:17,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1424 states to 1424 states and 1862 transitions. [2019-11-20 04:42:17,292 INFO L78 Accepts]: Start accepts. Automaton has 1424 states and 1862 transitions. Word has length 62 [2019-11-20 04:42:17,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:17,292 INFO L462 AbstractCegarLoop]: Abstraction has 1424 states and 1862 transitions. [2019-11-20 04:42:17,292 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:17,293 INFO L276 IsEmpty]: Start isEmpty. Operand 1424 states and 1862 transitions. [2019-11-20 04:42:17,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-20 04:42:17,294 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:17,294 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:17,294 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:17,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:17,295 INFO L82 PathProgramCache]: Analyzing trace with hash -2032591659, now seen corresponding path program 1 times [2019-11-20 04:42:17,295 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:17,295 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013139640] [2019-11-20 04:42:17,296 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:17,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:17,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:17,353 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013139640] [2019-11-20 04:42:17,354 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:17,354 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:17,354 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767379369] [2019-11-20 04:42:17,355 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:17,355 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:17,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:17,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:17,355 INFO L87 Difference]: Start difference. First operand 1424 states and 1862 transitions. Second operand 3 states. [2019-11-20 04:42:17,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:17,523 INFO L93 Difference]: Finished difference Result 3972 states and 5180 transitions. [2019-11-20 04:42:17,524 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:17,524 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-11-20 04:42:17,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:17,543 INFO L225 Difference]: With dead ends: 3972 [2019-11-20 04:42:17,543 INFO L226 Difference]: Without dead ends: 2642 [2019-11-20 04:42:17,546 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:17,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2642 states. [2019-11-20 04:42:17,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2642 to 2560. [2019-11-20 04:42:17,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2560 states. [2019-11-20 04:42:17,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2560 states to 2560 states and 3314 transitions. [2019-11-20 04:42:17,683 INFO L78 Accepts]: Start accepts. Automaton has 2560 states and 3314 transitions. Word has length 63 [2019-11-20 04:42:17,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:17,684 INFO L462 AbstractCegarLoop]: Abstraction has 2560 states and 3314 transitions. [2019-11-20 04:42:17,684 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:17,684 INFO L276 IsEmpty]: Start isEmpty. Operand 2560 states and 3314 transitions. [2019-11-20 04:42:17,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-20 04:42:17,686 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:17,686 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:17,686 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:17,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:17,687 INFO L82 PathProgramCache]: Analyzing trace with hash -1324102959, now seen corresponding path program 1 times [2019-11-20 04:42:17,687 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:17,687 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185042796] [2019-11-20 04:42:17,687 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:17,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:17,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:17,734 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [185042796] [2019-11-20 04:42:17,734 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:17,734 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:17,735 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780098446] [2019-11-20 04:42:17,735 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:17,735 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:17,735 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:17,736 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:17,736 INFO L87 Difference]: Start difference. First operand 2560 states and 3314 transitions. Second operand 3 states. [2019-11-20 04:42:17,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:17,860 INFO L93 Difference]: Finished difference Result 4968 states and 6441 transitions. [2019-11-20 04:42:17,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:17,861 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-11-20 04:42:17,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:17,876 INFO L225 Difference]: With dead ends: 4968 [2019-11-20 04:42:17,876 INFO L226 Difference]: Without dead ends: 2474 [2019-11-20 04:42:17,880 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:17,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2474 states. [2019-11-20 04:42:17,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2474 to 2474. [2019-11-20 04:42:17,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2474 states. [2019-11-20 04:42:18,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2474 states to 2474 states and 3208 transitions. [2019-11-20 04:42:18,001 INFO L78 Accepts]: Start accepts. Automaton has 2474 states and 3208 transitions. Word has length 63 [2019-11-20 04:42:18,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:18,001 INFO L462 AbstractCegarLoop]: Abstraction has 2474 states and 3208 transitions. [2019-11-20 04:42:18,001 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:18,002 INFO L276 IsEmpty]: Start isEmpty. Operand 2474 states and 3208 transitions. [2019-11-20 04:42:18,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-11-20 04:42:18,003 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:18,003 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:18,003 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:18,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:18,003 INFO L82 PathProgramCache]: Analyzing trace with hash -1607983393, now seen corresponding path program 1 times [2019-11-20 04:42:18,003 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:18,004 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6319451] [2019-11-20 04:42:18,004 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:18,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:18,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:18,061 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [6319451] [2019-11-20 04:42:18,061 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:18,061 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 04:42:18,062 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [552587312] [2019-11-20 04:42:18,062 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:18,062 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:18,062 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:18,063 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:18,063 INFO L87 Difference]: Start difference. First operand 2474 states and 3208 transitions. Second operand 3 states. [2019-11-20 04:42:18,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:18,321 INFO L93 Difference]: Finished difference Result 7190 states and 9333 transitions. [2019-11-20 04:42:18,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:18,321 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2019-11-20 04:42:18,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:18,353 INFO L225 Difference]: With dead ends: 7190 [2019-11-20 04:42:18,353 INFO L226 Difference]: Without dead ends: 4786 [2019-11-20 04:42:18,358 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:18,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4786 states. [2019-11-20 04:42:18,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4786 to 4754. [2019-11-20 04:42:18,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4754 states. [2019-11-20 04:42:18,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4754 states to 4754 states and 6114 transitions. [2019-11-20 04:42:18,607 INFO L78 Accepts]: Start accepts. Automaton has 4754 states and 6114 transitions. Word has length 64 [2019-11-20 04:42:18,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:18,608 INFO L462 AbstractCegarLoop]: Abstraction has 4754 states and 6114 transitions. [2019-11-20 04:42:18,608 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:18,608 INFO L276 IsEmpty]: Start isEmpty. Operand 4754 states and 6114 transitions. [2019-11-20 04:42:18,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2019-11-20 04:42:18,611 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:18,612 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:18,612 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:18,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:18,613 INFO L82 PathProgramCache]: Analyzing trace with hash 93244939, now seen corresponding path program 1 times [2019-11-20 04:42:18,613 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:18,618 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813535867] [2019-11-20 04:42:18,618 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:18,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:18,665 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:18,665 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1813535867] [2019-11-20 04:42:18,666 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:18,666 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:18,668 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103367898] [2019-11-20 04:42:18,668 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:18,669 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:18,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:18,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:18,669 INFO L87 Difference]: Start difference. First operand 4754 states and 6114 transitions. Second operand 3 states. [2019-11-20 04:42:19,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:19,151 INFO L93 Difference]: Finished difference Result 14046 states and 18043 transitions. [2019-11-20 04:42:19,152 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:19,152 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2019-11-20 04:42:19,152 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:19,209 INFO L225 Difference]: With dead ends: 14046 [2019-11-20 04:42:19,210 INFO L226 Difference]: Without dead ends: 9384 [2019-11-20 04:42:19,219 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:19,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9384 states. [2019-11-20 04:42:19,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9384 to 9384. [2019-11-20 04:42:19,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9384 states. [2019-11-20 04:42:19,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9384 states to 9384 states and 11994 transitions. [2019-11-20 04:42:19,796 INFO L78 Accepts]: Start accepts. Automaton has 9384 states and 11994 transitions. Word has length 81 [2019-11-20 04:42:19,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:19,797 INFO L462 AbstractCegarLoop]: Abstraction has 9384 states and 11994 transitions. [2019-11-20 04:42:19,797 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:19,797 INFO L276 IsEmpty]: Start isEmpty. Operand 9384 states and 11994 transitions. [2019-11-20 04:42:19,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-20 04:42:19,806 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:19,806 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:19,807 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:19,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:19,807 INFO L82 PathProgramCache]: Analyzing trace with hash -447123663, now seen corresponding path program 1 times [2019-11-20 04:42:19,807 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:19,808 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12530342] [2019-11-20 04:42:19,808 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:19,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:19,870 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-20 04:42:19,870 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12530342] [2019-11-20 04:42:19,871 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:19,871 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 04:42:19,872 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619126540] [2019-11-20 04:42:19,872 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:19,872 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:19,873 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:19,873 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:19,873 INFO L87 Difference]: Start difference. First operand 9384 states and 11994 transitions. Second operand 3 states. [2019-11-20 04:42:20,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:20,469 INFO L93 Difference]: Finished difference Result 22768 states and 29084 transitions. [2019-11-20 04:42:20,469 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:20,470 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-20 04:42:20,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:20,536 INFO L225 Difference]: With dead ends: 22768 [2019-11-20 04:42:20,536 INFO L226 Difference]: Without dead ends: 13486 [2019-11-20 04:42:20,554 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:20,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13486 states. [2019-11-20 04:42:21,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13486 to 13420. [2019-11-20 04:42:21,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13420 states. [2019-11-20 04:42:21,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13420 states to 13420 states and 17034 transitions. [2019-11-20 04:42:21,328 INFO L78 Accepts]: Start accepts. Automaton has 13420 states and 17034 transitions. Word has length 110 [2019-11-20 04:42:21,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:21,329 INFO L462 AbstractCegarLoop]: Abstraction has 13420 states and 17034 transitions. [2019-11-20 04:42:21,329 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:21,329 INFO L276 IsEmpty]: Start isEmpty. Operand 13420 states and 17034 transitions. [2019-11-20 04:42:21,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-20 04:42:21,340 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:21,340 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:21,341 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:21,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:21,341 INFO L82 PathProgramCache]: Analyzing trace with hash -2122456675, now seen corresponding path program 1 times [2019-11-20 04:42:21,341 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:21,342 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330960464] [2019-11-20 04:42:21,342 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:21,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:21,396 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-11-20 04:42:21,397 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [330960464] [2019-11-20 04:42:21,399 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:21,399 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 04:42:21,399 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231616502] [2019-11-20 04:42:21,400 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:21,400 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:21,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:21,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:21,400 INFO L87 Difference]: Start difference. First operand 13420 states and 17034 transitions. Second operand 3 states. [2019-11-20 04:42:22,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:22,238 INFO L93 Difference]: Finished difference Result 32624 states and 41352 transitions. [2019-11-20 04:42:22,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:22,238 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-20 04:42:22,239 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:22,276 INFO L225 Difference]: With dead ends: 32624 [2019-11-20 04:42:22,276 INFO L226 Difference]: Without dead ends: 19278 [2019-11-20 04:42:22,295 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:22,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19278 states. [2019-11-20 04:42:23,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19278 to 19180. [2019-11-20 04:42:23,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19180 states. [2019-11-20 04:42:23,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19180 states to 19180 states and 24146 transitions. [2019-11-20 04:42:23,361 INFO L78 Accepts]: Start accepts. Automaton has 19180 states and 24146 transitions. Word has length 110 [2019-11-20 04:42:23,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:23,361 INFO L462 AbstractCegarLoop]: Abstraction has 19180 states and 24146 transitions. [2019-11-20 04:42:23,361 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:23,362 INFO L276 IsEmpty]: Start isEmpty. Operand 19180 states and 24146 transitions. [2019-11-20 04:42:23,375 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-20 04:42:23,376 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:23,376 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:23,376 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:23,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:23,377 INFO L82 PathProgramCache]: Analyzing trace with hash -4233773, now seen corresponding path program 1 times [2019-11-20 04:42:23,377 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:23,377 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333707787] [2019-11-20 04:42:23,378 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:23,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:23,446 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-20 04:42:23,447 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333707787] [2019-11-20 04:42:23,447 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:23,447 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 04:42:23,448 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451919075] [2019-11-20 04:42:23,448 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 04:42:23,448 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:23,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 04:42:23,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 04:42:23,449 INFO L87 Difference]: Start difference. First operand 19180 states and 24146 transitions. Second operand 5 states. [2019-11-20 04:42:24,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:24,847 INFO L93 Difference]: Finished difference Result 47102 states and 59685 transitions. [2019-11-20 04:42:24,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 04:42:24,848 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-11-20 04:42:24,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:24,901 INFO L225 Difference]: With dead ends: 47102 [2019-11-20 04:42:24,901 INFO L226 Difference]: Without dead ends: 28012 [2019-11-20 04:42:24,927 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 04:42:24,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28012 states. [2019-11-20 04:42:25,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28012 to 19324. [2019-11-20 04:42:25,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19324 states. [2019-11-20 04:42:25,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19324 states to 19324 states and 23950 transitions. [2019-11-20 04:42:25,806 INFO L78 Accepts]: Start accepts. Automaton has 19324 states and 23950 transitions. Word has length 110 [2019-11-20 04:42:25,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:25,806 INFO L462 AbstractCegarLoop]: Abstraction has 19324 states and 23950 transitions. [2019-11-20 04:42:25,806 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 04:42:25,807 INFO L276 IsEmpty]: Start isEmpty. Operand 19324 states and 23950 transitions. [2019-11-20 04:42:25,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-20 04:42:25,821 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:25,822 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:25,822 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:25,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:25,823 INFO L82 PathProgramCache]: Analyzing trace with hash 2012797655, now seen corresponding path program 1 times [2019-11-20 04:42:25,823 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:25,823 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387067204] [2019-11-20 04:42:25,823 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:25,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:25,917 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-20 04:42:25,917 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387067204] [2019-11-20 04:42:25,917 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:25,918 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 04:42:25,918 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15467020] [2019-11-20 04:42:25,918 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 04:42:25,923 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:25,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 04:42:25,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 04:42:25,924 INFO L87 Difference]: Start difference. First operand 19324 states and 23950 transitions. Second operand 5 states. [2019-11-20 04:42:27,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:27,255 INFO L93 Difference]: Finished difference Result 45442 states and 56677 transitions. [2019-11-20 04:42:27,256 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 04:42:27,256 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-11-20 04:42:27,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:27,313 INFO L225 Difference]: With dead ends: 45442 [2019-11-20 04:42:27,313 INFO L226 Difference]: Without dead ends: 26232 [2019-11-20 04:42:27,336 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 04:42:27,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26232 states. [2019-11-20 04:42:28,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26232 to 19420. [2019-11-20 04:42:28,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19420 states. [2019-11-20 04:42:28,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19420 states to 19420 states and 23690 transitions. [2019-11-20 04:42:28,300 INFO L78 Accepts]: Start accepts. Automaton has 19420 states and 23690 transitions. Word has length 110 [2019-11-20 04:42:28,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:28,300 INFO L462 AbstractCegarLoop]: Abstraction has 19420 states and 23690 transitions. [2019-11-20 04:42:28,300 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 04:42:28,300 INFO L276 IsEmpty]: Start isEmpty. Operand 19420 states and 23690 transitions. [2019-11-20 04:42:28,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-20 04:42:28,315 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:28,315 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:28,315 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:28,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:28,316 INFO L82 PathProgramCache]: Analyzing trace with hash 564093659, now seen corresponding path program 1 times [2019-11-20 04:42:28,316 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:28,316 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591854606] [2019-11-20 04:42:28,317 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:28,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:28,359 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:28,360 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [591854606] [2019-11-20 04:42:28,360 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:28,360 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:28,360 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34033879] [2019-11-20 04:42:28,362 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:28,362 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:28,362 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:28,362 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:28,363 INFO L87 Difference]: Start difference. First operand 19420 states and 23690 transitions. Second operand 3 states. [2019-11-20 04:42:29,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:29,210 INFO L93 Difference]: Finished difference Result 29198 states and 35739 transitions. [2019-11-20 04:42:29,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:29,211 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-20 04:42:29,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:29,245 INFO L225 Difference]: With dead ends: 29198 [2019-11-20 04:42:29,245 INFO L226 Difference]: Without dead ends: 19420 [2019-11-20 04:42:29,256 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:29,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19420 states. [2019-11-20 04:42:30,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19420 to 19350. [2019-11-20 04:42:30,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19350 states. [2019-11-20 04:42:30,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19350 states to 19350 states and 23356 transitions. [2019-11-20 04:42:30,086 INFO L78 Accepts]: Start accepts. Automaton has 19350 states and 23356 transitions. Word has length 110 [2019-11-20 04:42:30,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:30,086 INFO L462 AbstractCegarLoop]: Abstraction has 19350 states and 23356 transitions. [2019-11-20 04:42:30,087 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:30,087 INFO L276 IsEmpty]: Start isEmpty. Operand 19350 states and 23356 transitions. [2019-11-20 04:42:30,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-11-20 04:42:30,100 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:30,100 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:30,101 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:30,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:30,101 INFO L82 PathProgramCache]: Analyzing trace with hash 770898653, now seen corresponding path program 1 times [2019-11-20 04:42:30,102 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:30,102 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761519707] [2019-11-20 04:42:30,102 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:30,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:30,171 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-20 04:42:30,171 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761519707] [2019-11-20 04:42:30,172 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:30,172 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 04:42:30,172 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753063996] [2019-11-20 04:42:30,173 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 04:42:30,173 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:30,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 04:42:30,174 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 04:42:30,174 INFO L87 Difference]: Start difference. First operand 19350 states and 23356 transitions. Second operand 5 states. [2019-11-20 04:42:31,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:31,172 INFO L93 Difference]: Finished difference Result 37116 states and 45101 transitions. [2019-11-20 04:42:31,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 04:42:31,173 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2019-11-20 04:42:31,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:31,189 INFO L225 Difference]: With dead ends: 37116 [2019-11-20 04:42:31,189 INFO L226 Difference]: Without dead ends: 17840 [2019-11-20 04:42:31,202 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 04:42:31,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17840 states. [2019-11-20 04:42:31,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17840 to 13178. [2019-11-20 04:42:31,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13178 states. [2019-11-20 04:42:31,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13178 states to 13178 states and 15698 transitions. [2019-11-20 04:42:31,735 INFO L78 Accepts]: Start accepts. Automaton has 13178 states and 15698 transitions. Word has length 111 [2019-11-20 04:42:31,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:31,735 INFO L462 AbstractCegarLoop]: Abstraction has 13178 states and 15698 transitions. [2019-11-20 04:42:31,736 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 04:42:31,736 INFO L276 IsEmpty]: Start isEmpty. Operand 13178 states and 15698 transitions. [2019-11-20 04:42:31,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-11-20 04:42:31,741 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:31,741 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:31,742 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:31,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:31,742 INFO L82 PathProgramCache]: Analyzing trace with hash 273196097, now seen corresponding path program 1 times [2019-11-20 04:42:31,743 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:31,743 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395280226] [2019-11-20 04:42:31,743 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:31,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:31,784 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:31,784 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395280226] [2019-11-20 04:42:31,785 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:31,785 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:31,785 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466675461] [2019-11-20 04:42:31,785 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:31,786 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:31,786 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:31,786 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:31,786 INFO L87 Difference]: Start difference. First operand 13178 states and 15698 transitions. Second operand 3 states. [2019-11-20 04:42:32,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:32,290 INFO L93 Difference]: Finished difference Result 21196 states and 25354 transitions. [2019-11-20 04:42:32,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:32,291 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-11-20 04:42:32,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:32,300 INFO L225 Difference]: With dead ends: 21196 [2019-11-20 04:42:32,300 INFO L226 Difference]: Without dead ends: 11030 [2019-11-20 04:42:32,308 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:32,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-11-20 04:42:32,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-11-20 04:42:32,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-11-20 04:42:32,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13114 transitions. [2019-11-20 04:42:32,725 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13114 transitions. Word has length 113 [2019-11-20 04:42:32,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:32,725 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13114 transitions. [2019-11-20 04:42:32,725 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:32,725 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13114 transitions. [2019-11-20 04:42:32,731 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2019-11-20 04:42:32,731 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:32,732 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:32,732 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:32,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:32,733 INFO L82 PathProgramCache]: Analyzing trace with hash 1857340375, now seen corresponding path program 1 times [2019-11-20 04:42:32,733 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:32,733 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683523256] [2019-11-20 04:42:32,733 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:32,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:32,781 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:32,782 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683523256] [2019-11-20 04:42:32,782 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:32,782 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:32,783 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114695847] [2019-11-20 04:42:32,783 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:32,783 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:32,783 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:32,784 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:32,784 INFO L87 Difference]: Start difference. First operand 11026 states and 13114 transitions. Second operand 3 states. [2019-11-20 04:42:33,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:33,204 INFO L93 Difference]: Finished difference Result 20200 states and 24102 transitions. [2019-11-20 04:42:33,204 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:33,204 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 146 [2019-11-20 04:42:33,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:33,214 INFO L225 Difference]: With dead ends: 20200 [2019-11-20 04:42:33,214 INFO L226 Difference]: Without dead ends: 11030 [2019-11-20 04:42:33,220 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:33,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-11-20 04:42:33,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-11-20 04:42:33,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-11-20 04:42:33,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13034 transitions. [2019-11-20 04:42:33,617 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13034 transitions. Word has length 146 [2019-11-20 04:42:33,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:33,618 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13034 transitions. [2019-11-20 04:42:33,618 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:33,618 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13034 transitions. [2019-11-20 04:42:33,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-11-20 04:42:33,626 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:33,626 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:33,627 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:33,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:33,627 INFO L82 PathProgramCache]: Analyzing trace with hash 1216535548, now seen corresponding path program 1 times [2019-11-20 04:42:33,627 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:33,628 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [875839846] [2019-11-20 04:42:33,628 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:33,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:33,716 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-20 04:42:33,716 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [875839846] [2019-11-20 04:42:33,717 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:33,717 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 04:42:33,718 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [150642879] [2019-11-20 04:42:33,719 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 04:42:33,720 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:33,720 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 04:42:33,722 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 04:42:33,722 INFO L87 Difference]: Start difference. First operand 11026 states and 13034 transitions. Second operand 5 states. [2019-11-20 04:42:34,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:34,903 INFO L93 Difference]: Finished difference Result 35306 states and 41589 transitions. [2019-11-20 04:42:34,903 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 04:42:34,904 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 176 [2019-11-20 04:42:34,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:34,922 INFO L225 Difference]: With dead ends: 35306 [2019-11-20 04:42:34,922 INFO L226 Difference]: Without dead ends: 24343 [2019-11-20 04:42:34,930 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 04:42:34,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24343 states. [2019-11-20 04:42:35,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24343 to 11410. [2019-11-20 04:42:35,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-11-20 04:42:35,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13328 transitions. [2019-11-20 04:42:35,458 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13328 transitions. Word has length 176 [2019-11-20 04:42:35,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:35,458 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13328 transitions. [2019-11-20 04:42:35,458 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 04:42:35,458 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13328 transitions. [2019-11-20 04:42:35,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-11-20 04:42:35,465 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:35,465 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:35,465 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:35,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:35,466 INFO L82 PathProgramCache]: Analyzing trace with hash 2104709508, now seen corresponding path program 1 times [2019-11-20 04:42:35,466 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:35,466 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299651414] [2019-11-20 04:42:35,466 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:35,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:35,528 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:35,528 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1299651414] [2019-11-20 04:42:35,528 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:35,529 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:35,529 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396286072] [2019-11-20 04:42:35,529 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:35,530 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:35,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:35,530 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:35,530 INFO L87 Difference]: Start difference. First operand 11410 states and 13328 transitions. Second operand 3 states. [2019-11-20 04:42:36,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:36,284 INFO L93 Difference]: Finished difference Result 19722 states and 23103 transitions. [2019-11-20 04:42:36,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:36,284 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2019-11-20 04:42:36,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:36,297 INFO L225 Difference]: With dead ends: 19722 [2019-11-20 04:42:36,297 INFO L226 Difference]: Without dead ends: 11442 [2019-11-20 04:42:36,309 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:36,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11442 states. [2019-11-20 04:42:37,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11442 to 11410. [2019-11-20 04:42:37,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-11-20 04:42:37,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13120 transitions. [2019-11-20 04:42:37,176 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13120 transitions. Word has length 176 [2019-11-20 04:42:37,177 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:37,177 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13120 transitions. [2019-11-20 04:42:37,177 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:37,177 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13120 transitions. [2019-11-20 04:42:37,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-20 04:42:37,186 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:37,186 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:37,187 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:37,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:37,187 INFO L82 PathProgramCache]: Analyzing trace with hash 251088387, now seen corresponding path program 1 times [2019-11-20 04:42:37,187 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:37,188 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852603935] [2019-11-20 04:42:37,188 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:37,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:37,237 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-20 04:42:37,237 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852603935] [2019-11-20 04:42:37,238 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:37,238 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:37,238 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1030194398] [2019-11-20 04:42:37,239 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:37,239 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:37,239 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:37,239 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:37,239 INFO L87 Difference]: Start difference. First operand 11410 states and 13120 transitions. Second operand 3 states. [2019-11-20 04:42:38,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:38,000 INFO L93 Difference]: Finished difference Result 22664 states and 25875 transitions. [2019-11-20 04:42:38,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:38,001 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-20 04:42:38,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:38,009 INFO L225 Difference]: With dead ends: 22664 [2019-11-20 04:42:38,010 INFO L226 Difference]: Without dead ends: 6788 [2019-11-20 04:42:38,020 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:38,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6788 states. [2019-11-20 04:42:38,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6788 to 6580. [2019-11-20 04:42:38,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-11-20 04:42:38,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7290 transitions. [2019-11-20 04:42:38,479 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7290 transitions. Word has length 178 [2019-11-20 04:42:38,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:38,480 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7290 transitions. [2019-11-20 04:42:38,480 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:38,480 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7290 transitions. [2019-11-20 04:42:38,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-20 04:42:38,488 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:38,488 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:38,488 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:38,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:38,489 INFO L82 PathProgramCache]: Analyzing trace with hash -32931800, now seen corresponding path program 1 times [2019-11-20 04:42:38,489 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:38,489 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248545975] [2019-11-20 04:42:38,489 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:38,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 04:42:38,551 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 04:42:38,551 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248545975] [2019-11-20 04:42:38,551 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 04:42:38,551 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 04:42:38,552 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1185279925] [2019-11-20 04:42:38,552 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 04:42:38,553 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 04:42:38,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 04:42:38,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:38,554 INFO L87 Difference]: Start difference. First operand 6580 states and 7290 transitions. Second operand 3 states. [2019-11-20 04:42:39,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 04:42:39,000 INFO L93 Difference]: Finished difference Result 11554 states and 12829 transitions. [2019-11-20 04:42:39,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 04:42:39,000 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 180 [2019-11-20 04:42:39,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 04:42:39,008 INFO L225 Difference]: With dead ends: 11554 [2019-11-20 04:42:39,008 INFO L226 Difference]: Without dead ends: 6580 [2019-11-20 04:42:39,013 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 04:42:39,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6580 states. [2019-11-20 04:42:39,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6580 to 6580. [2019-11-20 04:42:39,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-11-20 04:42:39,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7212 transitions. [2019-11-20 04:42:39,527 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7212 transitions. Word has length 180 [2019-11-20 04:42:39,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 04:42:39,528 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7212 transitions. [2019-11-20 04:42:39,528 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 04:42:39,528 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7212 transitions. [2019-11-20 04:42:39,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2019-11-20 04:42:39,536 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 04:42:39,536 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 04:42:39,536 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 04:42:39,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 04:42:39,537 INFO L82 PathProgramCache]: Analyzing trace with hash 1382104249, now seen corresponding path program 1 times [2019-11-20 04:42:39,537 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 04:42:39,537 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694317492] [2019-11-20 04:42:39,537 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 04:42:39,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 04:42:39,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 04:42:39,680 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 04:42:39,680 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-20 04:42:39,872 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 20.11 04:42:39 BoogieIcfgContainer [2019-11-20 04:42:39,873 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-20 04:42:39,873 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-20 04:42:39,873 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-20 04:42:39,874 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-20 04:42:39,882 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 04:42:15" (3/4) ... [2019-11-20 04:42:39,884 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-20 04:42:40,108 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_40c18fc6-3b1f-4d8d-8db1-7d9611293c93/bin/uautomizer/witness.graphml [2019-11-20 04:42:40,108 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-20 04:42:40,110 INFO L168 Benchmark]: Toolchain (without parser) took 26821.03 ms. Allocated memory was 1.0 GB in the beginning and 3.4 GB in the end (delta: 2.4 GB). Free memory was 950.1 MB in the beginning and 1.6 GB in the end (delta: -669.4 MB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. [2019-11-20 04:42:40,111 INFO L168 Benchmark]: CDTParser took 0.28 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 04:42:40,111 INFO L168 Benchmark]: CACSL2BoogieTranslator took 517.28 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 164.1 MB). Free memory was 950.1 MB in the beginning and 1.2 GB in the end (delta: -203.7 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. [2019-11-20 04:42:40,112 INFO L168 Benchmark]: Boogie Procedure Inliner took 62.09 ms. Allocated memory is still 1.2 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 04:42:40,112 INFO L168 Benchmark]: Boogie Preprocessor took 60.41 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-11-20 04:42:40,112 INFO L168 Benchmark]: RCFGBuilder took 1159.41 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 70.8 MB). Peak memory consumption was 70.8 MB. Max. memory is 11.5 GB. [2019-11-20 04:42:40,113 INFO L168 Benchmark]: TraceAbstraction took 24782.54 ms. Allocated memory was 1.2 GB in the beginning and 3.4 GB in the end (delta: 2.2 GB). Free memory was 1.1 GB in the beginning and 1.7 GB in the end (delta: -608.2 MB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. [2019-11-20 04:42:40,113 INFO L168 Benchmark]: Witness Printer took 234.89 ms. Allocated memory is still 3.4 GB. Free memory was 1.7 GB in the beginning and 1.6 GB in the end (delta: 65.0 MB). Peak memory consumption was 65.0 MB. Max. memory is 11.5 GB. [2019-11-20 04:42:40,118 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.28 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 517.28 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 164.1 MB). Free memory was 950.1 MB in the beginning and 1.2 GB in the end (delta: -203.7 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 62.09 ms. Allocated memory is still 1.2 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 60.41 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1159.41 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 70.8 MB). Peak memory consumption was 70.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 24782.54 ms. Allocated memory was 1.2 GB in the beginning and 3.4 GB in the end (delta: 2.2 GB). Free memory was 1.1 GB in the beginning and 1.7 GB in the end (delta: -608.2 MB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. * Witness Printer took 234.89 ms. Allocated memory is still 3.4 GB. Free memory was 1.7 GB in the beginning and 1.6 GB in the end (delta: 65.0 MB). Peak memory consumption was 65.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int t3_i ; [L27] int M_E = 2; [L28] int T1_E = 2; [L29] int T2_E = 2; [L30] int T3_E = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L687] int __retres1 ; [L600] m_i = 1 [L601] t1_i = 1 [L602] t2_i = 1 [L603] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L628] int kernel_st ; [L629] int tmp ; [L630] int tmp___0 ; [L634] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L271] COND TRUE m_i == 1 [L272] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L276] COND TRUE t1_i == 1 [L277] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L281] COND TRUE t2_i == 1 [L282] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t3_i == 1 [L287] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L408] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L413] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L418] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L187] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L206] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L225] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L244] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L254] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L451] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L456] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L461] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L642] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L645] kernel_st = 1 [L327] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L84] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L119] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L154] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L165] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L167] t3_pc = 1 [L168] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND TRUE \read(tmp_ndt_1) [L346] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L43] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L54] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L57] E_1 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND TRUE E_1 == 1 [L208] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND TRUE \read(tmp___0) [L509] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L59] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L62] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L64] m_pc = 1 [L65] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L84] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L87] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L103] E_2 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND TRUE E_2 == 1 [L227] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND TRUE \read(tmp___1) [L517] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L105] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L119] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L122] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L138] E_3 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND TRUE E_3 == 1 [L246] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND TRUE \read(tmp___2) [L525] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L140] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L154] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L157] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 276 locations, 1 error locations. Result: UNSAFE, OverallTime: 24.7s, OverallIterations: 27, TraceHistogramMax: 2, AutomataDifference: 12.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 10884 SDtfs, 10117 SDslu, 7643 SDs, 0 SdLazy, 500 SolverSat, 248 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 92 GetRequests, 50 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=19420occurred in iteration=18, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 9.7s AutomataMinimizationTime, 26 MinimizatonAttempts, 33813 StatesRemovedByMinimization, 16 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 0.8s InterpolantComputationTime, 2694 NumberOfCodeBlocks, 2694 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 2486 ConstructedInterpolants, 0 QuantifiedInterpolants, 403400 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 26 InterpolantComputations, 26 PerfectInterpolantSequences, 228/228 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...