./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 678e0110 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-678e011 [2019-11-20 01:22:18,902 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-20 01:22:18,903 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-20 01:22:18,924 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-20 01:22:18,925 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-20 01:22:18,926 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-20 01:22:18,928 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-20 01:22:18,940 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-20 01:22:18,941 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-20 01:22:18,942 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-20 01:22:18,943 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-20 01:22:18,944 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-20 01:22:18,944 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-20 01:22:18,945 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-20 01:22:18,946 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-20 01:22:18,947 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-20 01:22:18,948 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-20 01:22:18,949 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-20 01:22:18,950 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-20 01:22:18,952 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-20 01:22:18,961 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-20 01:22:18,965 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-20 01:22:18,969 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-20 01:22:18,970 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-20 01:22:18,976 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-20 01:22:18,977 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-20 01:22:18,977 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-20 01:22:18,980 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-20 01:22:18,980 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-20 01:22:18,982 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-20 01:22:18,982 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-20 01:22:18,983 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-20 01:22:18,983 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-20 01:22:18,984 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-20 01:22:18,985 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-20 01:22:18,985 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-20 01:22:18,986 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-20 01:22:18,986 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-20 01:22:18,986 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-20 01:22:18,988 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-20 01:22:18,989 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-20 01:22:18,990 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-20 01:22:19,008 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-20 01:22:19,008 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-20 01:22:19,009 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-20 01:22:19,009 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-20 01:22:19,010 INFO L138 SettingsManager]: * Use SBE=true [2019-11-20 01:22:19,010 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-20 01:22:19,010 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-20 01:22:19,010 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-20 01:22:19,010 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-20 01:22:19,010 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-20 01:22:19,011 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-20 01:22:19,011 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-20 01:22:19,011 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-20 01:22:19,011 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-20 01:22:19,011 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-20 01:22:19,012 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-20 01:22:19,012 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-20 01:22:19,012 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-20 01:22:19,012 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-20 01:22:19,012 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-20 01:22:19,013 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-20 01:22:19,013 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 01:22:19,013 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-20 01:22:19,013 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-20 01:22:19,013 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-20 01:22:19,014 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-20 01:22:19,014 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-20 01:22:19,014 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-20 01:22:19,014 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2019-11-20 01:22:19,147 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-20 01:22:19,158 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-20 01:22:19,161 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-20 01:22:19,162 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-20 01:22:19,163 INFO L275 PluginConnector]: CDTParser initialized [2019-11-20 01:22:19,163 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.04.cil.c [2019-11-20 01:22:19,226 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/data/f6fea85b4/eb2f276a7d5b45cdbcf06527c6a05e8b/FLAG38fc7a277 [2019-11-20 01:22:19,620 INFO L306 CDTParser]: Found 1 translation units. [2019-11-20 01:22:19,620 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/sv-benchmarks/c/systemc/transmitter.04.cil.c [2019-11-20 01:22:19,631 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/data/f6fea85b4/eb2f276a7d5b45cdbcf06527c6a05e8b/FLAG38fc7a277 [2019-11-20 01:22:19,942 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/data/f6fea85b4/eb2f276a7d5b45cdbcf06527c6a05e8b [2019-11-20 01:22:19,945 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-20 01:22:19,946 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-20 01:22:19,947 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-20 01:22:19,947 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-20 01:22:19,950 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-20 01:22:19,951 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 01:22:19" (1/1) ... [2019-11-20 01:22:19,953 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3958bb56 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:19, skipping insertion in model container [2019-11-20 01:22:19,953 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 01:22:19" (1/1) ... [2019-11-20 01:22:19,960 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-20 01:22:19,998 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-20 01:22:20,265 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 01:22:20,271 INFO L188 MainTranslator]: Completed pre-run [2019-11-20 01:22:20,360 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 01:22:20,380 INFO L192 MainTranslator]: Completed translation [2019-11-20 01:22:20,380 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20 WrapperNode [2019-11-20 01:22:20,380 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-20 01:22:20,381 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-20 01:22:20,381 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-20 01:22:20,381 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-20 01:22:20,388 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20" (1/1) ... [2019-11-20 01:22:20,396 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20" (1/1) ... [2019-11-20 01:22:20,450 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-20 01:22:20,450 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-20 01:22:20,450 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-20 01:22:20,451 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-20 01:22:20,460 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20" (1/1) ... [2019-11-20 01:22:20,460 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20" (1/1) ... [2019-11-20 01:22:20,466 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20" (1/1) ... [2019-11-20 01:22:20,467 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20" (1/1) ... [2019-11-20 01:22:20,497 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20" (1/1) ... [2019-11-20 01:22:20,519 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20" (1/1) ... [2019-11-20 01:22:20,523 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20" (1/1) ... [2019-11-20 01:22:20,531 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-20 01:22:20,531 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-20 01:22:20,531 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-20 01:22:20,532 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-20 01:22:20,533 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 01:22:20,600 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-20 01:22:20,600 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-20 01:22:21,916 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-20 01:22:21,917 INFO L285 CfgBuilder]: Removed 148 assume(true) statements. [2019-11-20 01:22:21,918 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 01:22:21 BoogieIcfgContainer [2019-11-20 01:22:21,918 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-20 01:22:21,919 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-20 01:22:21,919 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-20 01:22:21,923 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-20 01:22:21,923 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.11 01:22:19" (1/3) ... [2019-11-20 01:22:21,926 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3281deeb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 01:22:21, skipping insertion in model container [2019-11-20 01:22:21,927 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 01:22:20" (2/3) ... [2019-11-20 01:22:21,927 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3281deeb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 01:22:21, skipping insertion in model container [2019-11-20 01:22:21,928 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 01:22:21" (3/3) ... [2019-11-20 01:22:21,930 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.04.cil.c [2019-11-20 01:22:21,939 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-20 01:22:21,946 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-20 01:22:21,956 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-20 01:22:21,984 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-20 01:22:21,984 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-20 01:22:21,984 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-20 01:22:21,985 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-20 01:22:21,985 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-20 01:22:21,985 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-20 01:22:21,985 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-20 01:22:21,985 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-20 01:22:22,010 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states. [2019-11-20 01:22:22,020 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 01:22:22,020 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:22,021 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:22,022 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:22,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:22,027 INFO L82 PathProgramCache]: Analyzing trace with hash -1653942868, now seen corresponding path program 1 times [2019-11-20 01:22:22,033 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:22,034 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598295863] [2019-11-20 01:22:22,034 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:22,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:22,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:22,200 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598295863] [2019-11-20 01:22:22,200 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:22,201 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:22:22,202 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1273896894] [2019-11-20 01:22:22,207 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:22,207 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:22,219 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:22,220 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:22,222 INFO L87 Difference]: Start difference. First operand 374 states. Second operand 3 states. [2019-11-20 01:22:22,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:22,299 INFO L93 Difference]: Finished difference Result 743 states and 1159 transitions. [2019-11-20 01:22:22,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:22,301 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 01:22:22,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:22,320 INFO L225 Difference]: With dead ends: 743 [2019-11-20 01:22:22,320 INFO L226 Difference]: Without dead ends: 370 [2019-11-20 01:22:22,325 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:22,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370 states. [2019-11-20 01:22:22,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370 to 370. [2019-11-20 01:22:22,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 370 states. [2019-11-20 01:22:22,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370 states to 370 states and 561 transitions. [2019-11-20 01:22:22,397 INFO L78 Accepts]: Start accepts. Automaton has 370 states and 561 transitions. Word has length 73 [2019-11-20 01:22:22,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:22,398 INFO L462 AbstractCegarLoop]: Abstraction has 370 states and 561 transitions. [2019-11-20 01:22:22,398 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:22,398 INFO L276 IsEmpty]: Start isEmpty. Operand 370 states and 561 transitions. [2019-11-20 01:22:22,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 01:22:22,401 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:22,401 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:22,402 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:22,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:22,402 INFO L82 PathProgramCache]: Analyzing trace with hash -1161316694, now seen corresponding path program 1 times [2019-11-20 01:22:22,402 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:22,403 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888559428] [2019-11-20 01:22:22,403 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:22,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:22,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:22,467 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888559428] [2019-11-20 01:22:22,467 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:22,467 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:22,468 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [432316840] [2019-11-20 01:22:22,474 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:22,475 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:22,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:22,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:22,476 INFO L87 Difference]: Start difference. First operand 370 states and 561 transitions. Second operand 3 states. [2019-11-20 01:22:22,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:22,590 INFO L93 Difference]: Finished difference Result 1004 states and 1519 transitions. [2019-11-20 01:22:22,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:22,590 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 01:22:22,591 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:22,596 INFO L225 Difference]: With dead ends: 1004 [2019-11-20 01:22:22,596 INFO L226 Difference]: Without dead ends: 643 [2019-11-20 01:22:22,598 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:22,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 643 states. [2019-11-20 01:22:22,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 643 to 641. [2019-11-20 01:22:22,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-20 01:22:22,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 961 transitions. [2019-11-20 01:22:22,669 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 961 transitions. Word has length 73 [2019-11-20 01:22:22,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:22,669 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 961 transitions. [2019-11-20 01:22:22,669 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:22,669 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 961 transitions. [2019-11-20 01:22:22,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 01:22:22,677 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:22,678 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:22,678 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:22,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:22,678 INFO L82 PathProgramCache]: Analyzing trace with hash 1509510378, now seen corresponding path program 1 times [2019-11-20 01:22:22,678 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:22,679 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081496202] [2019-11-20 01:22:22,679 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:22,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:22,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:22,752 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081496202] [2019-11-20 01:22:22,753 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:22,753 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:22,753 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34033879] [2019-11-20 01:22:22,754 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:22,754 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:22,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:22,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:22,755 INFO L87 Difference]: Start difference. First operand 641 states and 961 transitions. Second operand 3 states. [2019-11-20 01:22:22,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:22,800 INFO L93 Difference]: Finished difference Result 1272 states and 1907 transitions. [2019-11-20 01:22:22,801 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:22,801 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 01:22:22,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:22,805 INFO L225 Difference]: With dead ends: 1272 [2019-11-20 01:22:22,806 INFO L226 Difference]: Without dead ends: 641 [2019-11-20 01:22:22,807 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:22,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-20 01:22:22,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-20 01:22:22,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-20 01:22:22,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 953 transitions. [2019-11-20 01:22:22,849 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 953 transitions. Word has length 73 [2019-11-20 01:22:22,849 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:22,849 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 953 transitions. [2019-11-20 01:22:22,849 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:22,850 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 953 transitions. [2019-11-20 01:22:22,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 01:22:22,853 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:22,853 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:22,854 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:22,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:22,854 INFO L82 PathProgramCache]: Analyzing trace with hash 1595666090, now seen corresponding path program 1 times [2019-11-20 01:22:22,854 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:22,855 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323590363] [2019-11-20 01:22:22,855 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:22,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:22,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:22,934 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323590363] [2019-11-20 01:22:22,934 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:22,935 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:22,935 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [602731070] [2019-11-20 01:22:22,935 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:22,936 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:22,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:22,936 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:22,936 INFO L87 Difference]: Start difference. First operand 641 states and 953 transitions. Second operand 3 states. [2019-11-20 01:22:22,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:22,984 INFO L93 Difference]: Finished difference Result 1271 states and 1890 transitions. [2019-11-20 01:22:22,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:22,985 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 01:22:22,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:22,989 INFO L225 Difference]: With dead ends: 1271 [2019-11-20 01:22:22,989 INFO L226 Difference]: Without dead ends: 641 [2019-11-20 01:22:22,991 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:22,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-20 01:22:23,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-20 01:22:23,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-20 01:22:23,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 945 transitions. [2019-11-20 01:22:23,023 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 945 transitions. Word has length 73 [2019-11-20 01:22:23,024 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:23,024 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 945 transitions. [2019-11-20 01:22:23,024 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:23,025 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 945 transitions. [2019-11-20 01:22:23,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 01:22:23,026 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:23,026 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:23,027 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:23,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:23,027 INFO L82 PathProgramCache]: Analyzing trace with hash 1178269484, now seen corresponding path program 1 times [2019-11-20 01:22:23,027 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:23,027 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441090992] [2019-11-20 01:22:23,028 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:23,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:23,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:23,104 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1441090992] [2019-11-20 01:22:23,104 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:23,104 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:23,105 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16851136] [2019-11-20 01:22:23,105 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:23,105 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:23,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:23,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,106 INFO L87 Difference]: Start difference. First operand 641 states and 945 transitions. Second operand 3 states. [2019-11-20 01:22:23,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:23,153 INFO L93 Difference]: Finished difference Result 1270 states and 1873 transitions. [2019-11-20 01:22:23,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:23,154 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 01:22:23,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:23,158 INFO L225 Difference]: With dead ends: 1270 [2019-11-20 01:22:23,158 INFO L226 Difference]: Without dead ends: 641 [2019-11-20 01:22:23,160 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-20 01:22:23,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-20 01:22:23,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-20 01:22:23,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 937 transitions. [2019-11-20 01:22:23,190 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 937 transitions. Word has length 73 [2019-11-20 01:22:23,190 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:23,190 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 937 transitions. [2019-11-20 01:22:23,190 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:23,190 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 937 transitions. [2019-11-20 01:22:23,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 01:22:23,192 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:23,192 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:23,192 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:23,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:23,193 INFO L82 PathProgramCache]: Analyzing trace with hash 52103404, now seen corresponding path program 1 times [2019-11-20 01:22:23,193 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:23,193 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553193783] [2019-11-20 01:22:23,193 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:23,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:23,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:23,254 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553193783] [2019-11-20 01:22:23,254 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:23,255 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:23,255 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1260919722] [2019-11-20 01:22:23,255 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:23,255 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:23,256 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:23,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,256 INFO L87 Difference]: Start difference. First operand 641 states and 937 transitions. Second operand 3 states. [2019-11-20 01:22:23,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:23,337 INFO L93 Difference]: Finished difference Result 1268 states and 1854 transitions. [2019-11-20 01:22:23,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:23,338 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 01:22:23,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:23,342 INFO L225 Difference]: With dead ends: 1268 [2019-11-20 01:22:23,342 INFO L226 Difference]: Without dead ends: 641 [2019-11-20 01:22:23,344 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-20 01:22:23,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-20 01:22:23,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-20 01:22:23,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 919 transitions. [2019-11-20 01:22:23,381 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 919 transitions. Word has length 73 [2019-11-20 01:22:23,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:23,382 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 919 transitions. [2019-11-20 01:22:23,382 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:23,382 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 919 transitions. [2019-11-20 01:22:23,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 01:22:23,383 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:23,383 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:23,384 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:23,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:23,388 INFO L82 PathProgramCache]: Analyzing trace with hash 2144832493, now seen corresponding path program 1 times [2019-11-20 01:22:23,388 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:23,388 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [835871458] [2019-11-20 01:22:23,388 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:23,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:23,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:23,463 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [835871458] [2019-11-20 01:22:23,463 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:23,463 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:23,464 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255524562] [2019-11-20 01:22:23,464 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:23,464 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:23,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:23,467 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,468 INFO L87 Difference]: Start difference. First operand 641 states and 919 transitions. Second operand 3 states. [2019-11-20 01:22:23,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:23,540 INFO L93 Difference]: Finished difference Result 1267 states and 1817 transitions. [2019-11-20 01:22:23,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:23,541 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 01:22:23,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:23,545 INFO L225 Difference]: With dead ends: 1267 [2019-11-20 01:22:23,545 INFO L226 Difference]: Without dead ends: 641 [2019-11-20 01:22:23,547 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-20 01:22:23,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-20 01:22:23,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-20 01:22:23,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 901 transitions. [2019-11-20 01:22:23,583 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 901 transitions. Word has length 73 [2019-11-20 01:22:23,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:23,583 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 901 transitions. [2019-11-20 01:22:23,583 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:23,583 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 901 transitions. [2019-11-20 01:22:23,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 01:22:23,609 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:23,609 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:23,610 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:23,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:23,612 INFO L82 PathProgramCache]: Analyzing trace with hash 1887883821, now seen corresponding path program 1 times [2019-11-20 01:22:23,612 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:23,613 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459821802] [2019-11-20 01:22:23,613 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:23,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:23,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:23,658 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459821802] [2019-11-20 01:22:23,658 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:23,658 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:23,659 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707830497] [2019-11-20 01:22:23,660 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:23,660 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:23,660 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:23,660 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,660 INFO L87 Difference]: Start difference. First operand 641 states and 901 transitions. Second operand 3 states. [2019-11-20 01:22:23,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:23,723 INFO L93 Difference]: Finished difference Result 1266 states and 1780 transitions. [2019-11-20 01:22:23,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:23,723 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 01:22:23,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:23,727 INFO L225 Difference]: With dead ends: 1266 [2019-11-20 01:22:23,727 INFO L226 Difference]: Without dead ends: 641 [2019-11-20 01:22:23,729 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-20 01:22:23,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-20 01:22:23,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-20 01:22:23,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 883 transitions. [2019-11-20 01:22:23,760 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 883 transitions. Word has length 73 [2019-11-20 01:22:23,760 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:23,760 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 883 transitions. [2019-11-20 01:22:23,760 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:23,760 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 883 transitions. [2019-11-20 01:22:23,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 01:22:23,761 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:23,761 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:23,762 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:23,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:23,762 INFO L82 PathProgramCache]: Analyzing trace with hash 1757929134, now seen corresponding path program 1 times [2019-11-20 01:22:23,762 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:23,762 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523462365] [2019-11-20 01:22:23,763 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:23,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:23,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:23,787 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523462365] [2019-11-20 01:22:23,787 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:23,788 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:23,788 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202948021] [2019-11-20 01:22:23,788 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:23,788 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:23,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:23,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,789 INFO L87 Difference]: Start difference. First operand 641 states and 883 transitions. Second operand 3 states. [2019-11-20 01:22:23,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:23,846 INFO L93 Difference]: Finished difference Result 1265 states and 1743 transitions. [2019-11-20 01:22:23,846 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:23,846 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 01:22:23,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:23,850 INFO L225 Difference]: With dead ends: 1265 [2019-11-20 01:22:23,850 INFO L226 Difference]: Without dead ends: 641 [2019-11-20 01:22:23,852 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-20 01:22:23,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-20 01:22:23,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-20 01:22:23,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 865 transitions. [2019-11-20 01:22:23,883 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 865 transitions. Word has length 73 [2019-11-20 01:22:23,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:23,883 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 865 transitions. [2019-11-20 01:22:23,883 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:23,883 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 865 transitions. [2019-11-20 01:22:23,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 01:22:23,884 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:23,884 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:23,884 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:23,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:23,885 INFO L82 PathProgramCache]: Analyzing trace with hash 1024701678, now seen corresponding path program 1 times [2019-11-20 01:22:23,885 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:23,885 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724281429] [2019-11-20 01:22:23,885 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:23,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:23,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:23,918 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724281429] [2019-11-20 01:22:23,918 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:23,918 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:23,919 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582711022] [2019-11-20 01:22:23,919 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:23,919 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:23,919 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:23,919 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,920 INFO L87 Difference]: Start difference. First operand 641 states and 865 transitions. Second operand 3 states. [2019-11-20 01:22:23,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:23,966 INFO L93 Difference]: Finished difference Result 1269 states and 1712 transitions. [2019-11-20 01:22:23,966 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:23,966 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 01:22:23,967 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:23,970 INFO L225 Difference]: With dead ends: 1269 [2019-11-20 01:22:23,970 INFO L226 Difference]: Without dead ends: 641 [2019-11-20 01:22:23,971 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:23,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-11-20 01:22:23,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-11-20 01:22:24,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-11-20 01:22:24,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 857 transitions. [2019-11-20 01:22:24,002 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 857 transitions. Word has length 73 [2019-11-20 01:22:24,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:24,003 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 857 transitions. [2019-11-20 01:22:24,003 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:24,003 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 857 transitions. [2019-11-20 01:22:24,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-20 01:22:24,003 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:24,004 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:24,004 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:24,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:24,004 INFO L82 PathProgramCache]: Analyzing trace with hash 1243556396, now seen corresponding path program 1 times [2019-11-20 01:22:24,004 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:24,004 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687955784] [2019-11-20 01:22:24,005 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:24,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:24,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:24,050 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687955784] [2019-11-20 01:22:24,050 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:24,050 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:22:24,051 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [399674718] [2019-11-20 01:22:24,051 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:24,051 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:24,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:24,052 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:24,052 INFO L87 Difference]: Start difference. First operand 641 states and 857 transitions. Second operand 3 states. [2019-11-20 01:22:24,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:24,144 INFO L93 Difference]: Finished difference Result 1812 states and 2410 transitions. [2019-11-20 01:22:24,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:24,144 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-11-20 01:22:24,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:24,151 INFO L225 Difference]: With dead ends: 1812 [2019-11-20 01:22:24,151 INFO L226 Difference]: Without dead ends: 1232 [2019-11-20 01:22:24,153 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:24,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1232 states. [2019-11-20 01:22:24,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1232 to 1168. [2019-11-20 01:22:24,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1168 states. [2019-11-20 01:22:24,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1168 states to 1168 states and 1539 transitions. [2019-11-20 01:22:24,212 INFO L78 Accepts]: Start accepts. Automaton has 1168 states and 1539 transitions. Word has length 73 [2019-11-20 01:22:24,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:24,212 INFO L462 AbstractCegarLoop]: Abstraction has 1168 states and 1539 transitions. [2019-11-20 01:22:24,212 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:24,213 INFO L276 IsEmpty]: Start isEmpty. Operand 1168 states and 1539 transitions. [2019-11-20 01:22:24,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-20 01:22:24,214 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:24,214 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:24,214 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:24,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:24,214 INFO L82 PathProgramCache]: Analyzing trace with hash -546581241, now seen corresponding path program 1 times [2019-11-20 01:22:24,215 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:24,215 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [396286072] [2019-11-20 01:22:24,215 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:24,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:24,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:24,254 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [396286072] [2019-11-20 01:22:24,255 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:24,255 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:22:24,255 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [221026487] [2019-11-20 01:22:24,255 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:24,256 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:24,256 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:24,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:24,256 INFO L87 Difference]: Start difference. First operand 1168 states and 1539 transitions. Second operand 3 states. [2019-11-20 01:22:24,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:24,409 INFO L93 Difference]: Finished difference Result 3182 states and 4193 transitions. [2019-11-20 01:22:24,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:24,410 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-11-20 01:22:24,411 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:24,422 INFO L225 Difference]: With dead ends: 3182 [2019-11-20 01:22:24,422 INFO L226 Difference]: Without dead ends: 2132 [2019-11-20 01:22:24,424 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:24,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2132 states. [2019-11-20 01:22:24,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2132 to 2034. [2019-11-20 01:22:24,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2034 states. [2019-11-20 01:22:24,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2034 states to 2034 states and 2664 transitions. [2019-11-20 01:22:24,529 INFO L78 Accepts]: Start accepts. Automaton has 2034 states and 2664 transitions. Word has length 74 [2019-11-20 01:22:24,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:24,530 INFO L462 AbstractCegarLoop]: Abstraction has 2034 states and 2664 transitions. [2019-11-20 01:22:24,531 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:24,531 INFO L276 IsEmpty]: Start isEmpty. Operand 2034 states and 2664 transitions. [2019-11-20 01:22:24,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-20 01:22:24,532 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:24,532 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:24,533 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:24,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:24,533 INFO L82 PathProgramCache]: Analyzing trace with hash 1027993841, now seen corresponding path program 1 times [2019-11-20 01:22:24,533 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:24,533 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [991263317] [2019-11-20 01:22:24,534 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:24,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:24,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:24,568 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [991263317] [2019-11-20 01:22:24,569 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:24,569 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:22:24,569 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1889128509] [2019-11-20 01:22:24,569 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:24,570 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:24,570 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:24,570 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:24,571 INFO L87 Difference]: Start difference. First operand 2034 states and 2664 transitions. Second operand 3 states. [2019-11-20 01:22:24,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:24,805 INFO L93 Difference]: Finished difference Result 5772 states and 7544 transitions. [2019-11-20 01:22:24,805 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:24,805 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2019-11-20 01:22:24,806 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:24,828 INFO L225 Difference]: With dead ends: 5772 [2019-11-20 01:22:24,828 INFO L226 Difference]: Without dead ends: 3856 [2019-11-20 01:22:24,832 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:24,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3856 states. [2019-11-20 01:22:25,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3856 to 3718. [2019-11-20 01:22:25,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3718 states. [2019-11-20 01:22:25,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3718 states to 3718 states and 4834 transitions. [2019-11-20 01:22:25,203 INFO L78 Accepts]: Start accepts. Automaton has 3718 states and 4834 transitions. Word has length 75 [2019-11-20 01:22:25,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:25,204 INFO L462 AbstractCegarLoop]: Abstraction has 3718 states and 4834 transitions. [2019-11-20 01:22:25,204 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:25,204 INFO L276 IsEmpty]: Start isEmpty. Operand 3718 states and 4834 transitions. [2019-11-20 01:22:25,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-20 01:22:25,206 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:25,206 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:25,207 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:25,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:25,207 INFO L82 PathProgramCache]: Analyzing trace with hash -934868943, now seen corresponding path program 1 times [2019-11-20 01:22:25,207 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:25,212 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519985367] [2019-11-20 01:22:25,212 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:25,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:25,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:25,234 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1519985367] [2019-11-20 01:22:25,234 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:25,234 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:22:25,235 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254200525] [2019-11-20 01:22:25,235 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:25,235 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:25,235 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:25,236 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:25,236 INFO L87 Difference]: Start difference. First operand 3718 states and 4834 transitions. Second operand 3 states. [2019-11-20 01:22:25,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:25,454 INFO L93 Difference]: Finished difference Result 7254 states and 9443 transitions. [2019-11-20 01:22:25,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:25,455 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2019-11-20 01:22:25,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:25,475 INFO L225 Difference]: With dead ends: 7254 [2019-11-20 01:22:25,475 INFO L226 Difference]: Without dead ends: 3608 [2019-11-20 01:22:25,481 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:25,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3608 states. [2019-11-20 01:22:25,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3608 to 3608. [2019-11-20 01:22:25,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3608 states. [2019-11-20 01:22:25,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3608 states to 3608 states and 4698 transitions. [2019-11-20 01:22:25,683 INFO L78 Accepts]: Start accepts. Automaton has 3608 states and 4698 transitions. Word has length 75 [2019-11-20 01:22:25,683 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:25,683 INFO L462 AbstractCegarLoop]: Abstraction has 3608 states and 4698 transitions. [2019-11-20 01:22:25,683 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:25,683 INFO L276 IsEmpty]: Start isEmpty. Operand 3608 states and 4698 transitions. [2019-11-20 01:22:25,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-11-20 01:22:25,684 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:25,684 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:25,685 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:25,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:25,685 INFO L82 PathProgramCache]: Analyzing trace with hash -607730891, now seen corresponding path program 1 times [2019-11-20 01:22:25,686 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:25,686 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640103666] [2019-11-20 01:22:25,686 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:25,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:25,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:25,722 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640103666] [2019-11-20 01:22:25,722 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:25,722 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:22:25,723 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563422402] [2019-11-20 01:22:25,723 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:25,723 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:25,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:25,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:25,724 INFO L87 Difference]: Start difference. First operand 3608 states and 4698 transitions. Second operand 3 states. [2019-11-20 01:22:26,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:26,078 INFO L93 Difference]: Finished difference Result 10194 states and 13246 transitions. [2019-11-20 01:22:26,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:26,079 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2019-11-20 01:22:26,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:26,116 INFO L225 Difference]: With dead ends: 10194 [2019-11-20 01:22:26,117 INFO L226 Difference]: Without dead ends: 6704 [2019-11-20 01:22:26,124 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:26,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6704 states. [2019-11-20 01:22:26,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6704 to 6542. [2019-11-20 01:22:26,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6542 states. [2019-11-20 01:22:26,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6542 states to 6542 states and 8460 transitions. [2019-11-20 01:22:26,525 INFO L78 Accepts]: Start accepts. Automaton has 6542 states and 8460 transitions. Word has length 76 [2019-11-20 01:22:26,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:26,525 INFO L462 AbstractCegarLoop]: Abstraction has 6542 states and 8460 transitions. [2019-11-20 01:22:26,525 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:26,525 INFO L276 IsEmpty]: Start isEmpty. Operand 6542 states and 8460 transitions. [2019-11-20 01:22:26,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-11-20 01:22:26,527 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:26,528 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:26,528 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:26,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:26,528 INFO L82 PathProgramCache]: Analyzing trace with hash 906360113, now seen corresponding path program 1 times [2019-11-20 01:22:26,529 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:26,529 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549963084] [2019-11-20 01:22:26,529 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:26,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:26,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:26,597 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549963084] [2019-11-20 01:22:26,598 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:26,598 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:22:26,598 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901215915] [2019-11-20 01:22:26,599 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:26,599 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:26,599 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:26,599 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:26,600 INFO L87 Difference]: Start difference. First operand 6542 states and 8460 transitions. Second operand 3 states. [2019-11-20 01:22:26,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:26,889 INFO L93 Difference]: Finished difference Result 12890 states and 16683 transitions. [2019-11-20 01:22:26,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:26,890 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2019-11-20 01:22:26,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:26,935 INFO L225 Difference]: With dead ends: 12890 [2019-11-20 01:22:26,935 INFO L226 Difference]: Without dead ends: 6434 [2019-11-20 01:22:26,944 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:26,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6434 states. [2019-11-20 01:22:27,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6434 to 6434. [2019-11-20 01:22:27,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6434 states. [2019-11-20 01:22:27,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6434 states to 6434 states and 8328 transitions. [2019-11-20 01:22:27,256 INFO L78 Accepts]: Start accepts. Automaton has 6434 states and 8328 transitions. Word has length 76 [2019-11-20 01:22:27,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:27,256 INFO L462 AbstractCegarLoop]: Abstraction has 6434 states and 8328 transitions. [2019-11-20 01:22:27,256 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:27,257 INFO L276 IsEmpty]: Start isEmpty. Operand 6434 states and 8328 transitions. [2019-11-20 01:22:27,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2019-11-20 01:22:27,258 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:27,258 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:27,259 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:27,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:27,259 INFO L82 PathProgramCache]: Analyzing trace with hash 675279555, now seen corresponding path program 1 times [2019-11-20 01:22:27,259 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:27,260 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220514772] [2019-11-20 01:22:27,260 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:27,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:27,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:27,297 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220514772] [2019-11-20 01:22:27,297 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:27,297 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:27,297 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [552965671] [2019-11-20 01:22:27,298 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:27,298 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:27,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:27,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:27,298 INFO L87 Difference]: Start difference. First operand 6434 states and 8328 transitions. Second operand 3 states. [2019-11-20 01:22:27,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:27,978 INFO L93 Difference]: Finished difference Result 18946 states and 24537 transitions. [2019-11-20 01:22:27,979 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:27,979 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 77 [2019-11-20 01:22:27,979 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:28,003 INFO L225 Difference]: With dead ends: 18946 [2019-11-20 01:22:28,003 INFO L226 Difference]: Without dead ends: 12602 [2019-11-20 01:22:28,012 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:28,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12602 states. [2019-11-20 01:22:28,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12602 to 12538. [2019-11-20 01:22:28,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12538 states. [2019-11-20 01:22:28,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12538 states to 12538 states and 16110 transitions. [2019-11-20 01:22:28,579 INFO L78 Accepts]: Start accepts. Automaton has 12538 states and 16110 transitions. Word has length 77 [2019-11-20 01:22:28,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:28,580 INFO L462 AbstractCegarLoop]: Abstraction has 12538 states and 16110 transitions. [2019-11-20 01:22:28,580 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:28,580 INFO L276 IsEmpty]: Start isEmpty. Operand 12538 states and 16110 transitions. [2019-11-20 01:22:28,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-11-20 01:22:28,586 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:28,586 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:28,586 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:28,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:28,587 INFO L82 PathProgramCache]: Analyzing trace with hash -1687722621, now seen corresponding path program 1 times [2019-11-20 01:22:28,587 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:28,587 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665302699] [2019-11-20 01:22:28,587 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:28,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:28,627 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:28,627 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [665302699] [2019-11-20 01:22:28,628 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:28,628 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:22:28,628 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858185165] [2019-11-20 01:22:28,628 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:28,633 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:28,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:28,633 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:28,634 INFO L87 Difference]: Start difference. First operand 12538 states and 16110 transitions. Second operand 3 states. [2019-11-20 01:22:29,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:29,734 INFO L93 Difference]: Finished difference Result 37260 states and 47825 transitions. [2019-11-20 01:22:29,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:29,735 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 96 [2019-11-20 01:22:29,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:29,786 INFO L225 Difference]: With dead ends: 37260 [2019-11-20 01:22:29,787 INFO L226 Difference]: Without dead ends: 24838 [2019-11-20 01:22:29,807 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:29,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24838 states. [2019-11-20 01:22:30,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24838 to 24838. [2019-11-20 01:22:30,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24838 states. [2019-11-20 01:22:30,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24838 states to 24838 states and 31776 transitions. [2019-11-20 01:22:30,930 INFO L78 Accepts]: Start accepts. Automaton has 24838 states and 31776 transitions. Word has length 96 [2019-11-20 01:22:30,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:30,931 INFO L462 AbstractCegarLoop]: Abstraction has 24838 states and 31776 transitions. [2019-11-20 01:22:30,931 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:30,931 INFO L276 IsEmpty]: Start isEmpty. Operand 24838 states and 31776 transitions. [2019-11-20 01:22:30,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-11-20 01:22:30,950 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:30,950 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:30,951 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:30,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:30,951 INFO L82 PathProgramCache]: Analyzing trace with hash 393922111, now seen corresponding path program 1 times [2019-11-20 01:22:30,951 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:30,951 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354107781] [2019-11-20 01:22:30,952 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:30,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:31,035 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-20 01:22:31,035 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354107781] [2019-11-20 01:22:31,035 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:31,036 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:31,036 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728494873] [2019-11-20 01:22:31,037 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:31,037 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:31,038 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:31,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:31,038 INFO L87 Difference]: Start difference. First operand 24838 states and 31776 transitions. Second operand 3 states. [2019-11-20 01:22:32,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:32,113 INFO L93 Difference]: Finished difference Result 60602 states and 77478 transitions. [2019-11-20 01:22:32,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:32,113 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-11-20 01:22:32,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:32,187 INFO L225 Difference]: With dead ends: 60602 [2019-11-20 01:22:32,187 INFO L226 Difference]: Without dead ends: 35876 [2019-11-20 01:22:32,225 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:32,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35876 states. [2019-11-20 01:22:33,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35876 to 35746. [2019-11-20 01:22:33,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35746 states. [2019-11-20 01:22:33,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35746 states to 35746 states and 45448 transitions. [2019-11-20 01:22:33,449 INFO L78 Accepts]: Start accepts. Automaton has 35746 states and 45448 transitions. Word has length 131 [2019-11-20 01:22:33,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:33,449 INFO L462 AbstractCegarLoop]: Abstraction has 35746 states and 45448 transitions. [2019-11-20 01:22:33,449 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:33,450 INFO L276 IsEmpty]: Start isEmpty. Operand 35746 states and 45448 transitions. [2019-11-20 01:22:33,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-11-20 01:22:33,471 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:33,471 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:33,472 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:33,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:33,472 INFO L82 PathProgramCache]: Analyzing trace with hash 760471151, now seen corresponding path program 1 times [2019-11-20 01:22:33,472 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:33,472 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315341659] [2019-11-20 01:22:33,473 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:33,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:33,527 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-20 01:22:33,527 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1315341659] [2019-11-20 01:22:33,528 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:33,528 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:33,528 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921834307] [2019-11-20 01:22:33,529 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:33,529 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:33,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:33,530 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:33,530 INFO L87 Difference]: Start difference. First operand 35746 states and 45448 transitions. Second operand 3 states. [2019-11-20 01:22:35,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:35,062 INFO L93 Difference]: Finished difference Result 87290 states and 110962 transitions. [2019-11-20 01:22:35,062 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:35,062 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-11-20 01:22:35,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:35,165 INFO L225 Difference]: With dead ends: 87290 [2019-11-20 01:22:35,166 INFO L226 Difference]: Without dead ends: 51680 [2019-11-20 01:22:35,196 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:35,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51680 states. [2019-11-20 01:22:36,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51680 to 51486. [2019-11-20 01:22:36,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51486 states. [2019-11-20 01:22:37,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51486 states to 51486 states and 65112 transitions. [2019-11-20 01:22:37,014 INFO L78 Accepts]: Start accepts. Automaton has 51486 states and 65112 transitions. Word has length 131 [2019-11-20 01:22:37,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:37,014 INFO L462 AbstractCegarLoop]: Abstraction has 51486 states and 65112 transitions. [2019-11-20 01:22:37,014 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:37,014 INFO L276 IsEmpty]: Start isEmpty. Operand 51486 states and 65112 transitions. [2019-11-20 01:22:37,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-11-20 01:22:37,037 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:37,037 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:37,038 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:37,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:37,038 INFO L82 PathProgramCache]: Analyzing trace with hash -776225517, now seen corresponding path program 1 times [2019-11-20 01:22:37,039 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:37,039 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213493313] [2019-11-20 01:22:37,039 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:37,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:37,105 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-11-20 01:22:37,106 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213493313] [2019-11-20 01:22:37,106 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:37,106 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 01:22:37,106 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539101116] [2019-11-20 01:22:37,107 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:37,107 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:37,107 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:37,107 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:37,108 INFO L87 Difference]: Start difference. First operand 51486 states and 65112 transitions. Second operand 3 states. [2019-11-20 01:22:39,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:39,294 INFO L93 Difference]: Finished difference Result 125690 states and 158770 transitions. [2019-11-20 01:22:39,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:39,294 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-11-20 01:22:39,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:39,387 INFO L225 Difference]: With dead ends: 125690 [2019-11-20 01:22:39,387 INFO L226 Difference]: Without dead ends: 74288 [2019-11-20 01:22:39,434 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:39,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74288 states. [2019-11-20 01:22:41,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74288 to 73998. [2019-11-20 01:22:41,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73998 states. [2019-11-20 01:22:41,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73998 states to 73998 states and 92936 transitions. [2019-11-20 01:22:41,934 INFO L78 Accepts]: Start accepts. Automaton has 73998 states and 92936 transitions. Word has length 131 [2019-11-20 01:22:41,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:41,935 INFO L462 AbstractCegarLoop]: Abstraction has 73998 states and 92936 transitions. [2019-11-20 01:22:41,935 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:41,935 INFO L276 IsEmpty]: Start isEmpty. Operand 73998 states and 92936 transitions. [2019-11-20 01:22:41,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-11-20 01:22:41,965 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:41,965 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:41,965 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:41,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:41,966 INFO L82 PathProgramCache]: Analyzing trace with hash 216677618, now seen corresponding path program 1 times [2019-11-20 01:22:41,966 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:41,966 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370563982] [2019-11-20 01:22:41,966 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:41,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:42,051 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-20 01:22:42,051 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370563982] [2019-11-20 01:22:42,051 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:42,052 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 01:22:42,052 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1831545665] [2019-11-20 01:22:42,052 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 01:22:42,052 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:42,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 01:22:42,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:22:42,054 INFO L87 Difference]: Start difference. First operand 73998 states and 92936 transitions. Second operand 5 states. [2019-11-20 01:22:45,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:45,345 INFO L93 Difference]: Finished difference Result 179776 states and 227199 transitions. [2019-11-20 01:22:45,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 01:22:45,346 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 131 [2019-11-20 01:22:45,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:45,456 INFO L225 Difference]: With dead ends: 179776 [2019-11-20 01:22:45,456 INFO L226 Difference]: Without dead ends: 105878 [2019-11-20 01:22:45,500 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 01:22:45,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105878 states. [2019-11-20 01:22:51,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105878 to 74430. [2019-11-20 01:22:51,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74430 states. [2019-11-20 01:22:51,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74430 states to 74430 states and 92212 transitions. [2019-11-20 01:22:51,760 INFO L78 Accepts]: Start accepts. Automaton has 74430 states and 92212 transitions. Word has length 131 [2019-11-20 01:22:51,760 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:51,760 INFO L462 AbstractCegarLoop]: Abstraction has 74430 states and 92212 transitions. [2019-11-20 01:22:51,760 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 01:22:51,760 INFO L276 IsEmpty]: Start isEmpty. Operand 74430 states and 92212 transitions. [2019-11-20 01:22:51,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-11-20 01:22:51,783 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:51,784 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:51,784 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:51,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:51,784 INFO L82 PathProgramCache]: Analyzing trace with hash -1889102986, now seen corresponding path program 1 times [2019-11-20 01:22:51,784 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:51,785 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626890775] [2019-11-20 01:22:51,785 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:51,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:51,842 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:22:51,842 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [626890775] [2019-11-20 01:22:51,843 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:51,843 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:22:51,843 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119572635] [2019-11-20 01:22:51,844 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:22:51,850 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:51,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:22:51,850 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:51,850 INFO L87 Difference]: Start difference. First operand 74430 states and 92212 transitions. Second operand 3 states. [2019-11-20 01:22:53,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:22:53,822 INFO L93 Difference]: Finished difference Result 112028 states and 139157 transitions. [2019-11-20 01:22:53,822 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:22:53,822 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-11-20 01:22:53,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:22:53,897 INFO L225 Difference]: With dead ends: 112028 [2019-11-20 01:22:53,897 INFO L226 Difference]: Without dead ends: 74430 [2019-11-20 01:22:53,926 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:22:53,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74430 states. [2019-11-20 01:22:56,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74430 to 74216. [2019-11-20 01:22:56,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74216 states. [2019-11-20 01:22:56,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74216 states to 74216 states and 91134 transitions. [2019-11-20 01:22:56,444 INFO L78 Accepts]: Start accepts. Automaton has 74216 states and 91134 transitions. Word has length 131 [2019-11-20 01:22:56,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:22:56,444 INFO L462 AbstractCegarLoop]: Abstraction has 74216 states and 91134 transitions. [2019-11-20 01:22:56,444 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:22:56,445 INFO L276 IsEmpty]: Start isEmpty. Operand 74216 states and 91134 transitions. [2019-11-20 01:22:56,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-11-20 01:22:56,466 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:22:56,466 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:22:56,466 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:22:56,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:22:56,467 INFO L82 PathProgramCache]: Analyzing trace with hash 1177275041, now seen corresponding path program 1 times [2019-11-20 01:22:56,467 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:22:56,467 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378052533] [2019-11-20 01:22:56,468 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:22:56,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:22:56,555 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2019-11-20 01:22:56,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [378052533] [2019-11-20 01:22:56,555 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:22:56,555 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 01:22:56,556 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2140709517] [2019-11-20 01:22:56,556 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 01:22:56,556 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:22:56,557 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 01:22:56,557 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:22:56,557 INFO L87 Difference]: Start difference. First operand 74216 states and 91134 transitions. Second operand 5 states. [2019-11-20 01:23:00,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:23:00,461 INFO L93 Difference]: Finished difference Result 172884 states and 213543 transitions. [2019-11-20 01:23:00,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 01:23:00,462 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-11-20 01:23:00,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:23:00,565 INFO L225 Difference]: With dead ends: 172884 [2019-11-20 01:23:00,565 INFO L226 Difference]: Without dead ends: 98792 [2019-11-20 01:23:00,601 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 01:23:00,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98792 states. [2019-11-20 01:23:03,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98792 to 74504. [2019-11-20 01:23:03,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74504 states. [2019-11-20 01:23:03,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74504 states to 74504 states and 90218 transitions. [2019-11-20 01:23:03,228 INFO L78 Accepts]: Start accepts. Automaton has 74504 states and 90218 transitions. Word has length 132 [2019-11-20 01:23:03,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:23:03,228 INFO L462 AbstractCegarLoop]: Abstraction has 74504 states and 90218 transitions. [2019-11-20 01:23:03,228 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 01:23:03,228 INFO L276 IsEmpty]: Start isEmpty. Operand 74504 states and 90218 transitions. [2019-11-20 01:23:03,254 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-11-20 01:23:03,254 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:23:03,255 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:23:03,255 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:23:03,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:23:03,255 INFO L82 PathProgramCache]: Analyzing trace with hash -1238601315, now seen corresponding path program 1 times [2019-11-20 01:23:03,256 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:23:03,256 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383444065] [2019-11-20 01:23:03,256 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:23:03,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:23:03,326 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2019-11-20 01:23:03,326 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [383444065] [2019-11-20 01:23:03,327 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:23:03,327 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 01:23:03,327 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14820199] [2019-11-20 01:23:03,328 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 01:23:03,328 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:23:03,328 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 01:23:03,328 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:23:03,328 INFO L87 Difference]: Start difference. First operand 74504 states and 90218 transitions. Second operand 5 states. [2019-11-20 01:23:08,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:23:08,441 INFO L93 Difference]: Finished difference Result 176172 states and 214583 transitions. [2019-11-20 01:23:08,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 01:23:08,442 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-11-20 01:23:08,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:23:08,546 INFO L225 Difference]: With dead ends: 176172 [2019-11-20 01:23:08,546 INFO L226 Difference]: Without dead ends: 101816 [2019-11-20 01:23:08,578 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 01:23:08,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101816 states. [2019-11-20 01:23:11,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101816 to 74792. [2019-11-20 01:23:11,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74792 states. [2019-11-20 01:23:11,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74792 states to 74792 states and 89302 transitions. [2019-11-20 01:23:11,628 INFO L78 Accepts]: Start accepts. Automaton has 74792 states and 89302 transitions. Word has length 132 [2019-11-20 01:23:11,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:23:11,629 INFO L462 AbstractCegarLoop]: Abstraction has 74792 states and 89302 transitions. [2019-11-20 01:23:11,629 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 01:23:11,629 INFO L276 IsEmpty]: Start isEmpty. Operand 74792 states and 89302 transitions. [2019-11-20 01:23:11,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-11-20 01:23:11,657 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:23:11,658 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:23:11,658 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:23:11,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:23:11,659 INFO L82 PathProgramCache]: Analyzing trace with hash -1048246887, now seen corresponding path program 1 times [2019-11-20 01:23:11,659 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:23:11,659 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [207058681] [2019-11-20 01:23:11,660 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:23:11,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:23:11,739 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2019-11-20 01:23:11,739 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [207058681] [2019-11-20 01:23:11,739 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:23:11,740 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 01:23:11,740 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164148637] [2019-11-20 01:23:11,740 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 01:23:11,740 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:23:11,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 01:23:11,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:23:11,741 INFO L87 Difference]: Start difference. First operand 74792 states and 89302 transitions. Second operand 5 states. [2019-11-20 01:23:16,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:23:16,321 INFO L93 Difference]: Finished difference Result 144386 states and 173411 transitions. [2019-11-20 01:23:16,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 01:23:16,321 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-11-20 01:23:16,321 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:23:16,402 INFO L225 Difference]: With dead ends: 144386 [2019-11-20 01:23:16,402 INFO L226 Difference]: Without dead ends: 69686 [2019-11-20 01:23:16,449 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 01:23:16,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69686 states. [2019-11-20 01:23:19,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69686 to 50828. [2019-11-20 01:23:19,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50828 states. [2019-11-20 01:23:19,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50828 states to 50828 states and 59968 transitions. [2019-11-20 01:23:19,694 INFO L78 Accepts]: Start accepts. Automaton has 50828 states and 59968 transitions. Word has length 132 [2019-11-20 01:23:19,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:23:19,694 INFO L462 AbstractCegarLoop]: Abstraction has 50828 states and 59968 transitions. [2019-11-20 01:23:19,694 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 01:23:19,694 INFO L276 IsEmpty]: Start isEmpty. Operand 50828 states and 59968 transitions. [2019-11-20 01:23:19,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-20 01:23:19,706 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:23:19,706 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:23:19,706 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:23:19,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:23:19,706 INFO L82 PathProgramCache]: Analyzing trace with hash -307341713, now seen corresponding path program 1 times [2019-11-20 01:23:19,707 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:23:19,707 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401442610] [2019-11-20 01:23:19,707 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:23:19,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:23:19,743 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:23:19,743 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [401442610] [2019-11-20 01:23:19,744 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:23:19,744 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:23:19,744 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1353275320] [2019-11-20 01:23:19,744 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:23:19,745 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:23:19,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:23:19,745 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:19,745 INFO L87 Difference]: Start difference. First operand 50828 states and 59968 transitions. Second operand 3 states. [2019-11-20 01:23:22,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:23:22,131 INFO L93 Difference]: Finished difference Result 81694 states and 96668 transitions. [2019-11-20 01:23:22,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:23:22,131 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2019-11-20 01:23:22,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:23:22,164 INFO L225 Difference]: With dead ends: 81694 [2019-11-20 01:23:22,164 INFO L226 Difference]: Without dead ends: 42420 [2019-11-20 01:23:22,178 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:22,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42420 states. [2019-11-20 01:23:24,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42420 to 42416. [2019-11-20 01:23:24,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42416 states. [2019-11-20 01:23:24,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42416 states to 42416 states and 50000 transitions. [2019-11-20 01:23:24,078 INFO L78 Accepts]: Start accepts. Automaton has 42416 states and 50000 transitions. Word has length 134 [2019-11-20 01:23:24,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:23:24,079 INFO L462 AbstractCegarLoop]: Abstraction has 42416 states and 50000 transitions. [2019-11-20 01:23:24,079 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:23:24,079 INFO L276 IsEmpty]: Start isEmpty. Operand 42416 states and 50000 transitions. [2019-11-20 01:23:24,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2019-11-20 01:23:24,091 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:23:24,092 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:23:24,092 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:23:24,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:23:24,092 INFO L82 PathProgramCache]: Analyzing trace with hash -451521753, now seen corresponding path program 1 times [2019-11-20 01:23:24,093 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:23:24,093 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076585308] [2019-11-20 01:23:24,093 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:23:24,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:23:24,140 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:23:24,141 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076585308] [2019-11-20 01:23:24,141 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:23:24,141 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:23:24,141 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1548106704] [2019-11-20 01:23:24,142 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:23:24,142 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:23:24,142 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:23:24,142 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:24,142 INFO L87 Difference]: Start difference. First operand 42416 states and 50000 transitions. Second operand 3 states. [2019-11-20 01:23:25,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:23:25,860 INFO L93 Difference]: Finished difference Result 69170 states and 81824 transitions. [2019-11-20 01:23:25,860 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:23:25,860 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 173 [2019-11-20 01:23:25,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:23:25,886 INFO L225 Difference]: With dead ends: 69170 [2019-11-20 01:23:25,886 INFO L226 Difference]: Without dead ends: 33872 [2019-11-20 01:23:25,903 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:25,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33872 states. [2019-11-20 01:23:27,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33872 to 33868. [2019-11-20 01:23:27,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33868 states. [2019-11-20 01:23:27,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33868 states to 33868 states and 39884 transitions. [2019-11-20 01:23:27,436 INFO L78 Accepts]: Start accepts. Automaton has 33868 states and 39884 transitions. Word has length 173 [2019-11-20 01:23:27,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:23:27,437 INFO L462 AbstractCegarLoop]: Abstraction has 33868 states and 39884 transitions. [2019-11-20 01:23:27,437 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:23:27,437 INFO L276 IsEmpty]: Start isEmpty. Operand 33868 states and 39884 transitions. [2019-11-20 01:23:27,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2019-11-20 01:23:27,448 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:23:27,449 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:23:27,449 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:23:27,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:23:27,449 INFO L82 PathProgramCache]: Analyzing trace with hash -1942944609, now seen corresponding path program 1 times [2019-11-20 01:23:27,449 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:23:27,449 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310141864] [2019-11-20 01:23:27,450 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:23:27,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:23:27,517 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:23:27,517 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310141864] [2019-11-20 01:23:27,517 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:23:27,517 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:23:27,518 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100986848] [2019-11-20 01:23:27,518 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:23:27,518 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:23:27,518 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:23:27,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:27,519 INFO L87 Difference]: Start difference. First operand 33868 states and 39884 transitions. Second operand 3 states. [2019-11-20 01:23:29,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:23:29,218 INFO L93 Difference]: Finished difference Result 63390 states and 74832 transitions. [2019-11-20 01:23:29,218 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:23:29,219 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 212 [2019-11-20 01:23:29,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:23:29,243 INFO L225 Difference]: With dead ends: 63390 [2019-11-20 01:23:29,243 INFO L226 Difference]: Without dead ends: 33872 [2019-11-20 01:23:29,252 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:29,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33872 states. [2019-11-20 01:23:30,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33872 to 33868. [2019-11-20 01:23:30,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33868 states. [2019-11-20 01:23:30,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33868 states to 33868 states and 39684 transitions. [2019-11-20 01:23:30,788 INFO L78 Accepts]: Start accepts. Automaton has 33868 states and 39684 transitions. Word has length 212 [2019-11-20 01:23:30,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:23:30,789 INFO L462 AbstractCegarLoop]: Abstraction has 33868 states and 39684 transitions. [2019-11-20 01:23:30,789 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:23:30,789 INFO L276 IsEmpty]: Start isEmpty. Operand 33868 states and 39684 transitions. [2019-11-20 01:23:30,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 249 [2019-11-20 01:23:30,801 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:23:30,801 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:23:30,801 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:23:30,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:23:30,802 INFO L82 PathProgramCache]: Analyzing trace with hash -980083650, now seen corresponding path program 1 times [2019-11-20 01:23:30,802 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:23:30,802 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075226812] [2019-11-20 01:23:30,802 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:23:30,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:23:30,878 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-20 01:23:30,878 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075226812] [2019-11-20 01:23:30,879 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:23:30,879 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 01:23:30,879 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894036422] [2019-11-20 01:23:30,880 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 01:23:30,880 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:23:30,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 01:23:30,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 01:23:30,880 INFO L87 Difference]: Start difference. First operand 33868 states and 39684 transitions. Second operand 5 states. [2019-11-20 01:23:34,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:23:34,609 INFO L93 Difference]: Finished difference Result 107663 states and 125750 transitions. [2019-11-20 01:23:34,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 01:23:34,610 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 248 [2019-11-20 01:23:34,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:23:34,670 INFO L225 Difference]: With dead ends: 107663 [2019-11-20 01:23:34,670 INFO L226 Difference]: Without dead ends: 73872 [2019-11-20 01:23:34,690 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 01:23:34,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73872 states. [2019-11-20 01:23:36,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73872 to 34876. [2019-11-20 01:23:36,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34876 states. [2019-11-20 01:23:36,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34876 states to 34876 states and 40450 transitions. [2019-11-20 01:23:36,989 INFO L78 Accepts]: Start accepts. Automaton has 34876 states and 40450 transitions. Word has length 248 [2019-11-20 01:23:36,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:23:36,990 INFO L462 AbstractCegarLoop]: Abstraction has 34876 states and 40450 transitions. [2019-11-20 01:23:36,990 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 01:23:36,990 INFO L276 IsEmpty]: Start isEmpty. Operand 34876 states and 40450 transitions. [2019-11-20 01:23:37,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 249 [2019-11-20 01:23:37,001 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:23:37,001 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:23:37,002 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:23:37,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:23:37,002 INFO L82 PathProgramCache]: Analyzing trace with hash -1127279802, now seen corresponding path program 1 times [2019-11-20 01:23:37,002 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:23:37,002 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484750115] [2019-11-20 01:23:37,002 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:23:37,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:23:37,068 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:23:37,068 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1484750115] [2019-11-20 01:23:37,069 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:23:37,069 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:23:37,069 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108937849] [2019-11-20 01:23:37,070 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:23:37,070 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:23:37,070 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:23:37,070 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:37,070 INFO L87 Difference]: Start difference. First operand 34876 states and 40450 transitions. Second operand 3 states. [2019-11-20 01:23:39,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:23:39,056 INFO L93 Difference]: Finished difference Result 62462 states and 72623 transitions. [2019-11-20 01:23:39,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:23:39,056 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 248 [2019-11-20 01:23:39,056 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:23:39,084 INFO L225 Difference]: With dead ends: 62462 [2019-11-20 01:23:39,084 INFO L226 Difference]: Without dead ends: 34940 [2019-11-20 01:23:39,101 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:39,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34940 states. [2019-11-20 01:23:42,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34940 to 34876. [2019-11-20 01:23:42,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34876 states. [2019-11-20 01:23:42,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34876 states to 34876 states and 39858 transitions. [2019-11-20 01:23:42,818 INFO L78 Accepts]: Start accepts. Automaton has 34876 states and 39858 transitions. Word has length 248 [2019-11-20 01:23:42,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:23:42,818 INFO L462 AbstractCegarLoop]: Abstraction has 34876 states and 39858 transitions. [2019-11-20 01:23:42,818 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:23:42,818 INFO L276 IsEmpty]: Start isEmpty. Operand 34876 states and 39858 transitions. [2019-11-20 01:23:42,830 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 252 [2019-11-20 01:23:42,830 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:23:42,830 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:23:42,830 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:23:42,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:23:42,831 INFO L82 PathProgramCache]: Analyzing trace with hash -301505065, now seen corresponding path program 1 times [2019-11-20 01:23:42,831 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:23:42,831 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953775980] [2019-11-20 01:23:42,831 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:23:42,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:23:42,909 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:23:42,909 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953775980] [2019-11-20 01:23:42,909 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:23:42,910 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:23:42,910 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1490341111] [2019-11-20 01:23:42,910 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:23:42,910 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:23:42,911 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:23:42,911 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:42,911 INFO L87 Difference]: Start difference. First operand 34876 states and 39858 transitions. Second operand 3 states. [2019-11-20 01:23:44,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:23:44,854 INFO L93 Difference]: Finished difference Result 59234 states and 67843 transitions. [2019-11-20 01:23:44,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:23:44,855 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 251 [2019-11-20 01:23:44,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:23:44,884 INFO L225 Difference]: With dead ends: 59234 [2019-11-20 01:23:44,884 INFO L226 Difference]: Without dead ends: 34940 [2019-11-20 01:23:44,900 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:44,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34940 states. [2019-11-20 01:23:46,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34940 to 34876. [2019-11-20 01:23:46,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34876 states. [2019-11-20 01:23:46,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34876 states to 34876 states and 39354 transitions. [2019-11-20 01:23:46,967 INFO L78 Accepts]: Start accepts. Automaton has 34876 states and 39354 transitions. Word has length 251 [2019-11-20 01:23:46,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:23:46,968 INFO L462 AbstractCegarLoop]: Abstraction has 34876 states and 39354 transitions. [2019-11-20 01:23:46,968 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:23:46,968 INFO L276 IsEmpty]: Start isEmpty. Operand 34876 states and 39354 transitions. [2019-11-20 01:23:46,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2019-11-20 01:23:46,979 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:23:46,979 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:23:46,980 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:23:46,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:23:46,980 INFO L82 PathProgramCache]: Analyzing trace with hash 391416485, now seen corresponding path program 1 times [2019-11-20 01:23:46,980 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:23:46,981 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299382842] [2019-11-20 01:23:46,981 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:23:46,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:23:47,047 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-20 01:23:47,048 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1299382842] [2019-11-20 01:23:47,048 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:23:47,048 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:23:47,048 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1402956379] [2019-11-20 01:23:47,049 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:23:47,049 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:23:47,049 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:23:47,049 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:47,049 INFO L87 Difference]: Start difference. First operand 34876 states and 39354 transitions. Second operand 3 states. [2019-11-20 01:23:48,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:23:48,575 INFO L93 Difference]: Finished difference Result 62718 states and 70361 transitions. [2019-11-20 01:23:48,579 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:23:48,580 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 254 [2019-11-20 01:23:48,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:23:48,593 INFO L225 Difference]: With dead ends: 62718 [2019-11-20 01:23:48,593 INFO L226 Difference]: Without dead ends: 16774 [2019-11-20 01:23:48,612 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:48,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16774 states. [2019-11-20 01:23:49,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16774 to 16254. [2019-11-20 01:23:49,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16254 states. [2019-11-20 01:23:49,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16254 states to 16254 states and 17772 transitions. [2019-11-20 01:23:49,487 INFO L78 Accepts]: Start accepts. Automaton has 16254 states and 17772 transitions. Word has length 254 [2019-11-20 01:23:49,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:23:49,487 INFO L462 AbstractCegarLoop]: Abstraction has 16254 states and 17772 transitions. [2019-11-20 01:23:49,488 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:23:49,488 INFO L276 IsEmpty]: Start isEmpty. Operand 16254 states and 17772 transitions. [2019-11-20 01:23:49,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 258 [2019-11-20 01:23:49,497 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:23:49,498 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:23:49,498 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:23:49,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:23:49,498 INFO L82 PathProgramCache]: Analyzing trace with hash -1392087481, now seen corresponding path program 1 times [2019-11-20 01:23:49,498 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:23:49,498 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1989905047] [2019-11-20 01:23:49,498 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:23:49,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 01:23:49,582 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 01:23:49,582 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1989905047] [2019-11-20 01:23:49,582 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 01:23:49,583 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 01:23:49,583 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [514245189] [2019-11-20 01:23:49,583 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 01:23:49,583 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 01:23:49,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 01:23:49,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:49,584 INFO L87 Difference]: Start difference. First operand 16254 states and 17772 transitions. Second operand 3 states. [2019-11-20 01:23:50,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 01:23:50,594 INFO L93 Difference]: Finished difference Result 28760 states and 31491 transitions. [2019-11-20 01:23:50,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 01:23:50,595 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 257 [2019-11-20 01:23:50,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 01:23:50,605 INFO L225 Difference]: With dead ends: 28760 [2019-11-20 01:23:50,606 INFO L226 Difference]: Without dead ends: 16254 [2019-11-20 01:23:50,610 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 01:23:50,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16254 states. [2019-11-20 01:23:51,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16254 to 16254. [2019-11-20 01:23:51,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16254 states. [2019-11-20 01:23:51,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16254 states to 16254 states and 17606 transitions. [2019-11-20 01:23:51,539 INFO L78 Accepts]: Start accepts. Automaton has 16254 states and 17606 transitions. Word has length 257 [2019-11-20 01:23:51,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 01:23:51,539 INFO L462 AbstractCegarLoop]: Abstraction has 16254 states and 17606 transitions. [2019-11-20 01:23:51,540 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 01:23:51,540 INFO L276 IsEmpty]: Start isEmpty. Operand 16254 states and 17606 transitions. [2019-11-20 01:23:51,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 261 [2019-11-20 01:23:51,549 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 01:23:51,549 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 01:23:51,549 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 01:23:51,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 01:23:51,550 INFO L82 PathProgramCache]: Analyzing trace with hash 1978087514, now seen corresponding path program 1 times [2019-11-20 01:23:51,550 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 01:23:51,550 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014880378] [2019-11-20 01:23:51,550 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 01:23:51,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 01:23:51,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 01:23:51,692 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 01:23:51,693 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-20 01:23:51,865 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 20.11 01:23:51 BoogieIcfgContainer [2019-11-20 01:23:51,869 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-20 01:23:51,870 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-20 01:23:51,870 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-20 01:23:51,870 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-20 01:23:51,870 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 01:22:21" (3/4) ... [2019-11-20 01:23:51,872 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-20 01:23:52,061 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_3279dab1-cf10-4a03-aff6-65193c5e49ff/bin/uautomizer/witness.graphml [2019-11-20 01:23:52,062 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-20 01:23:52,064 INFO L168 Benchmark]: Toolchain (without parser) took 92117.09 ms. Allocated memory was 1.0 GB in the beginning and 5.6 GB in the end (delta: 4.6 GB). Free memory was 950.1 MB in the beginning and 4.0 GB in the end (delta: -3.1 GB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2019-11-20 01:23:52,064 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 01:23:52,065 INFO L168 Benchmark]: CACSL2BoogieTranslator took 433.51 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 107.5 MB). Free memory was 950.1 MB in the beginning and 1.1 GB in the end (delta: -146.2 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. [2019-11-20 01:23:52,065 INFO L168 Benchmark]: Boogie Procedure Inliner took 69.05 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 11.5 GB. [2019-11-20 01:23:52,066 INFO L168 Benchmark]: Boogie Preprocessor took 80.60 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 14.2 MB). Peak memory consumption was 14.2 MB. Max. memory is 11.5 GB. [2019-11-20 01:23:52,066 INFO L168 Benchmark]: RCFGBuilder took 1387.08 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 988.7 MB in the end (delta: 86.3 MB). Peak memory consumption was 86.3 MB. Max. memory is 11.5 GB. [2019-11-20 01:23:52,067 INFO L168 Benchmark]: TraceAbstraction took 89950.09 ms. Allocated memory was 1.1 GB in the beginning and 5.6 GB in the end (delta: 4.5 GB). Free memory was 988.7 MB in the beginning and 4.1 GB in the end (delta: -3.1 GB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2019-11-20 01:23:52,067 INFO L168 Benchmark]: Witness Printer took 192.26 ms. Allocated memory is still 5.6 GB. Free memory was 4.1 GB in the beginning and 4.0 GB in the end (delta: 25.3 MB). Peak memory consumption was 25.3 MB. Max. memory is 11.5 GB. [2019-11-20 01:23:52,069 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 433.51 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 107.5 MB). Free memory was 950.1 MB in the beginning and 1.1 GB in the end (delta: -146.2 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 69.05 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 80.60 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 14.2 MB). Peak memory consumption was 14.2 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1387.08 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 988.7 MB in the end (delta: 86.3 MB). Peak memory consumption was 86.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 89950.09 ms. Allocated memory was 1.1 GB in the beginning and 5.6 GB in the end (delta: 4.5 GB). Free memory was 988.7 MB in the beginning and 4.1 GB in the end (delta: -3.1 GB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. * Witness Printer took 192.26 ms. Allocated memory is still 5.6 GB. Free memory was 4.1 GB in the beginning and 4.0 GB in the end (delta: 25.3 MB). Peak memory consumption was 25.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L811] int __retres1 ; [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L331] COND TRUE m_i == 1 [L332] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L492] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L497] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L502] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L228] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L247] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L266] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L285] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L304] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L545] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L550] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L555] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L766] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L769] kernel_st = 1 [L397] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L401] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L90] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L101] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L125] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L136] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L160] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L171] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L195] COND TRUE t4_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L206] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L208] t4_pc = 1 [L209] t4_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L401] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND TRUE \read(tmp_ndt_1) [L416] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L49] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L60] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L63] E_1 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND TRUE E_1 == 1 [L249] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND TRUE \read(tmp___0) [L614] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L65] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L68] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L70] m_pc = 1 [L71] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L90] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L93] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L109] E_2 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND TRUE E_2 == 1 [L268] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND TRUE \read(tmp___1) [L622] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L111] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L101] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L125] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L128] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L144] E_3 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND TRUE E_3 == 1 [L287] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND TRUE \read(tmp___2) [L630] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L146] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L136] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L163] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L179] E_4 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND TRUE E_4 == 1 [L306] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND TRUE \read(tmp___3) [L638] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L181] E_4 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L171] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L195] COND FALSE !(t4_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L198] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 374 locations, 1 error locations. Result: UNSAFE, OverallTime: 89.8s, OverallIterations: 35, TraceHistogramMax: 2, AutomataDifference: 45.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 19229 SDtfs, 17991 SDslu, 12915 SDs, 0 SdLazy, 695 SolverSat, 359 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 113 GetRequests, 59 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=74792occurred in iteration=25, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 41.6s AutomataMinimizationTime, 34 MinimizatonAttempts, 142630 StatesRemovedByMinimization, 21 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.1s InterpolantComputationTime, 4440 NumberOfCodeBlocks, 4440 NumberOfCodeBlocksAsserted, 35 NumberOfCheckSat, 4146 ConstructedInterpolants, 0 QuantifiedInterpolants, 888600 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 34 InterpolantComputations, 34 PerfectInterpolantSequences, 352/352 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...