./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 678e0110 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0e3598d1a4e9129bf22e72269576449e67f0febd .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-678e011 [2019-11-20 09:51:52,819 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-20 09:51:52,821 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-20 09:51:52,833 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-20 09:51:52,833 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-20 09:51:52,834 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-20 09:51:52,836 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-20 09:51:52,844 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-20 09:51:52,850 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-20 09:51:52,853 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-20 09:51:52,854 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-20 09:51:52,854 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-20 09:51:52,855 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-20 09:51:52,855 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-20 09:51:52,856 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-20 09:51:52,857 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-20 09:51:52,857 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-20 09:51:52,858 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-20 09:51:52,862 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-20 09:51:52,865 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-20 09:51:52,869 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-20 09:51:52,871 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-20 09:51:52,873 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-20 09:51:52,874 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-20 09:51:52,876 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-20 09:51:52,877 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-20 09:51:52,877 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-20 09:51:52,880 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-20 09:51:52,880 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-20 09:51:52,881 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-20 09:51:52,881 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-20 09:51:52,881 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-20 09:51:52,882 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-20 09:51:52,883 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-20 09:51:52,883 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-20 09:51:52,884 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-20 09:51:52,884 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-20 09:51:52,884 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-20 09:51:52,884 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-20 09:51:52,885 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-20 09:51:52,886 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-20 09:51:52,887 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-20 09:51:52,919 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-20 09:51:52,919 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-20 09:51:52,920 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-20 09:51:52,920 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-20 09:51:52,920 INFO L138 SettingsManager]: * Use SBE=true [2019-11-20 09:51:52,921 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-20 09:51:52,921 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-20 09:51:52,921 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-20 09:51:52,921 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-20 09:51:52,921 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-20 09:51:52,921 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-20 09:51:52,922 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-20 09:51:52,922 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-20 09:51:52,922 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-20 09:51:52,922 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-20 09:51:52,922 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-20 09:51:52,922 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-20 09:51:52,923 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-20 09:51:52,923 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-20 09:51:52,923 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-20 09:51:52,923 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-20 09:51:52,923 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 09:51:52,924 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-20 09:51:52,924 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-20 09:51:52,924 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-20 09:51:52,924 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-20 09:51:52,924 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-20 09:51:52,924 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-20 09:51:52,925 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0e3598d1a4e9129bf22e72269576449e67f0febd [2019-11-20 09:51:53,093 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-20 09:51:53,110 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-20 09:51:53,113 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-20 09:51:53,114 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-20 09:51:53,114 INFO L275 PluginConnector]: CDTParser initialized [2019-11-20 09:51:53,116 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2019-11-20 09:51:53,176 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/data/96a10f9e7/07c0b9c71feb4ce1806fe1fe5d01831e/FLAGf9469ffa9 [2019-11-20 09:51:53,657 INFO L306 CDTParser]: Found 1 translation units. [2019-11-20 09:51:53,658 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/sv-benchmarks/c/systemc/transmitter.15.cil.c [2019-11-20 09:51:53,685 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/data/96a10f9e7/07c0b9c71feb4ce1806fe1fe5d01831e/FLAGf9469ffa9 [2019-11-20 09:51:54,188 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/data/96a10f9e7/07c0b9c71feb4ce1806fe1fe5d01831e [2019-11-20 09:51:54,190 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-20 09:51:54,191 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-20 09:51:54,195 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-20 09:51:54,196 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-20 09:51:54,199 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-20 09:51:54,199 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 09:51:54" (1/1) ... [2019-11-20 09:51:54,201 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@74469f10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54, skipping insertion in model container [2019-11-20 09:51:54,201 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 09:51:54" (1/1) ... [2019-11-20 09:51:54,207 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-20 09:51:54,250 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-20 09:51:54,587 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 09:51:54,594 INFO L188 MainTranslator]: Completed pre-run [2019-11-20 09:51:54,681 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 09:51:54,707 INFO L192 MainTranslator]: Completed translation [2019-11-20 09:51:54,708 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54 WrapperNode [2019-11-20 09:51:54,708 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-20 09:51:54,708 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-20 09:51:54,709 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-20 09:51:54,709 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-20 09:51:54,715 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54" (1/1) ... [2019-11-20 09:51:54,727 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54" (1/1) ... [2019-11-20 09:51:54,834 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-20 09:51:54,834 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-20 09:51:54,835 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-20 09:51:54,835 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-20 09:51:54,844 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54" (1/1) ... [2019-11-20 09:51:54,844 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54" (1/1) ... [2019-11-20 09:51:54,859 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54" (1/1) ... [2019-11-20 09:51:54,859 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54" (1/1) ... [2019-11-20 09:51:54,897 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54" (1/1) ... [2019-11-20 09:51:54,938 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54" (1/1) ... [2019-11-20 09:51:54,949 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54" (1/1) ... [2019-11-20 09:51:54,959 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-20 09:51:54,960 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-20 09:51:54,960 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-20 09:51:54,960 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-20 09:51:54,961 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-20 09:51:55,023 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-20 09:51:55,023 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-20 09:51:58,061 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-20 09:51:58,062 INFO L285 CfgBuilder]: Removed 589 assume(true) statements. [2019-11-20 09:51:58,064 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 09:51:58 BoogieIcfgContainer [2019-11-20 09:51:58,064 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-20 09:51:58,065 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-20 09:51:58,065 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-20 09:51:58,067 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-20 09:51:58,068 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.11 09:51:54" (1/3) ... [2019-11-20 09:51:58,072 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@78313759 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 09:51:58, skipping insertion in model container [2019-11-20 09:51:58,072 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 09:51:54" (2/3) ... [2019-11-20 09:51:58,073 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@78313759 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.11 09:51:58, skipping insertion in model container [2019-11-20 09:51:58,073 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 09:51:58" (3/3) ... [2019-11-20 09:51:58,076 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.15.cil.c [2019-11-20 09:51:58,085 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-20 09:51:58,095 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-20 09:51:58,104 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-20 09:51:58,151 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-20 09:51:58,151 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-20 09:51:58,151 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-20 09:51:58,152 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-20 09:51:58,152 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-20 09:51:58,152 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-20 09:51:58,152 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-20 09:51:58,152 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-20 09:51:58,189 INFO L276 IsEmpty]: Start isEmpty. Operand 1886 states. [2019-11-20 09:51:58,202 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:51:58,203 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:51:58,203 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:51:58,204 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:51:58,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:51:58,209 INFO L82 PathProgramCache]: Analyzing trace with hash 735925127, now seen corresponding path program 1 times [2019-11-20 09:51:58,217 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:51:58,217 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30121350] [2019-11-20 09:51:58,218 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:51:58,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:51:58,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:51:58,446 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [30121350] [2019-11-20 09:51:58,446 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:51:58,447 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 09:51:58,448 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1034283662] [2019-11-20 09:51:58,452 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:51:58,453 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:51:58,464 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:51:58,465 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:51:58,467 INFO L87 Difference]: Start difference. First operand 1886 states. Second operand 3 states. [2019-11-20 09:51:58,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:51:58,629 INFO L93 Difference]: Finished difference Result 3767 states and 5677 transitions. [2019-11-20 09:51:58,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:51:58,631 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:51:58,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:51:58,666 INFO L225 Difference]: With dead ends: 3767 [2019-11-20 09:51:58,666 INFO L226 Difference]: Without dead ends: 1882 [2019-11-20 09:51:58,680 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:51:58,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1882 states. [2019-11-20 09:51:58,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1882 to 1882. [2019-11-20 09:51:58,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1882 states. [2019-11-20 09:51:58,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1882 states to 1882 states and 2802 transitions. [2019-11-20 09:51:58,874 INFO L78 Accepts]: Start accepts. Automaton has 1882 states and 2802 transitions. Word has length 167 [2019-11-20 09:51:58,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:51:58,874 INFO L462 AbstractCegarLoop]: Abstraction has 1882 states and 2802 transitions. [2019-11-20 09:51:58,875 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:51:58,875 INFO L276 IsEmpty]: Start isEmpty. Operand 1882 states and 2802 transitions. [2019-11-20 09:51:58,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:51:58,880 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:51:58,880 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:51:58,880 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:51:58,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:51:58,881 INFO L82 PathProgramCache]: Analyzing trace with hash 237368325, now seen corresponding path program 1 times [2019-11-20 09:51:58,882 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:51:58,882 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870846180] [2019-11-20 09:51:58,882 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:51:58,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:51:59,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:51:59,007 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [870846180] [2019-11-20 09:51:59,007 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:51:59,008 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 09:51:59,008 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2099393132] [2019-11-20 09:51:59,011 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:51:59,011 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:51:59,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:51:59,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:51:59,012 INFO L87 Difference]: Start difference. First operand 1882 states and 2802 transitions. Second operand 3 states. [2019-11-20 09:51:59,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:51:59,090 INFO L93 Difference]: Finished difference Result 3751 states and 5582 transitions. [2019-11-20 09:51:59,090 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:51:59,090 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:51:59,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:51:59,101 INFO L225 Difference]: With dead ends: 3751 [2019-11-20 09:51:59,101 INFO L226 Difference]: Without dead ends: 1882 [2019-11-20 09:51:59,105 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:51:59,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1882 states. [2019-11-20 09:51:59,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1882 to 1882. [2019-11-20 09:51:59,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1882 states. [2019-11-20 09:51:59,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1882 states to 1882 states and 2801 transitions. [2019-11-20 09:51:59,160 INFO L78 Accepts]: Start accepts. Automaton has 1882 states and 2801 transitions. Word has length 167 [2019-11-20 09:51:59,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:51:59,162 INFO L462 AbstractCegarLoop]: Abstraction has 1882 states and 2801 transitions. [2019-11-20 09:51:59,162 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:51:59,162 INFO L276 IsEmpty]: Start isEmpty. Operand 1882 states and 2801 transitions. [2019-11-20 09:51:59,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:51:59,169 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:51:59,170 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:51:59,170 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:51:59,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:51:59,170 INFO L82 PathProgramCache]: Analyzing trace with hash 2006839939, now seen corresponding path program 1 times [2019-11-20 09:51:59,171 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:51:59,171 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538509287] [2019-11-20 09:51:59,171 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:51:59,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:51:59,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:51:59,320 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538509287] [2019-11-20 09:51:59,321 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:51:59,321 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:51:59,322 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [506857898] [2019-11-20 09:51:59,323 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:51:59,324 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:51:59,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:51:59,325 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:51:59,325 INFO L87 Difference]: Start difference. First operand 1882 states and 2801 transitions. Second operand 3 states. [2019-11-20 09:51:59,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:51:59,559 INFO L93 Difference]: Finished difference Result 5360 states and 7953 transitions. [2019-11-20 09:51:59,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:51:59,559 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:51:59,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:51:59,580 INFO L225 Difference]: With dead ends: 5360 [2019-11-20 09:51:59,580 INFO L226 Difference]: Without dead ends: 3496 [2019-11-20 09:51:59,584 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:51:59,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3496 states. [2019-11-20 09:51:59,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3496 to 3494. [2019-11-20 09:51:59,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:51:59,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5163 transitions. [2019-11-20 09:51:59,701 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5163 transitions. Word has length 167 [2019-11-20 09:51:59,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:51:59,702 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5163 transitions. [2019-11-20 09:51:59,702 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:51:59,702 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5163 transitions. [2019-11-20 09:51:59,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:51:59,711 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:51:59,711 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:51:59,711 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:51:59,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:51:59,711 INFO L82 PathProgramCache]: Analyzing trace with hash -31533534, now seen corresponding path program 1 times [2019-11-20 09:51:59,712 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:51:59,712 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2067403896] [2019-11-20 09:51:59,712 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:51:59,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:51:59,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:51:59,809 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2067403896] [2019-11-20 09:51:59,809 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:51:59,809 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:51:59,809 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1943519751] [2019-11-20 09:51:59,810 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:51:59,811 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:51:59,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:51:59,811 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:51:59,811 INFO L87 Difference]: Start difference. First operand 3494 states and 5163 transitions. Second operand 3 states. [2019-11-20 09:51:59,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:51:59,944 INFO L93 Difference]: Finished difference Result 6969 states and 10294 transitions. [2019-11-20 09:51:59,944 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:51:59,945 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:51:59,945 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:51:59,964 INFO L225 Difference]: With dead ends: 6969 [2019-11-20 09:51:59,964 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:51:59,970 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:51:59,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:00,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:00,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:00,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5155 transitions. [2019-11-20 09:52:00,174 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5155 transitions. Word has length 167 [2019-11-20 09:52:00,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:00,174 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5155 transitions. [2019-11-20 09:52:00,175 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:00,175 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5155 transitions. [2019-11-20 09:52:00,176 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:00,176 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:00,176 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:00,177 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:00,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:00,177 INFO L82 PathProgramCache]: Analyzing trace with hash -675030430, now seen corresponding path program 1 times [2019-11-20 09:52:00,177 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:00,177 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737127461] [2019-11-20 09:52:00,177 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:00,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:00,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:00,246 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1737127461] [2019-11-20 09:52:00,247 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:00,247 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:00,247 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1711720187] [2019-11-20 09:52:00,247 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:00,248 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:00,248 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:00,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:00,248 INFO L87 Difference]: Start difference. First operand 3494 states and 5155 transitions. Second operand 3 states. [2019-11-20 09:52:00,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:00,382 INFO L93 Difference]: Finished difference Result 6968 states and 10277 transitions. [2019-11-20 09:52:00,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:00,382 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:00,383 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:00,402 INFO L225 Difference]: With dead ends: 6968 [2019-11-20 09:52:00,402 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:00,407 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:00,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:00,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:00,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:00,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5147 transitions. [2019-11-20 09:52:00,534 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5147 transitions. Word has length 167 [2019-11-20 09:52:00,535 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:00,535 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5147 transitions. [2019-11-20 09:52:00,535 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:00,535 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5147 transitions. [2019-11-20 09:52:00,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:00,537 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:00,537 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:00,537 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:00,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:00,538 INFO L82 PathProgramCache]: Analyzing trace with hash -939677920, now seen corresponding path program 1 times [2019-11-20 09:52:00,538 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:00,538 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411777170] [2019-11-20 09:52:00,538 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:00,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:00,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:00,589 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [411777170] [2019-11-20 09:52:00,590 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:00,590 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:00,590 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99578433] [2019-11-20 09:52:00,591 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:00,591 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:00,591 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:00,591 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:00,592 INFO L87 Difference]: Start difference. First operand 3494 states and 5147 transitions. Second operand 3 states. [2019-11-20 09:52:00,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:00,736 INFO L93 Difference]: Finished difference Result 6966 states and 10258 transitions. [2019-11-20 09:52:00,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:00,736 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:00,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:00,755 INFO L225 Difference]: With dead ends: 6966 [2019-11-20 09:52:00,755 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:00,761 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:00,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:00,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:00,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:00,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5139 transitions. [2019-11-20 09:52:00,891 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5139 transitions. Word has length 167 [2019-11-20 09:52:00,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:00,892 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5139 transitions. [2019-11-20 09:52:00,892 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:00,892 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5139 transitions. [2019-11-20 09:52:00,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:00,894 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:00,894 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:00,894 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:00,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:00,897 INFO L82 PathProgramCache]: Analyzing trace with hash 1188104928, now seen corresponding path program 1 times [2019-11-20 09:52:00,898 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:00,898 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940909663] [2019-11-20 09:52:00,898 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:00,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:00,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:00,950 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940909663] [2019-11-20 09:52:00,950 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:00,950 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:00,950 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458236239] [2019-11-20 09:52:00,951 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:00,951 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:00,951 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:00,951 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:00,952 INFO L87 Difference]: Start difference. First operand 3494 states and 5139 transitions. Second operand 3 states. [2019-11-20 09:52:01,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:01,150 INFO L93 Difference]: Finished difference Result 6965 states and 10241 transitions. [2019-11-20 09:52:01,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:01,150 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:01,151 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:01,170 INFO L225 Difference]: With dead ends: 6965 [2019-11-20 09:52:01,170 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:01,175 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:01,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:01,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:01,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:01,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5131 transitions. [2019-11-20 09:52:01,320 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5131 transitions. Word has length 167 [2019-11-20 09:52:01,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:01,321 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5131 transitions. [2019-11-20 09:52:01,321 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:01,321 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5131 transitions. [2019-11-20 09:52:01,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:01,323 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:01,323 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:01,323 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:01,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:01,323 INFO L82 PathProgramCache]: Analyzing trace with hash 841101088, now seen corresponding path program 1 times [2019-11-20 09:52:01,324 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:01,324 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873399665] [2019-11-20 09:52:01,324 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:01,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:01,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:01,373 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873399665] [2019-11-20 09:52:01,373 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:01,373 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:01,373 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091765789] [2019-11-20 09:52:01,374 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:01,374 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:01,374 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:01,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:01,375 INFO L87 Difference]: Start difference. First operand 3494 states and 5131 transitions. Second operand 3 states. [2019-11-20 09:52:01,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:01,518 INFO L93 Difference]: Finished difference Result 6964 states and 10224 transitions. [2019-11-20 09:52:01,518 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:01,519 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:01,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:01,538 INFO L225 Difference]: With dead ends: 6964 [2019-11-20 09:52:01,539 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:01,544 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:01,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:01,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:01,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:01,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5123 transitions. [2019-11-20 09:52:01,685 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5123 transitions. Word has length 167 [2019-11-20 09:52:01,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:01,685 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5123 transitions. [2019-11-20 09:52:01,685 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:01,686 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5123 transitions. [2019-11-20 09:52:01,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:01,687 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:01,687 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:01,688 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:01,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:01,688 INFO L82 PathProgramCache]: Analyzing trace with hash 1107002080, now seen corresponding path program 1 times [2019-11-20 09:52:01,688 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:01,688 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293119678] [2019-11-20 09:52:01,689 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:01,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:01,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:01,737 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [293119678] [2019-11-20 09:52:01,737 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:01,737 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:01,737 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [702421022] [2019-11-20 09:52:01,738 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:01,738 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:01,738 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:01,738 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:01,739 INFO L87 Difference]: Start difference. First operand 3494 states and 5123 transitions. Second operand 3 states. [2019-11-20 09:52:01,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:01,888 INFO L93 Difference]: Finished difference Result 6963 states and 10207 transitions. [2019-11-20 09:52:01,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:01,888 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:01,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:01,897 INFO L225 Difference]: With dead ends: 6963 [2019-11-20 09:52:01,897 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:01,902 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:01,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:02,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:02,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:02,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5115 transitions. [2019-11-20 09:52:02,058 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5115 transitions. Word has length 167 [2019-11-20 09:52:02,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:02,059 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5115 transitions. [2019-11-20 09:52:02,059 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:02,059 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5115 transitions. [2019-11-20 09:52:02,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:02,061 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:02,061 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:02,061 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:02,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:02,062 INFO L82 PathProgramCache]: Analyzing trace with hash 1808316192, now seen corresponding path program 1 times [2019-11-20 09:52:02,062 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:02,062 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138556476] [2019-11-20 09:52:02,062 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:02,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:02,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:02,128 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [138556476] [2019-11-20 09:52:02,128 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:02,128 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:02,129 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872642973] [2019-11-20 09:52:02,129 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:02,129 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:02,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:02,130 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:02,130 INFO L87 Difference]: Start difference. First operand 3494 states and 5115 transitions. Second operand 3 states. [2019-11-20 09:52:02,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:02,393 INFO L93 Difference]: Finished difference Result 6962 states and 10190 transitions. [2019-11-20 09:52:02,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:02,393 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:02,394 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:02,402 INFO L225 Difference]: With dead ends: 6962 [2019-11-20 09:52:02,402 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:02,406 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:02,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:02,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:02,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:02,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5107 transitions. [2019-11-20 09:52:02,547 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5107 transitions. Word has length 167 [2019-11-20 09:52:02,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:02,547 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5107 transitions. [2019-11-20 09:52:02,547 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:02,548 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5107 transitions. [2019-11-20 09:52:02,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:02,549 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:02,549 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:02,550 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:02,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:02,550 INFO L82 PathProgramCache]: Analyzing trace with hash 1969486560, now seen corresponding path program 1 times [2019-11-20 09:52:02,550 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:02,551 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765275863] [2019-11-20 09:52:02,551 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:02,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:02,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:02,600 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765275863] [2019-11-20 09:52:02,601 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:02,601 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:02,601 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249780035] [2019-11-20 09:52:02,602 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:02,602 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:02,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:02,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:02,602 INFO L87 Difference]: Start difference. First operand 3494 states and 5107 transitions. Second operand 3 states. [2019-11-20 09:52:02,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:02,770 INFO L93 Difference]: Finished difference Result 6961 states and 10173 transitions. [2019-11-20 09:52:02,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:02,770 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:02,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:02,778 INFO L225 Difference]: With dead ends: 6961 [2019-11-20 09:52:02,778 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:02,783 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:02,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:02,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:02,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:02,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5099 transitions. [2019-11-20 09:52:02,934 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5099 transitions. Word has length 167 [2019-11-20 09:52:02,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:02,934 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5099 transitions. [2019-11-20 09:52:02,934 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:02,935 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5099 transitions. [2019-11-20 09:52:02,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:02,936 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:02,937 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:02,937 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:02,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:02,937 INFO L82 PathProgramCache]: Analyzing trace with hash 1836138272, now seen corresponding path program 1 times [2019-11-20 09:52:02,937 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:02,938 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997277456] [2019-11-20 09:52:02,938 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:02,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:02,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:02,986 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1997277456] [2019-11-20 09:52:02,986 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:02,986 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:02,986 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764794933] [2019-11-20 09:52:02,987 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:02,987 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:02,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:02,987 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:02,988 INFO L87 Difference]: Start difference. First operand 3494 states and 5099 transitions. Second operand 3 states. [2019-11-20 09:52:03,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:03,159 INFO L93 Difference]: Finished difference Result 6960 states and 10156 transitions. [2019-11-20 09:52:03,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:03,159 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:03,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:03,166 INFO L225 Difference]: With dead ends: 6960 [2019-11-20 09:52:03,166 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:03,171 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:03,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:03,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:03,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:03,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5091 transitions. [2019-11-20 09:52:03,329 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5091 transitions. Word has length 167 [2019-11-20 09:52:03,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:03,329 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5091 transitions. [2019-11-20 09:52:03,330 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:03,330 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5091 transitions. [2019-11-20 09:52:03,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:03,331 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:03,332 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:03,332 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:03,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:03,335 INFO L82 PathProgramCache]: Analyzing trace with hash -2048218658, now seen corresponding path program 1 times [2019-11-20 09:52:03,336 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:03,336 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501607919] [2019-11-20 09:52:03,336 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:03,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:03,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:03,399 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501607919] [2019-11-20 09:52:03,399 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:03,400 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:03,400 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [813926036] [2019-11-20 09:52:03,400 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:03,400 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:03,401 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:03,401 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:03,401 INFO L87 Difference]: Start difference. First operand 3494 states and 5091 transitions. Second operand 3 states. [2019-11-20 09:52:03,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:03,623 INFO L93 Difference]: Finished difference Result 6958 states and 10137 transitions. [2019-11-20 09:52:03,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:03,623 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:03,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:03,630 INFO L225 Difference]: With dead ends: 6958 [2019-11-20 09:52:03,630 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:03,635 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:03,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:03,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:03,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:03,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5083 transitions. [2019-11-20 09:52:03,799 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5083 transitions. Word has length 167 [2019-11-20 09:52:03,800 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:03,800 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5083 transitions. [2019-11-20 09:52:03,800 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:03,801 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5083 transitions. [2019-11-20 09:52:03,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:03,802 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:03,802 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:03,803 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:03,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:03,803 INFO L82 PathProgramCache]: Analyzing trace with hash 2034093470, now seen corresponding path program 1 times [2019-11-20 09:52:03,803 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:03,807 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479248670] [2019-11-20 09:52:03,807 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:03,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:03,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:03,875 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [479248670] [2019-11-20 09:52:03,875 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:03,875 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:03,875 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193910728] [2019-11-20 09:52:03,876 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:03,876 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:03,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:03,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:03,877 INFO L87 Difference]: Start difference. First operand 3494 states and 5083 transitions. Second operand 3 states. [2019-11-20 09:52:04,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:04,066 INFO L93 Difference]: Finished difference Result 6957 states and 10120 transitions. [2019-11-20 09:52:04,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:04,067 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:04,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:04,073 INFO L225 Difference]: With dead ends: 6957 [2019-11-20 09:52:04,073 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:04,080 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:04,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:04,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:04,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:04,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5075 transitions. [2019-11-20 09:52:04,248 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5075 transitions. Word has length 167 [2019-11-20 09:52:04,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:04,248 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5075 transitions. [2019-11-20 09:52:04,249 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:04,249 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5075 transitions. [2019-11-20 09:52:04,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:04,251 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:04,251 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:04,251 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:04,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:04,251 INFO L82 PathProgramCache]: Analyzing trace with hash -2129186338, now seen corresponding path program 1 times [2019-11-20 09:52:04,252 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:04,252 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [527609741] [2019-11-20 09:52:04,252 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:04,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:04,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:04,319 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [527609741] [2019-11-20 09:52:04,319 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:04,319 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:04,319 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872068006] [2019-11-20 09:52:04,320 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:04,320 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:04,320 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:04,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:04,321 INFO L87 Difference]: Start difference. First operand 3494 states and 5075 transitions. Second operand 3 states. [2019-11-20 09:52:04,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:04,535 INFO L93 Difference]: Finished difference Result 6956 states and 10103 transitions. [2019-11-20 09:52:04,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:04,535 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:04,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:04,542 INFO L225 Difference]: With dead ends: 6956 [2019-11-20 09:52:04,542 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:04,549 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:04,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:04,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:04,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:04,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5039 transitions. [2019-11-20 09:52:04,727 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5039 transitions. Word has length 167 [2019-11-20 09:52:04,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:04,727 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5039 transitions. [2019-11-20 09:52:04,727 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:04,728 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5039 transitions. [2019-11-20 09:52:04,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:04,729 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:04,729 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:04,730 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:04,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:04,730 INFO L82 PathProgramCache]: Analyzing trace with hash 904313021, now seen corresponding path program 1 times [2019-11-20 09:52:04,730 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:04,730 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787822293] [2019-11-20 09:52:04,730 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:04,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:04,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:04,795 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [787822293] [2019-11-20 09:52:04,797 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:04,797 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:04,798 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854697022] [2019-11-20 09:52:04,798 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:04,798 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:04,799 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:04,799 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:04,799 INFO L87 Difference]: Start difference. First operand 3494 states and 5039 transitions. Second operand 3 states. [2019-11-20 09:52:05,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:05,065 INFO L93 Difference]: Finished difference Result 6955 states and 10030 transitions. [2019-11-20 09:52:05,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:05,066 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:05,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:05,074 INFO L225 Difference]: With dead ends: 6955 [2019-11-20 09:52:05,074 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:05,079 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:05,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:05,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:05,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:05,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5003 transitions. [2019-11-20 09:52:05,301 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5003 transitions. Word has length 167 [2019-11-20 09:52:05,301 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:05,301 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5003 transitions. [2019-11-20 09:52:05,301 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:05,302 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5003 transitions. [2019-11-20 09:52:05,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:05,304 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:05,304 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:05,304 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:05,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:05,305 INFO L82 PathProgramCache]: Analyzing trace with hash -2125714179, now seen corresponding path program 1 times [2019-11-20 09:52:05,305 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:05,305 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323865960] [2019-11-20 09:52:05,305 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:05,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:05,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:05,456 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323865960] [2019-11-20 09:52:05,457 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:05,457 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:05,457 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004199011] [2019-11-20 09:52:05,457 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:05,458 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:05,458 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:05,458 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:05,458 INFO L87 Difference]: Start difference. First operand 3494 states and 5003 transitions. Second operand 3 states. [2019-11-20 09:52:05,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:05,684 INFO L93 Difference]: Finished difference Result 6954 states and 9957 transitions. [2019-11-20 09:52:05,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:05,685 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:05,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:05,692 INFO L225 Difference]: With dead ends: 6954 [2019-11-20 09:52:05,692 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:05,699 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:05,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:05,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:05,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:05,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4967 transitions. [2019-11-20 09:52:05,866 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4967 transitions. Word has length 167 [2019-11-20 09:52:05,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:05,866 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4967 transitions. [2019-11-20 09:52:05,866 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:05,867 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4967 transitions. [2019-11-20 09:52:05,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:05,868 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:05,868 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:05,869 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:05,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:05,869 INFO L82 PathProgramCache]: Analyzing trace with hash 1803688540, now seen corresponding path program 1 times [2019-11-20 09:52:05,869 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:05,870 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326823313] [2019-11-20 09:52:05,870 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:05,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:05,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:05,928 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326823313] [2019-11-20 09:52:05,928 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:05,928 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:05,928 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1287658902] [2019-11-20 09:52:05,929 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:05,933 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:05,933 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:05,933 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:05,934 INFO L87 Difference]: Start difference. First operand 3494 states and 4967 transitions. Second operand 3 states. [2019-11-20 09:52:06,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:06,136 INFO L93 Difference]: Finished difference Result 6953 states and 9884 transitions. [2019-11-20 09:52:06,137 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:06,137 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:06,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:06,144 INFO L225 Difference]: With dead ends: 6953 [2019-11-20 09:52:06,144 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:06,150 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:06,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:06,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:06,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:06,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4931 transitions. [2019-11-20 09:52:06,317 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4931 transitions. Word has length 167 [2019-11-20 09:52:06,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:06,317 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4931 transitions. [2019-11-20 09:52:06,317 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:06,317 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4931 transitions. [2019-11-20 09:52:06,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:06,319 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:06,319 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:06,320 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:06,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:06,320 INFO L82 PathProgramCache]: Analyzing trace with hash -1908957540, now seen corresponding path program 1 times [2019-11-20 09:52:06,321 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:06,322 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225845806] [2019-11-20 09:52:06,322 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:06,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:06,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:06,372 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225845806] [2019-11-20 09:52:06,372 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:06,372 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:06,373 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231609257] [2019-11-20 09:52:06,374 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:06,374 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:06,374 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:06,374 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:06,375 INFO L87 Difference]: Start difference. First operand 3494 states and 4931 transitions. Second operand 3 states. [2019-11-20 09:52:06,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:06,570 INFO L93 Difference]: Finished difference Result 6952 states and 9811 transitions. [2019-11-20 09:52:06,570 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:06,571 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:06,571 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:06,578 INFO L225 Difference]: With dead ends: 6952 [2019-11-20 09:52:06,578 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:06,586 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:06,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:06,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:06,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:06,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4895 transitions. [2019-11-20 09:52:06,737 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4895 transitions. Word has length 167 [2019-11-20 09:52:06,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:06,737 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4895 transitions. [2019-11-20 09:52:06,737 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:06,737 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4895 transitions. [2019-11-20 09:52:06,739 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:06,739 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:06,739 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:06,739 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:06,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:06,740 INFO L82 PathProgramCache]: Analyzing trace with hash 1048299385, now seen corresponding path program 1 times [2019-11-20 09:52:06,740 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:06,740 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149896778] [2019-11-20 09:52:06,740 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:06,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:06,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:06,801 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149896778] [2019-11-20 09:52:06,801 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:06,801 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:06,802 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069305375] [2019-11-20 09:52:06,802 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:06,802 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:06,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:06,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:06,803 INFO L87 Difference]: Start difference. First operand 3494 states and 4895 transitions. Second operand 3 states. [2019-11-20 09:52:07,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:07,028 INFO L93 Difference]: Finished difference Result 6950 states and 9736 transitions. [2019-11-20 09:52:07,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:07,028 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:07,028 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:07,035 INFO L225 Difference]: With dead ends: 6950 [2019-11-20 09:52:07,035 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:07,039 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:07,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:07,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:07,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:07,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4859 transitions. [2019-11-20 09:52:07,183 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4859 transitions. Word has length 167 [2019-11-20 09:52:07,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:07,183 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4859 transitions. [2019-11-20 09:52:07,183 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:07,183 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4859 transitions. [2019-11-20 09:52:07,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:07,185 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:07,185 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:07,186 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:07,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:07,186 INFO L82 PathProgramCache]: Analyzing trace with hash 1051443672, now seen corresponding path program 1 times [2019-11-20 09:52:07,186 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:07,187 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073193455] [2019-11-20 09:52:07,187 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:07,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:07,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:07,257 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2073193455] [2019-11-20 09:52:07,257 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:07,258 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:07,258 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853317524] [2019-11-20 09:52:07,258 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:07,258 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:07,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:07,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:07,259 INFO L87 Difference]: Start difference. First operand 3494 states and 4859 transitions. Second operand 3 states. [2019-11-20 09:52:07,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:07,434 INFO L93 Difference]: Finished difference Result 6949 states and 9663 transitions. [2019-11-20 09:52:07,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:07,435 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:07,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:07,441 INFO L225 Difference]: With dead ends: 6949 [2019-11-20 09:52:07,442 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:07,446 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:07,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:07,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:07,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:07,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4823 transitions. [2019-11-20 09:52:07,593 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4823 transitions. Word has length 167 [2019-11-20 09:52:07,593 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:07,593 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4823 transitions. [2019-11-20 09:52:07,593 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:07,593 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4823 transitions. [2019-11-20 09:52:07,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:07,595 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:07,595 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:07,596 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:07,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:07,596 INFO L82 PathProgramCache]: Analyzing trace with hash -1890753000, now seen corresponding path program 1 times [2019-11-20 09:52:07,596 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:07,596 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971355750] [2019-11-20 09:52:07,597 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:07,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:07,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:07,650 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971355750] [2019-11-20 09:52:07,650 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:07,650 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:07,651 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [989771459] [2019-11-20 09:52:07,651 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:07,651 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:07,651 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:07,652 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:07,652 INFO L87 Difference]: Start difference. First operand 3494 states and 4823 transitions. Second operand 3 states. [2019-11-20 09:52:07,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:07,829 INFO L93 Difference]: Finished difference Result 6948 states and 9590 transitions. [2019-11-20 09:52:07,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:07,830 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:07,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:07,836 INFO L225 Difference]: With dead ends: 6948 [2019-11-20 09:52:07,836 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:07,841 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:07,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:07,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:07,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:07,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4787 transitions. [2019-11-20 09:52:07,986 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4787 transitions. Word has length 167 [2019-11-20 09:52:07,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:07,986 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4787 transitions. [2019-11-20 09:52:07,986 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:07,986 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4787 transitions. [2019-11-20 09:52:07,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:07,988 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:07,988 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:07,989 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:07,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:07,989 INFO L82 PathProgramCache]: Analyzing trace with hash 2068907767, now seen corresponding path program 1 times [2019-11-20 09:52:07,989 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:07,989 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794653425] [2019-11-20 09:52:07,990 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:08,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:08,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:08,062 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794653425] [2019-11-20 09:52:08,062 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:08,062 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:08,064 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [472079524] [2019-11-20 09:52:08,064 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:08,068 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:08,069 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:08,069 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:08,069 INFO L87 Difference]: Start difference. First operand 3494 states and 4787 transitions. Second operand 3 states. [2019-11-20 09:52:08,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:08,248 INFO L93 Difference]: Finished difference Result 6947 states and 9517 transitions. [2019-11-20 09:52:08,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:08,249 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:08,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:08,255 INFO L225 Difference]: With dead ends: 6947 [2019-11-20 09:52:08,255 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:08,259 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:08,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:08,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:08,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:08,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4751 transitions. [2019-11-20 09:52:08,419 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4751 transitions. Word has length 167 [2019-11-20 09:52:08,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:08,420 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4751 transitions. [2019-11-20 09:52:08,420 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:08,422 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4751 transitions. [2019-11-20 09:52:08,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:08,424 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:08,424 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:08,424 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:08,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:08,426 INFO L82 PathProgramCache]: Analyzing trace with hash -1861907562, now seen corresponding path program 1 times [2019-11-20 09:52:08,426 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:08,426 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103776142] [2019-11-20 09:52:08,426 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:08,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:08,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:08,499 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [103776142] [2019-11-20 09:52:08,500 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:08,500 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:08,500 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093438036] [2019-11-20 09:52:08,500 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:08,501 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:08,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:08,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:08,502 INFO L87 Difference]: Start difference. First operand 3494 states and 4751 transitions. Second operand 3 states. [2019-11-20 09:52:08,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:08,734 INFO L93 Difference]: Finished difference Result 6946 states and 9444 transitions. [2019-11-20 09:52:08,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:08,735 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:08,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:08,741 INFO L225 Difference]: With dead ends: 6946 [2019-11-20 09:52:08,741 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:08,747 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:08,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:08,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:08,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:08,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4715 transitions. [2019-11-20 09:52:08,942 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4715 transitions. Word has length 167 [2019-11-20 09:52:08,942 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:08,942 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4715 transitions. [2019-11-20 09:52:08,942 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:08,942 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4715 transitions. [2019-11-20 09:52:08,944 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:08,944 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:08,944 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:08,945 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:08,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:08,945 INFO L82 PathProgramCache]: Analyzing trace with hash 723537750, now seen corresponding path program 1 times [2019-11-20 09:52:08,945 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:08,945 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303847100] [2019-11-20 09:52:08,946 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:08,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:09,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:09,004 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303847100] [2019-11-20 09:52:09,004 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:09,004 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:09,004 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821683882] [2019-11-20 09:52:09,005 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:09,005 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:09,005 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:09,005 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:09,005 INFO L87 Difference]: Start difference. First operand 3494 states and 4715 transitions. Second operand 3 states. [2019-11-20 09:52:09,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:09,197 INFO L93 Difference]: Finished difference Result 6945 states and 9371 transitions. [2019-11-20 09:52:09,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:09,197 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:09,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:09,203 INFO L225 Difference]: With dead ends: 6945 [2019-11-20 09:52:09,203 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:09,207 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:09,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:09,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:09,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:09,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4679 transitions. [2019-11-20 09:52:09,355 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4679 transitions. Word has length 167 [2019-11-20 09:52:09,355 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:09,356 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4679 transitions. [2019-11-20 09:52:09,356 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:09,356 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4679 transitions. [2019-11-20 09:52:09,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:09,357 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:09,358 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:09,358 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:09,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:09,358 INFO L82 PathProgramCache]: Analyzing trace with hash 1570454133, now seen corresponding path program 1 times [2019-11-20 09:52:09,358 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:09,359 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1928541924] [2019-11-20 09:52:09,359 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:09,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:09,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:09,409 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1928541924] [2019-11-20 09:52:09,410 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:09,410 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:09,410 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [576805665] [2019-11-20 09:52:09,411 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:09,411 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:09,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:09,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:09,412 INFO L87 Difference]: Start difference. First operand 3494 states and 4679 transitions. Second operand 3 states. [2019-11-20 09:52:09,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:09,605 INFO L93 Difference]: Finished difference Result 6944 states and 9298 transitions. [2019-11-20 09:52:09,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:09,606 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:09,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:09,611 INFO L225 Difference]: With dead ends: 6944 [2019-11-20 09:52:09,611 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:09,616 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:09,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:09,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:09,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:09,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4643 transitions. [2019-11-20 09:52:09,767 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4643 transitions. Word has length 167 [2019-11-20 09:52:09,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:09,767 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4643 transitions. [2019-11-20 09:52:09,767 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:09,768 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4643 transitions. [2019-11-20 09:52:09,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:09,769 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:09,770 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:09,770 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:09,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:09,770 INFO L82 PathProgramCache]: Analyzing trace with hash -1777475277, now seen corresponding path program 1 times [2019-11-20 09:52:09,770 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:09,771 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201676108] [2019-11-20 09:52:09,771 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:09,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:09,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:09,849 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [201676108] [2019-11-20 09:52:09,849 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:09,850 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:09,850 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366228203] [2019-11-20 09:52:09,850 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:09,850 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:09,851 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:09,851 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:09,851 INFO L87 Difference]: Start difference. First operand 3494 states and 4643 transitions. Second operand 3 states. [2019-11-20 09:52:10,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:10,012 INFO L93 Difference]: Finished difference Result 6967 states and 9252 transitions. [2019-11-20 09:52:10,013 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:10,013 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:10,013 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:10,019 INFO L225 Difference]: With dead ends: 6967 [2019-11-20 09:52:10,019 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:10,023 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:10,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:10,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:10,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:10,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4635 transitions. [2019-11-20 09:52:10,184 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4635 transitions. Word has length 167 [2019-11-20 09:52:10,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:10,185 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4635 transitions. [2019-11-20 09:52:10,185 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:10,185 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4635 transitions. [2019-11-20 09:52:10,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:10,186 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:10,187 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:10,187 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:10,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:10,187 INFO L82 PathProgramCache]: Analyzing trace with hash 2123125233, now seen corresponding path program 1 times [2019-11-20 09:52:10,187 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:10,187 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640875893] [2019-11-20 09:52:10,188 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:10,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:10,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:10,266 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640875893] [2019-11-20 09:52:10,266 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:10,266 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:10,266 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1710284990] [2019-11-20 09:52:10,267 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:10,267 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:10,267 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:10,267 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:10,267 INFO L87 Difference]: Start difference. First operand 3494 states and 4635 transitions. Second operand 3 states. [2019-11-20 09:52:10,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:10,475 INFO L93 Difference]: Finished difference Result 6959 states and 9228 transitions. [2019-11-20 09:52:10,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:10,476 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:10,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:10,481 INFO L225 Difference]: With dead ends: 6959 [2019-11-20 09:52:10,481 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:10,484 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:10,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:10,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:10,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:10,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4627 transitions. [2019-11-20 09:52:10,641 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4627 transitions. Word has length 167 [2019-11-20 09:52:10,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:10,641 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4627 transitions. [2019-11-20 09:52:10,641 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:10,642 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4627 transitions. [2019-11-20 09:52:10,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:10,643 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:10,643 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:10,644 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:10,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:10,644 INFO L82 PathProgramCache]: Analyzing trace with hash 1613652143, now seen corresponding path program 1 times [2019-11-20 09:52:10,645 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:10,645 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178282292] [2019-11-20 09:52:10,645 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:10,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:10,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:10,729 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [178282292] [2019-11-20 09:52:10,730 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:10,730 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 09:52:10,730 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1598623855] [2019-11-20 09:52:10,731 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:10,731 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:10,731 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:10,731 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:10,731 INFO L87 Difference]: Start difference. First operand 3494 states and 4627 transitions. Second operand 3 states. [2019-11-20 09:52:10,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:10,945 INFO L93 Difference]: Finished difference Result 6951 states and 9204 transitions. [2019-11-20 09:52:10,945 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:10,945 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:10,946 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:10,951 INFO L225 Difference]: With dead ends: 6951 [2019-11-20 09:52:10,951 INFO L226 Difference]: Without dead ends: 3494 [2019-11-20 09:52:10,956 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:10,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-11-20 09:52:11,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-11-20 09:52:11,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-11-20 09:52:11,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4591 transitions. [2019-11-20 09:52:11,119 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4591 transitions. Word has length 167 [2019-11-20 09:52:11,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:11,120 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4591 transitions. [2019-11-20 09:52:11,120 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:11,120 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4591 transitions. [2019-11-20 09:52:11,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-11-20 09:52:11,122 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:11,122 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:11,122 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:11,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:11,123 INFO L82 PathProgramCache]: Analyzing trace with hash 796003693, now seen corresponding path program 1 times [2019-11-20 09:52:11,123 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:11,123 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641638004] [2019-11-20 09:52:11,123 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:11,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:11,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:11,190 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1641638004] [2019-11-20 09:52:11,190 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:11,191 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 09:52:11,192 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2028224241] [2019-11-20 09:52:11,193 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-20 09:52:11,193 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:11,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 09:52:11,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:11,194 INFO L87 Difference]: Start difference. First operand 3494 states and 4591 transitions. Second operand 3 states. [2019-11-20 09:52:11,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:11,566 INFO L93 Difference]: Finished difference Result 10209 states and 13370 transitions. [2019-11-20 09:52:11,566 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 09:52:11,566 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-11-20 09:52:11,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:11,578 INFO L225 Difference]: With dead ends: 10209 [2019-11-20 09:52:11,578 INFO L226 Difference]: Without dead ends: 6884 [2019-11-20 09:52:11,583 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 09:52:11,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6884 states. [2019-11-20 09:52:11,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6884 to 6694. [2019-11-20 09:52:11,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6694 states. [2019-11-20 09:52:11,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6694 states to 6694 states and 8737 transitions. [2019-11-20 09:52:11,915 INFO L78 Accepts]: Start accepts. Automaton has 6694 states and 8737 transitions. Word has length 167 [2019-11-20 09:52:11,916 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:11,916 INFO L462 AbstractCegarLoop]: Abstraction has 6694 states and 8737 transitions. [2019-11-20 09:52:11,916 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-20 09:52:11,916 INFO L276 IsEmpty]: Start isEmpty. Operand 6694 states and 8737 transitions. [2019-11-20 09:52:11,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:11,918 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:11,919 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:11,919 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:11,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:11,919 INFO L82 PathProgramCache]: Analyzing trace with hash -1437788242, now seen corresponding path program 1 times [2019-11-20 09:52:11,919 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:11,920 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713821510] [2019-11-20 09:52:11,920 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:11,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:12,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:12,010 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [713821510] [2019-11-20 09:52:12,010 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:12,010 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:12,010 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1679310057] [2019-11-20 09:52:12,011 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:12,011 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:12,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:12,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:12,012 INFO L87 Difference]: Start difference. First operand 6694 states and 8737 transitions. Second operand 5 states. [2019-11-20 09:52:13,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:13,276 INFO L93 Difference]: Finished difference Result 18864 states and 24680 transitions. [2019-11-20 09:52:13,276 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:13,277 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:13,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:13,295 INFO L225 Difference]: With dead ends: 18864 [2019-11-20 09:52:13,295 INFO L226 Difference]: Without dead ends: 12386 [2019-11-20 09:52:13,302 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:13,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12386 states. [2019-11-20 09:52:13,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12386 to 6781. [2019-11-20 09:52:13,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6781 states. [2019-11-20 09:52:13,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6781 states to 6781 states and 8795 transitions. [2019-11-20 09:52:13,756 INFO L78 Accepts]: Start accepts. Automaton has 6781 states and 8795 transitions. Word has length 168 [2019-11-20 09:52:13,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:13,756 INFO L462 AbstractCegarLoop]: Abstraction has 6781 states and 8795 transitions. [2019-11-20 09:52:13,756 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:13,756 INFO L276 IsEmpty]: Start isEmpty. Operand 6781 states and 8795 transitions. [2019-11-20 09:52:13,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:13,758 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:13,759 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:13,759 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:13,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:13,760 INFO L82 PathProgramCache]: Analyzing trace with hash 1575006768, now seen corresponding path program 1 times [2019-11-20 09:52:13,760 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:13,760 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [964682639] [2019-11-20 09:52:13,760 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:13,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:13,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:13,846 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [964682639] [2019-11-20 09:52:13,847 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:13,847 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:13,847 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741986167] [2019-11-20 09:52:13,848 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:13,848 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:13,848 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:13,849 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:13,849 INFO L87 Difference]: Start difference. First operand 6781 states and 8795 transitions. Second operand 5 states. [2019-11-20 09:52:14,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:14,657 INFO L93 Difference]: Finished difference Result 15355 states and 20058 transitions. [2019-11-20 09:52:14,658 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:14,658 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:14,658 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:14,673 INFO L225 Difference]: With dead ends: 15355 [2019-11-20 09:52:14,673 INFO L226 Difference]: Without dead ends: 8686 [2019-11-20 09:52:14,680 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:14,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8686 states. [2019-11-20 09:52:15,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8686 to 6787. [2019-11-20 09:52:15,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6787 states. [2019-11-20 09:52:15,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6787 states to 6787 states and 8745 transitions. [2019-11-20 09:52:15,181 INFO L78 Accepts]: Start accepts. Automaton has 6787 states and 8745 transitions. Word has length 168 [2019-11-20 09:52:15,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:15,181 INFO L462 AbstractCegarLoop]: Abstraction has 6787 states and 8745 transitions. [2019-11-20 09:52:15,182 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:15,182 INFO L276 IsEmpty]: Start isEmpty. Operand 6787 states and 8745 transitions. [2019-11-20 09:52:15,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:15,186 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:15,186 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:15,186 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:15,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:15,187 INFO L82 PathProgramCache]: Analyzing trace with hash -992815566, now seen corresponding path program 1 times [2019-11-20 09:52:15,187 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:15,187 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853395269] [2019-11-20 09:52:15,187 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:15,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:15,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:15,335 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853395269] [2019-11-20 09:52:15,335 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:15,335 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:15,336 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624153499] [2019-11-20 09:52:15,336 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:15,336 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:15,336 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:15,337 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:15,337 INFO L87 Difference]: Start difference. First operand 6787 states and 8745 transitions. Second operand 5 states. [2019-11-20 09:52:16,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:16,215 INFO L93 Difference]: Finished difference Result 16335 states and 21156 transitions. [2019-11-20 09:52:16,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:16,216 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:16,216 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:16,228 INFO L225 Difference]: With dead ends: 16335 [2019-11-20 09:52:16,228 INFO L226 Difference]: Without dead ends: 9688 [2019-11-20 09:52:16,235 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:16,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9688 states. [2019-11-20 09:52:16,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9688 to 6799. [2019-11-20 09:52:16,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6799 states. [2019-11-20 09:52:16,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6799 states to 6799 states and 8703 transitions. [2019-11-20 09:52:16,777 INFO L78 Accepts]: Start accepts. Automaton has 6799 states and 8703 transitions. Word has length 168 [2019-11-20 09:52:16,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:16,778 INFO L462 AbstractCegarLoop]: Abstraction has 6799 states and 8703 transitions. [2019-11-20 09:52:16,778 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:16,778 INFO L276 IsEmpty]: Start isEmpty. Operand 6799 states and 8703 transitions. [2019-11-20 09:52:16,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:16,779 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:16,780 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:16,780 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:16,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:16,780 INFO L82 PathProgramCache]: Analyzing trace with hash 1995009332, now seen corresponding path program 1 times [2019-11-20 09:52:16,780 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:16,781 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078799532] [2019-11-20 09:52:16,781 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:16,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:16,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:16,871 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078799532] [2019-11-20 09:52:16,871 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:16,872 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:16,872 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724305718] [2019-11-20 09:52:16,872 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:16,872 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:16,873 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:16,873 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:16,873 INFO L87 Difference]: Start difference. First operand 6799 states and 8703 transitions. Second operand 5 states. [2019-11-20 09:52:17,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:17,713 INFO L93 Difference]: Finished difference Result 16679 states and 21436 transitions. [2019-11-20 09:52:17,714 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:17,714 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:17,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:17,723 INFO L225 Difference]: With dead ends: 16679 [2019-11-20 09:52:17,724 INFO L226 Difference]: Without dead ends: 10034 [2019-11-20 09:52:17,730 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:17,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10034 states. [2019-11-20 09:52:18,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10034 to 6811. [2019-11-20 09:52:18,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6811 states. [2019-11-20 09:52:18,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6811 states to 6811 states and 8661 transitions. [2019-11-20 09:52:18,268 INFO L78 Accepts]: Start accepts. Automaton has 6811 states and 8661 transitions. Word has length 168 [2019-11-20 09:52:18,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:18,268 INFO L462 AbstractCegarLoop]: Abstraction has 6811 states and 8661 transitions. [2019-11-20 09:52:18,268 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:18,268 INFO L276 IsEmpty]: Start isEmpty. Operand 6811 states and 8661 transitions. [2019-11-20 09:52:18,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:18,270 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:18,270 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:18,270 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:18,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:18,271 INFO L82 PathProgramCache]: Analyzing trace with hash -948572746, now seen corresponding path program 1 times [2019-11-20 09:52:18,271 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:18,271 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209676785] [2019-11-20 09:52:18,271 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:18,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:18,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:18,345 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209676785] [2019-11-20 09:52:18,346 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:18,346 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:18,346 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857123159] [2019-11-20 09:52:18,346 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:18,347 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:18,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:18,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:18,347 INFO L87 Difference]: Start difference. First operand 6811 states and 8661 transitions. Second operand 5 states. [2019-11-20 09:52:19,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:19,219 INFO L93 Difference]: Finished difference Result 17023 states and 21716 transitions. [2019-11-20 09:52:19,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:19,219 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:19,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:19,226 INFO L225 Difference]: With dead ends: 17023 [2019-11-20 09:52:19,226 INFO L226 Difference]: Without dead ends: 10380 [2019-11-20 09:52:19,234 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:19,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10380 states. [2019-11-20 09:52:19,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10380 to 6823. [2019-11-20 09:52:19,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6823 states. [2019-11-20 09:52:19,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6823 states to 6823 states and 8619 transitions. [2019-11-20 09:52:19,666 INFO L78 Accepts]: Start accepts. Automaton has 6823 states and 8619 transitions. Word has length 168 [2019-11-20 09:52:19,667 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:19,667 INFO L462 AbstractCegarLoop]: Abstraction has 6823 states and 8619 transitions. [2019-11-20 09:52:19,667 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:19,667 INFO L276 IsEmpty]: Start isEmpty. Operand 6823 states and 8619 transitions. [2019-11-20 09:52:19,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:19,668 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:19,668 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:19,668 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:19,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:19,669 INFO L82 PathProgramCache]: Analyzing trace with hash -1719306312, now seen corresponding path program 1 times [2019-11-20 09:52:19,669 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:19,669 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704940287] [2019-11-20 09:52:19,669 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:19,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:19,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:19,753 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704940287] [2019-11-20 09:52:19,753 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:19,754 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:19,754 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1944848139] [2019-11-20 09:52:19,754 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:19,754 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:19,755 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:19,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:19,755 INFO L87 Difference]: Start difference. First operand 6823 states and 8619 transitions. Second operand 5 states. [2019-11-20 09:52:20,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:20,682 INFO L93 Difference]: Finished difference Result 17367 states and 21996 transitions. [2019-11-20 09:52:20,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:20,682 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:20,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:20,689 INFO L225 Difference]: With dead ends: 17367 [2019-11-20 09:52:20,689 INFO L226 Difference]: Without dead ends: 10726 [2019-11-20 09:52:20,695 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:20,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10726 states. [2019-11-20 09:52:21,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10726 to 6835. [2019-11-20 09:52:21,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6835 states. [2019-11-20 09:52:21,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6835 states to 6835 states and 8577 transitions. [2019-11-20 09:52:21,278 INFO L78 Accepts]: Start accepts. Automaton has 6835 states and 8577 transitions. Word has length 168 [2019-11-20 09:52:21,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:21,278 INFO L462 AbstractCegarLoop]: Abstraction has 6835 states and 8577 transitions. [2019-11-20 09:52:21,278 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:21,278 INFO L276 IsEmpty]: Start isEmpty. Operand 6835 states and 8577 transitions. [2019-11-20 09:52:21,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:21,279 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:21,280 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:21,280 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:21,280 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:21,280 INFO L82 PathProgramCache]: Analyzing trace with hash -394450118, now seen corresponding path program 1 times [2019-11-20 09:52:21,280 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:21,280 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229933618] [2019-11-20 09:52:21,280 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:21,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:21,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:21,352 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229933618] [2019-11-20 09:52:21,352 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:21,352 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:21,353 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [558899595] [2019-11-20 09:52:21,353 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:21,353 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:21,353 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:21,354 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:21,354 INFO L87 Difference]: Start difference. First operand 6835 states and 8577 transitions. Second operand 5 states. [2019-11-20 09:52:22,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:22,297 INFO L93 Difference]: Finished difference Result 17711 states and 22276 transitions. [2019-11-20 09:52:22,298 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:22,298 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:22,298 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:22,306 INFO L225 Difference]: With dead ends: 17711 [2019-11-20 09:52:22,306 INFO L226 Difference]: Without dead ends: 11072 [2019-11-20 09:52:22,311 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:22,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11072 states. [2019-11-20 09:52:23,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11072 to 6847. [2019-11-20 09:52:23,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6847 states. [2019-11-20 09:52:23,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6847 states to 6847 states and 8535 transitions. [2019-11-20 09:52:23,024 INFO L78 Accepts]: Start accepts. Automaton has 6847 states and 8535 transitions. Word has length 168 [2019-11-20 09:52:23,024 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:23,024 INFO L462 AbstractCegarLoop]: Abstraction has 6847 states and 8535 transitions. [2019-11-20 09:52:23,024 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:23,025 INFO L276 IsEmpty]: Start isEmpty. Operand 6847 states and 8535 transitions. [2019-11-20 09:52:23,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:23,026 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:23,026 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:23,026 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:23,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:23,027 INFO L82 PathProgramCache]: Analyzing trace with hash -367384516, now seen corresponding path program 1 times [2019-11-20 09:52:23,027 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:23,027 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847272617] [2019-11-20 09:52:23,027 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:23,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:23,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:23,099 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847272617] [2019-11-20 09:52:23,099 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:23,100 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:23,100 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484315322] [2019-11-20 09:52:23,100 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:23,100 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:23,101 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:23,101 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:23,101 INFO L87 Difference]: Start difference. First operand 6847 states and 8535 transitions. Second operand 5 states. [2019-11-20 09:52:24,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:24,248 INFO L93 Difference]: Finished difference Result 18055 states and 22556 transitions. [2019-11-20 09:52:24,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:24,248 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:24,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:24,256 INFO L225 Difference]: With dead ends: 18055 [2019-11-20 09:52:24,256 INFO L226 Difference]: Without dead ends: 11418 [2019-11-20 09:52:24,262 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:24,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11418 states. [2019-11-20 09:52:24,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11418 to 6859. [2019-11-20 09:52:24,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6859 states. [2019-11-20 09:52:24,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6859 states to 6859 states and 8493 transitions. [2019-11-20 09:52:24,815 INFO L78 Accepts]: Start accepts. Automaton has 6859 states and 8493 transitions. Word has length 168 [2019-11-20 09:52:24,815 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:24,815 INFO L462 AbstractCegarLoop]: Abstraction has 6859 states and 8493 transitions. [2019-11-20 09:52:24,815 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:24,815 INFO L276 IsEmpty]: Start isEmpty. Operand 6859 states and 8493 transitions. [2019-11-20 09:52:24,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:24,816 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:24,817 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:24,817 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:24,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:24,817 INFO L82 PathProgramCache]: Analyzing trace with hash -1334735170, now seen corresponding path program 1 times [2019-11-20 09:52:24,817 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:24,817 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593533007] [2019-11-20 09:52:24,818 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:24,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:24,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:24,898 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1593533007] [2019-11-20 09:52:24,898 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:24,899 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:24,899 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1417408162] [2019-11-20 09:52:24,899 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:24,899 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:24,900 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:24,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:24,900 INFO L87 Difference]: Start difference. First operand 6859 states and 8493 transitions. Second operand 5 states. [2019-11-20 09:52:26,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:26,105 INFO L93 Difference]: Finished difference Result 18399 states and 22836 transitions. [2019-11-20 09:52:26,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:26,106 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:26,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:26,113 INFO L225 Difference]: With dead ends: 18399 [2019-11-20 09:52:26,113 INFO L226 Difference]: Without dead ends: 11764 [2019-11-20 09:52:26,117 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:26,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11764 states. [2019-11-20 09:52:26,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11764 to 6871. [2019-11-20 09:52:26,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6871 states. [2019-11-20 09:52:26,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6871 states to 6871 states and 8451 transitions. [2019-11-20 09:52:26,711 INFO L78 Accepts]: Start accepts. Automaton has 6871 states and 8451 transitions. Word has length 168 [2019-11-20 09:52:26,712 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:26,712 INFO L462 AbstractCegarLoop]: Abstraction has 6871 states and 8451 transitions. [2019-11-20 09:52:26,712 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:26,712 INFO L276 IsEmpty]: Start isEmpty. Operand 6871 states and 8451 transitions. [2019-11-20 09:52:26,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:26,713 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:26,714 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:26,714 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:26,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:26,714 INFO L82 PathProgramCache]: Analyzing trace with hash 1274052288, now seen corresponding path program 1 times [2019-11-20 09:52:26,714 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:26,715 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074641989] [2019-11-20 09:52:26,715 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:26,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:26,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:26,796 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074641989] [2019-11-20 09:52:26,796 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:26,796 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:26,797 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [892984984] [2019-11-20 09:52:26,797 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:26,797 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:26,797 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:26,798 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:26,798 INFO L87 Difference]: Start difference. First operand 6871 states and 8451 transitions. Second operand 5 states. [2019-11-20 09:52:28,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:28,169 INFO L93 Difference]: Finished difference Result 18743 states and 23116 transitions. [2019-11-20 09:52:28,169 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:28,169 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:28,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:28,177 INFO L225 Difference]: With dead ends: 18743 [2019-11-20 09:52:28,177 INFO L226 Difference]: Without dead ends: 12110 [2019-11-20 09:52:28,184 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:28,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12110 states. [2019-11-20 09:52:29,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12110 to 6883. [2019-11-20 09:52:29,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6883 states. [2019-11-20 09:52:29,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6883 states to 6883 states and 8409 transitions. [2019-11-20 09:52:29,025 INFO L78 Accepts]: Start accepts. Automaton has 6883 states and 8409 transitions. Word has length 168 [2019-11-20 09:52:29,025 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:29,025 INFO L462 AbstractCegarLoop]: Abstraction has 6883 states and 8409 transitions. [2019-11-20 09:52:29,025 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:29,026 INFO L276 IsEmpty]: Start isEmpty. Operand 6883 states and 8409 transitions. [2019-11-20 09:52:29,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:29,026 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:29,027 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:29,027 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:29,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:29,027 INFO L82 PathProgramCache]: Analyzing trace with hash 1834752066, now seen corresponding path program 1 times [2019-11-20 09:52:29,027 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:29,027 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599206469] [2019-11-20 09:52:29,027 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:29,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:29,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:29,105 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1599206469] [2019-11-20 09:52:29,105 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:29,106 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:29,106 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [964729426] [2019-11-20 09:52:29,106 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:29,106 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:29,107 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:29,107 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:29,107 INFO L87 Difference]: Start difference. First operand 6883 states and 8409 transitions. Second operand 5 states. [2019-11-20 09:52:30,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:30,527 INFO L93 Difference]: Finished difference Result 19395 states and 23796 transitions. [2019-11-20 09:52:30,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:30,528 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:30,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:30,537 INFO L225 Difference]: With dead ends: 19395 [2019-11-20 09:52:30,537 INFO L226 Difference]: Without dead ends: 12778 [2019-11-20 09:52:30,542 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:30,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12778 states. [2019-11-20 09:52:31,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12778 to 6895. [2019-11-20 09:52:31,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6895 states. [2019-11-20 09:52:31,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6895 states to 6895 states and 8367 transitions. [2019-11-20 09:52:31,229 INFO L78 Accepts]: Start accepts. Automaton has 6895 states and 8367 transitions. Word has length 168 [2019-11-20 09:52:31,229 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:31,229 INFO L462 AbstractCegarLoop]: Abstraction has 6895 states and 8367 transitions. [2019-11-20 09:52:31,229 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:31,229 INFO L276 IsEmpty]: Start isEmpty. Operand 6895 states and 8367 transitions. [2019-11-20 09:52:31,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:31,230 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:31,230 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:31,231 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:31,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:31,231 INFO L82 PathProgramCache]: Analyzing trace with hash 1481663684, now seen corresponding path program 1 times [2019-11-20 09:52:31,231 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:31,231 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2132705322] [2019-11-20 09:52:31,231 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:31,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 09:52:31,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 09:52:31,314 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2132705322] [2019-11-20 09:52:31,314 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 09:52:31,314 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 09:52:31,314 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1835904329] [2019-11-20 09:52:31,315 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-20 09:52:31,315 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 09:52:31,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 09:52:31,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 09:52:31,315 INFO L87 Difference]: Start difference. First operand 6895 states and 8367 transitions. Second operand 5 states. [2019-11-20 09:52:32,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 09:52:32,894 INFO L93 Difference]: Finished difference Result 19739 states and 24076 transitions. [2019-11-20 09:52:32,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 09:52:32,895 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-11-20 09:52:32,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-20 09:52:32,904 INFO L225 Difference]: With dead ends: 19739 [2019-11-20 09:52:32,904 INFO L226 Difference]: Without dead ends: 13124 [2019-11-20 09:52:32,908 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-20 09:52:32,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13124 states. [2019-11-20 09:52:33,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13124 to 6907. [2019-11-20 09:52:33,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6907 states. [2019-11-20 09:52:33,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6907 states to 6907 states and 8325 transitions. [2019-11-20 09:52:33,644 INFO L78 Accepts]: Start accepts. Automaton has 6907 states and 8325 transitions. Word has length 168 [2019-11-20 09:52:33,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-20 09:52:33,644 INFO L462 AbstractCegarLoop]: Abstraction has 6907 states and 8325 transitions. [2019-11-20 09:52:33,644 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-20 09:52:33,644 INFO L276 IsEmpty]: Start isEmpty. Operand 6907 states and 8325 transitions. [2019-11-20 09:52:33,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-11-20 09:52:33,645 INFO L402 BasicCegarLoop]: Found error trace [2019-11-20 09:52:33,645 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 09:52:33,646 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-20 09:52:33,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 09:52:33,646 INFO L82 PathProgramCache]: Analyzing trace with hash 1905310406, now seen corresponding path program 1 times [2019-11-20 09:52:33,646 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 09:52:33,646 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088465735] [2019-11-20 09:52:33,646 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 09:52:33,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 09:52:33,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 09:52:33,800 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 09:52:33,800 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-20 09:52:33,995 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 20.11 09:52:33 BoogieIcfgContainer [2019-11-20 09:52:33,995 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-20 09:52:33,996 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-20 09:52:33,996 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-20 09:52:33,996 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-20 09:52:33,997 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 09:51:58" (3/4) ... [2019-11-20 09:52:33,998 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-20 09:52:34,212 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_139bed1f-8568-45ec-88a5-b1642ed69ce2/bin/uautomizer/witness.graphml [2019-11-20 09:52:34,212 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-20 09:52:34,214 INFO L168 Benchmark]: Toolchain (without parser) took 40022.56 ms. Allocated memory was 1.0 GB in the beginning and 4.1 GB in the end (delta: 3.1 GB). Free memory was 951.4 MB in the beginning and 2.1 GB in the end (delta: -1.1 GB). Peak memory consumption was 2.0 GB. Max. memory is 11.5 GB. [2019-11-20 09:52:34,214 INFO L168 Benchmark]: CDTParser took 0.22 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 09:52:34,215 INFO L168 Benchmark]: CACSL2BoogieTranslator took 513.59 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.0 MB). Free memory was 946.1 MB in the beginning and 1.1 GB in the end (delta: -177.6 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. [2019-11-20 09:52:34,215 INFO L168 Benchmark]: Boogie Procedure Inliner took 125.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2019-11-20 09:52:34,216 INFO L168 Benchmark]: Boogie Preprocessor took 125.21 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2019-11-20 09:52:34,216 INFO L168 Benchmark]: RCFGBuilder took 3104.07 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 956.4 MB in the end (delta: 135.1 MB). Peak memory consumption was 233.6 MB. Max. memory is 11.5 GB. [2019-11-20 09:52:34,216 INFO L168 Benchmark]: TraceAbstraction took 35930.66 ms. Allocated memory was 1.2 GB in the beginning and 4.1 GB in the end (delta: 3.0 GB). Free memory was 956.4 MB in the beginning and 2.1 GB in the end (delta: -1.1 GB). Peak memory consumption was 1.8 GB. Max. memory is 11.5 GB. [2019-11-20 09:52:34,217 INFO L168 Benchmark]: Witness Printer took 216.65 ms. Allocated memory is still 4.1 GB. Free memory was 2.1 GB in the beginning and 2.1 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 11.5 GB. [2019-11-20 09:52:34,218 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.22 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 513.59 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.0 MB). Free memory was 946.1 MB in the beginning and 1.1 GB in the end (delta: -177.6 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 125.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 125.21 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 3104.07 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 956.4 MB in the end (delta: 135.1 MB). Peak memory consumption was 233.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 35930.66 ms. Allocated memory was 1.2 GB in the beginning and 4.1 GB in the end (delta: 3.0 GB). Free memory was 956.4 MB in the beginning and 2.1 GB in the end (delta: -1.1 GB). Peak memory consumption was 1.8 GB. Max. memory is 11.5 GB. * Witness Printer took 216.65 ms. Allocated memory is still 4.1 GB. Free memory was 2.1 GB in the beginning and 2.1 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int t9_pc = 0; [L25] int t10_pc = 0; [L26] int t11_pc = 0; [L27] int t12_pc = 0; [L28] int t13_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int t5_st ; [L35] int t6_st ; [L36] int t7_st ; [L37] int t8_st ; [L38] int t9_st ; [L39] int t10_st ; [L40] int t11_st ; [L41] int t12_st ; [L42] int t13_st ; [L43] int m_i ; [L44] int t1_i ; [L45] int t2_i ; [L46] int t3_i ; [L47] int t4_i ; [L48] int t5_i ; [L49] int t6_i ; [L50] int t7_i ; [L51] int t8_i ; [L52] int t9_i ; [L53] int t10_i ; [L54] int t11_i ; [L55] int t12_i ; [L56] int t13_i ; [L57] int M_E = 2; [L58] int T1_E = 2; [L59] int T2_E = 2; [L60] int T3_E = 2; [L61] int T4_E = 2; [L62] int T5_E = 2; [L63] int T6_E = 2; [L64] int T7_E = 2; [L65] int T8_E = 2; [L66] int T9_E = 2; [L67] int T10_E = 2; [L68] int T11_E = 2; [L69] int T12_E = 2; [L70] int T13_E = 2; [L71] int E_1 = 2; [L72] int E_2 = 2; [L73] int E_3 = 2; [L74] int E_4 = 2; [L75] int E_5 = 2; [L76] int E_6 = 2; [L77] int E_7 = 2; [L78] int E_8 = 2; [L79] int E_9 = 2; [L80] int E_10 = 2; [L81] int E_11 = 2; [L82] int E_12 = 2; [L83] int E_13 = 2; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=0, m_pc=0, m_st=0, T10_E=2, t10_i=0, t10_pc=0, t10_st=0, T11_E=2, t11_i=0, t11_pc=0, t11_st=0, T12_E=2, t12_i=0, t12_pc=0, t12_st=0, T13_E=2, t13_i=0, t13_pc=0, t13_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0, T7_E=2, t7_i=0, t7_pc=0, t7_st=0, T8_E=2, t8_i=0, t8_pc=0, t8_st=0, T9_E=2, t9_i=0, t9_pc=0, t9_st=0] [L1927] int __retres1 ; [L1830] m_i = 1 [L1831] t1_i = 1 [L1832] t2_i = 1 [L1833] t3_i = 1 [L1834] t4_i = 1 [L1835] t5_i = 1 [L1836] t6_i = 1 [L1837] t7_i = 1 [L1838] t8_i = 1 [L1839] t9_i = 1 [L1840] t10_i = 1 [L1841] t11_i = 1 [L1842] t12_i = 1 [L1843] t13_i = 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1868] int kernel_st ; [L1869] int tmp ; [L1870] int tmp___0 ; [L1874] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L871] COND TRUE m_i == 1 [L872] m_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L876] COND TRUE t1_i == 1 [L877] t1_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L881] COND TRUE t2_i == 1 [L882] t2_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L886] COND TRUE t3_i == 1 [L887] t3_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L891] COND TRUE t4_i == 1 [L892] t4_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L896] COND TRUE t5_i == 1 [L897] t5_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L901] COND TRUE t6_i == 1 [L902] t6_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L906] COND TRUE t7_i == 1 [L907] t7_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L911] COND TRUE t8_i == 1 [L912] t8_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L916] COND TRUE t9_i == 1 [L917] t9_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L921] COND TRUE t10_i == 1 [L922] t10_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L926] COND TRUE t11_i == 1 [L927] t11_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L931] COND TRUE t12_i == 1 [L932] t12_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L936] COND TRUE t13_i == 1 [L937] t13_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1248] COND FALSE !(M_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1253] COND FALSE !(T1_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1258] COND FALSE !(T2_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1263] COND FALSE !(T3_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1268] COND FALSE !(T4_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1273] COND FALSE !(T5_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1278] COND FALSE !(T6_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1283] COND FALSE !(T7_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1288] COND FALSE !(T8_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1293] COND FALSE !(T9_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1298] COND FALSE !(T10_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1303] COND FALSE !(T11_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1308] COND FALSE !(T12_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1313] COND FALSE !(T13_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1318] COND FALSE !(E_1 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1323] COND FALSE !(E_2 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1328] COND FALSE !(E_3 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1333] COND FALSE !(E_4 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1338] COND FALSE !(E_5 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1343] COND FALSE !(E_6 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1348] COND FALSE !(E_7 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1353] COND FALSE !(E_8 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1358] COND FALSE !(E_9 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1363] COND FALSE !(E_10 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1368] COND FALSE !(E_11 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1373] COND FALSE !(E_12 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1378] COND FALSE !(E_13 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1531] int tmp ; [L1532] int tmp___0 ; [L1533] int tmp___1 ; [L1534] int tmp___2 ; [L1535] int tmp___3 ; [L1536] int tmp___4 ; [L1537] int tmp___5 ; [L1538] int tmp___6 ; [L1539] int tmp___7 ; [L1540] int tmp___8 ; [L1541] int tmp___9 ; [L1542] int tmp___10 ; [L1543] int tmp___11 ; [L1544] int tmp___12 ; [L594] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L597] COND FALSE !(m_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L607] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L609] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1548] tmp = is_master_triggered() [L1550] COND FALSE !(\read(tmp)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L613] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L616] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L626] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L628] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1556] tmp___0 = is_transmit1_triggered() [L1558] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L632] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L635] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L645] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L647] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1564] tmp___1 = is_transmit2_triggered() [L1566] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L651] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L654] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L664] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L666] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1572] tmp___2 = is_transmit3_triggered() [L1574] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L670] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L673] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L683] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L685] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1580] tmp___3 = is_transmit4_triggered() [L1582] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L689] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L692] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L702] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L704] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1588] tmp___4 = is_transmit5_triggered() [L1590] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L708] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L711] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L721] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L723] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1596] tmp___5 = is_transmit6_triggered() [L1598] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L727] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L730] COND FALSE !(t7_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L740] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L742] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1604] tmp___6 = is_transmit7_triggered() [L1606] COND FALSE !(\read(tmp___6)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L746] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L749] COND FALSE !(t8_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L759] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L761] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1612] tmp___7 = is_transmit8_triggered() [L1614] COND FALSE !(\read(tmp___7)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L765] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L768] COND FALSE !(t9_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L778] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L780] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1620] tmp___8 = is_transmit9_triggered() [L1622] COND FALSE !(\read(tmp___8)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L784] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L787] COND FALSE !(t10_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L797] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L799] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1628] tmp___9 = is_transmit10_triggered() [L1630] COND FALSE !(\read(tmp___9)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L803] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L806] COND FALSE !(t11_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L816] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L818] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1636] tmp___10 = is_transmit11_triggered() [L1638] COND FALSE !(\read(tmp___10)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L822] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L825] COND FALSE !(t12_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L835] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L837] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1644] tmp___11 = is_transmit12_triggered() [L1646] COND FALSE !(\read(tmp___11)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L841] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L844] COND FALSE !(t13_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L854] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L856] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1652] tmp___12 = is_transmit13_triggered() [L1654] COND FALSE !(\read(tmp___12)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1391] COND FALSE !(M_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1396] COND FALSE !(T1_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1401] COND FALSE !(T2_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1406] COND FALSE !(T3_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1411] COND FALSE !(T4_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1416] COND FALSE !(T5_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1421] COND FALSE !(T6_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1426] COND FALSE !(T7_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1431] COND FALSE !(T8_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1436] COND FALSE !(T9_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1441] COND FALSE !(T10_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1446] COND FALSE !(T11_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1451] COND FALSE !(T12_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1456] COND FALSE !(T13_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1461] COND FALSE !(E_1 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1466] COND FALSE !(E_2 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1471] COND FALSE !(E_3 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1476] COND FALSE !(E_4 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1481] COND FALSE !(E_5 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1486] COND FALSE !(E_6 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1491] COND FALSE !(E_7 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1496] COND FALSE !(E_8 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1501] COND FALSE !(E_9 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1506] COND FALSE !(E_10 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1511] COND FALSE !(E_11 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1516] COND FALSE !(E_12 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1521] COND FALSE !(E_13 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1882] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1885] kernel_st = 1 [L1027] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1031] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L946] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L949] COND TRUE m_st == 0 [L950] __retres1 = 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1022] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1034] tmp = exists_runnable_thread() [L1036] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1041] COND TRUE m_st == 0 [L1042] int tmp_ndt_1; [L1043] tmp_ndt_1 = __VERIFIER_nondet_int() [L1044] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1055] COND TRUE t1_st == 0 [L1056] int tmp_ndt_2; [L1057] tmp_ndt_2 = __VERIFIER_nondet_int() [L1058] COND FALSE !(\read(tmp_ndt_2)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L11] __VERIFIER_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 1886 locations, 1 error locations. Result: UNSAFE, OverallTime: 35.8s, OverallIterations: 43, TraceHistogramMax: 1, AutomataDifference: 19.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 108702 SDtfs, 149913 SDslu, 65057 SDs, 0 SdLazy, 1934 SolverSat, 1116 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 147 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=6907occurred in iteration=42, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 11.9s AutomataMinimizationTime, 42 MinimizatonAttempts, 52260 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 7194 NumberOfCodeBlocks, 7194 NumberOfCodeBlocksAsserted, 43 NumberOfCheckSat, 6984 ConstructedInterpolants, 0 QuantifiedInterpolants, 1620728 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 42 InterpolantComputations, 42 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...